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Part Manufacturer Description Datasheet BUY
SN74LS00N-00 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDIP14 visit Texas Instruments
SN74LS00DBR Texas Instruments Quad 2-input positive-NAND gates 14-SSOP 0 to 70 visit Texas Instruments Buy
SN74LS00NE4 Texas Instruments Quad 2-input positive-NAND gates 14-PDIP 0 to 70 visit Texas Instruments
SN74LS00DBRE4 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, GREEN, PLASTIC, SSOP-14 visit Texas Instruments
SN74LS00NSR Texas Instruments Quad 2-input positive-NAND gates 14-SO 0 to 70 visit Texas Instruments Buy
SN74LS00J-00 Texas Instruments IC LS SERIES, QUAD 2-INPUT NAND GATE, CDIP14, Gate visit Texas Instruments

TTL 74ls00

Catalog Datasheet MFG & Type PDF Document Tags

TTL 74ls00

Abstract: AS5305 RL = 820 A/B/Index from AS5304/6 TTL 74LS00 CL = 20pF Figure 13: Typical digital load
austriamicrosystems AG
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AS5304 AS5306 TTL 74ls00 AS5305 Rotary Encoder ES 72* hall IC 3 pole AS5306A AS5304/AS5306

TTL 74LS00

Abstract: AS5306 See Figure 13 See Figure 13 Push/Pull mode VDD = 5V RL = 820 A/B/Index from AS5304/6 TTL 74LS00 CL = 20pF Figure 13: 9.5 Typical digital load CAO Analogue Output Buffer
austriamicrosystems AG
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magnetic strip encoder 12mm Rotary Encoder switch rotary encoder 500 pulses per revolution quadrature JESD78 MO-153-AC

TTL 74ls00

Abstract: AS5306 µs 39 VDD = 5V RL = 820 A/B/Index from AS5304/6 TTL 74LS00 CL = 20pF Figure 13
austriamicrosystems AG
Original
5304 marking code EN Rotary optical encoder AS5304A incremental optical encoder 5V ttl quadrature hall rotary encoder 500 pulses .5"quadrature
Abstract: Revision 1.9 am lc s on A te G nt st il VDD = 5V RL = 820 A/B/Index from AS5304/6 TTL 74LS00 CL = austriamicrosystems AG
Original
Abstract: /Index from AS5304/6 TTL 74LS00 C L = 20pF 6.4 CAO Analog Output Buffer Table 6. CAO Analog austriamicrosystems AG
Original
AS5304/

3A71

Abstract: TTL 74LS00 CL = 20pF 1 #29;C#30;#16;5381#23;#31;8 @$#22; 6(DCB678#27;C#30;CE6787F6#27;8 -#20;/8#20;467F#30;#16;38/#16;ED#16;E8
austriamicrosystems AG
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3A71 C4365864 CA80FE65 81FECF4893E3BECF48 2343567893AB5CDECF48 38F61 7F5781

74LS00

Abstract: 74LS00 TTL two additional TTL chips. If your 8051 design I/O Port Interface is completely I/O based with no , AD1 AD2 AD3 AD4 AD5 AD6 AD7 1 2 OE CHIP 1\ CS CHIP 1\ 74LS00 5 4 6 Y0 Y1 Y2 , \ CS CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW , 74LS00 13 12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 6 74LS00 A8 A9 A10 PHA PHB PHC
Hewlett-Packard
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HCTL1100 CS1100 RD1100 WR1100 74LS00 TTL 3 to 8 line decoder using 8051 8051s 74LS00 DATA microcontroller 8051s interfaces M-015 HCTL-1100/8051 OE1100 6000H

74LS00

Abstract: 74LS00 TTL Output Current - Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/74LS00 DC , SN54/74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC , ns tPHL Turn-On Delay, Input to Output 10 15 ns FAST AND LS TTL DATA 5-3
Motorola
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74LS00 truth table 74LS00DC 74ls00 tphl tplh NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE motorola 74LS00 SN54/74LS00 SN54LSXXJ SN74LSXXN SN74LSXXD

3 to 8 line decoder using 8051

Abstract: 74LS00 sense to use the HCTL-1100 bus interface circuit. This approach requires only two additional TTL chips , AD2 AD3 AD4 AD5 AD6 AD7 1 2 OE CHIP 1\ CS CHIP 1\ 74LS00 5 4 6 Y0 Y1 Y2 Y3 , CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW SIGNAL , 39 38 38 34 1 A 2 B 3 C 11 MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 3 74LS00 13
Avago Technologies
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74LS138 DATASHEET HCTL-1100 M-015 HCTL-1100s LOGIC OF 74LS138 74LS00 application 8051 reset circuit 5964-3776E

74LS00 TTL

Abstract: TTL 74LS00 Output Current - Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/74LS00 DC , SN54/74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC , AND LS TTL DATA 5-3 Motorola
Motorola
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74ls00 NAND gate 74ls00 datasheet 74LS00 gate 74LS00 TTL datasheet 751A-02

74LS00 TTL

Abstract: 74LS00 truth table Output Current - High Output Current - Low mA mA FAST AND LS TTL DATA 5-2 SN54/74LS00 DC , MOTOROLA SN54/74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE fn l [ïïl fïïl [Til fïïl ITI 171 J SUFFIX CERAMIC CASE 632-08 VCC LOW POWER SCHOTTKY Lü Ll I Ll I L±l Ll I Ll I LzJ GND N SUFFIX ,r p îïï , 'S :. D SUFFIX SOIC CASE 751A-02 5 , Conditions Vcc = 5 0 V C[_= 15 pF 5 FAST AND LS TTL DATA 5-3
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IC TTL 74LS00 IC 74LS00

t74ls157

Abstract: 74LS00 fan out LOW POWER SCHOTTKY TTL-54/74 LS SERIES DESIGN CONSIDERATIONS SUPPLY VOLTAGE â'" +5V ± 10% T54 , , VIH 2.0V, Vol 0.5V, VOH 2.7V T74 SERIES INPUT LOADING â'" THE 74LS00 INPUT LOADING IS Iil 0.36mA (LOW INPUT) AND I IH 20MA (HIGH INPUT) OUTPUT DRIVE â'" THE 74LS00 OUTPUT DRIVE IS Iol 8.0mA (SINK) AND I oh , DEVICES WITHIN THE FAMILY AND IS NORMALIZED AROUND THE INPUT REQUIREMENTS OF THE 74LS00.E.G. THE 74LS00 , TECHNOLOGY AND SERVICE! 52 This Material Copyrighted By Its Respective Manufacturer LOW POWER SCHOTTKY TTL
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t74ls157 74LS00 fan out 74LS00E T74LS74 T54LS/T74LS163 74ls00 series TTL-54/74 T54LSXXD2 T74LSXXB1 T74LSXXD1 T74LSXXM T54LS/T74LS00

TTL 74ls00

Abstract: 74LS00 Current â'" Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-2 SN54/74LS00 DC CHARACTERISTICS OVER , (g) MOTOROLA QUAD 2-INPUT NAND GATE â'¢ ESD > 3500 Volts vcc nn [ïïi ra m ra m m LlI LLI LLI LLI LiJ LLI LLI gnd SN54/74LS00 QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES f0 1 J SUFFIX CERAMIC CASE 632-08 Jfllffi 1 N SUFFIX PLASTIC CASE 646-06 1 D SUFFIX SOIC CASE , AND LS TTL DATA 5-3
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truth table NAND gate 74

74LS00 TTL

Abstract: 74LS00 noise immunity +125°C. TTL families may be mixed for optimum system design. The following table specify the worst case noise immunity in mixed systems. WORST CASE TTL DC NOISE IMMUNITY/NOISE MARGINS Electrical Characteristics Item 6 7 10 Symbol TTL HTTL LSTTL SGS-THOMSON TTL Families Standard TTL (54/74) High Speed TTL (54H/74H) Low Power Schottky TTL (54LS/74LS) Military ( - 5 5 t o +125 C) V il V ih V ol V oh , . LOW Level Noise Margins (Military) T° From TTL HTTL LSTTL From "V ol" to "V JL " LOW Level Noise
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74LS00 noise immunity 74LS00 fan-out 7400 fan-in 74ls00 applications 74LS00 Electrical and Switching characteristics TTL 7400 rise and fall time

ls 7400

Abstract: 7400 signetics TTL Signetìcs I 7400, LSOO, SOO Gates Logic Products Quad Two-Input NAND Gate Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , tor 74LS; VM - 1.5V tor all other TTL families input Pulse Definition FAMILY INPUT PULSE , .) PARAMETER TEST CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max , 1,3V for 74LS; VM = 1.5V for all other TTL families. Waveform 1. Waveform For Inverting Outputs AC
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ls 7400 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74SOO N7400N N74LS00N N74S00N N74LS00D N74S00D

7400 signetics

Abstract: 74LS00 7400 74S00 Signetics I 7400, LS00, SOO Gates Logic Products Quad Two-Input NAND Gate Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , 74LS; Vu - 1.5V for all other TTL families. Input Pulse Definition FAMILY INPUT PULSE REQUIREMENTS , CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max HIGH-level OH output , other TTL families. Waveform 1. Waveform For Inverting Outputs AC ELECTRICAL CHARACTERISTICS TA = 25Â
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7400 signetics 74LS00 7400 74S00 74LS00 function table TTL 7400 pin configuration 74LS00 74LS00 pin configuration LS03Z90S

74LS00 function table

Abstract: pin configuration logic symbol 74LS00 Signelics | 7400, LS00, S00 Gates Quad Two-Input NAND Gate Product Specification Logic Products TYPE 7400 74LS00 74S00 TYPICAL PROPAGATION DELAY 9ns 9.5ns 3ns TYPICAL SUPPLY CURRENT , TEST CIRCUITS AND WAVEFORMS VM - 1.3V for 74LS; VM = 1.5V for all other TTL families. Test , 74LS00 Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 .5 0.5 0.4 -1 .5 Max Min 2.7 74S00 UNIT Min Typ2 3.4 0.2 , 70S Vm = 1.3V for 74LS; = 1.5V for all other TTL families. Waveform 1. Waveform For
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pin configuration logic symbol 74LS00 specification of 74ls00 logic symbol 74LS00 7400 quad NAND pin configuration N74LS00 N74S00 N74SOOD

7404 TTL CMOS

Abstract: TTL 74h04 /7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , . a> Q. » Q c o ï 2
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7404 TTL CMOS TTL 74h04 TTL 7400 fairchild 7404 ttl inverter TTL 7404 fairchild 9016 CI 74LS00 54H/74H04 54S/74S04 54LS/74LS04 9S05A 54H/74H05 54S/74S05

TTL 7410

Abstract: TTL 7401 /7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , Ended 16 3.0 -5.2 510 4 E105 4L,6B 2 54S/ 74S140 Dual 2-NAND Any TTL TTL Volt Single Ended 40 4.0 +5.0 88 2 D5 3I, 6A,9A 3 54LS/ 74LS240 Octal Inverting Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 175 8 D73 9Z 4 54LS/ 74LS241 Octal Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 180 8 D74 9Z 5 54LS/ 74LS244 Octal Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 180 8 D77 9Z 6 54LS/ 74LS540
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TTL 7410 TTL 7401 TTL 7420 TTL 74LS04 7404 TTL 74H04 54L8/74LS05 54LS/74LS14 54LS/74LS00 54LS/74LS03 54LS/74LS26 54LS/74LS37

TTL SN 54S00

Abstract: . J PACKAGE SN 54LS00, SN 54S00 . . . J OR W PACKAG E SN 7400 . . . N PACKAG E SN 74LS00, SN , V IE W ) £Q < O «- t- z TTL Devices 2 FUNCTION TA B LE le a c h g a te ) o , -INPUT PQSITIVE-NAND GATES TTL Devices R e s is t o r v a lu e s s h o w n a re n o m in a l. absolute maximum , OFFICE BOX 6 5 5 0 1 2 â'¢ D ALLAS . TEXAS 7 5 2 6 5 U N IT TTL Devices PARAM ETER SN54LS00, SN74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES recommended operating conditions SN 74LS00 SN 54LS00
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TTL SN 54S00 SN5400 SIU54S00 SN7400 SN74S00
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