NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| SN74126J-00 | Texas Instruments | IC TTL/H/L SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDIP14, Bus Driver/Transceiver | 
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| SN74126N-10 | Texas Instruments | IC TTL/H/L SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDIP14, Bus Driver/Transceiver |
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| SN74126N3 | Texas Instruments | IC TTL/H/L SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDIP14, Bus Driver/Transceiver |
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| SN74126N-00 | Texas Instruments | IC TTL/H/L SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDIP14, Bus Driver/Transceiver |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Signelics 74125, 74126, LS125A LS125A, LS 126A Buffers Logic Products Quad 3-State Buffer Product , SUPPLY CURRENT (TOTAL) 74125 10ns 32mA 74LS125A 74LS125A 8ns 11mA 74126 10ns 36mA 74LS126A 74LS126A 9ns 12mA ORDERING , Product Specification Buffers 74125, 74126, LS125A LS125A, LS126A LS126A PIN CONFIGURATION LOGIC SYMBOL LOGIC , Product Specification Buffers 74125, 74126, LS125A LS125A, LS126A LS126A DC ELECTRICAL CHARACTERISTICS (Over , 74126 74LS125A 74LS125A 74LS126A 74LS126A UNIT Min Typ2 Max Min Typ2 Max HIGH-level OH output voltage vcg = min ... | OCR Scan |
5 pages, |
LS126A N74125N N74LS125AD N74LS125N N74LS126N 74LS126A 74LS125A 74LS125 74LS N74126N ls125a 74125 S0324 74126 pin configuration of 74125 LS125A LS125A LS125A abstract |
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| Abstract: SignetÃcs 74125, 74126, LS125A LS125A, LS126A LS126A Buffers Logic Products Quad 3-State Buffer Product , ) 74125 10ns 32mA 74LS125A 74LS125A 8ns 11mA 74126 10ns 36mA 74LS126A 74LS126A 9ns 12mA ORDERING CODE PACKAGES , Its Respective Manufacturer Signetics Logic Products Product Specification Buffers 74125, 74126 , , 74126, LS125A LS125A, LS126A LS126A DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 74125 74126 74LS125A 74LS125A 74LS126A 74LS126A UNIT ... | OCR Scan |
5 pages, |
N74125N N74126N 74LS126A N74LS125AD N74LS125N N74LS126N 74125 SIGNETICS 74126 LS126A N74126N NON INVERTING ic 74126 information ic ttl 74ls ls125a logic table of ic 74126 LS125A LS126A LS125A abstract |
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| Abstract: in ~?i r?i Lj ui lii y ili iii u E D O E D O QND D67 54/74126, 54LS/74LS126 54LS/74LS126 Vcc E D O E DO , ] li] LÌ] li] liJ LJ GND 13-51 FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) Item Function'1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High , (3S) - 54LS/74LS126 54LS/74LS126 54/74126 - - D67 3I,6A,9A 18 Hex (3S) - 54LS/74LS365 54LS/74LS365 - - - D68 4L,6B,9B 19 Hex ... | OCR Scan |
2 pages, |
TTL 74ls126 74H55 74LS366 9006 74125 TTL 74125 74126 high speed 74ls gate symbols 74LS series logic gates 3 input or gate buffer 74ls series logic gates ic 74125 ic 74126 74LS125 TTL 74126 54LS/74LS13 54LS/74LS13 abstract |
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| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D33 54H/74H55 54H/74H55 D34 54LS/74LS55 54LS/74LS55 Vcc Vcc 0 1 D35 S4H/74H61 S4H/74H61 D36 9006, 54/7460, 54H/74H60 54H/74H60 ra ra ra m y m Vcc ST Iii Iii , liJ IU Lil liJ lil u OND 13-46 FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) Item Function'1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High , (3S) - 54LS/74LS126 54LS/74LS126 54/74126 - - D67 3I,6A,9A 18 Hex (3S) - 54LS/74LS365 54LS/74LS365 - - - D68 4L,6B,9B 19 Hex ... | OCR Scan |
2 pages, |
TTL 74ls125 7450 ttl 74LS series logic gates 74LS126 74LS266 9006 9S42 TTL 74125 74125 ic 74125 r025 buffer 74ls series logic gates 74H62 74125 ic 54H/74H55 54LS/74LS55 54H/74H55 abstract |
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| Abstract: FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) E « g s u c 3 LL. 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 54S/74S 3 ns/19 mW LogicConnection Diagram'2' S 0> a> o> cs O , Buffer (3S) - 54LS/74LS125 54LS/74LS125 54/74125 - - D66 3I,6A,9A 17 Quad Buffer (3S) - 54LS/74LS126 54LS/74LS126 54/74126 - - D67 ... | OCR Scan |
1 pages, |
74LS266 TTL 74125 74H55 9S42 9006 74LS series logic gates 74126 high speed Fairchild logic/connection diagrams ttl 74ls gate symbols 74LS series logic gates 3 input or gate 7450 ttl TTL 74126 54LS/74LS 54LS/74LS 54H/74H 54LS/74LS abstract |
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| Abstract: FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) Item Function'1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 54S/74S 3 ns/19 mW Logic/Connection Diagram(2) 5 , Buffer (3S) - 54LS/74LS125 54LS/74LS125 54/74125 - - D66 3I,6A,9A 17 Quad Buffer (3S) - 54LS/74LS126 54LS/74LS126 54/74126 - - D67 ... | OCR Scan |
1 pages, |
9006 ic 74126 ic 74125 9S42 74H55 74LS266 r025 74125 ic 74LS series logic gates 3 input or gate 74LS series logic gates 54LS/74LS 54H/74H 54S/74S 54H/74H52 54LS/74LS abstract |
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| Abstract: ^ Additional Devices DM70/DM8093 DM70/DM8093, 94 General Description The DM7093/DM8093 DM7093/DM8093 and DM7094/DM8094 DM7094/DM8094 are quad two input buffers which accept normal TTL or DTL input levels; and have outputs which provide either normal low-impedance TTL characteristics, or a high-impedance third logic state One of the two inputs to each buffer is used as a control line to gate the output into the high-impedance state. The , (7093/8093) and DM54126/74126 (7094/8094) â- Up to 128 devices can be connected to a common bus line â- ... | OCR Scan |
2 pages, |
DM8094 DM7094 DM70 TTL 74125 DM7093 74126 DM70/DM8093 DM7093/DM8093 DM7094/DM8094 DM54125/74125 DM54126/74126 DM70/DM8093 abstract |
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| Abstract: 33 Additional Devices DM70/DM8093 DM70/DM8093, 94 General Description The DM7093/DM8093 DM7093/DM8093 and DM7094/DM8094 DM7094/DM8094 are quad two-input buffers which accept normal TTL or DTL input levels; and have outputs which provide either normal low-impedance TTL characteristics, or a high-impedance third logic state. One of the two inputs to each buffer is used as a control line to gâte the output into the high-impedance state. The , (7093/8093) and DM54126/74126 (7094/8094) â- Up to 128 devices can be connected to a common bus line â- ... | OCR Scan |
2 pages, |
DM70/DM8093 DM7093/DM8093 DM7094/DM8094 DM54125/74125 DM54126/74126 DM70/DM8093 abstract |
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| Abstract: TTL SSI FUNCTIONS (Cont'd) Item Function'1 ' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 54S/74S , 54LS/74LS125 54LS/74LS125 54/74125 - - D66 3I,6A,9A 17 Quad Buffer (3S) - 54LS/74LS126 54LS/74LS126 54/74126 - - D67 3I,6A,9A ... | OCR Scan |
2 pages, |
ic 74125 74H51 74H55 74LS series logic gates 74S64 74S65 74S84 9006 9S42 7454 74LS series logic gates 3 input or gate 54H/74H52 54H/74H52 abstract |
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| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D65 54/7413, 54LS/74LS13 54LS/74LS13 Vcc NC HKiEiraiaram 3 LlI lil Id li] li] Là J Ui NC QND D66 54/74125, 54LS/74LS125 54LS/74LS125 Vcc E D O E D O ism a ra a in ~?i r?i Lj ui lii y ili iii u E D O E D O QND D67 54/74126, 54LS/74LS126 54LS/74LS126 Vcc E D O E DO , ] li] LÌ] li] liJ LJ GND 13-51 FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) E a o o e 3 LL 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 54LS/74LS 5 ns/2 mW Std. TTL 54/74 10 ns/10 mW High Speed 54H ... | OCR Scan |
2 pages, |
74LS08 ttl 74LS02 7486 ci 7409 7408 and ci 7432 ttl TTL 74ls125 TTL 7486 TTL 74126 TTL 7409 FL 9014 EI 54 CI 74LS32 7408 54LS/74LS13 54LS/74LS13 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| Data Sheet Abstract: SN54126 SN54126 SN54126 SN54126, SN54LS125A SN54LS125A SN54LS125A SN54LS125A, SN74125 SN74125 SN74125 SN74125, SN74126, SN74LS125A SN74LS125A SN74LS125A SN74LS125A, SN74LS126A SN74LS126A SN74LS126A SN74LS126A:QUADRUPLE BUS , SN54126 SN54126 SN54126 SN54126, SN54LS125A SN54LS125A SN54LS125A SN54LS125A, SN54LS126A SN54LS126A SN54LS126A SN54LS126A, SN74125 SN74125 SN74125 SN74125, SN74126,SN74LS125A SN74LS125A SN74LS125A SN74LS125A, SN74LS126A SN74LS126A SN74LS126A SN74LS126A QUADRUPLE BUS BUFFERS WITH 3 feature three-state outputs that, when enabled, havethe low impedance characteristics of a TTL output with 74126N, SN74LS125AD SN74LS125AD SN74LS125AD SN74LS125AD, SN74LS125ADR SN74LS125ADR SN74LS125ADR SN74LS125ADR, SN74LS125AN SN74LS125AN SN74LS125AN SN74LS125AN, SN74LS125AN3 SN74LS125AN3 SN74LS125AN3 SN74LS125AN3, SN74LS125ANSLE SN74LS125ANSLE SN74LS125ANSLE SN74LS125ANSLE, SN74LS126AD SN74LS126AD SN74LS126AD SN74LS126AD, SN74LS126ADR SN74LS126ADR SN74LS126ADR SN74LS126ADR , SN74126 , SN74LS125A SN74LS125A SN74LS125A SN74LS125A , SN74LS126A SN74LS126A SN74LS126A SN74LS126A Go to the Engineering Design Center to locate www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/sdls044.htm |
Texas Instruments | 01/06/1998 | 6.36 Kb | HTM | sdls044.htm |
| .INFO> SN54125 SN54125, SN54126 SN54126 SN54126 SN54126, SN54LS125A SN54LS125A SN54LS125A SN54LS125A, SN54LS126A SN54LS126A SN54LS126A SN54LS126A, SN74125 SN74125 SN74125 SN74125, SN74126, SN74LS125A SN74LS125A SN74LS125A SN74LS125A that, when enabled, have the low impedance characteristics of a TTL output with additional drive www.datasheetarchive.com/files/texas-instruments/asl_data/aslbooks/graphics/sdls044/sdls044.fea |
Texas Instruments | 16/12/1996 | 2.62 Kb | FEA | sdls044.fea |
| _inverter(rise_delay=8n fall_delay=12n) .ends * * * *SRC=74126;74126;TTL;74xx;Bus buffer *SYM * * * STANDARD TTL DIGITAL LIBRARY BASED ON THE TEXAS * * INSTRUMENTS DATA BOOK (Volume 1 * * * * * *SRC=7400;7400;TTL;74xx;2 input NAND gate *SYM=NAND2 *7400 QUADRUPLE 2-INPUT POSITIVE-NAND GATES * * * *SRC=7402;7402;TTL;74xx;2 input NOR gate *SYM=NOR2 *7402 QUADRUPLE 2-INPUT POSITIVE-NOR GATES * * * *SRC=7404;7404;TTL;74xx;inverter *SYM=INV *7404 HEX INVERTERS * .subckt 7404 in out *FAMILY www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/7400.lib |
Spice Models | 18/04/2010 | 72.32 Kb | LIB | 7400.lib |
| - * Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to 2-7 * bss 2 * * * - 7401 - * Quad 2-Input Nand Gates With Open-Collector Outputs * * The TTL Logic Data Book * * * - 7402 - * Quad 2-Input Nor Gates * * The TTL Logic Data Book, 1988, TI Pages 2-13 to 2 * * * - 7403 - * Quad 2-Input Nand Gates With Open-Collector Outputs * * The TTL Logic Data Book * * * - 7404 - * Hex Inverters * * The TTL Logic Data Book, 1988, TI Pages 2-25 to 2-29 * bss 2 www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/digdemo.lib |
Spice Models | 18/04/2010 | 128.15 Kb | LIB | digdemo.lib |
| * * * STANDARD TTL DIGITAL LIBRARY BASED ON THE TEXAS * * INSTRUMENTS DATA BOOK (Volume 1 * * * * * *SRC=54152A;54152A;TTL;54xx;2 input NAND *SYM=T54152A T54152A T54152A T54152A *54152A MULTIPLEXER/DATA SELECTOR 8-1 LINE ;5400;TTL;54xx;2 input NAND gate *SYM=NAND2 *5400 QUADRUPLE 2-INPUT POSITIVE-NAND GATES * .subckt 5400 * * * *SRC=5402;5402;TTL;54xx;2 input NOR gate *SYM=NOR2 *5402 QUADRUPLE 2-INPUT POSITIVE-NOR GATES * * * *SRC=5404;5404;TTL;54xx;inverter *SYM=INV *5404 HEX INVERTERS * .subckt 5404 in out *FAMILY www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/5400.lib |
Spice Models | 18/04/2010 | 67.42 Kb | LIB | 5400.lib |
| ;54LS126A 54LS126A 54LS126A 54LS126A;TTL;54LSxx;Bus buffer *SYM=T74126 *54LS126A 54LS126A 54LS126A 54LS126A QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS * * * * * *SRC=54LS00 54LS00 54LS00 54LS00;54LS00 54LS00 54LS00 54LS00;TTL;54LSxx;2 input NAND gate *SYM=NAND2 *54LS00 54LS00 54LS00 54LS00 QUADRUPLE 2-INPUT POSITIVE ) .ends * * * *SRC=54LS01 54LS01 54LS01 54LS01;54LS01 54LS01 54LS01 54LS01;TTL;54LSxx;2 input NAND gate *SYM=NAND2 *54LS =54LS02 54LS02 54LS02 54LS02;54LS02 54LS02 54LS02 54LS02;TTL;54LSxx;2 input NOR gate *SYM=NOR2 *54LS02 54LS02 54LS02 54LS02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES * * * *SRC=54LS03 54LS03 54LS03 54LS03;54LS03 54LS03 54LS03 54LS03;TTL;54LSxx;2 input NAND gate *SYM=NAND2 *54LS03 54LS03 54LS03 54LS03 QUADRUPLE 2-INPUT POSITIVE www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/54ls.lib |
Spice Models | 18/04/2010 | 59.29 Kb | LIB | 54ls.lib |
| _delay=7n) .ends * * * *SRC=74LS126A 74LS126A 74LS126A 74LS126A;74LS126A 74LS126A 74LS126A 74LS126A;TTL;74LSxx;Bus buffer *SYM=T74126 * * * * * *SRC=74LS00 74LS00 74LS00 74LS00;74LS00 74LS00 74LS00 74LS00;TTL;74LSxx;2 input NAND gate *SYM=NAND2 *74LS00 74LS00 74LS00 74LS00 QUADRUPLE 2-INPUT POSITIVE ;74LS01 74LS01 74LS01 74LS01;TTL;74LSxx;2 input NAND gate *SYM=NAND2 *74LS01 74LS01 74LS01 74LS01 QUADRUPLE 2-INPUT POSITIVE-NAND GATES *WITH ;74LS02 74LS02 74LS02 74LS02;TTL;74LSxx;2 input NOR gate *SYM=NOR2 *74LS02 74LS02 74LS02 74LS02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES _nor(rise_delay=10n fall_delay=10n) .ends * * * *SRC=74LS03 74LS03 74LS03 74LS03;74LS03 74LS03 74LS03 74LS03;TTL;74LSxx;2 input NAND www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/74ls.lib |
Spice Models | 18/04/2010 | 63.91 Kb | LIB | 74ls.lib |
| * Library of Standard 74 TTL Family Digital Models * * Copyright OrCAD, Inc. 1998 All Rights :32:32 $ * * *$ *- * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *$ *- * 7401 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2 + ) *$ *- * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *$ *- * 7403 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/7400.lib |
Spice Models | 29/07/2012 | 282.15 Kb | LIB | 7400.lib |
| * Library of Standard 74 TTL Family Digital Models * * Copyright Cadence Design Systems, Inc :26:32 $ * * *$ *- * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *$ *- * 7401 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2 + ) *$ *- * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *$ *- * 7403 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book www.datasheetarchive.com/files/spicemodels/misc/7400.lib |
Spice Models | 19/12/2001 | 282.17 Kb | LIB | 7400.lib |
| Triple 3-input Posit ive-And Gates * 74S11 74S11 74S11 74S11 S-series TTL Triple 3-input Positive Bus Buffer with 3-state Outputs * 74126 Quadruple Bus Buffer with 3-state * *- * * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *- *$ * 7401 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2 =8ns tphlmx=15ns + ) *- *$ * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL www.datasheetarchive.com/files/spicemodels/misc/eval.lib |
Spice Models | 20/12/2001 | 295.35 Kb | LIB | eval.lib |