TSM2N7002 TSM2N7002CX - Datasheet Archive

 

60V N-Channel Enhancement Mode MOSFET Pin assignment: 1. Gate 2. Source 3. Drain VDS = 60V RDS (on), Vgs @ 10V, Ids @ 500mA = 7.5

 

TSM2N7002 TSM2N7002 60V N-Channel Enhancement Mode MOSFET Pin assignment: 1. Gate 2. Source 3. Drain VDS = 60V RDS (on), Vgs @ 10V, Ids @ 500mA = 7.5 RDS (on), Vgs @ 5V, Ids @ 50mA = 13.5 Features Advanced trench process technology No minority carrier storage time High density cell design for low on-resistance CMOS logic compatible input High input impedance No secondary breakdown High speed switching Compact and low profile SOT-23 package Block Diagram Ordering Information Part No. TSM2N7002CX TSM2N7002CX Packing Tape & Reel Package SOT-23 Absolute Maximum Rating (Ta = 25oC unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage VDS 60 V Gate-Source Voltage VGS ± 20 V ID 115 mA IDM 800 mA PD 225 mW 1.8 MW/ C Continuous Drain Current Pulsed Drain Current Maximum Power Dissipation o Ta = 25 C o Ta > 25 C o TJ o C TJ, TSTG - 55 to +150 o C Limit Unit TL Operating Junction and Storage Temperature Range +150 Symbol Operating Junction Temperature 5 S Rja 417 Thermal Performance Parameter Lead Temperature (1/8" from case) Junction to Ambient Thermal Resistance (PCB mounted) Note: Surface mounted on FR4 board t