90255AB TSL1301 TSL1401 MLX90255 MLX90255AA MLX90255AB - Datasheet Archive

 

1. FEATURES · 128 x 1 Sensor-Element Organization (1 Not Connected, 1 dummy, 128 real, 1 dummy and 1 Dark Pixel) ·

 

MLX 90255AB 90255AB Optical array 1. FEATURES · 128 x 1 Sensor-Element Organization (1 Not Connected, 1 dummy, 128 real, 1 dummy and 1 Dark Pixel) · 385 Dots-Per-Inch (DPI) Sensor Pitch · High Linearity and Uniformity for 256 Gray-Scale (8-Bit) Applications · Optimization: less Gain in order to get better Signal To Noise behavior: up to 13 bits · Output becomes high impedance after CLK 132 · Extremely low integration times possible: up to 10 µs! (independent of clock speed) · Output Referenced to Ground · Low Image Lag . 0.5% Typ · Single 5-V Supply · Replacement of Texas Instruments TSL1301 TSL1301 & TSL1401 TSL1401 · Operation to 1MHz The MLX90255 MLX90255 linear sensor array consists of a 128 × 1 array of photodiodes, associated charge amplifier circuitry, and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 200µm (H) by 66µm (W) and 8 µm spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. MLX90255AA MLX90255AA Optical Array Page 1 March 2000 Detailed description The sensor consists of 128 photodiodes arranged in a linear array. Light energy falling on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 132-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. This causes all 132 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Two dummy pixel values are shifted out first, then the 128 actual pixel bits, followed by two additional dummy pixel bits, for a total of 132 data bits. The integrator-reset period ends 132 clock cycles after the SI pulse is clocked in. So the light integration nd starts after the 132 CLK pulse. The light integration ends at the next SI pulse. Between the end of the 132nd clock pulse and the next SI pulse, a minimum time of 10µs is necessary for an effective S&H function. So the minimum integration time for the MLX90255AB MLX90255AB is 10µs. The AO is driven by a source follower that requires an external pulldown resistor. (typically 330ohm) After the nd 132 CLK pulse, the output becomes high impendance. The output is nominally 125mV for no light input and 2.4V for a nominal full-scale output. There is no cosine compensation: all 132 pixels have the same gain. The MLX90255 MLX90255 is intended for use in a wide variety of applications, including: image scanning, mark and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding. The MLX90255 MLX90255 is a replacement for the Texas Instruments' TSL1301 TSL1301 and TSL1401 TSL1401 parts. Timing Waveform CLK minimal 10µs SI Internal reset 132 Clock Cycles integration Not Integrating Integrating 2+128+2 clock cycles high impedance AO MLX90255AA MLX90255AA Optical Array Page 2 March 2000 2. ABSOLUTE MAXIMUM RATINGS Supply Voltage, Vdd Digital input current range Operating free-air temperature range, Ta +7V -20 to 20 mA -40degC to +125degC (automotive compliant optical package) -40degC to +125degC 260degC Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3. ELECTRICAL CHARACTERISTICS Characteristics Limits Min Supply voltage Vdd Input voltage, Vi High-level input voltage, Vih Low-level input voltage, Vil Wavelength of light source Clock frequency, Fclock Sensor integration time below 60degC, Tint (1) Sensor integration time full Temperature range, Tint (2) Pixel Charge Transfer Time (full Temp range), Tqt Setup time, serial input, Tsu(si) Hold time, serial input, Th(si) (3) Operating free-air temperature, Tamb Clock Pulse Duration (high), Tw (H) Clock Pulse Duration (low), Tw (L) 4.5 0 Vdd*0.7 0 400 5 0.01 0.01 8 100 20 -40 320 320 Unit Typ Max 5 5.5 Vdd Vdd Vdd*0.3 1000 1000 100 2 +125 V V V V nm kHz ms ms µs ns ns DegC ns ns (1): we reset till clock pulse 132 (on declining flank) minimum integration time = (132 ­ 132)*CLK period + 10 µs (this is the time the S&H cap need to follow) the minimum integration time becomes 0.01ms, independent of clock speed (2): at 125degC, the integration time should be limited to 2ms (3): the SI pulse must go low before the rising edge of the next clock pulse MLX90255AA MLX90255AA Optical Array Page 3 March 2000 Typical Waveforms 2 All tests are made with 3.5ms integration time, at 10µW/cm light = 100% at 25°C at 880 nm and with a clock speed of 500kHz in, and 250kHz out, unless otherwise specified in the Test Conditions. Parameter Test Conditions Average Analogue Output VaoLight Average Analogue Output Initial offset Average Analogue Output VaoDark Highest Dark Pixel Vaodarkmax Non Linearity Pixel Response Non Uniformity (1) Pixel Interaction Test Noise Level Nlao1 PRNU Hold Spec, same as PRNU PRNUH Output Settling Time Ts Array Lag Alag Dark Signal Non Uniformity DSNU PIT Vn Analogue Output Saturation Change in Sensitivity with Temperature at 880nm (2) Operating Free Temp. Supply Current Min Typ Max Unit At 25 °C 100% light At 25 °C 0% light At 125 °C 0% light At 125 °C at 0.25ms SI At 25 °C At all Temp 100% light At 25 °C At 25 °C 2.2 2.4 2.6 V 0 0.10 0.2 V 0 0.35 1.0 V 0.8 V + 1.2% + 8.5% FS FS At all Temp 100% light at 62.5 kHz At all Temp At all SI At 25 °C at 0.5ms At 25 °C At 125 °C At 25 °C At 125 °C + 0.5% + 3.0% 5% 2 6 + 4.0% + 8.5% FS mV (RMS) FS 450 750 ns 0.5% 60 0 -40 Idd 5 FS 120 440 3.0 3.0 0.8 %/°C +125 8 °C mA (1) The 90255AB 90255AB has no cosine shaped gain: all pixels have the same gain (2) See description of test methods => VaoLight at 125degC must be between 4uW and 12.5uW MLX90255AA MLX90255AA Optical Array Page 4 March 2000 mV mV V Typical Photodiode spectral responsivity curve (%), without the Anti Reflection Coating There is also an option for an Anti Reflection Coating. This will remove the interference ripples in the figure above. MLX90255AA MLX90255AA Optical Array Page 5 March 2000 4. MECHANICAL INFORMATION & PINOUT 4.1. GLP5-package MLX90255AA MLX90255AA Optical Array Page 6 March 2000 GLP5 package pinout Pin Symbol Description Number 1 2 3 4 5 SI CLK AO Vdd Vss Serial input. SI defines the start of the data-out sequence Clock. The clock controls charge transfer, pixel output and reset (together with SI) Analog output Supply voltage. Supply voltage for both analog and digital circuits Ground (substrate). All voltages are referenced to the substrate. GLP5 leadframe MLX90255AA MLX90255AA Optical Array Page 7 March 2000 4.2. SMD8-package MLX90255AA MLX90255AA Optical Array Page 8 March 2000 SMD8 package pinout Pin Nr. Symbol Description 1 2 3 4 5 6 7 8 SI CLK AO Vdd Vss Vss Vss Vss Serial input. SI defines the start of the data-out sequence Clock. The clock controls charge transfer, pixel output and reset (together with SI) Analog output Supply voltage. Supply voltage for both analog and digital circuits Ground (substrate). All voltages are referenced to the substrate. Ground (substrate). All voltages are referenced to the substrate. Ground (substrate). All voltages are referenced to the substrate. Ground (substrate). All voltages are referenced to the substrate. Note: all 4 Vss pins are internally connected to form a large ground plane to get better EMC characteristics. MLX90255AA MLX90255AA Optical Array Page 9 March 2000 SMD8 leadframe Sam Maddalena Copyright © 2000 Melexis. All rights reserved. Revised: March, 2000 MLX90255AA MLX90255AA Optical Array 2000 Page 10 March