TSC2117 SLAS550A 48-QFN P1/R33 P0/R116 P0/R65 P1/R38 P1/R42 P1/R32 P1/R43 - Datasheet Archive

 

Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller

 

TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 1 INTRODUCTION 1.1 Features · · · · · · · · · · · · · · · · · · · · · · Low-Power 13-mW Stereo 48-kHz Playback Stereo Audio DAC and Monaural ADC Support 8-kHz to 192-kHz Sample Rates Instruction-Programmable miniDSP Available for Record and Playback Paths Bass Boost/Treble/EQ With up to Five Biquads for Record and up to Six Biquads for Playback Stereo 1.29-W Class-D BTL 8- Speaker Driver With Direct Battery Connection Smart Four-Wire Touch-Screen Controller With Autonomous Timing Programmable-Gain Amplifiers Microphone Bias Hardware-Implemented AGC Used With Microphone Input for Audio ADC Path Digital Microphone Interface Digital Mixing Capability Pin Control or Register Control for Digital-Playback Volume-Control Settings Programmable 12-Bit SAR ADC Built-In Capability for Temperature, Battery, or Auxiliary Measurements Programmable DRC for Digital Playback Sine-Wave Generator for Beep Generator for Touch-Pad Press Acknowledgement Integrated PLL Used for Programmable Digital Audio Processor SPI, I2C, and I2S Serial Interfaces SPI , I2C Have Register Auto-Increment Full Power-Down Control Power Supplies: ­ Analog: 2.7 V­3.6 V ­ Digital Core: 1.65 V­1.95 V ­ Digital I/O: 1.1 V­3.6 V ­ Class-D: 2.7 V­5.5 V (SLVDD and SRVDD AVDD) 7-mm × 7-mm 48-QFN 48-QFN Package 1.2 Applications · · · Portable Gaming Devices Mobile Internet Devices Adaptive Filtering Applications 1.3 Description The TSC2117 TSC2117 is a low-power, highly integrated, high-performance codec and touch-screen controller which features stereo class-D speaker amplifiers, a stereo audio DAC, mono audio ADC, and a SAR ADC. The TSC2117 TSC2117 supports 16-bit stereo playback and monaural record functionality. The device integrates several analog features, such as a microphone interface, headphone drivers, and speaker drivers. The TSC2117 TSC2117 has two fully programmable miniDSPs for digital audio processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ are supported by the preprogrammed modes of the programmable digital signal-processing block. An on-chip PLL provides the high-speed clock needed by the digital signal-processing block. The volume level can be controlled by either a pin control or by register control. The TSC2117 TSC2117 has a 12-bit converter that supports a four-wire resistive touch-screen complete with drivers. All functions can be controlled by an I2C or SPI interface. A programmable beep generator is included. An on-chip processor is used in the touch-screen mode and provides extensive features specifically designed to reduce the host-processor and interface-bus overhead. The TSC2117 TSC2117 has three dedicated analog inputs for system voltage measurements, with an on-chip temperature sensor that can be read by the SAR ADC, and is available in a 7-mm × 7-mm 48-pin QFN package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PurePath is a trademark of Texas Instruments. MATLAB is a trademark of The MathWorks, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009­2009, Texas Instruments Incorporated TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 SLVDD www.ti.com SRVDD SLVSS SRVSS 2 V/2.5 V/AVDD MICBIAS P1/R33 P1/R33­R34 P0/R116 P0/R116 7-Bit ADC VOL/ MICDET HVSS HVDD AVSS AVDD De-Pop and SoftStart Audio Output Stage Power Management Left and Right VolumeControl Register RC CLK GPIO1 GPIO2 P0/R65 P0/R65­R66 Analog Attenuation 0 dB to ­78 dB and Mute (0.5-dB Steps / Nonlinear) P1/R38 P1/R38 MIX_L Class-D Speaker Driver P1/R42 P1/R42 SPLP SPLN P1/R32 P1/R32 6 dB to 24 dB (6-dB Steps) P1/R43 P1/R43 P1/R39 P1/R39 SPRP SPRN GPIO Note: All functions are controllable via MIX_R 2 2 I C I C or SPI. It is not recommended to 2 P1/R30 P1/R30 SDA SCL SS use both I C and SPI simultaneously. Analog Attenuation 0 dB to ­78 dB and Mute (0.5-dB Steps / Nonlinear) P1/R36 P1/R36 MIX_L Class A/B Headphone/Lineout Driver P1/R40 P1/R40 GPI1 GPI2 GPI3 SPI SCLK MOSI MISO HPL P1/R31 P1/R31 P1/R44 P1/R44 0 dB to 9 dB (1-dB Steps) P1/R41 P1/R41 P1/R37 P1/R37 Note: Normally, MCLK is PLL input; however, BCLK, GPIO1, etc., can also be PLL input. MIX_R HPR MIX_R MIX_L PLL MCLK MIC2_LINE_L S DAC_L D-S DAC S S AUX1_MIC3_LINE_R S DAC_R D-S DAC Prog DSP Engine Digital Vol 24 dB to Mute P1/R35 P1/R35 S P0/R71 P0/R71 P0/R72 P0/R72 MIC AUX2_MIC1 S AUX1_MIC3_LINE_R P1/R48 P1/R48 Selectable Gain/Input Impedance Selectable Gain/Input Impedance Digital Vol ­12.20 dB Step = 0.5 dB SDOUT WCLK SDIN BCLK Prog DSP Engine P0/R86 P0/R86­R93 AGC S VCOM Data Note: Digital Mic Clock and Data routed to GPIO1 and GPIO2 pins. P0/R51 P0/R51­R52 Digtal Mic Interface P1/R49 P1/R49 Divider TSVDD P3/R4­R5 RESET MCLK RC CLK TouchPanel Drivers SAR_Mode P3/R17 P3/R17 P3/R2­R3 AUX1 TouchScreen Processing SAR ADC AUX2 VBAT D-S ADC Clock AUX2_MIC1 P3/R15 P3/R15­R16 Digital Beep Generator 2 to ­61 dB P1/R47 P1/R47 (1-dB Steps) 0 to 59.5 dB (0.5-dB steps) Mono ADC P0/R82 P0/R82­R83 MIC2_LINE_L XP YP XN YN Digital Audio Processing and Serial Interface S P0/R64 P0/R64 Digital Vol Ctl Input CM P1/R50 P1/R50 P0/R63 P0/R63 Reference ÷5 VREF (Internal) P3/R6 TSVDD TSVSS VREF Control Interface FIFO OSC RC CLK DVDD DVSS P3/R13 P3/R13 IOVDD IOVSS B0205-04 B0205-04 Figure 1-1. Functional Block Diagram 2 INTRODUCTION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE This data manual is designed using PDF document-viewing features that allow quick access to information. For example, performing a global search on, e.g., "page 0/register 15" produces all references to this page and register in a list. This makes is easy to traverse the list and find all information related to a page and register. Note that the search string must be of the indicated format. Also, this document includes document hyperlinks to allow the user to quickly find a document reference. To come back to the original page, click the green left arrow near the PDF page number at the bottom of the file. The hot-key for this function is alt-left arrow on the keyboard. Another way to find information quickly is to use the PDF bookmarks. 2 PACKAGE AND SIGNAL DESCRIPTIONS Package/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TSC2117 TSC2117 QFN-48 QFN-48 RGZ ­40°C to 85°C Submit Documentation Feedback ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TSC2117IRGZT TSC2117IRGZT Tape and reel, 250 TSC2117IRGZR TSC2117IRGZR Tape and reel, 2500 PACKAGE AND SIGNAL DESCRIPTIONS 3 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 2.1 Device Information 37 SPRN 38 SRVDD 39 SRVSS 40 SPRP 41 HPL 42 HVDD 43 HVSS 44 HPR 45 GPI3 46 GPI2 47 GPI1 48 RESET RGZ Package (Top View) MISO 1 36 SPLP MOSI 2 35 SLVDD SS 3 34 SLVSS SCLK 4 33 SPLN GPIO1 5 32 TSVDD GPIO2 6 31 XP TSC2117 TSC2117 IOVSS 7 30 YP IOVDD 8 29 DVSS DVDD 9 28 XN SDOUT 10 27 YN SDIN 11 26 TSVSS WCLK 12 VBAT 24 AVDD 23 AVSS 22 AUX2 21 AUX1 20 MIC 19 MICBIAS 18 VOL/MICDET 17 SCL 16 SDA 15 MCLK 14 BCLK 13 25 VREF P0023-17 P0023-17 Table 2-1. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AUX1 20 I AUX1 (primary aux. input to SAR ADC), also routed to audio ADC input mixer and audio DAC output mixer AUX2 21 I AUX2 (secondary aux. input to SAR ADC), also routed to audio ADC input mixer AVDD 23 ­ Analog power supply AVSS 22 ­ Analog ground BCLK 13 I/O DVDD 9 ­ Digital power ­ digital core DVSS 29 ­ Digital ground (internally connected to HVSS) GPI1 47 I General-purpose input and multifunction pin GPI2 46 I General-purpose input and multifunction pin GPI3 45 I General-purpose input and multifunction pin GPIO1 5 I/O General-purpose input/output pin and multifunction pin GPIO2 6 I/O General-purpose input/output pin and multifunction pin HPL 41 O Left-channel headphone driver output HPR 44 O Right-channel headphone driver output HVDD 42 ­ Headphone driver and PLL power 4 Audio serial clock PACKAGE AND SIGNAL DESCRIPTIONS Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 Table 2-1. TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. HVSS 43 ­ Driver and PLL ground (internally connected to DVSS) IOVDD 8 ­ Digital interface power IOVSS 7 ­ Digital interface ground MCLK 14 I External master clock MIC 19 I Microphone input (routed to audio ADC input mixer and audio DAC output mixer) MICBIAS 18 O Microphone bias voltage MISO 1 O Data output from SPI (Hi-Z capable) MOSI 2 I Data input to SPI RESET 48 I Reset for logic and all internal registers ­ active-low SCL 16 I/O SCLK 4 I SDA 15 I/O SDIN 11 I Playback audio serial-data input SDOUT 10 O Record audio serial-data output (hi-Z capable) SLVDD 35 ­ Left-channel class-D speaker-amplifier power supply SLVSS 34 ­ Left-channel class-D speaker-amplifier power-supply ground SPLN 33 O Left-channel speaker-driver inverting output SPLP 36 O Left-channel speaker-driver noninverting output SPRN 37 O Right-channel speaker-driver inverting output SPRP 40 O Right-channel speaker-driver noninverting output SRVDD 38 ­ Right-channel class-D speaker-amplifier power supply SRVSS 39 ­ Right-channel class-D speaker-amplifier power-supply ground SS 3 I SPI chip select ­ active-low TSVDD 32 ­ Touch-screen controller power (used for touch-screen panel driver) TSVSS 26 ­ Touch-screen driver ground VBAT 24 I Battery-monitor input to SAR ADC VOL/MICDET 17 I Playback digital volume control or microphone-detection functionality VREF 25 I/O Voltage reference input for SAR ADC WCLK 12 I/O Audio serial-bus channel clock XN 28 I/O Touch-screen X­ positional input and driver XP 31 I/O Touch-screen X+ positional input and driver YN 27 I/O Touch-screen Y­ positional input and driver YP 30 I/O Touch-screen Y+ positional input and driver Submit Documentation Feedback I2C control bus clock input External clock to SPI I2C control-bus data I/O PACKAGE AND SIGNAL DESCRIPTIONS 5 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 3 ELECTRICAL SPECIFICATIONS 3.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT AVDD to AVSS ­0.3 to 3.9 V DVDD to DVSS ­0.3 to 2.5 V HVDD to HVSS ­0.3 to 3.9 V ­0.3 to 6 V SLVDD to SLVSS SRVDD to SRVSS ­0.3 to 6 V IOVDD to IOVSS ­0.3 to 3.9 V TSVDD to TSVSS ­0.3 to 3.9 V VREF to AVSS AVSS ­ 0.3 to AVDD V Digital input voltage IOVSS ­ 0.3 to IOVDD + 0.3 V Analog input voltage AVSS ­ 0.3 to AVDD + 0.3 V ­0.3 to 6 V Operating temperature range ­40 to 85 °C Storage temperature range ­55 to 150 °C 105 °C VBAT Junction temperature (TJ Max) Power dissipation Lead temperature (1) (TJ Max ­ TA)/RJA W RJA Thermal impedance (with thermal pad soldered to board) QFN package 27 °C/W Infrared (15 s) 300 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 3-1. System Thermal Characteristics (1) Power Rating at 25°C 6 Power Rating at 70°C Power Rating at 85°C 3W (1) Derating Factor 37.04 mW/°C 1.3 W 0.74 W This data was taken using 2-oz. (0.071-mm thick) trace and copper pad that is soldered to a JEDEC high-K, standard 4-layer 3-in. × 3 in. (7.62-cm × 7.62-cm) PCB. ELECTRICAL SPECIFICATIONS Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com 3.2 SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN AVDD 2.7 3.3 3.6 1.65 1.8 1.95 Referenced to HVSS(2) 2.7 3.3 3.6 Referenced to AVSS DVDD HVDD MAX (2) Referenced to SLVSS 2.7 Referenced to SRVSS(2) 2.7 5.5 TSVDD Referenced to TSVSS(2) 2.7 3.3 IOVDD (2) UNIT 5.5 SRVDD (1) SLVDD (1) NOM (2) Referenced to DVSS(2) (1) Power-supply voltage range 3.6 AVDD Resistance applied across class-D output pins (BTL) 8 AC coupled to RL 16 AVDD = 3.3V, single-ended Stereo line output load impedance SCLK 3.3 Analog audio full-scale input voltage MCLK 3.6 0 Headphone impedance AC coupled to RL Master clock frequency IOVDD = 3.3V 50 MHz SCLK frequency (3) 3.3 Referenced to AVSS(2) Speaker impedance VI 1.1 External voltage reference VREF Referenced to IOVSS V IOVDD = 3.3V 30 MHz SCLK duty cycle 0.707 Operating free-air temperature 50% SCL clock frequency TA (1) (2) (3) 3.3 VRMS 10 40% SCL V k 60% 400 kHz 85 ­40 °C To minimize battery-current leakage, the SLVDD and SRVDD voltage levels should not be below the AVDD voltage level. All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground signals. By use of a wide trace or ground plane, ensure a low-impedance connection between HVSS and DVSS. The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock. Electrical Characteristics At 25°C, AVDD, HVDD, IOVDD, TSVDD, = 3.3 V, SLVDD, SRVDD = 3.6V, DVDD = 1.8 V, VREF = 3.3 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, SAR input is AUX1, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SAR CONVERTER Auxilary Analog Input Input voltage range Input impedance (1) Input capacitance 0 (1) pF µA 1 Battery-measurement mode V k 25 Input leakage current Input voltage range for VBAT VREF 1/(f×C) AUX1, AUX2, VBAT input selected as input by touch screen 0 6 V SAR input impedance is dependent on the sampling frequency, where the sampling capacitor is C = 25 pF. Submit Documentation Feedback ELECTRICAL SPECIFICATIONS 7 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD, HVDD, IOVDD, TSVDD, = 3.3 V, SLVDD, SRVDD = 3.6V, DVDD = 1.8 V, VREF = 3.3 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, SAR input is AUX1, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Touch-Screen SAR ADC Resolution 12-bit resolution 11 Bits Integral nonlinearity 12-bit resolution, conversion clock = 2 MHz ±7 LSB Offset error 12-bit resolution, conversion clock = 2 MHz ±7 LSB Gain error 12-bit resolution, conversion clock = 2 MHz ±7 LSB Noise INL Programmable: 8-bit, 10-bit, 12-bit No missing codes 8 12 Bits 12-bit resolution, conversion clock = 2 MHz, AUX2 = 1 Vdc 0.8 LSB Conversion Rate Normal conversion operation 12 bits, internal conversion clock = 2 MHz 119 kHz High-speed conversion operation 8 bits, internal conversion clock = 6 MHz (Conversion accuracy is reduced.) 250 kHz Voltage Reference-VREF Voltage range Internal VREF output voltage Internal VREF 1.25 2.5 External VREF 1.25 AVDD Measured with 1-µF capacitor to analog ground. Internal VREF selected as 1.25 V (page 3/register 6, bit D6 = 0) V 1.23 V 8.2 MHz INTERNAL OSCILLATOR-RC_CLK Oscillator frequency for SAR VOLUME CONTROL PIN (ADC); VOL/MICDET pin enabled Input voltage range VOL/MICDET pin configured as volume control (page 0/register 116, bit D7 = 1 and page 0/register 67, bit D7 = 0) 0.5 × AVDD 0 Input capacitance 2 Volume control steps V pF 128 Steps 0.707 VRMS AUDIO ADC Microphone Input to ADC, 984-Hz Sine-Wave Input, fS = 48 kHz, AGC = OFF Input signal level (0-dB) MIC with R1 = 20 k (page 1/register 48 and register 49, bits D7­D6) Signal-to-noise ratio fS = 48 kHz, 0-dB PGA gain, MIC input ac-shorted to ground; measured as idle-channel noise, A-weighted (1) (2) Dynamic range THD+N THD SNR (2) 8 90 dB fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at ­60-dBFS input applied, referenced to 0.707-Vrms input, A-weighted (1) (2) 91 dB Total harmonic distortion + noise fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at ­2 dBFS input applied, referenced to 0.707 Vrms input ­83 Total harmonic distortion fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at ­2 dBFS input applied, referenced to 0.707 Vrms input ­90 dB Input capacitance (1) 80 MIC input 2 pF ­70 dB Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. ELECTRICAL SPECIFICATIONS Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 Electrical Characteristics (continued) At 25°C, AVDD, HVDD, IOVDD, TSVDD, = 3.3 V, SLVDD, SRVDD = 3.6V, DVDD = 1.8 V, VREF = 3.3 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, SAR input is AUX1, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.25 2.5 2.75 UNIT Microphone Bias Voltage output Voltage regulation Page 1/register 46, bits D1­D0 = 10 Page 1/register 46, bits D1­D0 = 01 2 At 4-mA load current, page 1/register 46, bits D1­D0 = 10 (MICBIAS = 2.5 V) 5 At 4-mA load current, page 1/register 46, bits D1­D0 = 01 (MICBIAS = 2 V) V 7 mV Audio ADC Digital Decimation Filter Characteristics See Section 5.5.4.4 for audio ADC decimation filter characteristics. DAC HEADPHONE OUTPUT, AC-coupled load = 16 (single-ended), driver gain = 0 dB, parasitic capacitance = 30 pF Full-scale output voltage (0 dB) Output common-mode setting = 1.65 V 0.707 (1) (2) SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted THD Total harmonic distortion 0-dBFS input ­85 ­65 dB THD+N Total harmonic distortion + noise 0-dBFS input ­82 ­60 dB Mute attenuation PSRR Power-supply rejection ratio (3) PO Maximum output power 80 Vrms 95 dB 87 dB Ripple on HVDD (3.3 V) = 200 mVp-p at 1 kHz 62 dB RL = 32 , THD+N ­60 dB 20 RL = 16 , THD+N ­60 dB 60 mW DAC LINEOUT (HP Driver in Lineout Mode) SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted 95 dB THD Total harmonic distortion 0-dBFS input, 0-dB gain ­86 dB THD+N Total harmonic distortion + noise 0-dBFS input, 0-dB gain ­82 dB DAC Digital Interpolation Filter Characteristics See Section 5.6.1.4 for DAC interpolation filter characteristics. DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8 (differential), 50 pF 2.2 SLVDD = SRVDD = 3.6 V, BTL measurement, DAC input = ­2 dBFS, DAC VCM (page 1/register 31, bits D4­D3) = 1.65 V, class-D gain = 6 dB, THD ­20 dB Output voltage SLVDD = SRVDD = 3.6 V, BTL measurement, DAC input = 0 dBFS, DAC VCM (page 1/register 31, bits D4­D3) = 1.65 V, class-D gain = 6 dB, THD ­16.5 dB 2.1 Output, common-mode SNR (1) (2) (3) SLVDD = SRVDD = 3.6 V, BTL measurement, DAC input = mute, DAC VCM (page 1/register 31, bits D4­D3) = 1.65 V, class-D gain = 6 dB Signal-to-noise ratio SLVDD = SRVDD = 3.6 V, BTL measurement, class-D gain = 6 dB, measured as idle-channel noise, A-weighted (with respect to full-scale output value of 2.2 Vrms) (1) (2) Vrms 1.65 V 87 dB Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. é VSIGSupp ù PSRR = 20 log10 ê ú ê VDACOUT ú ë û DAC to headphone-out PSRR measurement is calculated as Submit Documentation Feedback ELECTRICAL SPECIFICATIONS 9 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD, HVDD, IOVDD, TSVDD, = 3.3 V, SLVDD, SRVDD = 3.6V, DVDD = 1.8 V, VREF = 3.3 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, SAR input is AUX1, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8 (differential), 50 pF (continued) THD Total harmonic distortion SLVDD = SRVDD = 3.6 V, BTL measurement, DAC input = ­6 dBFS, DAC VCM (page 1/register 31, bits D4­D3) = 1.65 V, class-D gain = 6 dB ­72 dB THD+N Total harmonic distortion + noise SLVDD = SRVDD = 3.6 V, BTL measurement, DAC input = ­6 dBFS, DAC VCM (page 1/register 31, bits D4­D3) = 1.65 V, class-D gain = 6 dB ­71 dB PSRR Power-supply rejection ratio (1) SLVDD = SRVDD = 3.6 V, BTL measurement, ripple on SLVDD/SRVDD = 200 mVp-p at 1 kHz 57 dB 110 dB Mute attenuation SLVDD = SRVDD = 3.6 V, BTL measurement, DAC VCM (page 1/register 31, bits D4­D3) = 1.65 V, class-D gain = 18 dB, THD = 10% Maximum output power Output-stage leakage current for direct battery connection SLVDD = SRVDD = 4.3 V, BTL measurement, DAC VCM (page 1/register 31, bits D4­D3) = 1.65 V, class-D gain = 18 dB, THD = 10% 790 SLVDD = SRVDD = 5.5 V, BTL measurement, DAC VCM (page 1/register 31, bits D4­D3) = 1.65 V, class-D gain = 18 dB, THD = 10% PO 540 1.29 W SLVDD = SRVDD = 4.3 V, device is powered down (power-up-reset condition) 80 nA mW ADC and DAC POWER CONSUMPTION For ADC and DAC power consumption based per selected processing block, see Section 5.4 DIGITAL INPUT/OUTPUT Logic family CMOS IIH = 5 µA, IOVDD 1.6 V VIL IOVDD IIL = 5 µA, IOVDD 1.6 V Logic level 0.7 × IOVDD IIH = 5 µA, IOVDD < 1.6 V VIH ­0.3 V 0.3 × IOVDD IIL = 5 µA, IOVDD < 1.6 V VOH 0.8 × IOVDD IOH = 2 TTL loads VOL IOL = 2 TTL loads Capacitive load (1) 10 DAC to speaker-out PSRR measurement is calculated as ELECTRICAL SPECIFICATIONS V 0.1 × IOVDD 10 PSRR + 20 log10 V 0 VSIG Supp V SPK12 SPK12 V pF . Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 3.4 Timing Characteristics 3.4.1 I2S/LJF/RJF Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK tr td(WS) BCLK td(DO-WS) tf td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-06 T0145-06 PARAMETER td(WS) td(DO-WS) td(DO-BCLK) ts(DI) th(DI) tr tf WCLK delay WCLK to DOUT delay (for LJF mode only) BCLK to DOUT delay SDIN setup SDIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 45 45 45 8 8 25 25 IOVDD = 3.3 V MIN MAX 20 20 20 6 6 10 10 UNITS ns ns ns ns ns ns ns Figure 3-1. I2S/LJF/RJF Timing in Master Mode Submit Documentation Feedback ELECTRICAL SPECIFICATIONS 11 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 3.4.2 www.ti.com I2S/LJF/RJF Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK tr th(WS) tH(BCLK) tS(WS) BCLK tL(BCLK) td(DO-WS) tf td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-07 T0145-07 PARAMETER tH(BCLK) tL(BCLK) ts(WS) th(WS) td(DO-WS) td(DO-BCLK) ts(DI) th(DI) tr tf BCLK high period BCLK low period WCLK setup WCLK hold WCLK to DOUT delay (for LJF mode only) BCLK to DOUT delay SDIN setup SDIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 35 35 8 8 45 45 8 8 4 4 IOVDD = 3.3 V MIN MAX 35 35 6 6 20 20 6 6 4 4 UNIT ns ns ns ns ns ns ns ns ns ns Figure 3-2. I2S/LJF/RJF Timing in Slave Mode 12 ELECTRICAL SPECIFICATIONS Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com 3.4.3 SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK td(WS) td(WS) tf BCLK tr td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-05 T0146-05 PARAMETER td(WS) td(DO-BCLK) ts(DI) th(DI) tr tf WCLK delay BCLK to DOUT delay SDIN setup SDIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 45 45 8 8 25 25 IOVDD = 3.3 V MIN MAX 20 20 8 8 10 10 UNITS ns ns ns ns ns ns Figure 3-3. DSP Timing in Master Mode Submit Documentation Feedback ELECTRICAL SPECIFICATIONS 13 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 3.4.4 www.ti.com DSP Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK tS(WS) tS(WS) th(WS) th(WS) tf tL(BCLK) BCLK tr td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-06 T0146-06 PARAMETER tH(BCLK) tL(BCLK) ts(WS) th(WS) td(DO-BCLK) ts(DI) th(DI) tr tf BCLK high period BCLK low period WCLK setup WCLK hold BCLK to DOUT delay SDIN setup SDIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 35 35 8 8 45 8 8 4 4 IOVDD = 3.3 V MIN MAX 35 35 8 8 20 8 8 4 4 UNITS ns ns ns ns ns ns ns ns ns Figure 3-4. DSP Timing in Slave Mode 14 ELECTRICAL SPECIFICATIONS Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com 3.4.5 SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 I2C Interface Timing All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. SDA tBUF tLOW tr tHIGH tf tHD;STA SCL tHD;STA tSU;DAT tHD;DAT STO tSU;STO tSU;STA STA STA STO T0295-02 T0295-02 PARAMETER fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time: For I2C bus devices Data set-up time SDA and SCL Rise Time SDA and SCL Fall Time Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Standard-Mode MIN TYP 0 4.0 MAX 100 4.7 4.0 4.7 0 250 Fast-Mode MIN TYP 0 0.8 UNITS MAX 400 µs µs µs 1.3 0.6 0.8 3.45 1000 300 4.0 4.7 400 kHz µs 300 300 µs ns ns ns µs µs 400 0 100 20 + 0.1Cb 20 + 0.1Cb 0.8 1.3 pF 0.9 Figure 3-5. I2C Interface Timing Submit Documentation Feedback ELECTRICAL SPECIFICATIONS 15 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 3.4.6 www.ti.com SPI Interface Timing All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. SS S t t Lead t Lag t td sck SCLK t wsck tf tr t wsck tv MISO t ho MSB OUT t dis BIT 6 . . . 1 LSB OUT ta t hi t su MOSI MSB IN PARAMETER twsck tLead tLag ttd ta tdis tsu thi tv tr tf SCLK pulse duration Enable lead time Enable lag time Sequential transfer delay MISO slave data-out access time MISO slave data-out disable time MOSI dataiin setup time MOSI data-in hold time MISO data-valid time SCLK rise time SCLK fall time BIT 6 . . . 1 IOVDD = 1.1 V MIN 50 50 50 40 LSB IN MAX IOVDD = 3.3 V MIN 20 20 20 20 40 40 15 15 MAX 20 20 10 10 25 4 4 18 4 4 UNITS ns ns ns ns ns ns ns ns ns ns ns Figure 3-6. SPI Interface Timing Diagram 16 ELECTRICAL SPECIFICATIONS Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 4 TYPICAL PERFORMANCE 4.1 Audio ADC Performance AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 AVDD = HVDD = TSVDD = IOVDD = SVDD = 3.3 V DVDD = 1.8 V -20 -40 Amplitude - dBFS -40 Amplitude - dBFS AVDD = HVDD = TSVDD = IOVDD = SVDD = 3.3 V DVDD = 1.8 V -20 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 5 10 15 20 0 5 f - Frequency - kHz 10 15 20 f - Frequency - kHz G018 G019 Figure 4-1. FFT - ADC Idle Channel Differential Figure 4-2. FFT- ADC Single-Ended Input AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 AVDD = HVDD = TSVDD = IOVDD = SVDD = 3.3 V DVDD = 1.8 V -20 -40 Amplitude - dBFS -40 Amplitude - dBFS AVDD = HVDD = TSVDD = IOVDD = SVDD = 3.3 V DVDD = 1.8 V -20 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 5 10 15 20 f - Frequency - kHz 0 5 10 15 20 f - Frequency - kHz G017 Figure 4-3. FFT - ADC Differential Input Submit Documentation Feedback G020 Figure 4-4. FFT - ADC Idle Channel Single-Ended TYPICAL PERFORMANCE 17 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com SNR vs PGA CHANNEL GAIN 100 95 Diff = 10k 90 Diff = 20k SNR - dB 85 80 Diff = 40k 75 SE = 10k 70 65 SE = 20k 60 55 SE = 40k 50 -10 0 10 20 30 40 50 60 70 Channel Gain - dB G022 Figure 4-5. 4.2 DAC Performance AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY -20 -40 -40 Amplitude - dBFS 0 -20 Amplitude - dBFS 0 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 5 10 15 20 f - Frequency - kHz 0 5 10 15 G023 Figure 4-6. FFT - DAC to Line Output 18 TYPICAL PERFORMANCE 20 f - Frequency - kHz G026 Figure 4-7. FFT - DAC to Headphone Output Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N - Total Harmonic Distortion + Noise - dB 0 RL = 16 HVDD = 2.7 V CM = 1.35 V -10 -20 -30 -40 HVDD = 3 V CM = 1.5 V -50 -60 HVDD = 3.3 V CM = 1.65 V -70 -80 HVDD = 3.6 V CM = 1.8 V -90 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 PO - Output Power - W G025 Figure 4-8. Headphone Output Power (RL = 16 ) 4.3 Class-D Speaker Driver Performance TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER -10 -20 0 THD+N - Total Harmonic Distortion + Noise - dB THD+N - Total Harmonic Distortion + Noise - dB 0 AVDD = HVDD = TSVDD = IOVDD = 3.3 V SVDD = 5.5 V DVDD = 1.8 V -30 12 dB -40 -50 -60 24 dB 18 dB -70 6 dB -80 0.0 0.5 1.0 1.5 PO - Output Power - W 2.0 G014 Figure 4-9. Max Class-D Speaker-Driver Output Power (RL = 8 , Driver Gain = 6 dB to 24 dB) Submit Documentation Feedback SLVDD = 3.3 V -10 -20 SLVDD = 3.6 V -30 -40 -50 SLVDD = 4.3 V -60 SLVDD = 5.5 V -70 -80 0.0 RL = 8 0.5 1.0 1.5 PO - Output Power - W 2.0 G015 Figure 4-10. Class-D Speaker-Driver Output Power (RL = 8 , SLVDD = 3.3 V to 5.5V, Driver Gain = 18 dB) TYPICAL PERFORMANCE 19 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 4.4 Analog Bypass Performance AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY -20 -40 -40 Amplitude - dBFS 0 -20 Amplitude - dBFS 0 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 5 10 15 20 0 5 f - Frequency - kHz 10 15 20 f - Frequency - kHz G024 G027 Figure 4-11. FFT - Line In Bypass to Line Output Figure 4-12. FFT - Line In Bypass to Headphone Output 4.5 MICBIAS Performance VOLTAGE vs CURRENT 3.5 3.0 Micbias = AVDD (3.3 V) V - Voltage - V 2.5 Micbias = 2.5 V 2.0 Micbias = 2 V 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I - Current - mA G016 Figure 4-13. Micbias 20 TYPICAL PERFORMANCE Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5 APPLICATION INFORMATION 5.1 Typical Circuit Configuration +3.3VA SVDD 0.1 mF 22 mF 0.1 mF 0.1 mF 22 mF SLVDD SRVDD 0.1 mF 10 mF 10 mF HVDD AVDD SLVSS SRVSS AVSS HVSS 8W GPIO1 SPLP SPLN GPIO2 Speakers GPI1 8W SPRP SPRN GPI2 GPI2 VOL/MICDET SDA 2.2 kW MICBIAS SCL 0.1 mF MCLK HPL Headset 47 mF HPR SDOUT TSC2117 TSC2117 WCLK SDIN HOST PROCESSOR MIC 47 mF BCLK 1 mF Analog_In1 AUX1 1 mF Analog_In2 RESET AUX2 System Battery SS SVDD Note: VBAT is used for voltage measurement. Touch Screen SCLK VBAT MOSI MISO XP YP XN YN 2 4 ´ 0.1 mF TSVDD TSVSS VREF +3.3VA DVSS +1.8VD 10 mF 0.1 mF DVDD 10 mF 0.1 mF IOVDD IOVSS IOVDD 10 mF 0.1 mF Note: Either I C or SPI or both can be used in any mode. It is not recommended to 2 use I C and SPI simultaneously. 10 mF Note: VREF can also be supplied externally. S0400-01 S0400-01 Figure 5-1. Typical Circuit Configuration Submit Documentation Feedback APPLICATION INFORMATION 21 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 5.2 Overview The TSC2117 TSC2117 is a highly integrated stereo audio DAC and monaural ADC with touch-screen controller for portable computing, communication, and entertainment applications. A register-based architecture eases integration with microprocessor-based systems through standard serial-interface buses. This device supports the four-wire SPI bus and the 2-wire I2C bus interfaces. The I2C interface and the SPI interface provide full register access. The SPI data bus can be used for higher-speed communication and for high-speed retrieval of SAR ADC data. All peripheral functions are controlled through these registers and the onboard state machines. The TSC2117 TSC2117 consists of the following blocks: · Touch-panel drivers · Microphone interfaces (analog and digital) · Audio codec (mono ADC and stereo DAC) · AGC and DRC · Two miniDSP digital signal-processing blocks (record and playback paths) · Beep generator · Stereo headphone/lineout amplifier · Class-D stereo amplifier for 8- speakers · Pin-controlled or register-controlled volume level · Power-down de-pop and power-up soft start · SAR ADC for touch-panel, voltage, and temperature measurements · FIFO buffer mode for SAR auxiliary and touch-screen data · Auxiliary inputs · SPI control interface · I2C control interface · Power-down control block Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The SPI or I2C interface can be used to write to the control registers to configure the device. The I2C address assigned to the TSC2117 TSC2117 is 001 1000. This device always operates in an I2C slave mode. All registers are 8-bit, and all writable registers have read-back capability. The device auto-increments to support sequential addressing and can be used with I2C fast mode. Once the device is reset, all appropriate registers are updated by the host processor to configure the device as needed by the user. SAR ADC data is transferred though the SPI/I2C bus, and audio data (for audio ADC and DAC) is transferred through the audio serial interface. The SPI interface requires that the SS signal be driven low to communicate with the TSC2117 TSC2117. Data is then shifted into or out of the TSC2117 TSC2117 under control of the host microprocessor, which also provides the SPI serial clock. 5.2.1 Device Initialization 5.2.1.1 Reset The TSC2117 TSC2117 internal logic must be initialized to a known condition for proper device function. To initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up. It is recommended that while the DVDD supply is being powered up, the RESET pin be pulled low. The device can also be reset via software reset. Writing a 1 into page 0/register 1, bit D0 resets the device. 22 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.2.1.2 Device Start-Up Lockout Times After the TSC2117 TSC2117 is initialized through hardware reset at power-up or software reset, the internal memories are initialized to default values. This initialization takes place within 1 ms after pulling the RESET signal high. During this initialization phase, no register-read or register-write operation should be performed on ADC or DAC coefficient buffers. Also, no block within the codec should be powered up during the initialization phase. 5.2.1.3 PLL Start-Up Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up command of the PLL and before the clocks are available to the codec. This delay is to ensure stable operation of the PLL and clock-divider logic. 5.2.1.4 Power-Stage Reset The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has occurred. Using this reset re-enables the output stage without resetting all of the registers in the device. Each of the four power stages has its own dedicated reset bit. The headphone power-stage reset is performed by setting page 1/register 31, bit D7 for HPL and by setting page 1/register 31, bit D6 for HPR. The speaker power-stage reset is performed by setting page 1/register 32, bit D7 for SPLP and SPLN, and by setting page 1/register 32, bit D6 for SPRP and SPRN. 5.2.1.5 Software Power Down By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit block can be controlled by writing to the appropriate control register. This approach allows the lowest power-supply current for the functionality required. However, when a block is powered down, all of the register settings are maintained as long as power is still being applied to the device. The TSC2117 TSC2117 touch-detection circuitry is enabled by default, and it can be powered down by writing to page 3/register 4, bit D7. 5.2.2 Audio Analog I/O The TSC2117 TSC2117 has a stereo audio DAC and a monaural ADC. It supports a wide range of analog interfaces to support different headsets and analog outputs. The TSC2117 TSC2117 has features to interface output drivers (8-, 16-, 32-) and a microphone PGA with AGC control. A special circuit has also been included in the TSC2117 TSC2117 to insert a short key-click sound into the stereo audio output. The key-click sound is used to provide feedback to the user when a particular button is pressed or item is selected. The specific sound of the keyclick can be adjusted by varying several register bits that control its frequency, duration, and amplitude. See Key-Click Functionality With Beep Generator, Section 5.6.5 5.3 miniDSP The TSC2117 TSC2117 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC; the second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP must be loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the ADC and on the DAC side, offering the possibility for advanced, very low-group-delay DSP algorithms. The ADC miniDSP has 384 programmable instructions, 256 data memory locations, and 128 programmable coefficients. The DAC miniDSP has 1024 programmable instructions, 896 data memory locations, and 512 programmable coefficients (in the adaptive mode, each bank has 256 programmable coefficients). Submit Documentation Feedback APPLICATION INFORMATION 23 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.3.1 www.ti.com Software Software development for the TSC2117 TSC2117 is supported through TI's comprehensive PurePathTM Studio software development environment, a powerful, easy-to-use tool designed specifically to simplify software development on Texas Instruments miniDSP audio platforms. The graphical development environment consists of a library of common audio functions that can be dragged and dropped into an audio signal flow and graphically connected together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse. See the TSC2117 TSC2117 product folder on www.ti.com to learn more about PurePath Studio and the latest status on available, ready-to-use DSP algorithms. 5.4 Digital Processing Low-Power Modes The TSC2117 TSC2117 device can be tuned to minimize power dissipation, to maximize performance, or to an operating point between the two extremes to best fit the application. The choice of processing blocks, PRB_P1 to PRB_P25 for stereo playback and PRB_R4 to PRB_R18 for mono recording, also influences the power consumption. In fact, the numerous processing blocks have been implemented to offer a choice among configurations having a different balance of power-optimization and signal-processing capabilities. 5.4.1 ADC, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V AOSR = 128, Processing Block = PRB_R4 (Decimation Filter A) Power consumption = 9.01 mW Table 5-1. PRB_R4 Alternative Processing Blocks, 9.01 mW Processing Block Filter Estimated Power Change (mW) PRB_R5 A 0.23 PRB_R6 A 0.22 AOSR = 64, Processing Block = PRB_R11 (Decimation Filter B) Power consumption = 7.99 mW Table 5-2. PRB_R11 Alternative Processing Blocks, 7.99 mW Processing Block Estimated Power Change (mW) PRB_R4 A 0.43 PRB_R5 A 0.67 PRB_R6 A 0.66 PRB_R10 B ­0.14 PRB_R12 5.4.2 Filter B 0.04 ADC, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V AOSR = 128, Processing Block = PRB_R4 (Decimation Filter A) Power consumption = 6.77 mW Table 5-3. PRB_R4 Alternative Processing Blocks, 6.77 mW Processing Block Estimated Power Change (mW) A 0.03 PRB_R6 24 Filter PRB_R5 A 0.03 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 AOSR = 64, Processing Block = PRB_R11 (Decimation Filter B) Power consumption = 6.61 mW Table 5-4. PRB_R11 Alternative Processing Blocks, 6.61 mW Processing Block Estimated Power Change (mW) A 0.07 PRB_R5 A 0.11 PRB_R6 A 0.11 PRB_R10 B ­0.02 PRB_R12 5.4.3 Filter PRB_R4 B 0.01 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HVDD = 3.3 V DOSR = 128, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 24.28 mW Table 5-5. PRB_P7 Alternative Processing Blocks, 24.28 mW Processing Block Filter Estimated Power Change (mW) PRB_P1 A 1.34 PRB_P2 A 2.86 PRB_P3 A 2.11 PRB_P8 B 1.18 PRB_P9 B 0.53 PRB_P10 B 1.89 PRB_P11 B 0.87 PRB_P23 A 1.48 PRB_P24 A 2.89 PRB_P25 A 3.23 DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 24.5 mW Table 5-6. PRB_P7 Alternative Processing Blocks, 24.5 mW Processing Block Filter Estimated Power Change (mW) PRB_P1 A 1.17 PRB_P2 A 2.62 PRB_P3 A 2 PRB_P8 B 0.99 PRB_P9 B 0.5 PRB_P10 B 1.46 PRB_P11 B 0.66 PRB_P23 A 1.43 PRB_P24 A 2.69 PRB_P25 A 2.92 Submit Documentation Feedback APPLICATION INFORMATION 25 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.4.4 www.ti.com DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HVDD = 3.3 V DOSR = 128, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 15.4 mW Table 5-7. PRB_P12 Alternative Processing Blocks, 15.4 mW Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.57 PRB_P5 A 1.48 PRB_P6 A 1.08 PRB_P13 B 0.56 PRB_P14 B 0.27 PRB_P15 B 0.89 PRB_P16 B 0.31 DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 15.54 mW Table 5-8. PRB_P12 Alternative Processing Blocks, 15.54 mW Processing Block Estimated Power Change (mW) PRB_P4 A 0.37 PRB_P5 A 1.23 PRB_P6 A 1.15 PRB_P13 B 0.43 PRB_P14 B 0.13 PRB_P15 B 0.85 PRB_P16 5.4.5 Filter B 0.21 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HVDD = 3.3 V DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 22.44 mW Table 5-9. PRB_P7 Alternative Processing Blocks, 22.44 mW Processing Block Filter Estimated Power Change (mW) PRB_P1 A 0.02 PRB_P2 A 0.31 PRB_P3 A 0.23 PRB_P8 B 0.28 PRB_P9 ­0.03 B 0.14 PRB_P11 B 0.05 PRB_P23 A 0.29 PRB_P24 A 0.26 PRB_P25 26 B PRB_P10 A 0.47 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 DOSR = 384, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 22.83 mW Table 5-10. PRB_P7 Alternative Processing Blocks, 22.83 mW Processing Block Estimated Power Change (mW) A 0.27 PRB_P2 A 0.4 PRB_P3 A 0.34 PRB_P8 B 0.2 PRB_P9 B 0.08 PRB_P10 B 0.24 PRB_P11 B 0.12 PRB_P23 A 0.23 PRB_P24 A 0.42 PRB_P25 5.4.6 Filter PRB_P1 A 0.46 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HVDD = 3.3 V DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 14.49 mW Table 5-11. PRB_P12 Alternative Processing Blocks, 14.49 mW Processing Block Filter Estimated Power Change (mW) PRB_P4 A ­0.04 PRB_P5 A 0.2 PRB_P6 A ­0.01 PRB_P13 B 0.1 PRB_P14 B 0.05 PRB_P15 B ­0.03 PRB_P16 B 0.07 DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 14.42 mW Table 5-12. PRB_P12 Alternative Processing Blocks, 14.42 mW Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.16 PRB_P5 A 0.3 PRB_P6 A 0.2 PRB_P13 B 0.15 PRB_P14 B 0.07 PRB_P15 B 0.18 PRB_P16 B 0.09 Submit Documentation Feedback APPLICATION INFORMATION 27 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.4.7 www.ti.com DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HVDD = 3.3 V DOSR = 32, Processing Block = PRB_P17 (Interpolation Filter C) Power consumption = 27.05 mW Table 5-13. PRB_P17 Alternative Processing Blocks, 27.05 mW Processing Block Estimated Power Change (mW) C 5.28 PRB_P19 5.4.8 Filter PRB_P18 C 1.98 DAC Playback on Line Out (10 k- load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.0 V, HVDD = 3.0 V DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 12.85 mW 5.5 Audio ADC and Analog Inputs 5.5.1 MICBIAS and Microphone Preamplifier The TSC2117 TSC2117 includes a microphone bias circuit which can source up to 4 mA of current, and is programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1/register 46, bits D1­D0. This functionality is shown in Table 5-14. Table 5-14. MICBIAS Settings D1 D0 0 0 MICBIAS output is powered down. FUNCTIONALITY 0 1 MICBIAS output is powered to 2 V. 1 0 MICBIAS output is powered to 2.5 V. 1 1 MICBIAS output is powered to AVDD. During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the model of microphone that is selected, optimal performance might be obtained at another setting, so the performance at a given setting should be verified. The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current consumption occurs when MICBIAS is set at AVDD. Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog anti-aliasing filtering are very relaxed. The TSC2117 TSC2117 integrates a second-order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides sufficient anti-aliasing filtering without requiring any external components. The MIC PGA supports analog gain control from from 0 dB to 59.5 dB in steps of 0.5 dB. These gain levels can be controlled by writing to page 1/register 47, bits D6­D0. The PGA gain changes are implemented with internal soft-stepping. This soft-stepping ensures that volume-control changes occur smoothly with no audible artifacts. On reset, the MIC PGA gain defaults to a mute condition, with soft stepping enabled. The ADC soft-stepping control can be enabled or disabled by writing to page 0/register 81, bits D1­D0. ADC soft-stepping timing is provided by the internal oscillator and internal divider logic block. 28 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 The input feed-forward resistance for the MIC input of the microphone PGA stage has three settings of 10 k, 20 k, and 40 k, which are controlled by writing to page 1/register 48, bits D7 and D6. The input feed-forward resistance value selected affects the gain of the microphone PGA. The ADC PGA gain for the MIC input depends on the setting of page1/registers 48 and 49, bits D7­D6. If D7­D6 are set to 01, then the ADC PGA has 6 dB more gain with respect to the value programmed using page 1/register 47. If D7­D6 are set to 10, then the ADC PGA has the same gain as programmed using page 1/register 47. If D7­D6 are set to 11, then the ADC PGA has 6 dB less gain with respect to the value programmed using page 1/register 47. The same gain scaling is also valid for the AUX1 and AUX2 input, based on the feed-forward resistance selected using page 1/register 48, bits D5­D2. The MIC PGA gain can be controlled either by an AGC loop or as a fixed gain. See Figure 1-1 for the various analog input routings to the MIC PGA that are supported in the single-ended and differential configurations. The AGC can be enabled by writing to page 0/register 86, bit D7. If the AGC is not enabled, then setting a fixed gain is done by writing to page 1/register 47, bits D6­D0. Because the TSC2117 TSC2117 supports soft-stepping gain changes, a read-only flag on page 0/register 36, bit D7 is set whenever the gain applied by PGA equals the desired value set by the gain register. The MIC PGA can be enabled by writing to page 1/register 47, bit D7. ADC muting can be done by writing to page 0/register 82, bit D7 and page 1/register 47, bit D7. Disabling the MIC PGA sets the gain to 0 dB. Muting the ADC causes the digital output to mute so that the output value remains fixed. When soft-stepping is enabled, the CODEC_CLKIN signal must stay active until after the ADC power-down register is written, in order to ensure that soft-stepping to mute has had time to complete. When the ADC POWER UP flag is no longer set, the CODEC_CLKIN signal can be shut down. 5.5.2 Automatic Gain Control (AGC) The TSC2117 TSC2117 includes automatic gain control (AGC) for the microphone input (MIC). AGC can be used to maintain nominally constant output-signal amplitude when recording speech signals. This circuitry automatically adjusts the MIC PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer to or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA applicable, that allow the algorithm to be fine-tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal. Because the gain can be changed at the sample interval time, the AGC algorithm operates at the ADC_fS clock rate. Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TSC2117 TSC2117 allows programming of eight different target levels, which can be programmed from ­5.5 dB to ­24 dB relative to a full-scale signal. Because the TSC2117 TSC2117 reacts to the signal absolute average and not to peak levels, it is recommended that the target level be set with enough margin to avoid clipping at the occurrence of loud sounds. An AGC low-pass filter is used to help determine the average level of the input signal. This average level is compared to the programmed detection levels in the AGC to provide the correct functionality. This low-pass filter is in the form of a first-order IIR filter. Programming this filter is done by writing to page 4/registers 2­7. Two 8-bit registers are used to form the 16-bit digital coefficient as shown on the register map. In this way, a total of six registers are programmed to form the three IIR coefficients. Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. Programming the attack time is done by writing to page 0/register 89, bits D7­D0. Decay time determines how quickly the PGA gain is increased when the input signal is too low. Programming the decay time is done by writing to page 0/register 90, bits D7­D0. Submit Documentation Feedback APPLICATION INFORMATION 29 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com Noise threshold is a reference level. If the input speech average value falls below the noise threshold, the AGC considers it as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the noise-threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise-threshold setting. This ensures that noise is not amplified in the absence of speech. The noise-threshold level in the AGC algorithm is programmable from ­30 dB to ­90 dB for the microphone input. When the AGC noise threshold is set to ­70 dB, ­80 db, or ­90 dB, the microphone input maximum PGA applicable setting must be greater than or equal to 11.5 dB, 21.5 dB, or 31.5 dB, respectively. This operation includes debounce and hysteresis to prevent the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise-threshold flag is set, the status of the gain applied by the AGC and the saturation flag should be ignored. Programming the noise debounce is done by writing to page 0/register 91, bits D4­D0. Programming the signal debounce is done by writing to page 0/register 92, bits D3­D0. Max PGA applicable allows the user to restrict maximum gain applied by AGC. This can be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold. Microphone input maximum PGA can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB. Programming the maximum PGA gain allowed by the AGC is done by writing to page 0/register 88, bits D6­D0. See Table 5-15 for various AGC programming options. AGC can be used only if the microphone input is routed to the ADC channel. Table 5-15. AGC Settings (1) CONTROL REGISTER BIT FUNCTION 36 D3 (Read-only) ADC saturation flag 45 D6 (Read-only) Signal to level setting of noise threshold 86 D7 AGC enable 86 D6­D4 Target level 87 D7­D6 Hysteresis 87 D5­D1 Noise threshold 88 D6­D0 Maximum PGA applicable 89 D7­D0 Time constants (attack time) 90 D7­D0 Time constants (decay time) 91 D4­D0 Debounce time (noise) 92 D3­D0 Debounce time (signal) 93 30 AGC saturation flag 39 (1) D5 (Read-only) D7­D0 (Read-only) Gain applied by AGC All registers shown in this table are located on page 0. APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 Input Signal Output Signal Target Level AGC Gain Decay Time Attack Time W0002-01 W0002-01 Figure 5-2. AGC Characteristics The AGC settings should be set based on user and system conditions, such as microphone selection and sensitivity, acoustics (plastics) around the microphone which affect the microphone pattern, expected distance and direction between microphone and sound source, acoustic background noise, etc. One example of AGC code follows, but actual use of code should be verified based on application usage. Note that the AGC code should be set up before powering up the ADC. ####################### AGC ENABLE EXAMPLE CODE ##################### ## Switch to Page-0 w 30 00 00 # Set AGC enable and Target Level = -10 dB # Target level can be set lower if clipping occurs during speech # Target level is adjusted considering Max Gain also w 30 56 A0 # AGC hysteresis=DISABLE, noise threshold = -90dB # Noise threshold should be set at higher level if noisy background is present in application w 30 57 FE # AGC maximum gain= 40 dB # Higher Max gain is a trade off between gaining up a low sensitivity MIC, and the background # acoustic noise # Microphone bias voltage (MICBIAS) level can be used to change the Microphone Sensitivity w 30 58 50 # Attack time=864/Fs w 30 59 68 # Decay time=22016/Fs w 30 5A A8 # Noise debounce 0 ms # Noise debounce time can be increased if needed w 30 5B 00 # Signal debounce 0 ms # Signal debounce time can be increased if needed w 30 5C 00 ######################## END of AGC SET UP ################################# Submit Documentation Feedback APPLICATION INFORMATION 31 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.5.3 www.ti.com Delta-Sigma ADC The analog-to-digital converter has a delta-sigma modulator with an oversampling ratio (AOSR) up to 128. The ADC can support a maximum output rate of 192 kHz. ADC power up is controlled by writing to page 0/register 81, bit D7. An ADC power-up condition can be verified by reading page 0/register 36, bit D6. 5.5.4 ADC Decimation Filtering and Signal Processing The TSC2117 TSC2117 ADC channel includes built-in digital decimation filters to process the oversampled data from the delta-sigma modulator to generate digital data at the Nyquist sampling rate with high dynamic range. The decimation filter can be chosen from three different types, depending on the required frequency response, group delay, and sampling rate. 5.5.4.1 ADC Processing Blocks The TSC2117 TSC2117 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied. The choices among these processing blocks allow the system designer to balance power conservation and signal-processing flexibility. Less signal-processing capability reduces the power consumed by the device. Table 5-16 gives an overview of the available processing blocks of the ADC channel and their properties. The Resource Class (RC) column gives an approximate indication of power consumption. The signal processing blocks available are: · First-order IIR · Scalable number of biquad filters · Variable-tap FIR filter · AGC The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in combination with various signal-processing effects such as audio effects and frequency shaping. The available first-order IIR, biquad, and FIR filters have fully user-programmable coefficients. Table 5-16. ADC Processing Blocks Processing Blocks Channel Decimation Filter 1st Order IIR Available Number BiQuads FIR Required AOSR Value Resource Class PRB_R4 Mono A Yes 0 No 128, 64 3 PRB_R5 Mono A Yes 5 No 128, 64 4 PRB_R6 Mono A Yes 0 25-tap 128, 64 4 PRB_R10 Mono B Yes 0 No 64 2 PRB_R11 Mono B Yes 3 No 64 2 PRB_R12 Mono B Yes 0 20-tap 64 2 PRB_R16 Mono C Yes 0 No 32 2 PRB_R17 Mono C Yes 5 No 32 2 PRB_R18 Mono C Yes 0 25-tap 32 2 32 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.5.4.2 ADC Processing Blocks ­ Signal Chain Details 5.5.4.2.1 First-Order IIR, AGC, Filter A From Delta-Sigma Modulator or Digital Microphone Filter A AGC Gain Compen Sation st 1 Order IIR ´ To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-3. Signal Chain for PRB_R4 5.5.4.2.2 Five Biquads, First-Order IIR, AGC, Filter A From Delta-Sigma Modulator or Digital Microphone HA Filter A HB HC HD HE st 1 Order IIR ´ AGC Gain Compen sation To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-4. Signal Chain for PRB_R5 5.5.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A From Delta-Sigma Modulator or Digital Microphone st Filter A ´ 25-Tap FIR 1 Order IIR AGC Gain Compen sation To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-5. Signal Chain for PRB_R6 5.5.4.2.4 First-Order IIR, AGC, Filter B From Delta-Sigma Modulator or Digital Microphone st Filter B ´ 1 Order IIR AGC Gain Compen sation To Audio Interface To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-6. Signal Chain for PRB_R10 Submit Documentation Feedback APPLICATION INFORMATION 33 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 5.5.4.2.5 Three Biquads, First-Order IIR, AGC, Filter B From Delta-Sigma Modulator or Digital Microphone Filter B HA HB HC AGC Gain Compen sation 1stOrder IIR ´ To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-7. Signal Chain for PRB_R11 5.5.4.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B From Delta-Sigma Modulator or Digital Microphone st 20-Tap FIR Filter B ´ 1 Order IIR AGC Gain Compen sation To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-8. Signal Chain for PRB_R12 5.5.4.2.7 First-Order IIR, AGC, Filter C From Delta-Sigma Modulator or Digital Microphone Filter C ´ st 1 Order IIR AGC Gain Compen sation To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-9. Signal Chain for PRB_R16 34 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.5.4.2.8 Five Biquads, First-Order IIR, AGC, Filter C From Delta-Sigma Modulator or Digital Microphone Filter C HA HB HC HD HE ´ st 1 Order IIR AGC Gain Compen sation To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-10. Signal Chain for PRB_R17 5.5.4.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C From Delta-Sigma Modulator or Digital Microphone st Filter C 25-Tap FIR ´ 1 Order IIR AGC Gain Compen sation To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-11. Signal Chain for PRB_R18 5.5.4.3 User-Programmable Filters Depending on the selected processing block, different types and orders of digital filtering are available. A first-order IIR filter is always available, and is useful to filter out possible dc components of the signal efficiently. Up to five biquad sections or, alternatively, FIR filters of up to 25 taps are available for specific processing blocks. The coefficients of the available filters are arranged as sequentially indexed coefficients. The coefficients of these filters are each 16 bits wide, in 2s-complement format, and occupy two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from ­1.0 (0x8000) to 0.999969482421875 (0x7FFF), as shown in Figure 5-12. 2 ­15 2 2 ­4 ­1 Bit Bit Largest Positive Number: = 0.111111111111111111 = 0.999969482421875 = 1.0 ­ 1 LSB Bit Largest Negative Number: = 1.000010000100001000 = 0x8000 = ­1.0 (by definition) Fraction Point Sign Bit S.xxxxxxxxxxxxxxxxxx Figure 5-12. 1.15 2s-Complement Coefficient Format Submit Documentation Feedback APPLICATION INFORMATION 35 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 5.5.4.3.1 First-Order IIR Section The transfer function for the first-order IIR filter is given by H(z) = N0 + N1z -1 215 - D1z -1 (5-1) The frequency response for the first-order IIR section with default coefficients is flat at a gain of 0 dB. Table 5-17. ADC First-Order IIR Filter Coefficients Filter Filter Coefficient ADC Coefficient Default (Reset) Values N0 Page 4/registers 8­9 0x7FFF (decimal 1.0 ­ LSB value) N1 Page 4/registers 10­11 0x0000 D1 First-order IIR Page 4/registers 12­13 0x0000 5.5.4.3.2 Biquad Section The transfer function of each of the biquad filters is given by H(z) = N0 + 2 ´ N1z -1 + N2 z -2 215 - 2 ´ D1z -1 - D2 z -2 (5-2) The default values for each biquad section yield an all-pass (flat) frequency response at a gain of 0 dB. Table 5-18. ADC Biquad Filter Coefficients Filter Coefficient RAM Location Filter Filter Coefficient Biquad A N0 Page 4/registers 14­15 0x7FFF (decimal 1.0 ­ LSB value) N1 Page 4/registers 16­17 0x0000 N2 Page 4/registers 18­19 0x0000 D1 Page 4/registers 20­21 0x0000 D2 Page 4/registers 22­23 0x0000 N0 Page 4/registers 24­25 0x7FFF (decimal 1.0 ­ LSB value) N1 Page 4/registers 26­27 0x0000 N2 Page 4/registers 28­29 0x0000 D1 Page 4/registers 30­31 0x0000 D2 Page 4/registers 32­33 0x0000 N0 Page 4/registers 34­35 0x7FFF (decimal 1.0 ­ LSB value) N1 Page 4/registers 36­37 0x0000 N2 Page 4/registers 38­39 0x0000 D1 Page 4/registers 40­41 0x0000 D2 Page 4/registers 42­43 0x0000 N0 Page 4/registers 44­45 0x7FFF (decimal 1.0 ­ LSB value) N1 Page 4/registers 46­47 0x0000 N2 Page 4/registers 48­49 0x0000 D1 Page 4/registers 50­51 0x0000 D2 Page 4/registers 52­53 0x0000 N0 Page 4/registers 54­55 0x7FFF (decimal 1.0 ­ LSB value) N1 Page 4/registers 56­57 0x0000 N2 Page 4/registers 58­59 0x0000 D1 Page 4/registers 60­61 0x0000 D2 Page 4/registers 62­63 0x0000 Biquad B Biquad C Biquad D Biquad E 36 APPLICATION INFORMATION Default (Reset) Values Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.5.4.3.3 FIR Section Three of the available ADC processing blocks offer FIR filters for signal processing. Processing block PRB_R12 features a 20-tap FIR filter, whereas the processing blocks PRB_R6 and PRB_R18 feature a 25-tap FIR filter. M H(z) = å FIRn z-n n =0 M = 24 for PRB _ R6, PRB _ R18 M = 19 for PRB _ R12 (5-3) The coefficients of the FIR filters are 16-bit 2s-complement format (2 bytes each) and correspond to the ADC coefficient space as listed in Table 5-19. Note that the default (reset) coefficients are not vaild for the FIR filter. When the FIR filter is used, all applicable coefficients must be reprogrammed by the user. To reprogram the FIR filter coefficients as an all-pass filter, write value 0x00 to page 4/registers 24, 25, 34, 35, 44, 45, 54, and 55. Table 5-19. ADC FIR Filter Coefficients Filter Coefficient FIlter Coefficient RAM Location Default (Reset) Values ­ Not Valid for the FIR Filter ­ Must Be Reprogrammed by User Fir0 Page 4/registers 14­15 0x7FFF (decimal 1.0 ­ LSB value) Fir1 Page 4/registers 16­17 0x0000 Fir2 Page 4/registers 18­19 0x0000 Fir3 Page 4/registers 20­21 0x0000 Fir4 Page 4/registers 22­23 0x0000 Fir5 Page 4/registers 24­25 0x7FFF (decimal 1.0 ­ LSB value) Fir6 Page 4/registers 26­27 0x0000 Fir7 Page 4/registers 28­29 0x0000 Fir8 Page 4/registers 30­31 0x0000 Fir9 Page 4/registers 32­33 0x0000 Fir10 Page 4/registers 34­35 0x7FFF (decimal 1.0 ­ LSB value) Fir11 Page 4/registers 36­37 0x0000 Fir12 Page 4/registers 38­39 0x0000 Fir13 Page 4/registers 40­41 0x0000 Fir14 Page 4/registers 42­43 0x0000 Fir15 Page 4/registers 44­45 0x7FFF (decimal 1.0 ­ LSB value) Fir16 Page 4/registers 46­47 0x0000 Fir17 Page 4/registers 48­49 0x0000 Fir18 Page 4/registers 50­51 0x0000 Fir19 Page 4/registers 52­53 0x0000 Fir20 Page 4/registers 54­55 0x7FFF (decimal 1.0 ­ LSB value) Fir21 Page 4/registers 56­57 0x0000 Fir22 Page 4/registers 58­59 0x0000 Fir23 Page 4/registers 60­61 0x0000 Fir24 Page 4/registers 62­63 0x0000 Submit Documentation Feedback APPLICATION INFORMATION 37 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 5.5.4.4 ADC Digital Decimation Filter Characteristics The TSC2117 TSC2117 offers three different types of decimation filters. The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of AOSR × fS to the final output sampling rate of fS. The decimation filtering is achieved using a higher-order CIC filter followed by linear-phase FIR filters. The decimation filter cannot be chosen by itself; it is implicitly set through the chosen processing block. The following subsections describe the properties of the available filters A, B, and C. 5.5.4.4.1 Decimation Filter A This filter is intended for use at sampling rates up to 48 kHz. When configuring this filter, the oversampling ratio of the ADC can either be 128 or 64. For highest performance, the oversampling ratio must be set to 128. Filter A can also be used for 96 kHz at an AOSR of 64. Table 5-20. ADC Decimation Filter A, Specification Parameter Condition Value (Typical) Unit AOSR = 128 Filter gain pass band 0.0.39 fS 0.062 dB Filter gain stop band 0.55.64 fS ­73 dB Filter group delay 17/fS s Pass-band ripple, 8 ksps 0.0.39 fS 0.062 dB Pass-band ripple, 44.1 ksps 0.0.39 fS 0.05 dB Pass-band ripple, 48 ksps 0.0.39 fS 0.05 dB Filter gain pass band 0.0.39 fS 0.062 dB Filter gain stop band 0.55.32 fS ­73 dB AOSR = 64 Filter group delay 17/fS s Pass-band ripple, 8 ksps 0.0.39 fS 0.062 dB Pass-band ripple, 44.1 ksps 0.0.39 fS 0.05 dB Pass-band ripple, 48 ksps 0.0.39 fS 0.05 dB Pass-band ripple, 96 ksps 0.20 kHz 0.1 dB ADC Channel Response for Decimation Filter A (Red line corresponds to -73 dB) 0 -10 Magnitude - dB -20 -30 -40 -50 -60 -70 -80 -90 -100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Frequency Normalized w.r.t. FS 2 Figure 5-13. ADC Decimation Filter A, Frequency Response 38 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.5.4.4.2 Decimation Filter B Filter B is intended to support sampling rates up to 96 kHz at an oversampling ratio of 64. Table 5-21. ADC Decimation Filter B, Specifications Parameter Condition Value (Typical) Unit AOSR = 64 Filter gain pass band 0.0.39 fS ±0.077 dB Filter gain stop band 0.60 fS.32 fS ­46 dB 11/fS s Filter group delay Pass-band ripple, 8 ksps 0.0.39 fS 0.076 dB Pass-band ripple, 44.1 ksps 0.0.39 fS 0.06 dB Pass-band ripple, 48 ksps 0.0.39 fS 0.06 dB Pass-band ripple, 96 ksps 0.20 kHz 0.11 dB 0 ADC Channel Response for Decimation Filter A (Red line corresponds to -44 dB) -10 Magnitude - dB -20 -30 -40 -50 -60 -70 -80 -90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Frequency Normalized w.r.t. FS 2 Figure 5-14. ADC Decimation Filter B, Frequency Response Submit Documentation Feedback APPLICATION INFORMATION 39 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 5.5.4.4.3 Decimation Filter C Filter C along with an AOSR of 32 is specially designed for 192-ksps operation for the ADC. The pass band, which extends up to 0.11 × fS (corresponding to 21 kHz), is suited for audio applications. Table 5-22. ADC Decimation Filter C, Specifications Parameter Condition Value (Typical) Unit Filter gain from 0 to 0.11 fS 0.0.11 fS ±0.033 dB Filter gain from 0.28 fS to 16 fS 0.28 fS.16 fS ­60 dB Filter group delay 11/fS s Pass-band ripple, 8 ksps 0.0.11 fS 0.033 dB Pass-band ripple, 44.1 ksps 0.0.11 fS 0.033 dB Pass-band ripple, 48 ksps 0.0.11 fS 0.032 dB Pass-band ripple, 96 ksps 0.0.11 fS 0.032 dB Pass-band ripple, 192 ksps 0.20 kHz 0.086 dB 0 ADC Channel Response for Decimation Filter C (Red line corresponds to -60 dB) Magnitude - dB -20 -40 -60 -80 -100 -120 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Frequency Normalized w.r.t. FS 2 Figure 5-15. ADC Decimation Filter C, Frequency Response 5.5.4.5 ADC Data Interface The decimation filter and signal processing block in the ADC channel passes 32-bit data words to the audio serial interface once every cycle of ADC_fS. During each cycle of ADC_fS, a pair of data words (for left and right channel) is passed. The audio serial interface rounds the data to the required word length of the interface before converting to serial data. Because the TSC2117 TSC2117 has only a mono ADC, it passes the same data to both the left and right channels of the audio serial interface. 5.5.5 Updating ADC Digital Filter Coefficients During Record When it is required to update the ADC digital filter coefficients during record, care must be taken to avoid click and pop noise or even a possible oscillation noise. These artifacts can occur if the ADC coefficients are updated without following the proper update sequence. The correct sequence is shown in Figure 5-16. The values for the times listed are conservative and should be used for software purposes. 40 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 Record - Paused Volume Ramp Down Soft Mute Wait (A) ms ADC Volume Ramp Down WAIT Time (A) For fS = 32 kHz ® Wait 10 ms (min) ADC Power Down Update Digital Filter Coefficients For fS = 48 kHz ® Wait 8 ms (min) ADC Volume Ramp Up Time (B) For fS = 32 kHz ® 10 ms ADC Power UP For fS = 48 kHz ® 8 ms Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Record - Continue F0023-02 F0023-02 Figure 5-16. Updating ADC Digital Filter Coefficients During Record 5.5.6 Digital Microphone Function In addition to supporting analog microphones, the TSC2117 TSC2117 can also interface to one digital microphone using using the mono ADC channel. Figure 5-17 shows the digial microphone interface block diagram and Figure 5-18 shows the timing diagram for the digital microphone interface. Submit Documentation Feedback APPLICATION INFORMATION 41 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com D-S GPIO1 GPIO2 MISO Signal Processing Blocks DIG_MIC_IN ADC_MOD_CLK Mono ADC CIC Filter SDIN SCLK Figure 5-17. Digital Microphone in the TSC2117 TSC2117 The TSC2117 TSC2117 outputs internal clock ADC_MOD_CLK on the GPIO1 pin (page 0/register 51, bits D5­D2 = 1010), GPIO2 pin (page 0/register 52, bits D5­D2 = 1010), or MISO pin (page 0/register 55, bits D4­D1 = 0111). This clock can be connected to the external digital microphone device. The single-bit output of the external digital microphone device can be connected to the GPIO1, GPIO2, SDIN, or SCLK pins (for this mode, page 0/register 51, 52, 54, or 56 must be configured as a secondary input). Internally, the TSC2117 TSC2117 latches the steady value of the mono ADC data on the rising edge of ADC_MOD_CLK. ADC_MOD_CLK DIG_MIC_IN MONO DATA NO DATA MONO DATA NO DATA MONO DATA NO DATA Figure 5-18. Timing Diagram for Digital Microphone Interface When the digital microphone mode is enabled, the analog section of the ADC can be powered down and bypassed for power efficiency. The AOSR value for the ADC channel must be configured to select the desired decimation ratio to be achieved, based on the external digital microphone properties. 5.5.7 DC Measurement The TSC2117 TSC2117 supports a highly flexible dc measurement feature using the high-resolution oversampling and noise-shaping ADC. This mode can be used when the ADC channel is not used for the voice/audio record function. This mode can be enabled by programming page 0/register 102, bit D7. The converted data is 24 bits, using the 2.22 numbering format. The value of the converted data for ADC channel can be read back from page 0/registers 104­106. Before reading back the converted data, page 0/register 103, bit D6 must be programmed to 1 in order to latch the converted data into the read-back registers. After the converted data is read back, page 0/register 103, bit D6 must be immediately reset to 0. In dc-measurement mode, two measurement modes are supported. Mode A In dc-measurement mode A, a variable-length averaging filter is used. The length of averaging filter D can be programmed from 1 to 20 by programming page 0/register 102, bits D4­D0. To choose mode A, page 0/register 102, bit D5 must be programmed to 0. 42 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 Mode B To choose mode B, page 0/register 102, bit D5 must be programmed to 1. In dc-measurement mode B, a first-order IIR filter is used. The coefficients of this filter are determined by D, page 0/register 102, bits D4­D0. The nature of the filter is given in Table 5-23. Table 5-23. DC Measurement Bandwidth Settings D:Page 0/Register 102, Bits D4­D0 ­3 dB BW (kHz) 1 688.44 ­0.5 dB BW (kHz) 236.5 2 275.97 96.334 3 127.4 44.579 4 61.505 21.532 5 30.248 10.59 6 15.004 5.253 7 7.472 2.616 8 3.729 1.305 9 1.862 652 10 931 326 11 465 163 12 232.6 81.5 13 116.3 40.7 14 58.1 20.3 15 29.1 10.2 16 14.54 5.09 17 7.25 2.54 18 3.63 1.27 19 1.8 0.635 20 0.908 0.3165 By programming page 0/register 103, bit D5 to 1, the averaging filter is periodically reset after 2R number of ADC_MOD_CLK periods, where R is programmed in page 0/register 103, bits D4­D0. When page 0/register 103, bit D5 is set to 1, then the value of D should be less than the value of R. When page 0/register 103, bit D5 is programmed to 0, the averaging filter is never reset. 5.6 Audio DAC and Audio Analog Outputs Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital delta-sigma modulator, and an analog reconstruction filter. This high oversampling ratio (normally DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include stereo headphone/lineouts and stereo class-D speaker outputs. 5.6.1 DAC The TSC2117 TSC2117 stereo audio DAC supports data rates from 8 kHz to 192 kHz. Each channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power dissipation and performance, the TSC2117 TSC2117 allows the system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0/registers 13 and 14. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates. Submit Documentation Feedback APPLICATION INFORMATION 43 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com The TSC2117 TSC2117 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on required frequency response, group delay, and sampling rate. DAC power up is controlled by writing to page 0/register 63, bit D7 for the left channel and bit D6 for the right channel. The left-channel DAC clipping flag is provided as a read-only bit on page 0/register 39, bit D7. The right-channel DAC clipping flag is provided as a read-only bit on page 0/register 39, bit D6. 5.6.1.1 DAC Processing Blocks The TSC2117 TSC2117 implements signal-processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may use and which interpolation filter is applied. The choices among these processing blocks allows the system designer to balance power conservation and signal-processing flexibility. Table 5-24 gives an overview of all available processing blocks of the DAC channel and their properties. The resource-class column gives an approximate indication of power consumption for the digital (DVDD) supply; however, based on the out-of-band noise specturum, the analog power consumption of the drivers (HVDD) may differ. The signal processing blocks available are: · First-order IIR · Scalable number of biquad filters · 3D effect · Beep generator The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients. 44 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 Table 5-24. Overview ­ DAC Predefined Processing Blocks First-Order IIR Available Number of Biquads Stereo No Stereo Yes A Stereo PRB_P4 A PRB_P5 A PRB_P6 Processing Block No. Interpolation Filter Channel DRC 3D Beep Generator PRB_P1 A PRB_P2 A PRB_P3 Resource Class 3 No No No 8 6 Yes No No 12 Yes 6 No No No 10 Left No 3 No No No 4 Left Yes 6 Yes No No 6 A Left Yes 6 No No No 6 PRB_P7 B Stereo Yes 0 No No No 6 PRB_P8 B Stereo No 4 Yes No No 8 PRB_P9 B Stereo No 4 No No No 8 PRB_P10 B Stereo Yes 6 Yes No No 10 PRB_P11 B Stereo Yes 6 No No No 8 PRB_P12 B Left Yes 0 No No No 3 PRB_P13 B Left No 4 Yes No No 4 PRB_P14 B Left No 4 No No No 4 PRB_P15 B Left Yes 6 Yes No No 6 PRB_P16 B Left Yes 6 No No No 4 PRB_P17 C Stereo Yes 0 No No No 3 PRB_P18 C Stereo Yes 4 Yes No No 6 PRB_P19 C Stereo Yes 4 No No No 4 PRB_P20 C Left Yes 0 No No No 2 PRB_P21 C Left Yes 4 Yes No No 3 PRB_P22 C Left Yes 4 No No No 2 PRB_P23 A Stereo No 2 No Yes No 8 PRB_P24 A Stereo Yes 5 Yes Yes No 12 PRB_P25 A Stereo Yes 5 Yes Yes Yes 12 5.6.1.2 DAC Processing Blocks ­ Signal Chain Details 5.6.1.2.1 Three Biquads, Filter A BiQuad A from Interface BiQuad B BiQuad C Interp. Filter A ´ to Modulator Digital Volume Ctrl Figure 5-19. Signal Chain for PRB_P1 and PRB_P4 5.6.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D BiQuad E BiQuad F HPF Interp . Filter A,B ´ DRC to Modulator Digital Volume Ctrl Figure 5-20. Signal Chain for PRB_P2, PRB_P5, PRB_P10, and PRB_P15 Submit Documentation Feedback APPLICATION INFORMATION 45 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 5.6.1.2.3 Six Biquads, First-Order IIR, Filter A or B BiQuad A IIR from Interface BiQuad B BiQuad C BiQuad D BiQuad E Interp . Filter A,B BiQuad F to Modulator ´ Digital Volume Ctrl Figure 5-21. Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16 5.6.1.2.4 IIR, Filter B or C Interp. Filter B,C IIR from Interface to Modulator ´ Digital Volume Ctrl Figure 5-22. Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20 5.6.1.2.5 Four Biquads, DRC, Filter B from Interface BiQuad A BiQuad B BiQuad C BiQuad D Interp . Filter B HPF ´ to Modulator Digital Volume Ctrl DRC Figure 5-23. Signal Chain for PRB_P8 and PRB_P13 5.6.1.2.6 Four Biquads, Filter B BiQuad A from Interface BiQuad B BiQuad C BiQuad D Interp. Filter B ´ to Modulator Digital Volume Ctrl Figure 5-24. Signal Chain for PRB_P9 and PRB_P14 5.6.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C IIR BiQuad A BiQuad B BiQuad C Interp. Filter C BiQuad D from Interface HPF DRC ´ to Modulator Digital Volume Ctrl Figure 5-25. Signal Chain for PRB_P18 and PRB_P21 46 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.6.1.2.8 Four Biquads, First-Order IIR, Filter C IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to modulator Digital Volume Ctrl Figure 5-26. Signal Chain for PRB_P19 and PRB_P22 5.6.1.2.9 Two Biquads, 3D, Filter A From LeftChannel Interface + Biquad BL + Biquad CL Interp. Filter A ´ To Modulator + Digital Volume Ctrl + From RightChannel Interface Biquad AL + ­ Biquad AR 3D PGA + ­ + Biquad BR Biquad CR Interp. Filter A ´ To Modulator Digital Volume Ctrl NOTE: AL means biquad A of the left channel, and similarly, BR means biquad B of the right channel. Figure 5-27. Signal Chain for PRB_P23 Submit Documentation Feedback APPLICATION INFORMATION 47 TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 www.ti.com 5.6.1.2.10 Five Biquads, DRC, 3D, Filter A IIR from Left Left Channel Interface + BiQuad BL + BiQuad CL BiQuad DL BiQuad EL BiQuad FL Interp . Filter A to Modulator ´ + HPF + BiQuad AL + - Digital Volume Ctrl DRC 3D PGA BiQuad AR from Right Channel Interface IIR Right + BiQuad BR + BiQuad CR BiQuad DR BiQuad ER BiQuad FR HPF Interp . Filter A to Modulator ´ Digital Volume Ctrl DRC Figure 5-28. Signal Chain for PRB_P24 5.6.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A From LeftChannel Interface + Biquad DL Biquad BL + Biquad CL Biquad EL Biquad FL Interp. Filter A HPF IIR Left DRC + ´ + + + Biquad AL Biquad AR 3D PGA Digital Volume Ctrl Beep Volume Ctrl ´ Beep Volume Ctrl ­ To Modulator ´ Beep Gen. From RightChannel Interface ­ Biquad DR + + Biquad BR Biquad CR Biquad ER Biquad FR Interp. Filter A HPF IIR Right DRC ´ + To Modulator Digital Volume Ctrl Figure 5-29. Signal Chain for PRB_P25 48 APPLICATION INFORMATION Submit Documentation Feedback TSC2117 TSC2117 Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller www.ti.com SLAS550A SLAS550A ­ APRIL 2009 ­ REVISED JUNE 2009 5.6.1.3 DAC User-Programmable Filters Depending on the selected processing block, different types and orders of digital filtering are available. Up to six biquad sections are available for specific processing blocks. The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched on-the-fly. When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed for either read or write. H