TSB83AA22C SLLS802 SB1394 S400B REG18 REQ64 ACK64 P0039-01 REG64 TSB83AA2 PAR64 - Datasheet Archive

 

PHY and OHCI Link Device Data Manual Literature Number: SLLS802 February 2007 PRODUCTION DATA information is current as of

 

TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device Data Manual Literature Number: SLLS802 SLLS802 February 2007 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 Contents 1 Introduction. 9 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 2 Electrical Characteristics. 24 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 4 Power-Class Programming . Power-Up Reset . Crystal Oscillator Selection . Bus Reset . 35 37 37 38 LLC Section Service Request . Status Transfer . Receive . Transmit . 41 44 46 49 TSB83AA22C TSB83AA22C Link Layer Controller Programming Model . 51 6.1 2 24 24 24 26 26 27 27 28 28 Principles of Operation (IEEE Std 1394b-2002 Interface) . 40 5.1 5.2 5.3 5.4 6 Absolute Maximum Ratings . Dissipation Ratings . Recommended Operating Conditions . Electrical Characteristics, PHY Driver . Electrical Characteristics, PHY Receiver. Electrical Characteristics, General . Thermal Characteristics . Switching Characteristics for PHY Portion . Switching Characteristics for PCI Interface . PHY Section Register Configuration . 29 PHY Section Application Information . 35 4.1 4.2 4.3 4.4 5 Features . 9 Description . 10 Terminal Assignments (Top View) . 14 Signals Sorted by Terminal Number . 15 Signals Sorted by Name . 16 Terminal Functions . 17 PCI Configuration Registers . 6.1.1 Vendor ID Register . 6.1.2 Device ID Register . 6.1.3 Command Register . 6.1.4 Status Register . 6.1.5 Revision ID Register . 6.1.6 Class Code Register . 6.1.7 Cache Line Size Register . 6.1.8 Latency Timer Register . 6.1.9 Header Type Register . 6.1.10 Built-In Self-Test (BIST) Register. 6.1.11 OHCI Base Address Register . 6.1.12 TI Extension Base Address Register . 6.1.13 CardBus CIS Base Address Register . 6.1.14 CardBus CIS Pointer Register . 6.1.15 Subsystem Vendor ID Register . 6.1.16 Subsystem ID Register . 6.1.17 Power Management Capabilities Pointer Register . 6.1.18 Interrupt Line Register . 6.1.19 Interrupt Pin Register . 6.1.20 Minimum Grant Register . Contents 51 52 52 52 53 54 55 56 56 56 57 57 58 58 59 60 60 60 61 61 61 Submit Documentation Feedback www.ti.com TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device SLLS802 SLLS802 ­ FEBRUARY 2007 6.2 6.1.21 Maximum Latency Register . 6.1.22 OHCI Control Register . 6.1.23 Capability ID Register . 6.1.24 Next-Item Pointer Register . 6.1.25 Power Management Capabilities Register . 6.1.26 Power Management Control and Status Register . 6.1.27 Power Management Extension Register . 6.1.28 Power Management Data Register . 6.1.29 Multifunction Select Register . 6.1.30 Miscellaneous Configuration Register . 6.1.31 LLC Section Enhancement Control Register . 6.1.32 Subsystem Access Register . 6.1.33 GPIO Control Register . OHCI Registers . 6.2.1 OHCI Version Register . 6.2.2 GUID ROM Register . 6.2.3 Asynchronous Transmit Retries Register . 6.2.4 CSR Data Register . 6.2.5 CSR Compare Data Register . 6.2.6 CSR Control Register . 6.2.7 Configuration ROM Header Register . 6.2.8 Bus Identification Register. 6.2.9 Bus Options Register . 6.2.10 GUID High Register . 6.2.11 GUID Low Register. 6.2.12 Configuration ROM Mapping Register . 6.2.13 Posted Write Address Low Register . 6.2.14 Posted Write Address High Register. 6.2.15 OHCI Vendor ID Register . 6.2.16 Host Controller Control Register. 6.2.17 Self-ID Buffer Pointer Register. 6.2.18 Self-ID Count Register . 6.2.19 Isochronous Receive Channel Mask High Register . 6.2.20 Isochronous Receive Channel Mask Low Register . 6.2.21 Interrupt Event Register . 6.2.22 Interrupt Mask Register . 6.2.23 Isochronous Transmit Interrupt Event Register. 6.2.24 Isochronous Transmit Interrupt Mask Register . 6.2.25 Isochronous Receive Interrupt Event Register . 6.2.26 Isochronous Receive Interrupt Mask Register . 6.2.27 Initial Bandwidth Available Register . 6.2.28 Initial Channels Available High Register. 6.2.29 Initial Channels Available Low Register . 6.2.30 Fairness Control Register . 6.2.31 LLC Section Control Register . 6.2.32 Node Identification Register . 6.2.33 PHY Layer Control Register. 6.2.34 Isochronous Cycle Timer Register . 6.2.35 Asynchronous Request Filter High Register . 6.2.36 Asynchronous Request Filter Low Register. 6.2.37 Physical Request Filter High Register . 6.2.38 Physical Request Filter Low Register . 6.2.39 Physical Upper Bound Register (Optional Register) . Contents 62 62 63 63 63 64 65 65 66 66 67 70 70 71 73 73 74 75 75 75 76 76 76 77 78 78 78 79 79 80 81 82 83 83 84 86 88 89 89 90 90 90 91 91 92 92 93 94 94 95 95 96 97 3 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 6.3 7 8 General-Purpose Input/Output (GPIO) Interface . 109 Serial EEPROM Interface . 110 8.1 4 6.2.40 Asynchronous Context Control Register . 97 6.2.41 Asynchronous Context Command Pointer Register . 98 6.2.42 Isochronous Transmit Context Control Register. 98 6.2.43 Isochronous Transmit Context Command Pointer Register . 99 6.2.44 Isochronous Receive Context Control Register . 100 6.2.45 Isochronous Receive Context Command Pointer Register . 102 6.2.46 Isochronous Receive Context Match Register . 102 TI Extension Registers . 103 6.3.1 DV Timestamp Enhancements . 103 6.3.2 MPEG2 Timestamp Procedure . 104 6.3.3 Isochronous Receive Digital Video Enhancements . 104 6.3.4 Isochronous Receive Digital Video Enhancements Register. 104 6.3.5 Link Enhancement Register . 105 6.3.6 Timestamp Offset Register . 108 MECHANICAL DATA. 112 Contents Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 List of Figures 2-1 Test Load Diagram. 28 2-2 Setup and Hold Time Waveforms for Dx, CTLx, and LREQ Inputs . 28 2-3 Dx and CTLx Output Delay Relative to xCLK Waveforms . 28 4-1 Typical Twisted Pair IEEE Std 1394a-2000 Cable Connections . 36 4-2 Typical DC-Isolated Outer Shield Termination . 36 4-3 Non-DC-Isolated Outer Shield Termination. 37 5-1 PHY Section-LLC Section Interface . 40 5-2 LREQ/PHY_LREQ Request Stream . 41 5-3 Bus Status Transfer . 45 5-4 PINT (PHY Section Interrupt) Stream . 45 5-5 Normal Packet Reception . 47 5-6 Normal Packet Reception With Optional Bus Status Transfer . 47 5-7 Null Packet Reception . 48 7-1 GPIO Logic Diagram . 109 List of Figures 5 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 List of Tables 3-1 Base Register Configuration . 29 3-2 Base Register Field Descriptions . 29 3-3 Page-0 (Port-Status) Register Configuration . 31 3-4 Page-0 (Port-Status) Register Field Descriptions . 32 3-5 Page 1 (Vendor ID) Register Configuration 3-6 3-7 3-8 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6 . Page 1 (Vendor ID) Register Field Descriptions . Page 7 (Vendor-Dependent) Register Configuration . Page 7 (Vendor-Dependent) Register Field Descriptions . Power Class Descriptions . CTL Encoding When PHY Section Has Control of the Bus . CTL Encoding When LLC Section Has Control of the Bus . Request Stream Bit Length . Request-Type Encoding. Bus Request . Bus-Request Format Encoding. Bus-Request Speed Encoding . Read Register Request . Write Register Request . Link Notification Request . Status Bits . PHY Status Transfer Encoding . Register Read (Solicited and Unsolicited) PHY Status Transfer Encoding . Receive Speed Codes and Format . Link-Request-Type Encoding During Packet Transmission . Link-Request Speed-Code Encoding During Packet Transmission . Link-Request Format Encoding During Packet Transmission . Subaction End-Notification Encoding During Packet Transmission . Format Type During Grant Cycle . Grant Type Values During Grant Cycle . Speed Type Values During Grant Cycle . Bit Field Access Tag Descriptions . PCI Configuration Register Map . Command Register Description . Status Register Description . Revision ID Register Description . Class Code Register Description . Cache Line Size Register Description . Latency Timer Register Description . Header Type Register Description . List of Tables 33 34 34 34 35 41 41 42 42 43 43 43 43 44 44 45 46 46 48 49 49 50 50 50 50 50 51 51 53 54 54 55 56 56 56 Submit Documentation Feedback www.ti.com TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device SLLS802 SLLS802 ­ FEBRUARY 2007 6-10 Built-In Self-Test (BIST) Register Description . 57 6-11 OHCI Base Address Register Description . 57 6-12 TI Base Address Register Description 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 6-42 6-43 6-44 6-45 6-46 6-47 6-48 6-49 6-50 . CardBus CIS Base Address Register Description . CardBus CIS Pointer Register Description . Subsystem Vendor ID Register Description . Subsystem ID Register Description. Interrupt Line Register Description . Interrupt Line and Pin Register Description . Minimum Grant Register Description . Maximum Latency Register Description . OHCI Control Register Description . Capability ID Register Description . Next-Item Pointer Register Description . Power Management Capabilities Register Description . Power Management Control and Status Register Description . Power Management Extension Register Description. Power Management Data Register Description . Multifunction Select Register . Miscellaneous Configuration Register . LLC Section Enhancement Control Register Description . Subsystem Access Register Description. GPIO Control Register Description . OHCI Register Map . OHCI Version Register Description . GUID ROM Register Description . Asynchronous Transmit Retries Register Description . CSR Control Register Description . Configuration ROM Header Register Description . Bus Options Register Description . Configuration ROM Mapping Register Description . Posted Write Address Low Register Description . Posted Write Address High Register Description . Vendor ID Register Description . Host Controller Control Register Description . Self-ID Count Register Description . Isochronous Receive Channel Mask High Register Description . Isochronous Receive Channel Mask Low Register Description . Interrupt Event Register Description . Interrupt Mask Register Description . Isochronous Transmit Interrupt Event Register Description . List of Tables 58 59 59 60 60 61 61 61 62 62 63 63 64 64 65 65 66 67 69 70 70 71 73 74 74 75 76 77 78 78 79 80 80 82 83 83 85 87 89 7 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 6-51 Isochronous Receive Interrupt Event Register Description . 90 6-52 Initial Bandwidth Available Register Description . 90 6-53 Initial Channels Available High Register Description . 91 6-54 Initial Channels Available High Register Description . 91 6-55 Fairness Control Register Description. 91 6-56 LLC Section Control Register Description . 92 6-57 Node Identification Register Description . 93 6-58 PHY Layer Control Register Description . 93 6-59 . 94 Asynchronous Request Filter High Register Description . 95 Asynchronous Request Filter Low Register Description . 95 Physical Request Filter High Register Description . 96 Physical Request Filter Low Register Description . 96 Asynchronous Context Control Register Description . 97 Asynchronous Context Command Pointer Register Description . 98 Isochronous Transmit Context Control Register Description . 99 Isochronous Receive Context Control Register Description . 101 Isochronous Receive Context Match Register Description . 103 TI Extension Register Map . 103 Isochronous Receive Digital Video Enhancements Register Description . 105 Link Enhancement Register Description. 107 Timestamp Offset Register Description. 108 Serial EEPROM Map . 111 6-60 6-61 6-62 6-63 6-64 6-65 6-66 6-67 6-68 6-69 6-70 6-71 6-72 8-1 8 Isochronous Cycle Timer Register Description List of Tables Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 1 Introduction 1.1 Features · · · · · · · · · · · · · · · · · Fully Supports Provisions of IEEE Std 1394b-2002 Revision 1.33+ at 1-Gigabit Signaling Rates Fully Supports Provisions of IEEE Std 1394a-2000 and IEEE Std 1394-1995 for High-Performance Serial Bus Fully Interoperable With FirewireTM, i.LINKTM, and SB1394 SB1394 Implementations of IEEE Std 1394 Provides Two Fully Backward-Compatible, (IEEE Std 1394a-2000 Fully Compliant) Bilingual IEEE Std 1394b-2002 Cable Ports at up to 800 Megabits per Second (Mbps) Full IEEE Std 1394a-2000 Support Includes: ­ Connection Debounce ­ Arbitrated Short Reset ­ Multispeed Concatenation ­ Arbitration Acceleration ­ Fly-By Concatenation ­ Port Disable/Suspend/Resume Extended Resume Signaling for Compatibility With Legacy DV Devices Power-Down Features to Conserve Energy in Battery-Powered Applications Low-Power Sleep Mode Fully Compliant With Open Host Controller Interface (OHCI) Requirements Cable Power Presence Monitoring Cable Ports Monitor Line Conditions for Active Connection to Remote Node Register Bits Give Software Control of Contender Bit, Power-Class Bits, Link Active Control Bit, and IEEE Std 1394a-2000 Features Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies Low-Jitter, External Crystal Oscillator Provides Transmit and Receive Data at 100/200/400/800 Mbps and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz Separate Bias (TPBIAS) for Each Port Software Device Reset (SWR) Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables Ports to · · · · · · · · · · · · · · Ensure That TSB83AA22C TSB83AA22C Does Not Load TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane IEEE Std 1394a-2000-Compliant Common-Mode Noise Filter on Incoming Bias Detect Circuit to Filter Out Crosstalk Noise Port Programmable to Force IEEE Std 1394a-2000 Mode to Allow Use of IEEE Std 1394a-2000 Connectors (IEEE Std 1394b-2002 Signaling Must Not Be Put Across IEEE Std 1394a-2000 Connectors or Cables) 3.3-V and 5-V PCI Signaling Environments Serial-Bus Data Rates of 100 Mbps, 200 Mbps, 400 Mbps, and 800 Mbps Physical Write Posting of up to Three Outstanding Transactions Serial ROM or Boot ROM Interface Supports 2-Wire Serial EEPROM Devices 33-MHz/32-Bit PCI Interface Multifunction Terminal (MFUNC Terminal 1): ­ PCI_CLKRUN Protocol Per PCI Mobile Design Guide ­ General-Purpose I/O (GPIO) ­ CYCLEIN/CYCLEOUT for External Cycle Timer Control for Customized Synchronization PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency ­ Transmit FIFO-5K Asynchronous ­ Transmit FIFO-2K Isochronous ­ Receive FIFO-2K Asynchronous ­ Receive FIFO-2K Isochronous D0, D1, D2, and D3 Power States and PME Events Per PCI Bus Power Management Interface Specification Programmable Asynchronous Transmit Threshold Isochronous Receive Dual-Buffer Mode Out-of-Order Pipelining for Asynchronous Transmit Requests Initial-Bandwidth-Available and Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. OHCI-Lynx is a trademark of Texas Instruments. Firewire is a trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 Initial-Channels-Available Registers 1.2 · Digital Video and Audio Performance Enhancements Description The TSB83AA22C TSB83AA22C is an IEEE Std 1394b-2002 link-layer design and physical layer (PHY) design combined in a single package to meet the demanding requirements of today's 1394 bus applications. The TSB83AA22C TSB83AA22C device is capable of exceptional 800-Mbps performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB83AA22C TSB83AA22C device also provides outstanding ultralow power operation and intelligent power-management capabilities. The device provides the IEEE 1394 LLC function and PHY function and is compatible with 100-Mbps, 200-Mbps, 400-Mbps, and 800-Mbps serial-bus data rates. The TSB83AA22C TSB83AA22C operates as the interface between 33-MHz/32-bit PCI local bus and an IEEE Std 1394a-2000 or IEEE Std 1394b-2002 serial-bus interface. It is capable of supporting serial data rates at 98.304, 196.608, 393.216, 491.52, or 786.432 Mbps (referred to as S100, S200, S400, S400B S400B, or S800 speeds, respectively). When acting as a PCI bus master, the TSB83AA22C TSB83AA22C device is capable of multiple cache-line bursts of data, which can transfer at 132M bytes/s for 32-bit transfers after connecting to the memory controller. Due to the high throughput potential of the TSB83AA22C TSB83AA22C device, it possible to encounter large PCI and legacy 1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the TSB83AA22C TSB83AA22C implements deep transmit and receive FIFOs (see Section 1.1, Features, for FIFO size information) to buffer the 1394 data, thus, preventing possible problems due to bus latency. This also ensures that the device can transmit and receive sustained maximum-size isochronous or asynchronous data payloads at S800. The TSB83AA22C TSB83AA22C LLC section implements other performance enhancements to improve overall performance of the device, such as a highly-tuned physical data path for enhanced SBP-2 performance, physical post writing buffers, multiple isochronous contexts, and advanced internal arbitration. The TSB83AA22C TSB83AA22C LLC section also implements hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at TI extension offset A80h (see Section 6.3.4, Isochronous Receive Digital Video Enhancements Register). These enhancements include automatic time-stamp insertion for transmitted DV and MPEG-formatted streams, and common isochronous packet (CIP) header stripping for received DV streams. The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization time stamp for both DV and audio/video CIP formats. The TSB83AA22C TSB83AA22C device supports modification of the synchronization time-stamp field to ensure that the value inserted via software is not stale - that is, less than the current cycle timer when the packet is transmitted. The TSB83AA22C TSB83AA22C performance and enhanced throughput make it an excellent choice for today's 1394 PC market; however, portable, mobile, and even desktop PC power-management schemes continue to require devices to use less and less power, and TI's 1394 product line has continued to raise the bar by providing the lowest-power 1394 devices in the industry. The TSB83AA22C TSB83AA22C device represents the next evolution of TI commitment to meet the challenge of power-sensitive applications. The TSB83AA22C TSB83AA22C device has ultralow operational power requirements and intelligent power-management capabilities that allow it to conserve power autonomously based on the device usage. The TSB83AA22C TSB83AA22C LLC section fully supports D0, D1, D2, and D3hot/cold power states, as specified in the PC 2001 Design Guide requirements and the PCI Power Management Specification. PME wake-event support is subject to operating-system support and implementation. 10 Introduction Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB83AA22C TSB83AA22C LLC section is fully compliant with the latest PCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394b-2002, IEEE Std 1394a-2000, and 1394 Open Host Controller Interface Specification. The TSB83AA22C TSB83AA22C PHY section provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB83AA22C TSB83AA22C is powered by multiple voltage supplies, 3.3-V supplies for I/O and the LLC section, and a core voltage supply for the PHY section. The core voltage supply is supplied to the PLLVDD_CORE and DVDD_CORE terminals in accordance with the requirements in the recommended operating conditions. The PLLVDD_CORE terminals must be separated from the DVDD_CORE terminals, the PLLVDD_CORE terminals are decoupled with 1-µF and smaller decoupling capacitors, and the DVDD_CORE terminals separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD_CORE and PLLVDD_CORE can be implemented by separate power-supply rails, or by a single power-supply rail, where the DVDD_CORE and PLLVDD_CORE are separated by a filter network to keep noise from the PLLVDD_CORE supply. In addition, REG_EN must be asserted low to enable the internal voltage regulator for the LLC section. If REG_EN is not pulled low, the a 1.8-V power rail must be applied to the REG18 REG18 pins. The TSB83AA22C TSB83AA22C requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbps (referred to as S100, S200, S400, S400B S400B, or S800 speed, respectively) as the outbound information stream. To ensure that the TSB83AA22C TSB83AA22C conforms to the IEEE Std 1394b-2002 standard, the BMODE terminal must be asserted. NOTE The BMODE terminal does not select the cable-interface mode of operation. The BMODE terminal selects the internal PHY section-LLC section interface mode of operation and affects the arbitration modes on the cable. BMODE must be pulled high during normal operation. The cable interface can follow either the IEEE Std 1394a-2000 protocol or the IEEE Std 1394b-2002 protocol on both ports. The mode of operation is determined by the interface capabilities of the ports being connected. When either of the ports is connected to an IEEE Std 1394a-2000-compliant device, the cable interface on that port operates in the IEEE Std 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to an IEEE Std 1394b-2002-compliant node, the cable interface on that port operates per the IEEE Std 1394b-2002 standard at S400B S400B or S800 speed. The TSB83AA22C TSB83AA22C automatically determines the correct cable interface connection method for the bilingual ports. Submit Documentation Feedback Introduction 11 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 To operate a port as an IEEE Std 1394b-2002 bilingual port, the data-strobe-only terminal for the port (DS0 or DS1) must be pulled to ground through a 1-k resistor. The port must be operated in the IEEE Std 1394b-2002 bilingual mode whenever an IEEE Std 1394b-2002 bilingual or an IEEE Std 1394b-2002 Beta-only connector is connected to the port. To operate the port as an IEEE Std 1394a-2000-only port, the data-strobe-only terminal (DS0 or DS1) must be pulled to 3.3-V VCC through a 1-k resistor. The only time the port must be forced to the data-strobe-only mode is if the port is connected to an IEEE Std 1394a-2000 connector (either 6 pin, which is recommended, or 4 pin). This mode is provided to ensure that IEEE Std 1394b-2002 signaling is never sent across an IEEE Std 1394a-2000 cable. During packet reception, the serial data bits are split into 2-, 4-, or 8-bit parallel streams by the PHY section and sent to the link-layer controller (LLC) section. The received data is also transmitted (repeated) on the other connected and active cable ports. Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to an IEEE Std 1394a-2000-compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during IEEE Std 1394a-2000-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage. When connected to an IEEE Std 1394a-2000-compliant node, the TSB83AA22C TSB83AA22C PHY section provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY section contains two independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. The line drivers in the TSB83AA22C TSB83AA22C PHY section are designed to work with external 112- termination resistor networks in order to match the 110- cable impedance. One termination network is required at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56- resistors. The midpoint of the pair of resistors that is connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground through a parallel RC network, with recommended values of 5 k and 270 pF. The values of the external line-termination resistors are selected to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. When the power supply of the TSB83AA22C TSB83AA22C is off while the twisted-pair cables are connected, the TSB83AA22C TSB83AA22C transmitter and receiver circuitry present to the cable a high-impedance signal that does not load the device at the other end of the cable. When the TSB83AA22C TSB83AA22C PHY section is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the port must be forced to the IEEE Std 1394a-2000-only mode (data-strobe-only mode), after which the TPB+ and TPB­ terminals can be tied together and then pulled to ground; or the TPB+ and TPB­ terminals can be connected to the suggested normal termination network. The TPA+ and TPA­ terminals of an unused port can be left unconnected. The TPBIAS terminal can be connected through a 1-µF capacitor to ground or left unconnected. The TESTM, TESTW, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM and TESTW terminals must be connected to VDD through a 1-k resistor. The SE and SM terminals must be tied to ground through a 1-k resistor. 12 Introduction Submit Documentation Feedback www.ti.com TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device SLLS802 SLLS802 ­ FEBRUARY 2007 Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They can be pulled high through a 1-k resistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB83AA22C TSB83AA22C, this bit can only be set by a write to the PHY register set. If a node is to be a contender for IRM or BM, the node software must set this bit in the PHY register set. The LPS (link power status) terminal of the PHY section works with the LKON terminal to manage the power usage in the node. The PHY_LPS signal from the LLC section is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application Information section) to indicate the active/power status of the LLC section. The LPS signal also resets, disables, and initializes the PHY section-LLC section interface (the state of the PHY section-LLC section interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit). The LPS terminal of the PHY section must be connected to the PHY_LPS terminal of the LLC section during normal operation. The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the PHY section detects that the LPS input is inactive, the PHY section-LLC section interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), the PHY section-LLC section interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB83AA22C TSB83AA22C continues the necessary PHY repeater functions required for normal network operation, regardless of the state of the PHY section-LLC section interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY section initializes the interface and returns to normal operation. The PHY section-LLC section interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB83AA22C TSB83AA22C issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY section and LLC section now being accessible). The PHY section uses the LKON terminal to notify the LLC section to power up and become active. When activated, the output LKON signal is a square wave. The PHY section activates the LKON output when the LLC section is inactive and a wake-up event occurs. The LLC section is considered inactive when either the LPS input is inactive, as previously described, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY section deasserts the LKON output when the LLC section becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY section also deasserts the LKON output when a bus reset occurs, unless a PHY interrupt condition exists, which would otherwise cause LKON to be active. If the TSB83AA22C TSB83AA22C is power cycled and the power class is 0 through 4, the PHY section asserts LKON for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1. Submit Documentation Feedback Introduction 13 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 1.3 Terminal Assignments (Top View) A B C D E F G H J K L M N 13 R1 D6 PHY_D2 D2 PHY_ D0-D0 PHY_ CTL0CTL0 LCLK PCLK PCI_ REQ64 REQ64 LREQ LKON/ DS2 PINT LPS 12 R0 PHY_D6 D5 DVDD_ 3.3 PHY_ D1-D1 PHY_ CTL1CTL1 REG18 REG18 DVDD_ 3.3 DVDD_ 3.3 CNA PCI_ ACK64 ACK64 D7 PHY_D5 AVDD_ 3.3 VCCP VCCP REG18 REG18 VCC VCC PD TESTM PCI_AD2 PCI_AD1 10 PLLGND PHY_D4 D4 AVDD_ 3.3 GND GND GND GND GND GND RESET PCI_AD4 PCI_AD3 09 XI PHY_D3 D3 VCC GND GND GND GND GND PCI_ AD13 BMODE PCI_AD6 PCI_AD7 08 PLLVDD_ CORE DS1 GND VCC GND GND GND GND GND PCI_ AD14 PCI_AD8 PCI_AD9 07 PLLVDD_ 3.3 PHY_ LCLK GND GND GND GND GND GND VCC DVDD_ 3.3 PCI_ SERR PCI_ AD12 TESTW 06 DS0 PHY_ PCLK DVDD_ CORE GND GND GND GND GND VCC DVDD_ CORE PCI_ PERR PCI_ AD11 PCI_ AD10 05 CPS SM DVDD_ CORE VCC VCC VCC AVDD_ 3.3 AVDD_ 3.3 PCI_ TRDY PCI_C/ BE2 PCI_ STOP PCI_ AD15 PC2 04 SE PHY_ LINKON SDA PHY_ LREQ PCI_ AD31 PCI_ AD24 PCI_ AD22 PCI_ IRDY PCI_ AD18 PC1 PC0 03 PHY_ PINT PCI_ INTA SCL PCI_ CLK 02 PHY_ LPS 01 MFUNC 11 PHY_D7 REG_EN TPBIAS0 TPB0­ TPB0+ PCI_RST G_RST PCI_PME PCI_AD5 PCI_AD0 PCI_C/ BE0 PCI_ GNT PCI_ REQ PCI_ AD27 PCI_ AD23 PCI_ AD25 PCI_ AD16 PCI_ FRAME PCI_C/ BE1 PCI_ PAR TPA0­ PCI_ AD30 TPB1+ PCI_ AD26 TPA1+ PCI_C/ BE3 PCI_ IDSEL PCI_ AD19 PCI_ DEVSEL TPA0+ PCI_ AD29 TPB1­ PCI_ AD28 TPA1­ TPBIAS1 PCI_ AD21 PCI_ AD20 PCI_ AD17 P0039-01 P0039-01 14 Introduction Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 1.3.1 Signals Sorted by Terminal Number Terminal Number Signal Name Terminal Number Signal Name Terminal Number Signal Name Terminal Number Signal Name A01 MFUNC D05 VCC G09 GND K13 LREQ A02 PHY_LPS D06 GND G10 GND L01 PC1_AD21 A03 PHY_PINT D07 GND G11 REG18 REG18 L02 PCI_IDSEL A04 SE D08 VCC G12 REG18 REG18 L03 PCI_FRAME A05 CPS D09 VCC G13 LCLK L04 PCI_AD18 A06 DS0 D10 AVDD_3.3 H01 PCI_AD28 L05 PCI_STOP A07 PLLVDD_3.3 D11 AVDD_3.3 H02 PCI_AD26 L06 PCI_PERR A08 PLLVDD_ CORE D12 DVDD_3.3 H03 PCI_AD23 L07 PCI_SERR A09 XI D13 D2 H04 PCI_AD24 L08 PCI_AD8 A10 PLLGND E01 TPA0+ H05 AVDD_3.3 L09 BMODE A11 PHY_D7 E02 TPA0­ H06 GND L10 RESET A12 R0 E03 PCI_GNT H07 GND L11 TESTM A13 R1 E04 G_RST H08 GND L12 PCI_AD0 B01 TPB0­ E05 VCC H09 GND L13 LKON/DS2 B02 N.C. E06 GND H10 GND M01 PCI_AD20 B03 PCI_INTA E07 GND H11 VCC M02 PCI_AD19 B04 PHY_LINKON E08 GND H12 DVDD_3.3 M03 PCI_C/BE1 B05 SM E09 GND H13 PCLK M04 PC1 B06 PHY_PCLK E10 GND J01 TPA1­ M05 PCI_AD15 B07 PHY_LCLK E11 VCCP J02 TPA1+ M06 PCI_AD11 B08 DS1 E12 PHY_D1-D1 J03 PCI_AD25 M07 PCI_AD12 B09 PHY_D3 E13 PHY_D0-D0 J04 PCI_AD22 M08 PCI_AD9 B10 PHY_D4 F01 PCI_AD29 J05 PCI_TRDY M09 PCI_AD6 B11 D7 F02 PCI_AD30 J06 VCC M10 PCI_AD4 B12 PHY_D6 F03 PCI_REQ J07 VCC M11 PCI_AD2 B13 D6 F04 PCI_PME J08 GND M12 CNA C01 TPB0+ F05 VCC J09 GND M13 PINT C02 REG_EN F06 GND J10 GND N01 PCI_AD17 C03 SCL F07 GND J11 VCC N02 PCI_DEVSEL C04 SDA F08 GND J12 DVDD_3.3 N03 PCI_PAR C05 DVDD_CORE F09 GND J13 PCI_REQ64 REQ64 N04 PC0 C06 DVDD_CORE F10 GND K01 TPBIAS1 N05 PC2 C07 GND F11 VCCP K02 PCI_C/BE3 N06 PCI_AD10 C08 GND F12 PHY_CTL1-CTL1 K03 PCI_AD16 N07 TESTW C09 D3 F13 PHY_CTL0-CTL0 K04 PCI_IRDY N08 PCI_C/BE0 C10 D4 G01 TPB1­ K05 PCI_C/BE2 N09 PCI_AD7 C11 PHY_D5 G02 TPB1+ K06 DVDD_CORE N10 PCI_AD3 C12 D5 G03 PCI_AD27 K07 DVDD_3.3 N11 PCI_AD1 C13 PHY_D2 G04 PCI_AD31 K08 PCI_AD14 N12 PCI_ACK64 ACK64 D01 PCI_RST G05 AVDD_3.3 K09 PCI_AD13 N13 LPS D02 TPBIAS0 G06 GND K10 GND D03 PCI_CLK G07 GND K11 PD D04 PHY_LREQ G08 GND K12 PCI_AD5 Submit Documentation Feedback Introduction 15 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 1.3.2 Signals Sorted by Name Signal Name AVDD_3.3 Terminal Number Signal Name Terminal Number Signal Name Terminal Number Signal Name Terminal Number D10, D11, N.C. B02 PCI_C/BE0 N08 PHY_PINT A03 G05, H05 PC0 N04 PCI_C/BE1 M03 PINT M13 BMODE L09 PC1 M04 PCI_C/BE2 K05 PLLGND A10 CNA M12 PC2 N05 PCI_C/BE3 K02 PLLVDD_3.3 A07 CPS A05 PCI_ACK64 ACK64 N12 PCI_CLK D03 PLLVDD_ CORE A08 D2 D13 PCI_AD0 L12 PCI_DEVSEL N02 R0 A12 D3 C09 PCI_AD1 N11 PCI_FRAME L03 R1 A13 D4 C10 PCI_AD2 M11 PCI_GNT E03 REG18 REG18 G11 D5 C12 PCI_AD3 N10 PCI_IDSEL L02 REG18 REG18 G12 D6 B13 PCI_AD4 M10 PCI_INTA B03 REG_EN C02 D7 B11 PCI_AD5 K12 PCI_IRDY K04 RESET L10 DS0 A06 PCI_AD6 M09 PCI_PAR N03 SCL C03 DS1 B08 PCI_AD7 N09 PCI_PERR L06 SDA C04 DVDD_3.3 D12, H12, PCI_AD8 L08 PCI_PME F04 SE A04 J12, K07 PCI_AD9 M08 PCI_REQ F03 SM B05 C05, C06, PCI_AD10 N06 PCI_REG64 REG64 J13 TESTM L11 K06 PCI_AD11 M06 PCI_RST D01 TESTW N07 C07, C08, PCI_AD12 M07 PCI_SERR L07 TPA0­ E02 D06, D07, PCI_AD13 K09 PCI_STOP L05 TPA0+ E01 E06, E07, PCI_AD14 K08 PCI_TRDY J05 TPA1­ J01 E08, E09, PCI_AD15 M05 PCLK H13 TPA1+ J02 E10, F06, PCI_AD16 K03 PD K11 TPB0­ B01 F07, F08, PCI_AD17 N01 PHY_CTL0-CTL0 F13 TPB0+ C01 F09, F10, PCI_AD18 L04 PHY_CTL1-CTL1 F12 TPB1­ G01 G06, G07, PCI_AD19 M02 PHY_D0-D0 E13 TPB1+ G02 G08, G09, PCI_AD20 M01 PHY_D1-D1 E12 TPBIAS0 D02 G10, H06, PCI_AD21 L01 PHY_D2 C13 TPBIAS1 K01 H07, H08, PC1_AD22 J04 PHY_D3 B09 VCC D05, D08, H09, H10, PCI_AD23 H03 PHY_D4 B10 D09, E05, J08, J09, PCI_AD24 H04 PHY_D5 C11 F05, H11, J10, K10 PCI_AD25 J03 PHY_D6 B12 J06, J07, G_RST E04 PCI_AD26 H02 PHY_D7 A11 LCLK G13 PCI_AD27 G03 PHY_LCLK B07 VCCP E11, F11 LKON/DS2 L13 PCI_AD28 H01 PHY_LINKON B04 XI A09 LPS N13 PCI_AD29 F01 PHY_LPS A02 LREQ K13 PCI_AD30 F02 PHY_LREQ D04 MFUNC A01 PCI_AD31 G04 PHY_PCLK B06 DVDD_CORE GND 16 Introduction J11 Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 1.3.3 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION Power Supply AVDD_3.3 D10, D11, G05, H05 Analog circuit power. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1-µF and 0.001-µF. Lower-frequency 10-µF filtering capacitors also are recommended. These supply terminals are separated from the other power terminals internal to the device to provide noise isolation. The PLLVDD_3.3, AVDD_3.3, and DVDD_3.3 terminals must be tied together with a low-dc-impedance connection on the circuit board. DVDD_CORE C05, C06, K06 Digital 1.95-V circuit power. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1-µF and 0.001-µF. An additional 1-µF capacitor is required for voltage regulation. These supply terminals are separated from the other power terminals internal to the device to provide noise isolation. DVDD_3.3 D12, H12, J12, K07 Digital 3.3-V circuit power. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1-µF and 0.001-µF. Lower-frequency 10-µF filtering capacitors also are recommended. The DVDD_3.3 terminals must be tied together at a low-impedance point on the circuit board. These supply terminals are separated from the other power terminals internal to the device to provide noise isolation. The PLLVDD_3.3, AVDD_3.3, and DVDD_3.3 terminals must be tied together with a low-dc-impedance connection on the circuit board. GND C07, C08, D06, D07, E06, E07, E08, E09, E10, F06, F07, F08, F09, F10, G06, G07, G08, G09, G10, H06, H07, H08, H09, H10, J08, J09, J10, K10 Ground. These terminals must be tied together to the low-impedance circuit-board ground plane. PLLGND A10 PLL circuit ground. These terminals must be tied together to the low-impedance circuit-board ground plane. PLLVDD_CORE A08 PLL 1.95-V circuit power. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1-µF and 0.001-µF. An additional 1-µF capacitor is required for voltage regulation, and the PLLVDD_CORE terminals must be separate from the DVDD_CORE terminals. These supply terminals are separated from the other power terminals internal to the device to provide noise isolation. PLLVDD_3.3 A07 PLL 3.3-V circuit power. A combination of high-frequency decoupling capacitors near the terminal is suggested, such as paralleled 0.1-µF and 0.001-µF. Lower-frequency 10-µF filtering capacitors also are recommended. This supply terminal is separated from the other power terminals internal to the device to provide noise isolation. The DVDD_3.3 terminals must be tied together at a low-impedance point on the circuit board. The PLLVDD_3.3, AVDD_3.3, and DVDD_3.3 terminals must be tied together with a low-dc-impedance connection. G11, G12 The REG18 REG18 terminals are connected to the internal 1.8-V LLC-section core voltage. They provide local bypass for the internal core voltage or to provide 1.8 V to the core externally if the internal regulator is disabled. REG18 REG18 REG_EN VCC VCCP C02 I D05, D08, D09 E05, F05, H11 J06, J07, J11 E11, F11 Submit Documentation Feedback Regulator enable. When this terminal is low, the internal 1.8-V regulator is enabled and generates the 1.8-V internal core voltage from the 3.3-V supply voltage. If it is disabled by pulling the terminal high through a 10-k or smaller resistor, 1.8 V must be provided to the REG18 REG18 terminals for normal operation. 3.3-V power supply. A parallel combination of high-frequency decoupling capacitors near each terminal is suggested, such as 0.1-µF and 0.001-µF. Lower-frequency 10-µF filtering capacitors also are recommended. They must be tied to a low-impedance point on the circuit board. I PCI signaling clamp voltage power. PCI signals are clamped per the PCI Local Bus Specification. In addition, if a 5-V ROM is used, the VCCP terminal must be connected to 5 V. Introduction 17 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 TERMINAL I/O DESCRIPTION NAME NO. BMODE L09 I PHY_CTL1-CTL1 PHY_CTL0-CTL0 F12 F13 I/O Control I/Os. These bidirectional control bus signals indicate the phase of operation of the PHY section-LLC section interface. On a reset of the interface, this bus is driven by the PHY section. When driven by the PHY section, information on PHY_CTL0 and PHY_CTL1 is synchronous to PHY_PCLK. When driven by the LLC section, information on PHY_CTL0 and PHY_CTL1 is synchronous to PHY_LCLK. D7 D6 D5 D4 D3 D2 D1 D0 B11 B13 C12 C10 C09 D13 E12 E13 I/O Data I/Os. These bidirectional data bus signals carry 1394 packet data, packet speed, and grant-type information between the PHY section and the LLC section. On a reset of the interface, this bus is driven by the PHY section. When driven by the PHY section, information on PHY_D7 through PHY_D0 is synchronous to PHY_PCLK. When driven by the LLC section, information on PHY_D7 through PHY_D0 is synchronous to PHY_LCLK. Bus holders are built into these terminals. This bus must be connected to the Phy_data I/O bus. PHY_D7 PHY_D6 PHY_D5 PHY_D4 PHY_D3 PHY_D2 PHY_D1 PHY_D0 A11 B12 C11 B10 B09 C13 E12 E13 I/O Data I/Os. These bidirectional data bus signals carry 1394 packet data, packet speed, and grant-type information between the PHY section and the LLC section. On a reset of the interface, this bus is driven by the PHY section. When driven by the PHY section, information on PHY_D7 through PHY_D0 is synchronous to PHY_PCLK. When driven by the LLC section, information on PHY_D7 through PHY_D0 is synchronous to PHY_LCLK. This bus must be connected to the data I/O bus. LCLK G13 I LLC-section clock. 98.304-MHz clock signal to synchronize data transfers from link to the PHY when the PHY section-LLC section interface is in the IEEE Std 1394b-2002 mode. A bus holder is built into this terminal. This terminal must be connected to the PHY_LCLK output terminal of the LLC section. PHY_LCLK B07 O LLC-section clock. PHY_LCLK is an output from the LLC section that is generated from the incoming PHY_PCLK signal. PHY_LCLK is frequency-locked to PHY_PCLK and synchronizes data and information generated by the LLC section. This terminal must be connected to the LCLK input terminal of the PHY section. LKON L13 I/O Link-on notification. It is necessary to pull the terminal high through a 470- or smaller resistor. This terminal must also be connected to the PHY_LINKON input terminal of the LLC section via a 1-k series resistor. A bus holder is built into this terminal. PHY Section-LLC Section Interface Beta-mode. This terminal determines the PHY section-LLC section interface connection protocol. When logic high (asserted), the PHY section-LLC section interface complies with the IEEE Std 1394b-2002 revision 1.33 Beta interface. When logic low (deasserted), the PHY section-LLC section interface complies with the legacy IEEE Std 1394a-2000. This terminal must be pulled high with a 1-k resistor during normal operation. After hardware reset, this terminal is the link-on output, which notifies the LLC section or other power-up logic to power up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (eight PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance. The link-on output is activated if the LLC section is inactive (the LPS input inactive or the LCtrl bit cleared) and when any of the following occurs: a) The TSB83AA2 TSB83AA2 receives a link-on PHY packet addressed to this node. b) The PEI (port-event interrupt) register bit is 1. c) Any of the configuration-timeout interrupt (CTOI), cable-power-status interrupt (CPSI), or state-time-out interrupt (STOI) register bits are 1 and the resuming-port interrupt enable (RPIE) register bit also is 1. d) The PHY is power cycled and the power class is 0 through 4. Once activated, the link-on output is active until the LLC section becomes active (both the LPS input active and the LCtrl bit set). The PHY section also deasserts the link-on output when a bus reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet) In the case of power cycling, the LKON signal must stop after 167 µs if the previous conditions have not been met. NOTE: If an interrupt condition exists which otherwise causes the link-on output to be activated if the LLC section were inactive, the link-on output is activated when the LLC section subsequently becomes inactive. 18 Introduction Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 TERMINAL I/O DESCRIPTION B04 I/O Link-on notification. PHY_LINKON is an input to the LLC section from the PHY section that is used to provide notification that a link-on packet has been received or an event, such as a port connection, has occurred. This input only has meaning when LPS is disabled. This includes the D0 (uninitialized), D2, and D3 power states. If PHY_LINKON becomes active in the D0 (uninitialized), D2, or D3 power state, the TSB83AA22C TSB83AA22C device sets bit 15 (PME_STS) in the power-management control and status register in the PCI configuration space at offset 48h (see Section 6.1.26, Power Management Control and Status Register). This terminal must be connected to the LKON output terminal of the PHY section. N13 I LLC-section power status. This terminal monitors the active/power status of the LLC section and controls the state of the PHY section-LLC section interface. This terminal must be connected to the PHY_LPS output of the LLC section, and must be pulled low with a 10-k resistor during normal operation. NAME NO. PHY_LINKON LPS The LPS input is considered inactive if it is sampled low by the PHY section for more than an LPS_RESET time (~2.6 µs), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 22 ns to be observed as high by the PHY section. When the PHY section detects that the LPS input is inactive, it places the PHY section-LLC section interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than an LPS_DISABLE time (~26 µs), the PHY section-LLC section interface is put into a low-power disabled state in which the PCLK output is also held inactive. The PHY section-LLC section interface is placed into the disabled state on hardware reset. The LLC section state that is communicated in the self-ID packet is considered active only if both the LPS input is active and the LCtrl register bit is set to 1. The LLC-section state that is communicated in the self-ID packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. PHY_LPS A02 O LLC-section power status. PHY_LPS is an output from the LLC section that, when active, indicates that the LLC section is powered and capable of maintaining communications over the PHY section-LLC section interface. When this signal is inactive, it indicates that the LLC section is not powered or that the LLC section has not been initialized by software. This signal is active when bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 6.2.16, Host Controller Control Register) has been set by software according to the initialization as specified in the 1394 Open Host Controller Interface specification. When active, the signal is nominally a 2-MHz pulse. This terminal must be connected to the LPS input of the PHY section. LREQ K13 I LLC-section request. The LLC section uses this input to initiate a service request to the PHY section. This terminal must be connected to the PHY_LREQ output of the LLC section. A bus holder is built into this terminal. PHY_LREQ D04 O LLC-section request. PHY_LREQ is a serial output from the LLC section to the PHY section used to request packet transmissions, read and write PHY section registers, and to indicate the occurrence of certain link events that are relevant to the PHY section. Information encoded on PHY_LREQ is synchronous to PHY_LCLK. This terminal must be connected to the LREQ input of the PHY section. PCLK H13 O PHY-section clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when the PHY section-LLC section interface is operating in the IEEE Std 1394b-2002 mode (BMODE asserted). This terminal must be connected to the PHY_PCLK input of the LLC section. PHY_PCLK B06 I PHY-section clock. PHY_PCLK is an input to the LLC section from the PHY section that, when active, provides a nominal 98.304-MHz clock with a 50/50 duty cycle or 40/60 duty cycle depending on port modes used). This terminal must be connected to the PCLK output of the PHY section. PINT M13 O PHY-section interrupt. The PHY section uses this output to transfer status and interrupt information serially to the LLC section. This terminal must be connected to the PHY_PINT input of the LLC section. A bus holder is built into this terminal. PHY_PINT A03 I PHY-section interrupt. PHY_PINT is a serial input to the LLC section from the PHY section that is used to transfer status, register, interrupt, and other information to the link. Information encoded on PHY_PINT is synchronous to PHY_PCLK. This terminal must be connected to the PINT output of the PHY section. Submit Documentation Feedback Introduction 19 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 TERMINAL I/O DESCRIPTION M12 O Cable not active. This terminal is asserted high when there are no ports receiving incoming bias voltage. When any port receives bias, this terminal goes low. CPS A05 I Cable power status. This terminal is normally connected to cable power through a 400-k resistor. This circuit drives an internal comparator that detects the presence of cable power. This transition from cable power sensed to cable power not sensed can be used to generate an interrupt. DS0 A06 I Data-strobe-only mode for port 0. IEEE Std 1394a-2000-only port-0-enable programming terminal. On hardware reset, this terminal allows the user to select whether port 0 acts like an IEEE Std 1394b-2002 bilingual port (terminal at logic 0) or as an IEEE Std 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-k or smaller resistor (to enable IEEE Std 1394b-2002 bilingual mode) or high through a 10-k or smaller resistor (to enable IEEE Std 1394a-2000-only mode). A bus holder is built into this terminal. DS1 B8 I Data-strobe-only mode for port 1. IEEE Std 1394a-2000-only port-1-enable programming terminal. On hardware reset, this terminal allows the user to select whether port 1 acts like an IEEE Std 1394b-2002 bilingual port (terminal at logic 0) or as an IEEE Std 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-k or smaller resistor (to enable IEEE Std 1394b-2002 bilingual mode) or high through a 10-k or smaller resistor (to enable IEEE Std 1394a-2000-only mode). A bus holder is built into this terminal. PC0 PC1 PC2 N04 M04 N05 I Power class programming. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying the terminals high through a 1-k or smaller resistor or by tying directly to ground through a 1-k or smaller resistor. Bus holders are built into these terminals. TPA0­ TPA0+ TPB0­ TPB0+ E02 E01 B01 C01 I/O Port 0 twisted-pair differential signal. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. TPA1­ TPA1+ TPB1­ TPB1+ J01 J02 G01 G02 I/O Port 1 twisted-pair differential signal. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. TPBIAS0 TPBIAS1 D02 K01 O Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection in IEEE Std 1394a-2000 mode. Each of these terminals, except for an unused port, must be decoupled with a 1-µF capacitor to ground. For the unused port, this terminal can be left unconnected. G_RST E04 I NAME NO. CNA PHY Section Cable Interface Reset, Clock, and Miscellaneous Terminals Global power reset. This reset brings all of the TSB83AA22C TSB83AA22C internal LLC-section registers to their default states, including those registers not reset by PCI_RST. When G_RST is asserted, the LLC section is completely nonfunctional. Additionally, G_RST must be asserted a minimum of 2 ms after both 3.3 V and 1.8 V are valid at the device. When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets to the TSB83AA22C TSB83AA22C device. G_RST is designed to be a one-time power-on reset, and PCI_RST must be connected to the PCI bus RST. MFUNC A01 I/O Multifunction. MFUNC is a multifunction terminal whose function is selected via the multifunction select register: Bits 2­0 Introduction PCI_CLKRUN 100­111 20 CYCLEOUT 011 I CYCLEIN 010 D01 General-purpose input/output (GPIO) 001 PCI_RST Function 000 Reserved PCI reset. When this bus reset is asserted, the TSB83AA22C TSB83AA22C device places all LLC-section output buffers in a high-impedance state and resets all LLC-section internal registers except device power-management context and vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the LLC section is completely nonfunctional. This terminal must be connected to PCI bus RST. Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 TERMINAL I/O DESCRIPTION NAME NO. PD K11 I Power down. A high on this terminal turns off all internal circuitry, except the cable-active monitor circuits that control the CNA output. Asserting PD high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic. RESET L10 I Logic reset. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see Power-Up Reset, Section 4.2). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain type driver. R0 R1 A12 A13 SCL C03 Current-setting resistor. These terminals are connected to a precision external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 k ± 1% is required to meet the IEEE Std 1394-1995 output voltage limits. I/O Serial clock. This terminal provides the SCL serial clock signaling. ROM is implemented: Connect terminal 3 to the SCL terminal on the ROM; the 2.7-k resistor pulls this signal to the ROM VCC. (SDA is implemented as open drain.) ROM is not implemented. Connect terminal 3 to ground with a 220- resistor. SDA C04 I/O Serial data. This terminal provides the SDA serial data signaling. This terminal is sampled at G_RST to determine if a serial ROM is implemented; thus if no ROM is implemented, then this terminal must be connected to ground. ROM is implemented: Connect terminal 4 to the SDA terminal on the ROM; the 2.7-k resistor pulls this signal to the ROM VCC. (SDA is implemented as open drain.) ROM is not implemented. Connect terminal 4 to ground with a 220- resistor. SE A04 I Test control. This input is used in the manufacturing test of the TSB83AA22C TSB83AA22C. For normal use, this terminal must be pulled low either through a 1-k resistor to GND or directly to GND. SM B05 I Test control. This input is used in the manufacturing test of the TSB83AA22C TSB83AA22C. For normal use, this terminal must be pulled low either through a 1-k resistor to GND or directly to GND. TESTM L11 I Test control. This input is used in the manufacturing test of the TSB83AA22C TSB83AA22C. For normal use, this terminal must be pulled high through a 1-k resistor to VDD. TESTW N07 I Test control. This input is used in the manufacturing test of the TSB83AA22C TSB83AA22C. For normal use, this terminal must be pulled high through a 1-k resistor to VDD. XI A09 I Oscillator input. This terminal connects to a 98.304-MHz low-jitter external oscillator. XI is a 1.8-V CMOS input. Oscillator jitter must be 5-ps RMS or better. If only 3.3-V oscillators can be acquired, great care must be taken to not introduce significant jitter by the means used to level shift from 3.3 V to 1.8 V. If a resistor divider is used, a high-current oscillator and low-value resistors must be used to minimize RC time constants. Submit Documentation Feedback Introduction 21 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 TERMINAL I/O DESCRIPTION NAME NO. PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 G04 F02 F01 H01 G03 H02 J03 H04 H03 J04 L01 M01 M02 L04 N01 K03 M05 K08 K09 M07 M06 N06 M08 L08 N09 M09 K12 M10 N10 M11 N11 L12 I/O PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 N08 M03 K05 K02 I/O PCI_CLK D03 I PCI_DEVSEL N02 I/O PCI device select. The TSB83AA22C TSB83AA22C device asserts this signal to claim a PCI cycle as the target device. As a PCI initiator, the TSB83AA22C TSB83AA22C device monitors this signal until a target responds. If no target responds before time-out occurs, the TSB83AA22C TSB83AA22C device terminates the cycle with an initiator abort. PCI_FRAME L03 I/O PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME is deasserted, the PCI bus transaction is in the final data phase. PCI_GNT E03 I PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB83AA22C TSB83AA22C device access to the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. PCI_IDSEL L02 I PCI initialization device select. PCI_IDSEL selects the TSB83AA22C TSB83AA22C device during configuration space accesses. PCI_IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. PCI_INTA B03 O PCI interrupt. This output indicates interrupts from the TSB83AA22C TSB83AA22C device to the host. This terminal is implemented as open drain. PCI_IRDY K04 I/O PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCI_CLK where both PCI_IRDY and PCI_TRDY are asserted. PCI_PAR N03 I/O PCI parity. In all PCI bus read and write cycles, the TSB83AA22C TSB83AA22C device calculates even parity across the PCI_AD31­PCI_AD0 and PCI_C/BE0­PCI_C/BE3 buses. As an initiator during PCI cycles, the TSB83AA22C TSB83AA22C device outputs this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (PCI_PERR). 32-Bit PCI Bus Interface 22 Introduction PCI address/data bus. These signals make up the multiplexed PCI address and data on the PCI interface. During the address phase of a PCI cycle, AD31­AD0 contain a 32-bit address or other destination information. During the data phase, AD31­AD0 contain data. PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle, PCI_C/BE3­PCI_C/BE0 define the bus command. During the data phase, this 4-bit bus is used as a byte enable. PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCI_CLK. Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 TERMINAL I/O DESCRIPTION NAME NO. PCI_PERR L06 I/O PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match PCI_PAR and/or PCI_PAR64 PAR64 when PERR_ENB (bit 6) is set to 1 in the command register at offset 04h in the PCI configuration space (see Section 6.1.3, Command Register). PCI_PME F04 O This terminal indicates wake events to the host. It is an open-drain signal which is asserted when PME_STS is asserted and bit 8 (PME_ENB) in the PCI power management control and status register at offset 48h in the PCI configuration space (see Section 6.1.26, Power Management Control and Status Register) has been set. Bit 15 (PME_STS) in the PCI power management control and status register is set due to any unmasked interrupt in the D0 (active) or D1 power state, and on a PHY_LINKON indication in the D2, D3, or D0 (uninitialized) power state. PCI_REQ F03 O PCI bus request. Asserted by the TSB83AA22C TSB83AA22C device to request access to the bus as an initiator. The host arbiter asserts PCI_GNT when the TSB83AA22C TSB83AA22C device has been granted access to the bus. PCI_SERR L07 O PCI system error. When SERR_ENB (bit 8) in the command register at offset 04h in the PCI configuration space (see Section 6.1.3, Command Register) is set to 1, the output is pulsed, indicating an address parity error has occurred. The TSB83AA22C TSB83AA22C device need not be the target of the PCI cycle to assert this signal. This terminal is implemented as open drain. PCI_STOP L05 I/O PCI cycle stop. This signal is driven by a PCI target to request the initiator to stop the current PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. PCI_TRDY J05 I/O PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCI_CLK where both PCI_IRDY and PCI_TRDY are asserted. PCI_ACK64 ACK64 N12 I PCI bus 64-bit transfer acknowledge. This terminal should be pulled high to VDD through a 4.7-k resistor. PCI_REQ64 REQ64 J13 I PCI bus request for 64-bit transfer. This terminal should be pulled high to VDD through a 4.7-k resistor. Submit Documentation Feedback Introduction 23 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 2 Electrical Characteristics 2.1 Absolute Maximum Ratings (1) over operating temperature ranges (unless otherwise noted) MIN ­0.3 AVDD_3.3, DVDD_3.3, PLLVDD_3.3, VCC MAX UNIT 3.6 V VSUP Supply voltage range (2) (3.3 V supplies) VCCP Supply voltage range ­0.5 5.5 V VI Input voltage range for PCI (2) ­0.5 VCCP + 0.5 V VO Output voltage range at any output ­0.5 VSUP + 0.5 V Continuous total power dissipation TA (2) 0 Storage temperature range °C 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground. 2.2 Dissipation Ratings TA 25°C POWER RATING PACKAGE DERATING FACTOR (1) ABOVE TA = 25°C ZAJ ­ PHY section TA = 70°C POWER RATING 15.6 mW/°C ZAJ ­ LLC section (1) 70 ­65 Operating free-air temperature range Tstg (1) See Section 2.2 19.4 mW/°C This is the inverse of the traditional junction-to-ambient thermal resistance (RJA). 2.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VSUP Supply voltage, 3.3-V VDD Supply voltage, core VCCP PCI I/O clamping voltage Nonsource power node 3.3-V operation LREQ, CTL0, CTL1, D0­D7, LCLK LKON, PC0, PC1, PC2, PD, BMODE VIH High-level input voltage RESET PCI interface, 3.3 V (3) MAX 3 3.3 3.6 3 (2) 3.3 3.6 1.85 Source power node NOM (1) 1.95 2.05 V 3 3.3 3.6 V 2.6 3.6 0.6 VSUP 0.475 VCCP VCCP 2 2 V VCCP PHY_PINT, PHY_CTL0, PHY_CTL1, PHY_D0­PHY_D7, PHY_PCLK (3) 24 V 0.7 VSUP PCI interface, 5 V (3) (1) (2) (3) UNIT 3.6 All nominal values are at VDD = 3.3 V and TA = 25°C. For a node that does not source power; see Section 4.2.2.2 in IEEE Std 1394a-2000. Applies to external inputs and bidirectional buffers without hysteresis Electrical Characteristics Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM (1) LREQ, CTL0, CTL1, D0­D7, LCLK MAX LKON, PC0, PC1, PC2, PD, BMODE Low-level input voltage VIL UNIT 1.2 0.2 VSUP RESET 0.3 VSUP PCI interface, 3.3 PCI interface, 5 V (3) 0 PHY_PINT, PHY_CTL0, PHY_CTL1, PHY_D0­PHY_D7, PHY_PCLK (3) 0.325 VCCP 0 V (3) 0.8 0 V 0.8 IOL/OH Output current CTL0, CTL1, D0­D7, CNA, LKON, PINT, PCLK IO Output current TPBIAS outputs RJA = 63.9°C/W, PHY section, TA = 70°C 102.6 TJ Maximum junction temperature (see RJA values listed in thermal characteristics table) RJA = 51.6°C/W, LLC section, TA = 70°C 96.5 TA ­4 4 mA ­5.6 1.3 mA °C Operating ambient temperature 0 25 70 °C 1394b differential input voltage Cable inputs, during data reception 1394a differential input voltage Cable inputs VIC 1394a common-mode input voltage TPB cable inputs tpu Power-up reset time RESET input VI PCI input voltage PCI interface, 3.3 V 0 VCCP V VO PCI output voltage (5) PCI interface, 3.3 V 0 VCCP V tt Input transition time (tr and tf) PCI interface 0 6 ns VID 200 800 During data reception 118 260 During arbitration 168 265 Source power node 0.4706 2.515 Nonsource power node 0.4706 2.015 (2) 2 (4) S100 operation 1394a receive input jitter ±1.08 (4) (5) ±0.5 ±0.315 ±0.8 S200 operation ±0.55 S400 operation Between TPA and TPB cable inputs S200 operation S100 operation 1394a receive input skew V ms S400 operation TPA, TPB cable inputs mV ±0.5 ns ns Time after valid clock received at PHY XI input terminal. Applies to external output buffers. Submit Documentation Feedback Electrical Characteristics 25 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 2.4 Electrical Characteristics, PHY Driver over recommended operating conditions (unless otherwise noted) PARAMETER 1394a differential output voltage VOD TEST CONDITIONS 56 , See Figure 2-1 MIN TYP 265 1394b differential output voltage IDIFF Driver difference current (TPA+, TPA­, TPB+, TPB­) ISP200 ISP200 MAX 172 700 UNIT mV ­1.05 (1) 1.05 (1) mA Common-mode speed signaling current S200 speed signaling enabled (TPB+, TPB­) ­4.84 (2) ­2.53 (2) mA ISP400 ISP400 Common-mode speed signaling current S400 speed signaling enabled (TPB+, TPB­) ­12.4 (2) ­8.1 (2) mA VOFF Off-state differential voltage 20 mV VCM 1394b common-mode voltage (1) (2) Drivers enabled, Speed signaling off Drivers disabled, See Figure 2-1 1.5 V Limits are defined as the algebraic sum of TPA+ and TPA­ driver currents. Limits also apply to TPB+ and TPB­ algebraic sum of driver currents. Limits are defined as the absolute limit of each of TPB+ and TPB­ driver currents. 2.5 Electrical Characteristics, PHY Receiver over recommended operating conditions (unless otherwise noted) PARAMETER ZID Differential impedance TEST CONDITIONS Drivers disabled MIN TYP 4 7 MAX UNIT k 4 20 pF k ZIC Common-mode impedance Drivers disabled 24 pF VTH-R Receiver input threshold voltage Drivers disabled ­30 30 mV VTH­CB Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1 V VTH+ Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV VTH­ Negative arbitration comparator threshold voltage Drivers disabled ­168 ­89 mV Speed signal threshold TPBIAS­TPA common-mode voltage, Drivers disabled 49 131 314 396 VTH­SP200 SP200 VTH­SP400 SP400 26 Electrical Characteristics mV Submit Documentation Feedback TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 2.6 Electrical Characteristics, General PARAMETER TYP MAX 3.3 VDD (1) 91 120 Core VDD (1) 68 75 IDD Supply current VTH TEST CONDITIONS Power status threshold, CPS input (2) MIN VOH 4.7 CTL0, CTL1, D0­D7, CNA, LKON, PCLK outputs High-level output voltage 400-k resistor (2) VDD = 3 V to 3.6 V, IOH = ­4 mA IOH = ­4 mA 2.8 IOH = ­8 mA VCC ­ 0.6 7.5 V IOH = ­0.5 mA PCI interface IOH = ­2 mA 0.9 VCC 2.4 CTL0, CTL1, D0­D7, CNA, LKON, PCLK outputs IOL = 4 mA 0.4 PHY_CTL0, PHY_CTL1, PHY_D0­PHY_D7, PHY_LINKON, PHY_LCLK, Low-level output voltage PHY_LPS VOL mA 2.8 PHY_CTL0, PHY_CTL1, PHY_D0­PHY_D7, PHY_LINKON, PHY_LCLK, PHY_LPS UNIT IOL = 8 mA 0.5 V IOL = 1.5 mA PCI interface 0.1 VCC IOL = 6 mA IOL = 4 mA PCI_PME 0.55 0.5 IBH+ Positive peak bus holder current (D0­D7, CTL0­CTL1, LREQ) VDD = 3.6 V, VI = 0 V to VDD 0.05 1 mA IBH­ Negative peak bus holder current (D0­D7, CTL0­CTL1, LREQ) VDD = 3.6 V, VI = 0 V to VDD ­1 ­0.05 mA IOZ Off-state output current CTL0, CTL1, D0­D7, LKON I/Os VO = VDD or 0 V ±5 LLC portion outputs VO = VDD or 0 V ±20 IIRST Pullup current (RESET input) VI = 1.5 V or 0 V VO TPBIAS output voltage At rated IO current (1) (2) µA ­90 ­20 µA 1.665 2.015 V Repeat max packet (one port receiving maximum-size isochronous packet-8192 bytes, sent on every isochronous interval, S800, data value of 0xCCCC CCCC; two ports repeating; all ports with beta-mode connection), VDD3.3 = 3.3 V, VDDCORE = 1.95 V, TA = 25°C Measured at cable power side of resistor 2.7 Thermal Characteristics PARAMETER RJA Junction-to-free-air thermal resistance RJC Junction-to-case thermal resistance RJA Junction-to-free-air thermal resistance RJC Junction-to-case thermal resistance Submit Documentation Feedback TEST CONDITIONS TYP PHY section: Two-signal, two-plane JEDEC board LLC section: Two-signal, two-plane JEDEC board UNIT 63.9 °C/W 39.3 °C/W 51.6 °C/W 27.1 °C/W Electrical Characteristics 27 TSB83AA22C TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device www.ti.com SLLS802 SLLS802 ­ FEBRUARY 2007 2.8 Switching Characteristics for PHY Portion MIN MAX tr TP differential rise time, transmit PARAMETER 10% to 90% at 1394 connector 0.5 1.2 ns tf TP differential fall time, transmit 90% to 10% at 1394 connector 0.5 1.2 ns tsu Setup time, CTL0, CTL1, D1­D7, LREQ until PCLK-1394a-2000 50% to 50%, See Figure 2-2 2.5 ns th Hold time, CTL0, CTL1, D1­D7, LREQ after PCLK-1394a-2000 50% to 50%, See Figure 2-2 0 ns tsu Setup time, CTL0, CTL1, D1­D7, LREQ until PCLK-1394b 50% to 50%, See Figure 2-2 2.5 ns th Hold time, CTL0, CTL1, D1­D7, LREQ after PCLK-1394b 50% to 50%, See Figure 2-2 0 ns td Delay time, PCLK until CTL0, CTL1, D1­D7, PINT 50% to 50%, See Figure 2-3 0.5 7 MIN MAX 2.9 TEST CONDITIONS UNIT ns Switching Characteristics for PCI Interface PARAMETER UNIT tsu Setup time before PCLK 7 ns th Hold time after PCLK 0 ns tval Delay time, PCLK to data valid 2 ns TPAx+ TPBx+ 56 W TPAx­ TPBx­ S0198-01 S0198-01 Figure 2-1. Test Load Diagram xCLK tsu