TSB82AA2 SCPS079D TSB81BA3 TSB82AA2PGE 144-PQFP TSB82AA2PGEG4 TSB82AA2GGW - Datasheet Archive

 

1394b OHCILynxt Controller Data Manual August 2006 Connectivity Solutions SCPS079D IMPORTANT NOTICE Texas Instruments

 

TSB82AA2 TSB82AA2 1394b OHCILynxt Controller Data Manual August 2006 Connectivity Solutions SCPS079D SCPS079D IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated Contents Section 1 2 3 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 TSB82AA2 TSB82AA2 Data Manual Document History . . . . . . . . . . . . . . . . . . . . . Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSB82AA2 TSB82AA2 Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 3.8 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 CardBus Cis Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 CardBus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . . 3.15 Interrupt Line and Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18 Capability ID and Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . 3.19 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 3.20 Power Management Control and Status Register . . . . . . . . . . . . . . . . 3.21 Power Management Extension Register . . . . . . . . . . . . . . . . . . . . . . . . 3.22 Multifunction Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.23 Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.24 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.25 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.26 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 1-1 1-1 1-2 1-3 1-3 1-3 1-3 2-1 3-1 3-3 3-3 3-4 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-9 3-10 3-11 3-11 3-12 3-12 3-13 3-13 3-14 3-15 3-15 3-16 3-17 3-18 3-19 3-20 iii Section 4 iv Title OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . 4.4 CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Self-ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 Self-ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . 4.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . 4.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . 4.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . 4.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4.27 Initial Bandwidth Available Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 Initial Channels Available High Register . . . . . . . . . . . . . . . . . . . . . . . . 4.29 Initial Channels Available Low Register . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.33 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.34 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.35 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . 4.36 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . 4.37 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.38 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.39 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . 4.40 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . 4.41 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . Page 4-1 4-4 4-4 4-5 4-5 4-5 4-6 4-6 4-7 4-8 4-9 4-9 4-10 4-10 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-19 4-21 4-21 4-22 4-22 4-23 4-23 4-24 4-24 4-25 4-26 4-27 4-27 4-28 4-30 4-31 4-33 4-33 4-34 4-35 Section 5 6 7 8 9 Title 4.42 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 4.43 Isochronous Transmit Context Command Pointer Register . . . . . . . . 4.44 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 4.45 Isochronous Receive Context Command Pointer Register . . . . . . . . 4.46 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . TI Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 DV Timestamp Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 MPEG2 Timestamp Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Isochronous Receive Digital Video Enhancements . . . . . . . . . . . . . . . 5.4 Isochronous Receive Digital Video Enhancements Register . . . . . . . 5.5 Link Enhancement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Timestamp Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Absolute Maximum Ratings Over Operating Temperature Ranges . 8.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Switching Characteristics for PCI Interface . . . . . . . . . . . . . . . . . . . . . . 8.5 Switching Characteristics for PHY-Link Interface . . . . . . . . . . . . . . . . . Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 4-36 4-37 4-37 4-39 4-40 5-1 5-1 5-1 5-2 5-2 5-4 5-6 6-1 7-1 8-1 8-1 8-2 8-3 8-3 8-3 9-1 v List of Illustrations Figure 2-1 2-2 3-1 6-1 vi Title Page PGE-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 GGW-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 TSB82AA2 TSB82AA2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 GPIO Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 List of Tables Table 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 4-1 4-2 4-3 4-4 4-5 Title Signal Names Sorted by PGE Terminal Numbers . . . . . . . . . . . . . . . . . . . Signal Names Sorted by GGW Terminal Numbers . . . . . . . . . . . . . . . . . . . Signal Names Sorted Alphanumerically to Terminal Number . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Bit PCI Bus Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI 64-Bit Bus Extension Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY-Link Interface Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . Latency Timer and Class Cache Line Size Register Description . . . . . . . Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . OHCI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . TI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus CIS Base Address Register Description . . . . . . . . . . . . . . . . . . . CardBus CIS Pointer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Identification Register Description . . . . . . . . . . . . . . . . . . . . . . Interrupt Line and Pin Register Description . . . . . . . . . . . . . . . . . . . . . . . . . MIN_GNT and MAX_LAT Register Description . . . . . . . . . . . . . . . . . . . . . OHCI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID and Next Item Pointer Register Description . . . . . . . . . . . . . Power Management Capabilities Register Description . . . . . . . . . . . . . . . Power Management Control and Status Register Description . . . . . . . . . Power Management Extension Register Description . . . . . . . . . . . . . . . . . Multifunction Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . . Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GUID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . . CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2-3 2-4 2-5 2-6 2-7 2-8 2-10 2-11 3-1 3-3 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-9 3-10 3-11 3-12 3-12 3-13 3-13 3-14 3-15 3-15 3-16 3-17 3-18 3-19 3-20 4-1 4-4 4-4 4-5 4-6 vii Table 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 5-1 5-2 5-3 5-4 7-1 viii Title Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . Posted Write Address Low Register Description . . . . . . . . . . . . . . . . . . . . Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . . Vendor ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Channel Mask High Register Description . . . . . . . Isochronous Receive Channel Mask Low Register Description . . . . . . . . Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . . Isochronous Receive Interrupt Event Register Description . . . . . . . . . . . Initial Bandwith Available Register Description . . . . . . . . . . . . . . . . . . . . . . Initial Channels Available High Register Description . . . . . . . . . . . . . . . . . Initial Channels Available Low Register Description . . . . . . . . . . . . . . . . . Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . . Asynchronous Request Filter High Register Description . . . . . . . . . . . . . Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . . Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . . Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . . Asynchronous Context Command Pointer Register Description . . . . . . . Isochronous Transmit Context Control Register Description . . . . . . . . . . Isochronous Receive Context Control Register Description . . . . . . . . . . . Isochronous Receive Context Match Register Description . . . . . . . . . . . . TI Extension Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Digital Video Enhancements Register Description Link Enhancement Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Timestamp Offset Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 4-6 4-8 4-10 4-10 4-10 4-11 4-12 4-14 4-15 4-16 4-17 4-19 4-21 4-22 4-23 4-23 4-24 4-24 4-25 4-26 4-27 4-27 4-28 4-30 4-31 4-33 4-34 4-35 4-36 4-37 4-40 5-1 5-2 5-4 5-6 7-2 1 Introduction This chapter provides an overview of the Texas Instruments TSB82AA2 TSB82AA2 device and its features. 1.1 Description The TSB82AA2 TSB82AA2 OHCI-Lynx controller is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today's 1394 bus designs. The TSB82AA2 TSB82AA2 device is capable of exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB82AA2 TSB82AA2 device also provides outstanding ultra-low power operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates. The TSB82AA2 TSB82AA2 improved throughput and increased bandwidth make it ideal for today's high-end PCs and open the door for the development of S800 RAID- and SAN-based peripherals. The TSB82AA2 TSB82AA2 OHCI-Lynx controller operates as the interface between a 33-MHz/64-bit or 33-MHz/32-bit PCI local bus and a compatible 1394b PHY-layer device (such as the TSB81BA3 TSB81BA3 device) that is capable of supporting serial data rates at 98.304M, 196.608M, 393.216M, or 786.432M bits/s (referred to as S100, S200, S400, or S800 speeds, respectively). When acting as a PCI bus master, the TSB82AA2 TSB82AA2 device is capable of multiple cacheline bursts of data, which can transfer at 264M bytes/s for 64-bit transfers or 132M bytes/s for 32-bit transfers after connecting to the memory controller. Due to the high throughput potential of the TSB82AA2 TSB82AA2 device, it possible to encounter large PCI and legacy 1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the TSB82AA2 TSB82AA2 implements deep transmit and receive FIFOs (see Section 1.2, Features, for FIFO size information) to buffer the 1394 data, thus preventing possible problems due to bus latency. This also ensures that the device can transmit and receive sustained maximum size isochronous or asynchronous data payloads at S800. The TSB82AA2 TSB82AA2 device implements other performance enhancements to improve overall performance of the device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing buffers, multiple isochronous contexts, and advanced internal arbitration. The TSB82AA2 TSB82AA2 device also implements hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at TI extension offset A80h (see Section 5.4, Isochronous Receive Digital Video Enhancements Register). These enhancements include automatic time stamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for received DV streams. The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video CIP formats. The TSB82AA2 TSB82AA2 device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale-that is, less than the current cycle timer when the packet is transmitted. The TSB82AA2 TSB82AA2 performance and enhanced throughput make it an excellent choice for today's 1394 PC market; however, the portable, mobile, and even today's desktop PCs power management schemes continue to require devices to use less and less power, and the TI 1394 OHCI-Lynx product line has continued to raise the bar by providing the lowest power 1394 link-layers in the industry. The TSB82AA2 TSB82AA2 device represents the next evolution of TI commitment to meet the challenge of power-sensitive applications. The TSB82AA2 TSB82AA2 device has ultra-low operational power requirements and intelligent power management capabilities that allow it to autonomously conserve power based on the device usage. One of the key elements for reducing the TSB82AA2 TSB82AA2 operational power requirements is the TI advanced CMOS process and the implementation of an internal 1.8-V core, which is supplied by an improved integrated 3.3-V to 1.8-V voltage regulator. The TSB82AA2 TSB82AA2 device implements a next-generation voltage regulator that is more efficient than 1-1 its predecessors, thus providing an overall reduction in the device operational power requirements especially when operating in D3cold using auxiliary power. In fact, the TSB82AA2 TSB82AA2 device fully supports D0, D1, D2, and D3hot/cold power states as specified in the PC 2001 Design Guide requirements and the PCI Power Management Specification. PME wake event support is subject to operating system support and implementation. As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB82AA2 TSB82AA2 device is fully compliant with the latest PCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Draft Std 1394b, IEEE Std 1394a-2000, and 1394 Open Host Controller Interface Specification (see Section 1.3, Related Documents, for a complete list). 1.2 Features The TSB82AA2 TSB82AA2 device supports the following features: · Single 3.3-V supply (1.8-V internal core voltage with regulator) · 3.3-V and 5-V PCI signaling environments · Serial bus data rates of 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s · Physical write posting of up to three outstanding transactions · Serial ROM or boot ROM interface supports 2-wire serial EEPROM devices · 33-MHz/64-bit and 33-MHz/32-bit selectable PCI interface · Multifunction terminal (MFUNC terminal 1) - - - · PCI_CLKRUN protocol per the PCI Mobile Design Guide General-purpose I/O CYCLEIN/CYCLEOUT for external cycle timer control for customized synchronization PCI burst transfers and deep FIFOs to tolerate large host latency - - - - Transmit FIFO-5K asynchronous Transmit FIFO-2K isochronous Receive FIFO-2K asynchronous Receive FIFO-2K isochronous · · Programmable asynchronous transmit threshold · Isochronous receive dual-buffer mode · Out-of-order pipelining for asynchronous transmit requests · Register access fail interrupt when the PHY SYSCLK is not active · Initial bandwidth available and initial channels available registers · Digital video and audio performance enhancements · Fabricated in advanced low-power CMOS process · 1-2 D0, D1, D2, and D3 power states and PME events per the PCI Bus Power Management Interface Specification Packaged in 144-terminal LQFP (PGE) or 176-ball MicroStar BGA (GGW package) 1.3 Related Documents · 1394 Open Host Controller Interface Specification (Revision 1.2) · IEEE Standard for a High-Performance Serial Bus (IEEE Std 1394-1995) · IEEE Standard for a High-Performance Serial Bus-Amendment 1 (IEEE Std 1394a-2000) · P1394b Draft Standard for High-Performance Serial Bus (Supplement) · PC 2001 Design Guide · PCI Bus Power Management Interface Specification (Revision 1.1) · PCI Local Bus Specification (Revision 2.3) · Serial Bus Protocol 2 (SBP-2) · Microsoft Windows Logo Program System and Device Requirements (Version 0.5) · Microsoft Windows Logo Program Desktop and Mobile PC Requirements (Version 1.1) · Digital Interface for Consumer Electronic Audio/Video Equipment Draft (Version 2.1) (IEC 61883) 1.4 Trademarks MicroStar BGA and OHCI-Lynx are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 1.5 Ordering Information ORDERING NUMBER NAME PACKAGE COMMENT TSB82AA2PGE TSB82AA2PGE OHCI-Lynxt PCI-Based IEEE 1394 Host Controller 144-PQFP 144-PQFP Standard lead (Pb) device TSB82AA2PGEG4 TSB82AA2PGEG4 OHCI-Lynxt PCI-Based IEEE 1394 Host Controller 144-PQFP 144-PQFP Lead-free (Pb-free) device with RoHS TSB82AA2GGW TSB82AA2GGW OHCI-Lynxt PCI-Based IEEE 1394 Host Controller 176-ball PBGA Standard lead (Pb) device TSB82AA2ZGW TSB82AA2ZGW OHCI-Lynxt PCI-Based IEEE 1394 Host Controller 176-ball PBGA Lead-free (Pb-free) device with RoHS 1.6 TSB82AA2 TSB82AA2 Data Manual Document History DATE REVISION PAGE PARAGRAPH DESCRIPTION 02/2003 Initial release 09/2003 A 1-3, 8-2 1.5, 8.2 Add "I" temperature version 05/2005 B 1-2, 1-3, 2-1 through 2-12, 9-2 1.2, 1.5, Chapter 2, Chapter 9 Added GGW package Deleted "I" temperature version 1-3 1-4 2 Terminal Descriptions 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PCI_AD43 PCI_AD44 PCI_AD45 PCI_AD46 PCI_AD47 GND VCC PCI_AD48 PCI_AD49 PCI_AD50 PCI_AD51 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 GND PCI_AD56 VCCP PCI_AD57 PCI_AD58 PCI_AD59 REG18 REG18 V CC PCI_AD60 PCI_AD61 PCI_AD62 PCI_AD63 GND PCI_PAR64 PAR64 PCI_C/BE4 PCI_C/BE5 PCI_C/BE6 GND VCC PCI_C/BE7 PCI_REQ64 REQ64 This section provides the terminal descriptions for the TSB82AA2 TSB82AA2 device. Figure 2-1 and Figure 2-2 show the signal assigned to each terminal in the PGE and GGW packages, respectively. Table 2-1, Table 2-2, and Table 2-3 provide a cross-reference between each terminal number and the name of the signal on that terminal. Table 2-1 is arranged in terminal number order for the PGE package, Table 2-2 is arranged in terminal number order for the GGW package, and Table 2-3 lists the signals in alphanumerical order. 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 143 144 PCI_ACK64 ACK64 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 GND VCC PCI_C/BE0 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 VCCP PCI_AD13 PCI_AD14 GND PCI_AD15 PCI_C/BE1 PCI_PAR PCI_SERR PCI_PERR PCI_STOP PCI_DEVSEL PCI_TRDY GND VCC PCI_IRDY PCI_FRAME PCI_C/BE2 PCI_AD16 PCI_AD17 MFUNC REG_EN SCL SDA PCI_INTA PCI_RST G_RST VCC GND PCI_CLK NC PCI_GNT PCI_REQ PCI_PME VCC REG18 REG18 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 VCCP GND PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_C/BE3 PCI_IDSEL PCI_AD23 PCI_AD22 VCC GND PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD42 PCI_AD41 PCI_AD40 GND PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 VCCP PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 GND PHY_D7 PHY_D6 PHY_D5 VCC GND PHY_D4 PHY_D3 PHY_D2 PHY_D1 PHY_D0 PHY_CTL1 PHY_CTL0 VCC PHY_LCLK GND PHY_PCLK VCC GND PHY_LREQ PHY_LINKON PHY_PINT PHY_LPS Figure 2-1. PGE-Package Terminal Diagram 2-1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC U 2 PCI_ AD16 PCI_ IRDY NC PCI_ DEVSEL PCI_ SERR PCI_ PAR PCI_ AD15 VCCP PCI_ AD9 NC PCI_ AD7 PCI_ AD4 PCI_ AD1 PCI_ ACK64 ACK64 PCI_ AD17 PCI_ FRAME NC PCI_ TRDY PCI_ PERR NC PCI_ AD13 PCI_ AD12 PCI_ AD8 NC PCI_ AD6 PCI_ AD3 PCI_ AD0 PCI_ C/BE2 VCC GND NC NC PCI_ AD14 PCI_ AD10 PCI_ C/BE0 GND PCI_ AD5 PCI_ AD2 PCI_ STOP PCI_ C/BE1 GND PCI_ AD11 VCC T NC R PCI_ AD18 NC P PCI_ AD21 PCI_ AD20 PCI_ AD19 N VCC NC M PCI_ IDSEL L 17 NC PCI_ REQ64 REQ64 PCI_ C/BE7 VCC NC NC GND GND PCI_ C/BE6 PCI_ C/BE5 PCI_ AD23 PCI_ AD22 PCI_ C/BE4 NC PCI_ PAR64 PAR64 PCI_ AD26 PCI_ AD25 PCI_ AD24 PCI_ C/BE3 GND PCI_ AD63 PCI_ AD62 PCI_ AD61 K VCCP NC PCI_ AD27 GND VCC REG18 REG18 PCI_ AD59 PCI_ AD60 J PCI_ AD30 PCI_ AD28 NC PCI_ AD29 PCI_ AD57 NC NC PCI_ AD58 H PCI_ PME PCI_ AD31 REG18 REG18 VCC GND PCI_ AD55 PCI_ AD56 VCCP G PCI_ REQ PCI_ GNT PCI_ CLK GND PCI_ AD51 PCI_ AD52 PCI_ AD53 PCI_ AD54 F NC NC VCC PCI_ AD48 PCI_ AD49 PCI_ AD50 E G_RST PCI_ RST PCI_ INTA GND NC VCC D SDA SCL REG_ EN PCI_ AD45 PCI_ AD46 PCI_ AD47 C MFUNC NC PCI_ AD43 PCI_ AD44 B NC VCC PHY_ D0 GND PHY_ D7 PCI_ AD35 1 VCC GND NC NC PHY_ D4 PHY_ D6 PCI_ AD34 PCI_ AD37 GND PCI_ AD42 PHY_ LPS PHY_ LREQ NC NC PHY_ CTL0 PHY_ D1 PHY_ D3 PHY_ D5 PCI_ AD33 PCI_ AD36 PCI_ AD39 PCI_ AD41 NC NC A PHY_ LINK ON PHY_ PINT GND PHY_ PCLK PHY_ LCLK PHY_ CTL1 PHY_ D2 VCC GND PCI_ AD32 VCCP PCI_ AD38 PCI_ AD40 NC NC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 2-2. GGW-Package Terminal Diagram 2-2 NC 17 Table 2-1. Signal Names Sorted by PGE Terminal Numbers NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME 1 MFUNC 37 PCI_AD17 73 PCI_REQ64 REQ64 109 PCI_AD42 2 REG_EN 38 PCI_AD16 74 PCI_C/BE7 110 PCI_AD41 3 SCL 39 PCI_C/BE2 75 PCI_AD40 SDA 40 PCI_FRAME 76 VCC GND 111 4 112 GND 5 PCI_INTA 41 PCI_IRDY 77 PCI_C/BE6 113 PCI_AD39 6 PCI_RST 42 PCI_C/BE5 114 PCI_AD38 G_RST 43 VCC GND 78 7 79 PCI_C/BE4 115 PCI_AD37 8 VCC GND 44 PCI_TRDY 80 PCI_PAR64 PAR64 116 PCI_AD36 9 45 PCI_DEVSEL 81 GND 117 10 PCI_CLK 46 PCI_STOP 82 PCI_AD63 118 VCCP PCI_AD35 11 NC 47 PCI_PERR 83 PCI_AD62 119 PCI_AD34 12 PCI_GNT 48 PCI_SERR 84 PCI_AD61 120 PCI_AD33 13 PCI_REQ 49 PCI_PAR 85 PCI_AD60 121 PCI_AD32 14 PCI_PME 50 PCI_C/BE1 86 122 GND 15 51 PCI_AD15 87 123 PHY_D7 16 VCC REG18 REG18 VCC REG18 REG18 52 GND 88 PCI_AD59 124 PHY_D6 17 PCI_AD31 53 PCI_AD14 89 PCI_AD58 125 PHY_D5 18 PCI_AD30 54 PCI_AD13 90 PCI_AD57 126 19 PCI_AD29 55 91 PCI_AD28 56 VCCP PCI_AD56 127 20 VCCP PCI_AD12 VCC GND 128 PHY_D4 21 VCCP GND 57 PCI_AD11 93 GND 129 PHY_D3 22 58 PCI_AD10 94 PCI_AD55 130 PHY_D2 23 PCI_AD27 59 PCI_AD9 95 PCI_AD54 131 PHY_D1 24 PCI_AD26 60 PCI_AD8 96 PCI_AD53 132 PHY_D0 25 PCI_AD25 61 PCI_C/BE0 97 PCI_AD52 133 PHY_CTL1 26 PCI_AD24 62 PCI_AD51 134 PHY_CTL0 PCI_C/BE3 63 VCC GND 98 27 99 PCI_AD50 135 28 PCI_IDSEL 64 PCI_AD7 100 PCI_AD49 136 VCC PHY_LCLK 29 PCI_AD23 65 PCI_AD6 101 PCI_AD48 137 GND 30 PCI_AD22 66 PCI_AD5 102 138 PHY_PCLK 31 67 PCI_AD4 103 139 32 VCC GND VCC GND 68 PCI_AD3 104 PCI_AD47 140 VCC GND 33 PCI_AD21 69 PCI_AD2 105 PCI_AD46 141 PHY_LREQ 34 PCI_AD20 70 PCI_AD1 106 PCI_AD45 142 PHY_LINKON 35 PCI_AD19 71 PCI_AD0 107 PCI_AD44 143 PHY_PINT 36 PCI_AD18 72 PCI_ACK64 ACK64 108 PCI_AD43 144 PHY_LPS 92 2-3 Table 2-2. Signal Names Sorted by GGW Terminal Numbers TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME A02 NC C17 PCI_AD44 J14 PCI_AD57 R02 NC A03 PHY_PINT D01 SDA J15 NC R04 PCI_C/BE2 A04 GND D02 SCL J16 NC R05 A05 PHY_PCLK D03 REG_EN J17 PCI_AD58 R06 VCC GND A06 PHY_LCLK D07 K01 NC PHY_CTL1 D08 K02 VCCP NC R07 A07 VCC PHY_D0 R08 NC A08 PHY_D2 D09 GND K03 PCI_AD27 R09 PCI_AD14 A09 D10 PHY_D7 K04 GND R10 PCI_AD10 A10 VCC GND D11 PCI_AD35 K14 PCI_C/BE0 PCI_AD32 D15 PCI_AD45 K15 VCC REG18 REG18 R11 A11 R12 GND A12 D16 PCI_AD46 K16 PCI_AD59 R13 PCI_AD5 A13 VCCP PCI_AD38 D17 PCI_AD47 K17 PCI_AD60 R14 PCI_AD2 A14 PCI_AD40 E01 G_RST L01 PCI_AD26 R16 PCI_REQ64 REQ64 A15 NC E02 PCI_RST L02 PCI_AD25 R17 PCI_C/BE7 A16 NC E03 PCI_INTA L03 PCI_AD24 T01 NC B01 NC E15 GND L04 PCI_C/BE3 T03 PCI_AD17 B03 PHY_LPS E16 NC L14 GND T04 PCI_FRAME B04 PHY_LREQ E17 L15 PCI_AD63 T05 NC B05 NC F01 VCC NC L16 PCI_AD62 T06 PCI_TRDY B06 NC F02 NC L17 PCI_AD61 T07 PCI_PERR B07 PHY_CTL0 F03 M01 PCI_IDSEL T08 NC B08 PHY_D1 F15 VCC PCI_AD48 M02 PCI_AD23 T09 PCI_AD13 B09 PHY_D3 F16 PCI_AD49 M03 PCI_AD22 T10 PCI_AD12 B10 PHY_D5 F17 PCI_AD50 M15 PCI_C/BE4 T11 PCI_AD8 B11 PCI_AD33 G01 PCI_REQ M16 NC T12 NC B12 PCI_AD36 G02 PCI_GNT M17 PCI_PAR64 PAR64 T13 PCI_AD6 B13 PCI_AD39 G03 PCI_CLK N01 T14 PCI_AD3 B14 PCI_AD41 G04 GND N02 VCC NC T15 PCI_AD0 B15 NC G14 PCI_AD51 N03 GND T17 NC B17 G15 PCI_AD52 N15 GND U02 NC MFUNC G16 PCI_AD53 N16 PCI_C/BE6 U03 PCI_AD16 C02 NC G17 PCI_AD54 N17 PCI_C/BE5 U04 PCI_IRDY C04 PHY_LINKON H01 PCI_PME P01 PCI_AD21 U05 NC C05 VCC GND H02 PCI_AD31 P02 PCI_AD20 U06 PCI_DEVSEL C06 H03 REG18 REG18 P03 PCI_AD19 U07 PCI_SERR C07 NC H04 PCI_STOP U08 PCI_PAR NC H14 VCC GND P07 C08 P08 PCI_C/BE1 U09 PCI_AD15 C09 PHY_D4 H15 PCI_AD55 P09 GND U10 C10 PHY_D6 H16 PCI_AD56 P10 PCI_AD11 U11 VCCP PCI_AD9 C11 PCI_AD34 H17 NC J01 P15 VCC VCC U12 PCI_AD37 VCCP PCI_AD30 P11 C12 U13 PCI_AD7 C13 GND J02 PCI_AD28 P16 NC U14 PCI_AD4 C14 PCI_AD42 J03 NC P17 NC U15 PCI_AD1 C16 2-4 NC C01 PCI_AD43 J04 PCI_AD29 R01 PCI_AD18 U16 PCI_ACK64 ACK64 Table 2-3. Signal Names Sorted Alphanumerically to Terminal Number NUMBER TERMINAL NAME NUMBER TERMINAL NAME NUMBER TERMINAL NAME PGE GGW PGE GGW PGE GGW GND 9 A04 PCI_AD17 37 T03 PCI_AD53 96 G16 GND 22 A10 PCI_AD18 36 R01 PCI_AD54 95 G17 GND 32 C06 PCI_AD19 35 P03 PCI_AD55 94 H15 GND 43 C13 PCI_AD20 34 P02 PCI_AD56 92 H16 GND 52 D09 PCI_AD21 33 P01 PCI_AD57 90 J14 GND 63 E15 PCI_AD22 30 M03 PCI_AD58 89 J17 GND 76 G04 PCI_AD23 29 M02 PCI_AD59 88 K16 GND 81 H14 PCI_AD24 26 L03 PCI_AD60 85 K17 GND 93 K04 PCI_AD25 25 L02 PCI_AD61 84 L17 GND 103 L14 PCI_AD26 24 L01 PCI_AD62 83 L16 GND 112 N03 PCI_AD27 23 K03 PCI_AD63 82 L15 GND 122 N15 PCI_AD28 20 J02 PCI_CLK 10 G03 GND 127 P09 PCI_AD29 19 J04 PCI_C/BE0 61 R11 GND 137 R06 PCI_AD30 18 J01 PCI_C/BE1 50 P08 GND 140 R12 PCI_AD31 17 H02 PCI_C/BE2 39 R04 G_RST 7 E01 PCI_AD32 121 A11 PCI_C/BE3 27 L04 MFUNC 1 C01 PCI_AD33 120 B11 PCI_C/BE4 79 M15 NC 11 A02, A15, A16, B01, B05, B06, B15, B17, C02, C07, C08, E16, F01, F02, J03, J15, J16, K02, M16, N02, P16, P17, R02, R07, R08, T01, T05, T08, T12, T17, U02, U05, U12, PCI_AD34 119 C11 PCI_C/BE5 78 N17 PCI_ACK64 ACK64 72 U16 PCI_AD35 118 D11 PCI_C/BE6 77 N16 PCI_AD0 71 T15 PCI_AD36 116 B12 PCI_C/BE7 74 R17 PCI_AD1 70 U15 PCI_AD37 115 C12 PCI_DEVSEL 45 U06 PCI_AD2 69 R14 PCI_AD38 114 A13 PCI_FRAME 40 T04 PCI_AD3 68 T14 PCI_AD39 113 B13 PCI_GNT 12 G02 PCI_AD4 67 U14 PCI_AD40 111 A14 PCI_IDSEL 28 M01 PCI_AD5 66 R13 PCI_AD41 110 B14 PCI_INTA 5 E03 PCI_AD6 65 T13 PCI_AD42 109 C14 PCI_IRDY 41 U04 PCI_AD7 64 U13 PCI_AD43 108 C16 PCI_PAR 49 U08 PCI_AD8 60 T11 PCI_AD44 107 C17 PCI_PAR64 PAR64 80 M17 PCI_AD9 59 U11 PCI_AD45 106 D15 PCI_PERR 47 T07 PCI_AD10 58 R10 PCI_AD46 105 D16 PCI_PME 14 H01 PCI_AD11 57 P10 PCI_AD47 104 D17 PCI_REQ 13 G01 PCI_AD12 56 T10 PCI_AD48 101 F15 PCI_REQ64 REQ64 73 R16 PCI_AD13 54 T09 PCI_AD49 100 F16 PCI_RST 6 E02 PCI_AD14 53 R09 PCI_AD50 99 F17 PCI_SERR 48 U07 PCI_AD15 51 U09 PCI_AD51 98 G14 PCI_STOP 46 P07 PCI_AD16 38 U03 PCI_AD52 97 G15 PCI_TRDY 44 T06 2-5 Table 2-3. Signal Names Sorted Alphanumerically to Terminal Number (Continued) NUMBER TERMINAL NAME NUMBER TERMINAL NAME NUMBER PGE GGW PGE GGW PHY_CTL0 134 B07 PHY_LPS 144 B03 PHY_CTL1 133 A07 PHY_LREQ 141 B04 PHY_D0 132 D08 PHY_PCLK 138 A05 PHY_D1 131 B08 PHY_PINT 143 A03 PHY_D2 130 A08 REG_EN 2 D03 PHY_D3 129 B09 REG18 REG18 16 H03 PHY_D4 128 C09 REG18 REG18 87 K15 PHY_D5 125 B10 SCL 3 D02 PHY_D6 124 C10 SDA 4 D01 TERMINAL NAME PHY_D7 123 D10 A09 136 A06 VCC VCC 8 PHY_LCLK 15 C05 PHY_LINKON 142 C04 VCC 31 D07 PGE GGW VCC VCC 42 E17 62 F03 VCC VCC 75 H04 86 K14 VCC VCC 102 N01 126 P11 VCC VCC 135 P15 139 R05 VCCP VCCP 21 A12 55 H17 VCCP VCCP 91 K01 117 U10 The terminals are grouped in tables by functionality, such as PCI system function and power supply function (see Table 2-4 through Table 2-8). The terminal numbers are also listed for convenient reference. Table 2-4. Power Supply Terminals TERMINAL NUMBER I/O DESCRIPTION A04, A10, C06, C13, D09, E15, G04, H14, K04, L14, N03, N15, P09, R06, R12 - Ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. 16 87 H03 K15 - The REG18 REG18 terminals are connected to the internal 1.8-V core voltage. They provide a mechanism to provide local bypass for the internal core voltage or to externally provide the 1.8 V to the core if the internal regulator is disabled. 2 D03 I Regulator enable. When this terminal is low, the internal regulator is enabled and generates the 1.8-V internal core voltage from the 3.3-V supply voltage. If it is disabled, then 1.8 V must be provided to the REG18 REG18 terminals for normal operation. VCC 8, 15, 31, 42, 62, 75, 86, 102, 126, 135, 139 A09, C05, D07, E17, F03, H04, K14, N01, P11, P15, R05 - 3.3-V power supply terminals. A parallel combination of high frequency decoupling capacitors near each terminal is suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. They must be tied to a low-impedance point on the circuit board. VCCP 21, 55, 91, 117 A12, H17, K01, U10 - PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification. In addition, if a 5-V ROM is used, then the VCCP terminal must be connected to 5 V. NAME PGE GGW 9, 22, 32, 43, 52, 63, 76, 81, 93, 103, 112, 122, 127, 137, 140 REG18 REG18 REG_EN GND 2-6 Table 2-5. Reset and Miscellaneous Terminals TERMINAL NUMBER NAME G_RST PGE 7 I/O DESCRIPTION I Global power reset. This reset brings all of the TSB82AA2 TSB82AA2 internal registers to their default states, including those registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional. Additionally, G_RST must be asserted a minimum of 2 ms after both 3.3 V and 1.8 V are valid at the device. GGW E01 When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets to the TSB82AA2 TSB82AA2 device. G_RST is designed to be a one-time power-on reset, and PCI_RST must be connected to the PCI bus RST. Multifunction terminal. MFUNC is a multifunction terminal whose function is selected via the multifunction select register: MFUNC PCI_RST 1 6 C01 E02 I/O I Bits 2-0 000 001 010 011 100-111 Function General-purpose input/output (GPIO) CYCLEIN CYCLEOUT PCI_CLKRUN Reserved PCI reset. When this bus reset is asserted, the TSB82AA2 TSB82AA2 device places all output buffers in a high-impedance state and resets all internal registers except device power management context and vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional. This terminal must be connected to PCI bus RST. Serial clock. This terminal provides the SCL serial clock signaling. SCL 3 D02 I/O ROM is implemented: Connect terminal 3 to the SCL terminal on the ROM; the 2.7-k resistor pulls this signal to the ROM VCC. (SDA is implemented as open-drain.) ROM is not implemented. Connect terminal 3 to ground with a 220- resistor. Serial data. This terminal provides the SDA serial data signaling. This terminal is sampled at G_RST to determine if a serial ROM is implemented; thus if no ROM is implemented, then this terminal must be connected to ground. SDA 4 D01 I/O ROM is implemented: Connect terminal 4 to the SDA terminal on the ROM; the 2.7-k resistor pulls this signal to the ROM VCC. (SDA is implemented as open-drain.) ROM is not implemented. Connect terminal 4 to ground with a 220- resistor. 2-7 Table 2-6. 32-Bit PCI Bus Terminals TERMINAL NUMBER NAME I/O DESCRIPTION H02 J01 J04 J02 K03 L01 L02 L03 M02 M03 P01 P02 P03 R01 T03 U03 U09 R09 T09 T10 P10 R10 U11 T11 U13 T13 R13 U14 T14 R14 U15 T15 I/O PCI address/data bus for the lower DWORD. These signals make up the multiplexed PCI address and data bus for the lower 32 bits on the PCI interface. During the address phase of a PCI cycle, AD31-AD0 AD31-AD0 contain a 32-bit address or other destination information. During the data phase, AD31-AD0 AD31-AD0 contain data. 61 50 39 27 R11 P08 R04 L04 I/O PCI bus commands and byte enables for lower DWORD. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle, PCI_C/BE3-PCI_C/BE0 define the bus command. During the data phase, this 4-bit bus is used as a byte enable for the lower 32 bits of data. 10 G03 I PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCI_CLK. PGE GGW PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 17 18 19 20 23 24 25 26 29 30 33 34 35 36 37 38 51 53 54 56 57 58 59 60 64 65 66 67 68 69 70 71 PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 PCI_CLK PCI_DEVSEL 45 U06 I/O PCI device select. The TSB82AA2 TSB82AA2 device asserts this signal to claim a PCI cycle as the target device. As a PCI initiator, the TSB82AA2 TSB82AA2 device monitors this signal until a target responds. If no target responds before time-out occurs, then the TSB82AA2 TSB82AA2 device terminates the cycle with an initiator abort. PCI_FRAME 40 T04 I/O PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME is deasserted, the PCI bus transaction is in the final data phase. PCI_GNT 12 G02 I PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB82AA2 TSB82AA2 device access to the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI bus request, depending upon the PCI bus parking algorithm. PCI_IDSEL 28 M01 I Initialization device select. PCI_IDSEL selects the TSB82AA2 TSB82AA2 device during configuration space accesses. PCI_IDSEL can be connected to 1 of the upper 24 PCI address lines on the PCI bus. PCI_INTA 5 E03 O Interrupt signal. This output indicates interrupts from the TSB82AA2 TSB82AA2 device to the host. This terminal is implemented as open-drain. 2-8 Table 2-6. 32-Bit PCI Bus Terminals (Continued) TERMINAL NUMBER NAME PCI_IRDY PGE 41 U04 I/O DESCRIPTION I/O PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and PCI_TRDY are asserted. GGW PCI_PAR 49 U08 I/O PCI parity. In all PCI bus read and write cycles, the TSB82AA2 TSB82AA2 device calculates even parity across the PCI_AD31-PCI AD31-PCI_AD0 and PCI_C/BE0-PCI_C/BE3 buses. As an initiator during PCI cycles, the TSB82AA2 TSB82AA2 device outputs this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (PCI_PERR). PCI_PERR 47 T07 I/O PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match PCI_PAR and/or PCI_PAR64 PAR64 when PERR_ENB (bit 6) is set to 1 in the command register at offset 04h in the PCI configuration space (see Section 3.4, Command Register). PCI_PME 14 H01 O This terminal indicates wake events to the host. It is an open-drain signal which is asserted when PME_STS is asserted and bit 8 (PME_ENB) in the PCI power management control and status register at offset 48h in the PCI configuration space (see Section 3.20, Power Management Control and Status Register) has been set. Bit 15 (PME_STS) in the PCI power management control and status register is set due to any unmasked interrupt in the D0 (active) or D1 power state, and on a PHY_LINKON indication in the D2, D3, or D0 (uninitialized) power state. PCI_REQ 13 G01 O PCI bus request. Asserted by the TSB82AA2 TSB82AA2 device to request access to the bus as an initiator. The host arbiter asserts PCI_GNT when the TSB82AA2 TSB82AA2 device has been granted access to the bus. PCI_SERR 48 U07 O PCI system error. When SERR_ENB (bit 8) in the command register at offset 04h in the PCI configuration space (see Section 3.4, Command Register) is set to 1, the output is pulsed, indicating an address parity error has occurred. The TSB82AA2 TSB82AA2 device need not be the target of the PCI cycle to assert this signal. This terminal is implemented as open-drain. PCI_STOP 46 P07 I/O PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do not support burst data transfers. PCI_TRDY 44 T06 I/O PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and PCI_TRDY are asserted. 2-9 Table 2-7. PCI 64-Bit Bus Extension Terminals TERMINAL NUMBER NAME PGE PCI_ACK64 ACK64 72 U16 PCI_AD63 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 PCI_AD56 PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 PCI_AD47 PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 PCI_AD40 PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 82 83 84 85 88 89 90 92 94 95 96 97 98 99 100 101 104 105 106 107 108 109 110 111 113 114 115 116 118 119 120 121 L15 L16 L17 K17 K16 J17 J14 H16 H15 G17 G16 G15 G14 F17 F16 F15 D17 D16 D15 C17 C16 C14 B14 A14 B13 A13 C12 B12 D11 C11 B11 A11 PCI_C/BE7 PCI_C/BE6 PCI_C/BE5 PCI_C/BE4 74 77 78 79 R17 N16 N17 M15 PCI_PAR64 PAR64 PCI_REQ64 REQ64 2-10 80 73 I/O DESCRIPTION I PCI bus 64-bit transfer acknowledge. Asserted by a target if it is willing to accept a 64-bit data transfer when it positively decodes its address for a memory transaction and the master has requested a 64-bit data transfer by asserting PCI_REQ64 REQ64. PCI_REQ64 REQ64 has identical timing to PCI_DEVSEL. When the TSB82AA2 TSB82AA2 device is bus master, it monitors PCI_REQ64 REQ64 when it has requested a 64-bit data transfer for the current transaction. If the target asserts PCI_REQ64 REQ64 when it claims the cycle, then the TSB82AA2 TSB82AA2 device transfers data using 64 bits. As a target, the TSB82AA2 TSB82AA2 does not support 64-bit data transfers and never asserts PCI_REQ64 REQ64 when another master has requested 64-bit transfer. I/O PCI address/data bus for the upper DWORD. These signals make up the multiplexed PCI address and data bus for the upper 32 bits of the PCI interface. During the address phase of a dual address command with PCI_REQ64 REQ64 asserted, AD63-AD32 AD63-AD32 contain the upper 32 bits of a 64-bit address. During the data phase, AD63-AD32 AD63-AD32 contain data when a 64-bit transfer has been negotiated by the assertion of PCI_REQ64 REQ64 by the master and PCI_ACK64 ACK64 by the target. Note, the TSB82AA2 TSB82AA2 does not support the dual address command. I/O PCI bus commands and byte enables for the upper DWORD. During the address phase of a bus cycle, PCI_C/BE7-PCI_C/BE4 are reserved and indeterminate since the TSB82AA2 TSB82AA2 does not support the dual address command. During the data phase, this 4-bit bus is used as a byte enable for the upper 32 bits when a 64-bit transfer has been negotiated by the assertion of PCI_REQ64 REQ64 by the master and PCI_ACK64 ACK64 by the target. I PCI parity for the upper DWORD. In all PCI bus read and write cycles, the TSB82AA2 TSB82AA2 device calculates even parity across the PCI_AD63-PCI AD63-PCI_AD32 and PCI_C/BE4-PCI_C/BE7 buses. As an initiator during PCI cycles, the TSB82AA2 TSB82AA2 device outputs this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (PCI_PERR). I PCI bus request for 64-bit transfer. Asserted by a bus master to request a 64-bit transfer for a memory transaction. The timing of PCI_REQ64 REQ64 is identical to PCI_FRAME. When the TSB82AA2 TSB82AA2 device is the bus master, it asserts PCI_REQ64 REQ64 to request a 64-bit transfer on the current transaction. The TSB82AA2 TSB82AA2 device only requests a 64-bit transfer for a memory transaction. The target asserts PCI_ACK64 ACK64 if it is willing to transfer data using 64 bits. GGW M17 R16 Table 2-8. PHY-Link Interface Terminals TERMINAL NUMBER NAME PGE PHY_CTL1 133 A07 PHY_CTL0 134 B07 PHY_D7 PHY_D6 PHY_D5 PHY_D4 PHY_D3 PHY_D2 PHY_D1 PHY_D0 123 124 125 128 129 130 131 132 D10 C10 B10 C09 B09 A08 B08 D08 I/O DESCRIPTION I/O PHY-link interface control. These bidirectional control bus signals indicate the phase of operation of the PHY-link interface. Upon a reset of the interface, this bus is driven by the PHY. When driven by the PHY, information on PHY_CTL0 and PHY_CTL1 is synchronous to PHY_PCLK. When driven by the link, information on PHY_CTL0 and PHY_CTL1 is synchronous to PHY_LCLK. I/O PHY-link interface data. These bidirectional data bus signals carry 1394 packet data, packet speed, and grant type information between the PHY and the link. Upon a reset of the interface, this bus is driven by the PHY. When driven by the PHY, information on PHY_D7 through PHY_D0 is synchronous to PHY_PCLK. When driven by the link, information on PHY_D7 through PHY_D0 is synchronous to PHY_LCLK. I/O Link-on notification. PHY_LINKON is an input to the TSB82AA2 TSB82AA2 device from the PHY that is used to provide notification that a link-on packet has been received, or, if the PHY is configured properly, an event such as a port connection has occurred. This input only has meaning when LPS is disabled. This includes the D0 (uninitialized), D2, and D3 power states. If PHY_LINKON becomes active in the D0 (uninitialized), D2, or D3 power state, then the TSB82AA2 TSB82AA2 device sets bit 15 (PME_STS) in the power management control and status register in the PCI configuration space at offset 48h (see Section 3.20, Power Management Control and Status Register). I/O Link power status. PHY_LPS is an output from the TSB82AA2 TSB82AA2 device that, when active, indicates that the link is powered and capable of maintaining communications over the PHY-link interface. When this signal is inactive, it indicates that the link is not powered or that the link has not been initialized by software. This signal is active when bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) has been set by software according to the initialization as specified in the 1394 Open Host Controller Interface specification. When active, the signal is nominally a 2-MHz pulse. GGW PHY_LINKON PHY_LPS 142 144 C04 B03 PHY_LREQ 141 B04 O Link request. PHY_LREQ is a serial output from the TSB82AA2 TSB82AA2 device to the PHY used to request packet transmissions, read and write PHY registers, and to indicate the occurrence of certain link events that are relevant to the PHY. Information encoded on PHY_LREQ is synchronous to PHY_LCLK. PHY_LCLK 136 A06 O Link clock. PHY_LCLK is an output from the TSB82AA2 TSB82AA2 device that is generated from the incoming PHY_PCLK signal. PHY_LCLK is freqency-locked to PHY_PCLK and synchronizes data and information generated by the link. PHY_PCLK 138 A05 I PHY clock. PHY_PCLK is an input to the TSB82AA2 TSB82AA2 device from the PHY that, when active, provides a nominal 98.304-MHz clock with a nominal 50% duty cycle. PHY_PINT 143 A03 I PHY interrupt. PHY_PINT is a serial input to the TSB82AA2 TSB82AA2 device from the PHY that is used to transfer status, register, interrupt, and other information to the link. Information encoded on PHY_PINT is synchronous to PHY_PCLK. 2-11 2-12 3 TSB82AA2 TSB82AA2 Controller Programming Model This section describes the internal PCI configuration registers used to program the TSB82AA2 TSB82AA2 device. All registers are detailed in the same format: a brief description for each register, followed by the register offset and a bit table describing the reset state for each register. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, field access tags which appear in the type column, and a detailed field description. Table 3-1 describes the field access tags. Table 3-1. Bit Field Access Tag Descriptions ACCESS TAG NAME R Read Field can be read by software. MEANING W Write Field can be written by software to any value. S Set C Clear Field can be set by a write of 1. Writes of 0 have no effect. Field can be cleared by a write of 1. Writes of 0 have no effect. U Update Field can be autonomously updated by the TSB82AA2 TSB82AA2 device. Figure 3-1 shows a simplified block diagram of the TSB82AA2 TSB82AA2 device. 3-1 PCI Target SM Internal Registers Serial ROM OHCI PCI Power Mgmt and CLKRUN GPIOs Misc Interface ISO Transmit Contexts Async Transmit Contexts Transmit FIFO Physical DMA and Response Response Timeout PCI Host Bus Interface Central Arbiter and PCI Initiator SM PHY Register Access & Status Monitor Request Filters Link Transmit Receive Acknowledge Cycle Start Generator and Cycle Monitor Link Receive Receive FIFO ISO Receive Contexts Figure 3-1. TSB82AA2 TSB82AA2 Block Diagram 3-2 PHY / Link Interface Synthesized Bus Reset General Request Receive Async Response Receive CRC 3.1 PCI Configuration Registers The TSB82AA2 TSB82AA2 device is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3-2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 3-2. PCI Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID Status Command Class code BIST 00h 04h Revision ID Header type 08h Cache line size Latency timer 0Ch OHCI registers base address 10h TI extension registers base address 14h CardBus CIS base address 18h Reserved 1Ch-27h CardBus CIS pointer 28h Subsystem ID Subsystem vendor ID 2Ch Reserved 30h Power management capabilities pointer 34h Interrupt line Reserved 3Ch Reserved Maximum latency Minimum grant 38h Interrupt pin OHCI control Power management capabilities Power management extension PM data 40h Next item pointer Capability ID 44h Power management control and status 48h Reserved 4Ch-ECh Miscellaneous configuration F0h Link enhancement control F4h Subsystem device ID alias GPIO3 Subsystem vendor ID alias F8h Reserved FCh GPIO2 3.2 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Type: Offset: Default: Read-only 00h 104Ch Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 3-3 3.3 Device ID Register The device ID register contains a value assigned to the TSB82AA2 TSB82AA2 device by Texas Instruments. The device identification for the TSB82AA2 TSB82AA2 device is 8025h. Type: Offset: Default: Read-only 02h 8025h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 3.4 Command Register The command register provides control over the TSB82AA2 TSB82AA2 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3-3 for a complete description of the register contents. Type: Offset: Default: Read/Write, Read-only 04h 0000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-3. Command Register Description BIT FIELD NAME TYPE 15-11 RSVD R 10 INT_DISABLE R/W INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals. 0 = INTx assertion is enabled (default) 1 = INTx assertion is disabled This bit has been defined as part of the PCI Local Bus Specification (Revision 2.3). 9 FBB_ENB R Fast back-to-back enable. The TSB82AA2 TSB82AA2 device does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. 8 SERR_ENB R/W PCI_SERR enable. When bit 8 is set to 1, the TSB82AA2 TSB82AA2 PCI_SERR driver is enabled. PCI_SERR can be asserted after detecting an address parity error on the PCI bus. 7 STEP_ENB R Address/data stepping control. The TSB82AA2 TSB82AA2 device does not support address/data stepping; therefore, bit 7 is hardwired to 0. 6 PERR_ENB R/W Parity error enable. When bit 6 is set to 1, the TSB82AA2 TSB82AA2 device is enabled to drive PCI_PERR response to parity errors through the PCI_PERR signal. 5 VGA_ENB R VGA palette snoop enable. The TSB82AA2 TSB82AA2 device does not feature VGA palette snooping; therefore, bit 5 returns 0 when read. 4 MWI_ENB R/W Memory write and invalidate enable. When bit 4 is set to 1, the TSB82AA2 TSB82AA2 device is enabled to generate MWI PCI bus commands. If this bit is cleared, then the TSB82AA2 TSB82AA2 device generates memory write commands instead. 3 SPECIAL R Special cycle enable. The TSB82AA2 TSB82AA2 function does not respond to special cycle transactions; therefore, bit 3 returns 0 when read. 2 MASTER_ENB R/W Bus master enable. When bit 2 is set to 1, the TSB82AA2 TSB82AA2 device is enabled to initiate cycles on the PCI bus. 1 MEMORY_ENB R/W Memory response enable. Setting bit 1 to 1 enables the TSB82AA2 TSB82AA2 device to respond to memory cycles on the PCI bus. This bit must be set to access OHCI registers. 0 IO_ENB R I/O space enable. The TSB82AA2 TSB82AA2 device does not implement any I/O-mapped functionality; therefore, bit 0 returns 0 when read. 3-4 DESCRIPTION Reserved. Bits 15-11 return 0s when read. 3.5 Status Register The status register provides status over the TSB82AA2 TSB82AA2 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 3-4 for a complete description of the register contents. Type: Offset: Default: Read/Clear/Update, Read-only 06h 0210h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 3-4. Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected. 14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1 when PCI_SERR is enabled and the TSB82AA2 TSB82AA2 device has signaled a system error to the host. 13 MABORT RCU Received master abort. Bit 13 is set to 1 when a cycle initiated by the TSB82AA2 TSB82AA2 device on the PCI bus is terminated by a master abort. 12 TABORT_REC RCU Received target abort. Bit 12 is set to 1 when a cycle initiated by the TSB82AA2 TSB82AA2 device on the PCI bus is terminated by a target abort. 11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1 by the TSB82AA2 TSB82AA2 device when it terminates a transaction on the PCI bus with a target abort. 10-9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b, indicating that the TSB82AA2 TSB82AA2 device asserts this signal at a medium speed on nonconfiguration cycle accesses. 8 DATAPAR RCU 7 FBB_CAP R Fast back-to-back capable. The TSB82AA2 TSB82AA2 device cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 UDF R User-definable features (UDF) supported. The TSB82AA2 TSB82AA2 device does not support the UDF; therefore, bit 6 is hardwired to 0. 5 66MHZ 66MHZ R 66-MHz capable. The TSB82AA2 TSB82AA2 device operates at a maximum PCI_CLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4 CAPLIST R Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3 INT_STATUS RU 2-0 RSVD R Data parity error detected. Bit 8 is set to 1 when the following conditions have been met: a. PCI_PERR was asserted by any PCI device including the TSB82AA2 TSB82AA2 device. b. The TSB82AA2 TSB82AA2 device was the bus master during the data parity error. c. Bit 6 (PERR_ENB) in the command register at offset 04h in the PCI configuration space (see Section 3.4, Command Register) is set to 1. Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (PCI offset 04h, see Section 3.4) is a 0 and this bit is a 1, is the function's INTx signal asserted. Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit. This bit has been defined as part of the PCI Local Bus Specification (Revision 2.3). Reserved. Bits 2-0 return 0s when read. 3-5 3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB82AA2 TSB82AA2 device as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 3-5 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read-only 08h 0C00 1001h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 Table 3-5. Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31-24 BASECLASS R Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus controller. 23-16 SUBCLASS R Subclass. This field returns 00h when read, which specifically classifies the function as controlling an IEEE 1394 serial bus. 15-8 PGMIF R Programming interface. This field returns 10h when read, which indicates that the programming model is compliant with the 1394 Open Host Controller Interface Specification. 7-0 CHIPREV R Silicon revision. This field returns 01h when read, indicating the silicon revision of the TSB82AA2 TSB82AA2 device. 3.7 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the TSB82AA2 TSB82AA2 device. See Table 3-6 for a complete description of the register contents. Type: Offset: Default: Read/Write 0Ch 0000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-6. Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 LATENCY_TIMER R/W PCI latency timer. The value in this register specifies the latency timer for the TSB82AA2 TSB82AA2 device, in units of PCI clock cycles. When the TSB82AA2 TSB82AA2 device is a PCI bus initiator and asserts PCI_FRAME, the latency timer begins counting from zero. If the latency timer expires before the TSB82AA2 TSB82AA2 transaction has terminated, then the TSB82AA2 TSB82AA2 device terminates the transaction when its PCI_GNT is deasserted. 7-0 CACHELINE_SZ R/W Cache line size. This value is used by the TSB82AA2 TSB82AA2 device during memory write and invalidate, memory-read line, and memory-read multiple transactions. 3-6 3.8 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the TSB82AA2 TSB82AA2 PCI header type, and indicates no built-in self test. See Table 3-7 for a complete description of the register contents. Type: Offset: Default: Read-only 0Eh 0000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-7. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 BIST R Built-in self test. The TSB82AA2 TSB82AA2 device does not include a BIST; therefore, this field returns 00h when read. 7-0 HEADER_TYPE R PCI header type. The TSB82AA2 TSB82AA2 device includes the standard PCI header, which is communicated by returning 00h when this field is read. 3.9 OHCI Base Address Register The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the OHCI registers. See Table 3-8 for a complete description of the register contents. Type: Offset: Default: Read/Write, Read-only 10h 0000 0000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-8. OHCI Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31-11 OHCIREG_PTR R/W OHCI register pointer. This field specifies the upper 21 bits of the 32-bit OHCI base address register. 10-4 OHCI_SZ R OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a 2K-byte region of memory. 3 OHCI_PF R OHCI register prefetch. Bit 3 returns 0 when read, indicating that the OHCI registers are nonprefetchable. 2-1 OHCI_MEMTYPE R OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 OHCI_MEM R OHCI memory indicator. Bit 0 returns 0 when read, indicating that the OHCI registers are mapped into system memory space. 3-7 3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the TI registers. See Table 3-9 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read/Write, Read-only 14h 0000 0000h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-9. TI Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31-11 TIREG_PTR R/W 10-4 TI_SZ R TI register size. This field returns 0s when read, indicating that the TI registers require a 2K-byte region of memory. TI register pointer. This field specifies the upper 21 bits of the 32-bit TI base address register. 3 R TI register prefetch. Bit 3 returns 0 when read, indicating that the TI registers are nonprefetchable. TI_MEMTYPE R TI memory type. This field returns 0s when read, indicating that the TI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 3-8 TI_PF 2-1 TI_MEM R TI memory indicator. Bit 0 returns 0 when read, indicating that the TI registers are mapped into system memory space. 3.11 CardBus CIS Base Address Register The TSB82AA2 TSB82AA2 device may be configured to support CardBus registers via bit 6 (CARDBUS) in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). If CARDBUS is low (default), then this 32-bit register returns 0s when read. If CARDBUS is high, then this register is to be programmed with a base address referencing the memory-mapped card information structure (CIS). This register must be programmed with a nonzero value before the CIS may be accessed. See Table 3-10 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read/Write, Read-only 18h 0000 0000h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-10. CardBus CIS Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31-11 CIS_BASE R/W CIS base address. This field specifies the upper 21 bits of the 32-bit CIS base address. If CARDBUS is sampled high on a G_RST, then this field is read-only, returning 0s when read. 10-4 CIS_SZ R CIS address space size. This field returns 0s when read, indicating that the CIS space requires a 2K-byte region of memory. 3 CIS_PF R CIS prefetch. Bit 3 returns 0 when read, indicating that the CIS is nonprefetchable. Furthermore, the CIS is a byte-accessible address space, and either a doubleword or 16-bit word access yields indeterminate results. 2-1 CIS_MEMTYPE R CIS memory type. This field returns 0s when read, indicating that the CardBus CIS base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 CIS_MEM R CIS memory indicator. This bit returns 0 when read, indicating that the CIS is mapped into system memory space. 3-9 3.12 CardBus CIS Pointer Register The TSB82AA2 TSB82AA2 device may be configured to support CardBus registers via bit 6 (CARDBUS) in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). If CARDBUS is low (default), then this register is read-only returning 0s when read. If CARDBUS is high, then this register contains the pointer to the CardBus card information structure (CIS). See Table 3-11 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read-only 28h 0000 000Xh 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X Table 3-11. CardBus CIS Pointer Register Description BIT FIELD NAME TYPE 31-28 ROM_IMAGE R Since the CIS is not implemented as a ROM image, this field returns 0s when read. 27-3 CIS_OFFSET R This field indicates the offset into the CIS address space where the CIS begins, and bits 7-3 are loaded from the serial EEPROM field CIS_Offset (7-3). This implementation allows the TSB82AA2 TSB82AA2 device to produce serial EEPROM addresses equal to the lower PCI address byte to acquire data from the serial EEPROM. 2-0 CIS_INDICATOR R This field indicates the address space where the CIS resides and returns 011b if bit 6 (CARDBUS) in the PCI miscellaneous configuration register is high, then 011b indicates that CardBus CIS base address register at offset 18h in the PCI configuration header contains the CIS base address. If CARDBUS is low, then this field returns 000b when read. 3-10 DESCRIPTION 3.13 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 3.25, Subsystem Access Register). See Table 3-12 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read/Update 2Ch 0000 0000h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-12. Subsystem Identification Register Description BIT FIELD NAME TYPE DESCRIPTION 31-16 OHCI_SSID RU Subsystem device ID. This field indicates the subsystem device ID. 15-0 OHCI_SSVID RU Subsystem vendor ID. This field indicates the subsystem vendor ID. 3.14 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the power-management register block resides. The TSB82AA2 TSB82AA2 configuration header doublewords at offsets 44h and 48h provide the power-management registers. This register is read-only and returns 44h when read. Type: Offset: Default: Read-only 34h 44h Bit 7 6 5 4 3 2 1 0 Default 0 1 0 0 0 1 0 0 3-11 3.15 Interrupt Line and Pin Register The interrupt line and pin register communicates interrupt line routing information. See Table 3-13 for a complete description of the register contents. Type: Offset: Default: Read/Write, Read-only 3Ch 0100h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Table 3-13. Interrupt Line and Pin Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 INTR_PIN R Interrupt pin. Returns 01h when read, indicating that the TSB82AA2 TSB82AA2 PCI function signals interrupts on the PCI_INTA terminal. 7-0 INTR_LINE R/W Interrupt line. This field is programmed by the system and indicates to software which interrupt line the TSB82AA2 TSB82AA2 PCI_INTA is connected to. 3.16 MIN_GNT and MAX_LAT Register The MIN_GNT and MAX_LAT register communicates to the system the desired setting of bits 15-8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 3.7, Latency Timer and Class Cache Line Size Register). If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a PCI_RST. If no serial EEPROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4. See Table 3-14 for a complete description of the register contents. Type: Offset: Default: Read/Update 3Eh 0402h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 Table 3-14. MIN_GNT and MAX_LAT Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level to the TSB82AA2 TSB82AA2 device. The default for this field indicates that the TSB82AA2 TSB82AA2 device may need to access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial EEPROM. 7-0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value to the TSB82AA2 TSB82AA2 device. The default for this field indicates that the TSB82AA2 TSB82AA2 device may need to sustain burst transfers for nearly 64 µs and thus request a large value be programmed in bits 15-8 of the TSB82AA2 TSB82AA2 latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 3.7, Latency Timer and Class Cache Line Size Register). 3-12 3.17 OHCI Control Register The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 3-15 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read/Write 40h 0000 0000h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-15. OHCI Control Register Description BIT FIELD NAME TYPE 31-1 RSVD R 0 GLOBAL_SWAP DESCRIPTION R/W Reserved. Bits 31-1 return 0s when read. When bit 0 is set to 1, all quadlets read from and written to the PCI interface are byte-swapped (big endian). This bit is loaded from serial EEPROM and must be cleared to 0 for normal operation. 3.18 Capability ID and Next Item Pointer Register The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item, respectively. See Table 3-16 for a complete description of the register contents. Type: Offset: Default: Read-only 44h 0001h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 3-16. Capability ID and Next Item Pointer Register Description BIT FIELD NAME TYPE DESCRIPTION 15-8 NEXT_ITEM R Next item pointer. The TSB82AA2 TSB82AA2 device supports only one additional capability that is communicated to the system through the extended capabilities list; therefore, this field returns 00h when read. 7-0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power-management capability. 3-13 3.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB82AA2 TSB82AA2 device related to PCI power management. See Table 3-17 for a complete description of the register contents. Type: Offset: Default: Read/Update, Read-only 46h 7E02h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 Table 3-17. Power Management Capabilities Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_D3COLD RU PCI_PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). The miscellaneous configuration register is loaded from ROM. When this bit is set to 1, it indicates that the TSB82AA2 TSB82AA2 device is capable of generating a PCI_PME wake event from D3cold. This bit state is dependent upon the TSB82AA2 TSB82AA2 VAUX implementation and may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register (see Section 3.23). 14-11 PME_SUPPORT R PCI_PME support. This 4-bit field indicates the power states from which the TSB82AA2 TSB82AA2 device may assert PCI_PME. This field returns a value of 1111b, indicating that PCI_PME may be asserted from the D3hot, D2, D1, and D0 power states. Bit 14 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D3hot state. Bit 13 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D2 state. Bit 12 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D1 state. Bit 11 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D0 state. 10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1, indicating that the function supports the D2 device power state. 9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1, indicating that the TSB82AA2 TSB82AA2 device supports the D1 power state. 8-6 AUX_CURRENT R Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15 (PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b. 000b = Self-powered 001b = 55 mA (3.3-VAUX maximum current required) 5 R Device-specific initialization. Bit 5 returns 0 when read, indicating that the TSB82AA2 TSB82AA2 device does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. 4 RSVD R Reserved. Bit 4 returns 0 when read. 3 PME_CLK R PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the TSB82AA2 TSB82AA2 device to generate PCI_PME. 2-0 3-14 DSI PM_VERSION R Power-management version. This field returns 010b when read, indicating that the TSB82AA2 TSB82AA2 device is compatible with the registers described in the PCI Bus Power Management Interface Specification (Revision 1.1). 3.20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 3-18 for a complete description of the register contents. Type: Offset: Default: Read/Clear, Read/Write, Read-only 48h 0000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-18. Power Management Control and Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_STS RC Bit 15 is set to 1 when the TSB82AA2 TSB82AA2 device normally asserts the PME signal, independent of the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME signal driven by the TSB82AA2 TSB82AA2 device. Writing a 0 to this bit has no effect. 14-9 RSVD R 8 PME_ENB R/W 7-2 RSVD PWR_STATE When bit 8 is set to 1, PME assertion is enabled. When bit 8 is cleared, PME assertion is disabled. This bit defaults to 0 if the function does not support PME generation from D3cold. If the function supports PME from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. Functions that do not support PME generation from any D-state (that is, bits 15-11 in the power management capabilities register at offset 46h in the PCI configuration space (see Section 3.19, Power Management Capabilities Register) equal 00000b), may hardwire this bit to be read-only, always returning a 0 when read by system software. R 1-0 Reserved. Bits 14-9 return 0s when read. R/W Reserved. Bits 7-2 return 0s when read. Power state. This 2-bit field is used to set the TSB82AA2 TSB82AA2 device power state and is encoded as follows: 00 = Current power state is D0. 01 = Current power state is D1. 10 = Current power state is D2. 11 = Current power state is D3. 3.21 Power Management Extension Register The power management extension register provides extended power-management features not applicable to the TSB82AA2 TSB82AA2 device; thus, it is read-only and returns 0s when read. See Table 3-19 for a complete description of the register contents. Type: Offset: Default: Read-only 4Ah 0000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-19. Power Management Extension Register Description BIT FIELD NAME TYPE 15-0 RSVD R DESCRIPTION Reserved. Bits 15-0 return 0s when read. 3-15 3.22 Multifunction Select Register The multifunction select register provides a method. See Table 3-20 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read/Write/Update, Read-only E8h 0000 0000h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3-20. Multifunction Select Register BIT TYPE 31-8 RSVD R Reserved. Bits 31-8 return 0s when read. 7 RSVD R Reserved. This read-only bit is for internal use only. 6-4 RSVD R Reserved. Bits 6-4 return 0s when read. 3-0 3-16 FIELD NAME DESCRIPTION MFUNC_SEL R/W/U Power state. This 2-bit field is used to set the TSB82AA2 TSB82AA2 device power state and is encoded as follows: 000 = General-purpose input/output 001 = CYCLEIN 010 = CYCLEOUT 011 = PCI_CLKRUN 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved 3.23 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3-21 for a complete description of the register contents. Type: Offset: Default: Read/Write, Read-only F0h 0000 0010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Table 3-21. Miscellaneous Configuration Register BIT FIELD NAME TYPE 31-16 RSVD R 15 PME_D3COLD R/W 14-11 RSVD R 10 Ignore IntMask.masterInt Enable_for_pme R/W Ignore IntMask.masterIntEnable for PME generation. When set to 1, this bit causes PME generation behavior to be changed. Also, when set to 1, this bit causes bit 26 of the OHCI vendor ID register at OHCI offset 40h to read 1; otherwise, bit 26 reads 0. 0 = PME behavior generated from unmasked interrupt bits and bit 31 (masterIntEnable) in the interrupt mask register at OHCI offset 88h (see Section 4.22, Interrupt Mask Register) (default) 1 = PME behavior does not depend on the value of bit 31 (masterIntEnable) 9-8 MR_ENHANCE R/W This field selects the read command behavior of the PCI master. 00 = Memory read line (default) 01 = Memory read 10 = Memory read multiple 11 = Reserved 7 RSVD R 6 CARDBUS R/W 5 RSVD R 4 DIS_TGT_ABT R/W DESCRIPTION Reserved. Bits 31-16 return 0s when read. PCI_PME support from D3cold. This bit programs bit 15 (PME_D3COLD) in the power management capabilities register at offset 46h in the PCI configuration space (see Section 3.19, Power Management Capabilities Register). Reserved. Bits 14-11 return 0s when read. Reserved. Bit 7 returns 0 when read. CardBus. When bit 6 is set to 1, CardBus register support is enabled, that is, the CardBus base register and CardBus CIS pointer are valid. Bit 6 is only set if a serial EEPROM is present and contains a valid CIS. If bit 6 is set to 1, then a valid CIS must be implemented in the EEPROM at an offset pointed to in EEPROM word 0x14, bits 7-3. Reserved. Bit 5 returns 0 when read. Bit 4 defaults to 1 disabling the target abort behavior when accesses are made to PHY clock domain registers when no clock is present. Bit 4 can be set to 0 to provide OHCI-Lynxt compatible target abort signaling. When this bit is set to 1, it enables the no-target-abort mode, in which the TSB82AA2 TSB82AA2 device returns indeterminate data instead of signaling target abort. The TSB82AA2 TSB82AA2 LLC is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the link that are not active because the SCLK is disabled, then a target abort is issued by the link.