TSB12LV21B TSB12LV21BI TSB12LV21BM SLLA213 TSB12LV21BIPGF TSB12LV21BPGF

TSB12LV21BI TSB12LV21BM www.ti.com SLLA213 JUNE 2006 (PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER FEATURES · ·

TSB12LV21B TSB12LV21B TSB12LV21BI TSB12LV21BI TSB12LV21BM TSB12LV21BM www.ti.com SLLA213 SLLA213 JUNE 2006 (PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER FEATURES · · · · · · · · · · · IEEE Standard for 1394-1995 Compliant IEEE Standard for 1212-1991 Compliant Supports IEEE 1394-1995 Link Layer Control PCI Local Bus Specification Rev. 2.1 Compliant Supports IEEE 1394 Transfer Rates of 100, 200, and 400 Mb per Second 3.3-V Core Logic While Maintaining 5-V Tolerant Inputs Performs the Function of 1394 Cycle Master Provides 4K Bytes of Configurable FIFO RAM Provides Five Scatter-Gather DMA Channels Provides Software Control of Interrupt Events Provides Four General-Purpose Input/Outputs · · · · · · · · Supports Plug-and-Play (PnP) Specification Generates 32-bit CRC for Transmission of 1394 Packets Performs 32-bit CRC Checking on Reception of 1394 Packets Provides PCI Bus Master Function for Supporting DMA Operations Provides PCI Slave Function for Read/Write Access of Internal Registers Supports Distributed DMA Transfers Between 1394 and Local Bus RAM, ROM, AUX, or Zoomed Video Advanced Submicron, Low-Power CMOS Technology Packaged in a 176-Pin PQFP (PGF) DESCRIPTION The TSB12LV21B TSB12LV21B (PCILynx-2) provides a high-performance IEEE 1394-1995 interface with the capability to transfer data between the 1394 PHY-link interface, the PCI bus interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical layer device; it is supported by the onboard link layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400 Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. The PCILynx2 complies with · PCI Local Bus Specification, Revision 2.1 · IEEE Standard for a 1394-1995 High Performance Serial Bus · IEEE Standard 1212-1991 · IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses An internal 4Kbyte-memory can be configured as multiple variable-size FIFOs, eliminating the need for external FIFOs. Separate FIFOs are user configurable to support 1394 receive, asynchronous transmit, and isosynchronous transmit transfer operations. The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating both as a master and as a target device. Configuration registers can be loaded from an external serial EEPROM, allowing board and system designers to assign their own unique identification codes. An autoboot mode allows data-moving systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU. The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is connected to a local bus port. The PCLs implement an instruction set that allows linking, conditional branching, 1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels accommodate programmable data types. PCLs can be chained together to form a channel control program that can be developed to support each DMA channel. Data can be stored in either big endian or little endian format, eliminating the need for the host CPU to perform byte swapping. Data can be transferred either to 4-byte aligned locations, to provide the highest performance, or to nonaligned locations, to provide the best memory use. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TSB12LV21B TSB12LV21B TSB12LV21BI TSB12LV21BI TSB12LV21BM TSB12LV21BM www.ti.com SLLA213 SLLA213 JUNE 2006 The RAM, ROM, AUX, ZV, and general-purpose I/O (GPIO) ports collectively make up the local bus interface. These ports mapped into the PCI address, can be accessed either through the PCI bus or through internal DMA transactions. Internal transactions do not appear on the external PCI bus, thereby conserving PCI bandwidth. DMA packet control lists or other data may be stored in external RAM or ROM attached to the local bus interface. This further reduces PCI bus use and generally improves performance. The ZV local bus port is designed to transfer data from 1394 video devices to an external device connected to the PCILynx-2 ZV port. This interface provides a method for receiving 1394 digital camera packets directly from a ZV-compliant device attached to the local bus interface. Built-in test registers, a dedicated test output terminal, and four GPIO terminals allow observation of internal states and provide a convenient software debug capability. Programmable interrupts are available to inform driver software of important events, such as 1394 bus resets and DMA-to-PCL transfer completion. The 3.3-V internal operation provides reduced power consumption, while maintaining compatibility with 5signaling environments. The PCI interface is compatible with both 3-V and 5-V PCI systems. The TSB12LV21B TSB12LV21B is characterized for operation over the commercial temperature range of 0°C to 70°C. The TSB12LV21BI TSB12LV21BI is characterized for operation over the industrial temperature range of 40°C to 85°C. The TSB12LV21BM TSB12LV21BM is characterized for operation over the military temperature range of 55°C to 125°C. NOTE: This product is for high-volume CE applications only. For a complete datasheet or more information contact support@ti.com. 2 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 28-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TSB12LV21BIPGF TSB12LV21BIPGF OBSOLETE LQFP PGF 176 TBD Call TI TSB12LV21BPGF TSB12LV21BPGF ACTIVE LQFP PGF 176 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TSB12LV21BPGFG4 TSB12LV21BPGFG4 ACTIVE LQFP PGF 176 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF TSB12LV21B TSB12LV21B : · Enhanced Product: TSB12LV21B-EP TSB12LV21B-EP NOTE: Qualified Version Definitions: · Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 1 MECHANICAL DATA OCTOBER 1994 PGF (S-PQFP-G176 S-PQFP-G176) PLASTIC QUAD FLATPACK 132 89 88 133 0,27 0,17 0,08 M 0,50 0,13 NOM 176 45 1 44 Gage Plane 21,50 SQ 24,20 SQ 23,80 26,20 SQ 25,80 0,25 0,05 MIN 0°- 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040134 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136 MO-136 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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