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1 - 14 of about 14 for TS83102G0 |
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First line: 10 GSPS ADC Released under TS83102G0 10-bit resolution. GSPS sampling rate. full power input bandwidth. Band flatness: (from GHz). Very input VSWR 1.15 from 2GHz (packaged device). Phase error: 0.2° (from 750MHz 1.5GHz) Power consumption SFDR= Effective Bits GSPS, [-1dBFS]. SFDR 52dBc Effective Abstract: .. DESCRIPTION The TS83102G0 is a monolithic 10-bit 10-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 2 Gsps. The TS83102G0 .. Tags: 10 GSPS ADC CBGA ADC 10 Ghz TS83102G0 |
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First line: Input/Output Termination Techniques This document provides Atmel ADCs DMUX users with different termination techniques used with Atmel products. wide panel configurations analog clock inputs well data outputs described detail. principles each technique also presented that eventually choose proper im Abstract: .. of an ADC device featuring an internal 50Ω termination inside the cavity for the TS83102G0 10-bit 10-bit 2 Gsps ADC and on package for the TS8388BG TS8388BG 8-bit 1 Gsps ADC . ADC Input Buffer. ADC Package. 50Ω impedance .. Tags: datasheet abstract.. |
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First line: Programmable DMUX ratio Data rate Gsps, (8b/10b)< (ECL output) Data Rate 2GSPS, (8b/10b)< (ECL output) 1:16 with TS8388B TS83102G0 DMUX. Parallel output mode. 8/10 bit. Differential input data. DataReady DataReady/2 input clock. Input clock sampling delay adjust. Single ended output data Adjus Abstract: .. max = 2GSPS, PD 8b/10b < 6 / 6.9 W ECL 50Ω output 1:16 with 1 TS8388B TS8388B or 1 TS83102G0 and 2 DMUX. Parallel output mode. 8/10 bit. ECL Differential input data. DataReady or DataReady/2 input clock .. Tags: TS83084G0* porte logique dmux 3/8 16a9 15B1 TS8388B TS83102G0 TS81102G0 |
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First line: Programmable DMUX Ratio: Data Rate Gsps (8b/10b) 4.3/4.7 (ECL Output) Data Rate Gsps (8b/10b) 6/6.9 (ECL Output) 1:16 With TS8388B TS83102G0 DMUX Parallel Output Mode 8/10-bit Differential Input Data Data Ready Data Ready Input Clock Input Clock Sampling Delay Adjust Single-ended Output Data: Adjust Abstract: .. 9 W ECL 50 Ω Output – 1:16 With 1 TS8388B TS8388B or 1 TS83102G0 and 2 DMUX Parallel Output Mode 8/10-bit 10-bit ECL Differential Input Data Data Ready or Data Ready 2 Input Clock Input Clock Sampling Delay Adjust .. Tags: TS81102G0CTP TS8388B TS83102G0 |
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First line: Applying Atmel DMUX This document aims presenting relevant information needed properly apply Atmel ADCs DMUX. describes different configurations product best performance results. important benefit full compatibility Atmel ADCs DMUX devices their evaluation boards. particular, this document offers so Abstract: .. When the TS83102G0 ADC is used, the internal sampling instant can be fine-tuned by the Sampling Delay adjust function of the ADC. In this case, it is not necessary to use the ADC delay adjust function .. Tags: TS83102G0* dmux ADC 10 Ghz 2167A TS830500 TS8388B TS83102G0B TS81102G0 |
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First line: Programmable DMUX Ratio: 1:4: Data Rate Gsps (8b/10b) 4.3/4.7 (ECL output) 1:8: Data Rate Gsps (8b/10b) 6/6.9 (ECL output) 1:16 with TS8388B TS83102G0 DMUX Parallel Output Mode 8-/10-bit Differential Input Data DataReady DataReady/2 Input Clock Input Clock Sampling Delay Adjust Single-ended Output D Abstract: .. 9 W ECL 50Ω output – 1:16 with 1 TS8388B TS8388B or 1 TS83102G0 and 2 DMUX Parallel Output Mode 8-/10-bit 10-bit ECL Differential Input Data DataReady or DataReady/2 Input Clock Input Clock Sampling Delay Adjust .. Tags: TS83084G0 dmux 3/8 TS8388B TS83102G0 |
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First line: n type connector at 2.2GHz - 3.3GHz 17vee IEC C13 pinout 16a8 input clock data (differential ECL) through 2.54mm pitch connectors. Demultiplexed outputs (single-ended ECL) adapted 2.54mm pitch connectors. DMUX functions adjusted jumpers potentiometers. Separated Ground supplies. Suitable high-freque Abstract: .. 8bits 1GHz TS8388B TS8388B 10bits 10bits 2GHz TS83102G0. TS81102GO TS81102GO . Clkln. delay. Number of bits 8/10 Synchronous or Asynchronous Reset. Vcc = +5V. Vee = -5V. VplusD = 0V → 3.3V. Please refer to the specific document .. Tags: IEC C13 pinout 17vee n type connector at 2.2GHz - 3.3GHz Radiall FR4 epoxy dielectric constant 4.2 DELTRON BANANA JACK 16a9 16a8 15B1 12b7* TS81102G0 |
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First line: FR4 epoxy dielectric constant 4.4 analog/DIODE MA DMUX 8-/10-bit 1:4/1:8 Gsps TSEV81102G0 Evaluation Board Abstract: .. 8-bit 1 GHz TS8388B TS8388B 10-bit 10-bit 2 GHz TS83102G0. TS81102G0 TS81102G0 . Clkln. delay. Number of bits 8/10 Synchronous or Asynchronous Reset. Vcc = +5V. 1 - 2 GHz 1b diff. Vee = -5V. VplusD = 0V → 3.3V. TTL + ref VplusD = 3.3V .. Tags: analog/DIODE MA TS81102G0CTP ro4003 Radiall itt Guide diode FR4 epoxy dielectric constant 4.4 2108D TSEV81102G0 |
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First line: DMUX 8-/10-bit 1:4/1:1.5 Gsps TSEV81102G0 Evaluation Board Section Overview Abstract: .. 8-bit 1 GHz TS8388B TS8388B 10-bit 10-bit 2 GHz TS83102G0. TS81102G0 TS81102G0 . Clkln. delay. Number of bits 8/10 Synchronous or Asynchronous Reset. Vcc = +5V. 750 MHz - 1.5 GHz 1b diff. Vee = -5V. VplusD = 0V → 3.3V. TTL + ref VplusD .. Tags: Radiall itt Guide diode FR4 epoxy dielectric constant 4.2 DELTRON BANANA JACK TSEV81102G0 |
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First line: 10-bit Gsps Evaluation Board TSEV83102G0B Abstract: .. TS83102G0. A2A3A4 A12 A7 A15. B1B2B3B4B5B6B7 B13 B14 B15 B16 C1C2C4C5C6C7C13 C1C2C4C5C6C7C13 D14 D15 D16 E1 E14 E15 F14 F15 G14 G15 G16. J2K2L2L16 J2K2L2L16 M13 P1P2P3P7P10 P1P2P3P7P10 P14 P15 P16 Q1Q2Q15 Q1Q2Q15 Q16 R2R15 R2R15 . A8 A9. A11 B8. B9 B11. B12 C3 .. Tags: FR4 epoxy dielectric constant 4.4 C30B* C22A C20B b17 zener diode TSEV83102G0B |
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First line: TS81102G0FS* Programmable DMUX Ratio: Data Rate Msps (8b/10b) 4.3/4.7W (ECL Output) Data Rate Gsps (8b/10b) 6/6.9W (ECL Output) 1:16 with TS8388B TS83102G0 DMUX Parallel Output Mode 8/10-bit Differential Input Data Data Ready Data Ready/2 Input Clock Input Clock Sampling Delay Adjust Single-ended Ou Abstract: .. 9W ECL 50Ω Output – 1:16 with 1 TS8388B TS8388B or 1 TS83102G0 and 2 DMUX Parallel Output Mode 8/10-bit 10-bit ECL Differential Input Data Data Ready or Data Ready/2 Input Clock Input Clock Sampling Delay Adjust .. Tags: TS81102G0FS* dmux 3/8 TS8388B TS83102G0 |
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First line: 10-bit Gsps Evaluation Board AT84AS008-EB Abstract: .. TS83102G0. A2A3A4 A12 A7 A15. B1B2B3B4B5B6B7 B13 B14 B15 B16 C1C2C4C5C6C7C13 C1C2C4C5C6C7C13 D14 D15 D16 E1 E14 E15 F14 F15 G14 G15 G16. J2K2L2L16 J2K2L2L16 M13 P1P2P3P7P10 P1P2P3P7P10 P14 P15 P16 Q1Q2Q15 Q1Q2Q15 Q16 R2R15 R2R15 . A8 A9. A11 B8. B9 B11. B12 C3 .. Tags: FR4 epoxy dielectric constant 4.4 C30B* C22A C20B AT84AS008-EB |
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First line: Programmable DMUX Ratio: 1:4: Data Rate Gsps (8b/10b) 4.3/4.7 (ECL output) 1:8: Data Rate Gsps (8b/10b) 6/6.9 (ECL output) 1:16 with TS8388B TS83102G0B DMUX Parallel Output Mode 8-/10-bit Differential Input Data DataReady DataReady/2 Input Clock Input Clock Sampling Delay Adjust Single-ended Output Abstract: .. 8bits 1 GHz TS8388B TS8388B 10bits 10bits 2 GHz TS83102G0. TS81102G0 TS81102G0 . Clkln. delay. Number of bits 8/10 Synchronous or Asynchronous Reset. Vcc = +5V. 1 - 2 GHz 1b diff. Vee = -5V. VplusD = 0V → 3.3V. TTL + ref VplusD = 3.3V .. Tags: TS83102G0 dmux 3/8 TS8388B TS83102G0B |
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First line: Programmable DMUX Ratio: 1:4: Data Rate Msps (8b/10b) 4.3/4.7 (ECL output) 1:8: Data Rate Gsps (8b/10b) 6/6.9 (ECL output) 1:16 with TS8388B TS83102G0B DMUX Parallel Output Mode 8-/10-bit Differential Input Data Data Ready Data Ready/2 Input Clock Input Clock Sampling Delay Adjust Single-ended Outpu Abstract: .. 8bits 1 GHz TS8388B TS8388B 10bits 10bits 2 GHz TS83102G0. TS81102G0 TS81102G0 . Clkln. delay. Number of bits 8/10 Synchronous or Asynchronous Reset. Vcc = +5V. 750 MHz - 1.5 GHz 1b diff. Vee = -5V. VplusD = 0V → 3.3V. TTL + ref VplusD .. Tags: dmux 3/8 TS8388B TS83102G0B |
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