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TS5071 Datasheet

Part Manufacturer Description PDF Type
TS5071 STMicroelectronics PROGRAMMABLE CODEC-FILTER COMBO 2ND GENERATION Original
TS5071 STMicroelectronics PROGRAMMABLE CODEC-FILTER COMBO 2ND GENERATION Original
TS5071FN Thomson Semiconductors Monolithic Programmable CODEC / Filter Scan
TS5071J Thomson Semiconductors Monolithic Programmable CODEC / Filter Scan
TS5071N STMicroelectronics PROGRAMMABLE CODEC-FILTER COMBO 2ND GENERATION Original
TS5071N STMicroelectronics PROGRAMMABLE CODEC-FILTER COMBO 2ND GENERATION Original
TS5071N STMicroelectronics Programmable Codec/Filter Combo 2nd Generation Original
TS5071N STMicroelectronics PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION Scan
TS5071N STMicroelectronics PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION Scan
TS5071P Thomson Semiconductors Monolithic Programmable CODEC / Filter Scan

TS5071

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Description IL5 through ILO are available on the TS5070, IL4 through ILO are available on the TS5071. Each , /O pinwich is provided on the TS5071. Serial control information is shifted into orout of COMBO IIG , output for the TS5071. TIME-SLOT ASSIGNMENT COMBO IIG can operatein eitherfixed time-slot or time-slot , for the TS5071. 2. T5 is the MSB of the time-slot assignment. (*) State at power-on initialization , capacitortechniquesthe TS5070 and TS5071 combine transmit bandpass and receive lowpass channel tilters with a com panding -
OCR Scan
DIP20
Abstract: TS5071 PIN CONNECTIONS DIP20 TS5071N PLCC28 TS5070FN (s) ct du ) ro P t(s te uc le , together in the TS5071. â'"5V±5% All analog and digital signals are referenced to this pin , available on the TS5071. Each interface Latch I/O pin may be individually programmed as an input or an , wich is provided on the TS5071. Serial control information is shifted into or out of COMBO IIG on , power-on initilization. Note: L5 should be programmed as an output for the TS5071. Table 6: Byte 2 of STMicroelectronics
Original
Abstract: mA mA °C °C 2/30 TS5070 - TS5071 PIN CONNECTIONS PLCC28 TS5070FN DIP20 TS5071N POWER , and MCLK are wired together in the TS5071. Description MCLK I 17 12 Master Clock 3 , are available on the TS5070, IL4 through IL0 are available on the TS5071. Each interface Latch I/O pin , provided on the TS5071. Serial control information is shifted into or out of COMBO IIG on this pin when CS , should be programmed as an output for the TS5071. TIME-SLOT ASSIGNMENT COMBO IIG can operate in either STMicroelectronics
Original

TS5070

Abstract: TS5071 . BCLK and MCLK are wired together in the TS5071. Function Description + 5V±5% ­ 5 V± 5 % All , TS5071. Each interface Latch I/O pin may be individually programmed as an input or an output determined , /output This is Control Data I/O pin wich is provided on the TS5071. Serial control information is , as an output for the TS5071. Table 6: Byte 2 of Time-slot and Port Assignment Instructions Bit , bit MUST always be set to 0 for the TS5071. 2. T5 is the MSB of the time-slot assignment. (*) State
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Original

TS5070FN

Abstract: STMicroelectronics DIODE marking code DX mA °C °C 3/32 TS5070 - TS5071 PIN CONNECTIONS DIP20 TS5071N PLCC28 TS5070FN uc , . BCLK and MCLK are wired together in the TS5071. du o Pr e let o (s) ct Function , available on the TS5071. Each interface Latch I/O pin may be individually programmed as an input or an , wich is provided on the TS5071. Serial control information is shifted into or out of COMBO IIG on , . Note: L5 should be programmed as an output for the TS5071. 0 X X ro P TIME-SLOT
STMicroelectronics
Original
TS5070FNTR STMicroelectronics DIODE marking code DX

TS5070FNTR

Abstract: TS5071 °C 3/32 TS5070 - TS5071 PIN CONNECTIONS DIP20 TS5071N PLCC28 TS5070FN POWER SUPPLY , the TS5071. ­5V±5% All analog and digital signals are referenced to this pin. TS5070 - TS5071 , IL5 through IL0 are available on the TS5070, IL4 through IL0 are available on the TS5071. Each , Control Data I/O pin wich is provided on the TS5071. Serial control information is shifted into or out of , initilization. Note: L5 should be programmed as an output for the TS5071. Table 6: Byte 2 of Time-slot and
STMicroelectronics
Original
LDR 24v

DIP20

Abstract: PLCC28 and synchronous with BCLK. BCLK and MCLK are wired together in the TS5071. ­ 5 V± 5% All analog , TS5070, IL4 through IL0 are available on the TS5071. Each interface Latch I/O pin may be individually , ­ 8 Control Data Input/output This is Control Data I/O pin wich is provided on the TS5071. , output for the TS5071. Table 6: Byte 2 of Time-slot and Port Assignment Instructions Bit Number 5 6 , Binary Coded Time-slot from 0­63 Notes: 1. The "PS" bit MUST always be set to 0 for the TS5071. 2
STMicroelectronics
Original

IL324

Abstract: T9128 MCLK are wired together in the TS5071. â'"-;- SGS-THOMSON _ 440 â  7^21237 0DL.37L.5 DbO â  This , TS5070, IL4 through (LO are available on the TS5071. Each interface Latch I/O pin may be individually , Control Data I/O pin wich is provided on the TS5071. Serial control information is shifted into or out of , Register (*) State at power-on initilization. Note: L5 should be programmed as an output for the TS5071. , MUST always be set to 0 for the TS5071. 2. T5 is the MSB of the time-slot assignment. (*) State at
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OCR Scan
IL324 T9128

li1516

Abstract: FZJ 165 (-40°C to 85°C for TS5070-Xand TS5071-X). TS5070 - TS5071 f = 1031.25 Hz, VFxl = 0 dBmO, DrO or Dr1 = , Respective Manufacturer TS5070 - TS5071 PIN CONNECTIONS PLCC28 TS5070FN DIP20 TS5071N u â  z 3 o , 4.096 MHz and synchronous with BCLK. BCLK and MCLK are wired together in the TS5071. /=7 SCS-THOMSON , Interface Latches IL5 through ILO are available on the TS5070, IL4 through ILO are available on the TS5071. , is provided on the TS5071. Serial control information is shifted into or out of COMBO IIG on this pin
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OCR Scan
li1516 FZJ 165
Abstract: or 4.096 MHz and synchronous with BCLK. BCLK and MCLK are wired together in the TS5071. Description , Description IL5 through ILO are available on the TS5070, IL4 through ILO are available on the TS5071. Each , /O pin wich is provided on the TS5071. Serial control information is shifted into or out of COMBO IIG , : L5 should be programmed as an output for the TS5071. TIME-SLOT ASSIGNMENT COMBO IIG can operate In , bit MUST always be set to 0 for the TS5071. 2. T5 is the MSB of the time-slot assignment. (') State at -
OCR Scan
Abstract: together in the TS5071. â  Description Function Positive Power Supply Negative Power Supply , available on the TS5071. Each interface Latch I/O pin may be individually programmed as an input or an , Control Data I/O pin wich is provided on the TS5071. Serial control information is shifted into or out of , . Note: L5 should be programmed as an output for the TS5071. Table 6: Byte 2 of Time-slot and Port , . The â'PSâ' bit MUST always be set to 0 for the TS5071. 2 .T5 is the MSB of the time-slot assignment -
OCR Scan

DIP20

Abstract: PLCC28 °C 3/32 TS5070 - TS5071 PIN CONNECTIONS DIP20 TS5071N PLCC28 TS5070FN POWER SUPPLY , the TS5071. ­5V±5% All analog and digital signals are referenced to this pin. TS5070 - TS5071 , IL5 through IL0 are available on the TS5070, IL4 through IL0 are available on the TS5071. Each , Control Data I/O pin wich is provided on the TS5071. Serial control information is shifted into or out of , initilization. Note: L5 should be programmed as an output for the TS5071. Table 6: Byte 2 of Time-slot and
STMicroelectronics
Original
TSP5071N
Abstract: M g â  7^21237 DDb37b4 124 â  TS5070 - TS5071 PIN CONNECTIONS DIP20 TS5071N , should be programmed as an output for the TS5071. Table 6: Byte 2 of Time-slot and Port Assignment , : 1. The "PS" bit MUST always be set to 0 for the TS5071. 2. T5 is the MSB of the time-slot , testing at Ta = 25 °C (-40°C to 85°C for TS5070-X and TS5071-X). f = 1031.25 Hz, VFxl = 0 dBmO, D , . Using advanced switched capacitor techniques the TS5070 and TS5071 combine transmit bandpass and -
OCR Scan
2S237
Abstract: clocks. This is Control Data I/O pin wich is provided on the TS5071. Serial control inform ation is , r z 7 * li. SGS-THOMSON M»iHICTMl(§S TS5070 TS5071 PROGRAMMABLE CO DEC/FILTER CO M BO 2ND , capacitortechniquesthe TS5070 and TS5071 com bine transmit bandpass and receive lowpass channel filters with a com , controlled via a serial control port. Decem ber 1997 DIP20 (Plastic) O RDERING NUMBER:TS5071 N PLCC28 , latches andtheTS 5071 5 latches. 1/32 TS5070 - TS5071 TS5070 PIN FUNCTIONALITY (PLCC28) No. 1 2 3 4 -
OCR Scan
TSP5070FN TSP5070FNTR PDIP20 TSW5070FNTR TSW5071

600W power amplifier schematic diagrams

Abstract: schematic diagram transformer North American master clock (1.536 or 1.544MHz). ­ 6 input/output interface latches (5 on the TS5071). , card kit to several telecom administrations requirements is also discussed. The TS5071 basic version , into the TS5070 COMBO II, at pin CI (or CI/O for the TS5071) on the falling edge of each CCLK clock , (CI/O pin for the TS5071), MSB first, on the rising edge of each CCLK clock pulse. As for the write , When using the TS5071 the IL5 pin should be programmed as an output. In the case of a L3092 SLIC, as
STMicroelectronics
Original
AN293 600W power amplifier schematic diagrams schematic diagram transformer d 5071 transistor 600w power amplifier circuit diagram ECHO schematic diagrams SLIC L3092 TS5070/5071 TS5070/71 M5913/14 096MH 544MH

600w power amplifier circuit diagram

Abstract: 600W power amplifier schematic diagrams interface latches (5 on the TS5071). These latches facilitate the logical interface with a transformer or , administrations requirements is also discussed. The TS5071 basic version of the COMBO II is packaged in a 20 , II, at pin CI (or CI/O for the TS5071) on the falling edge of each CCLK clock pulse, the most , , onto the CO pin (CI/O pin for the TS5071), MSB first, on the rising edge of each CCLK clock pulse , should be programmed as outputs. - When using the TS5071 the IL5 pin should be programmed as an output
STMicroelectronics
Original
echo cancellation schematic diagram Combo Driver combo 5054 datasheet Companding L3000N

schematic diagram transformer

Abstract: Combo Driver 1.544MHz). - 6 input/outputinterface latches (5 on the TS5071). These latches facilitate the logical , telecom administrations requirements is also discussed. The TS5071 basic version of the COMBO II is , readingfrom the TS5070 COMBO II, the data byte is shifted out, onto the CO pin (CI/O pin for the TS5071 , shifted into the TS5070 COMBO II, at pin CI (or CI/O for the TS5071) on the falling edge of each CCLK , When using the TS5071 the IL5 pin should be programmed as an output. APPLICATION NOTE In the case
STMicroelectronics
Original
AN293/0694 TS5070/71COMBO L3037
Abstract: (Plastic and Ceramic) ORDER CODE: TS5071N TS5071J DIP28L (Ceramic) ORDER CODE: TS5070J PLCC28 , . BCLK and MCLK are wired together in the TS5071. Function Positive Power + 5 V ± 5 % Supply , TS5070, IL4 through ILO are available on the TS5071. Each interface Latch I/O pin may be individually , This is Control Data I/O pin wich is provided on the TS5071. Serial control information is shifted , power-on initialization. Note : L5 should be programmed as an output for the TS5071. Table 6 : Byte 2 -
OCR Scan
OFTP3070 TP3071/COMBO

dip26

Abstract: dip16 TS5070 Universal Programmable COMBO PLCC28 TS5071 Universal Programmable COMBO DIP20
STMicroelectronics
Original
ETC5054D ETC5054D-X ETC5054FN ETC5054FN-X ETC5054N ETC5054N-X dip26 dip16 DIP-16 SO16 package SO-16 PLCC-20 PLCC20

SGS thomson power schottky

Abstract: 8J17 1 ^ DIP20 (Plastic and Ceramic) ORDER CODE: TS5071N TS5071J DIP28L (Ceramic) ORDER CODE , and synchronous with BCLK. BCLK and MCLK are wired together in the TS5071. MCLK 1 16 17 , Description IL5 through ILO are available on the TS5070, IL4 through ILO are available on the TS5071. Each , /O pin wich is provided on the TS5071. Serial control information is shifted into or out of COMBO IIG , the TS5071. S G S -T H 0M S 0 N Table 6 : Byte 2 of Tim e-slot and Port Assignment Instructions
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OCR Scan
SGS thomson power schottky 8J17 TDB 1033 7TST237 FTP3070 TP3071/COM PLCC44 DIP-20

MR1511

Abstract: 25CC , CLOCK Name Pin Typ* TS 5070 TS5071 Function Description Vec S 27 19 Positive power supply +â'¢ 5 V 1 5 , Material Copyrighted By Its Respective Manufacturer RECEIVE SECTION Nam« Pin type TS5070 TS5071 Function , >n the TS5070 IL4 through ILO are available on the TS5071 Each Interface Latch I/O pin may be , is the Control Data I/O pin which is provided on the TS5071. Serial control information is shifted , set to 0 for the TS5071 Note 2: T5 is the MSB of the Time-slot assignment TABLE VI Time-Slot and Port
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OCR Scan
MR1511 25CC TP3070 TP3071 TS50 ANI 1015 CB-194 CB-520
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