TR328 TR238 AD8016 AD8017 AD812 AD6438 AD6439 AD6437 AD6438BST 144LQFP AD6439BS

Second Generation DMT ADSL Chipset AD20msp918 Prelim inary Technical Inform ation FEATURES GENERAL DESCRIPTION Complete chipset

Second Generation DMT ADSL Chipset AD20msp918 Prelim inary Technical Inform ation FEATURES GENERAL DESCRIPTION Complete chipset for DMT based Asymmetric Digital Subscriber Loop (ADSL) AD20msp918 is a complete chipset for implementing ADSL modems designed to ANSI T1.413 Issue 2, ETSI TR328 TR328 and ITU G.dmt (including Annexes A and B). By incorporating all required components, including controller, analog front-end, driver/receiver and software, it significantly reduces system development time and risk. The same chipset is used for CO (central office) and RT (remote terminal) applications. Designed to ANSI T1.413 Issue 2, ETSI TR238 TR238, and ITU G.dmt and G.lite standards Performance of >11Mbps or reach of >20,000 ft Trellis code Flexible bin assignment: supports ADSL over ISDN (as per ETSI TM6 and ITU Annex B), enhanced upstream or symmetric rates Normal and reduced overhead framing modes ATM (UTOPIA 1 and 2) and STM interfaces Complete software control protocol stack/API Complete data-pump in five compact ICs Power 2.3 W (excluding driver and signal) CO: 3.9 W including AD8016 AD8016 line driver RT: 2.8 W including AD8017 AD8017 driver The AD20msp918 chipset is a second generation version of the field-proven AD20msp910 package. It adds trellis coding, ATM (UTOPIA 2) interface, and new framing modes for improved long reach performance. Flexible bin assignment allows free movement of frequency division for different applications, such as ADSL over ISDN (per ETSI TM6 recommendations), and non-standard modes like enhanced upstream or symmetric service. Supplied object code software for both modem and management/control functions (API or protocol stack) is a superset of those defined in T1.413 that handles all real-time functions, including performance logging and statistic gathering. -40 to +85ºC operation AD812 AD812 LNA RECEIVER AD6438 AD6438 FRAMER/ INTERFACE ATM OR STM AD6439 AD6439 DMT COPROCESSOR AD6437 AD6437 ANALOG FRONT END TO HYBRID TX, LINE AND POTS SPLITTER AD8016 AD8016 (FULL CO) AD8017 AD8017 RT TO RAM (INTERLEAVE) A DTS P -2183 CONTROL MESSAGES TO BOOT EPROM OR IDMA BOOT Figure 1: Block Diagram REV 0.4 (16 April 1999) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD20msp918 Specifications Table 1: ADSL Category 1 Modem Specifications Specification Value Units Comments Absolute Maximum Data Rates Downstream Duplex 12 1 Mbps Mbps Actual performance is primarily limited by loop noise and crosstalk. These figures apply to best-case loops, where the limit is a function of data-packing and interfacing. Serial Mode Jitter 28 ns ADSL Overhead, Normal Framing Mode (Mode 1) Downstream Duplex 192 96 kbps kbps ADSL Overhead, Reduced Overhead Mode (Mode 2, 3) Downstream Duplex 96 32 kbps kbps 0.111.1 301100 MHz kHz DS TX Power 20 dBm US TX Power 12 dBm Can be boosted to 15dBm. 4.3125 kHz As specified in T1.413, tolerance ±50ppm Max Symbols/Bin 16 bit Latency: Fast Channel Interleaved Channel