TPS40054-EP TPS40055-EP TPS40057-EP SGLS310A TPS40054 TPS40055 TPS40057 - Datasheet Archive

 

8 www.ti.com SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER FEATURES APPLICATIONS

 

TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP 8 www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER FEATURES APPLICATIONS · · · · · · · · · · · · · · · · · · · · (1) Controlled Baseline ­ One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Operating Input Voltage 8 V to 40 V Input Voltage Feed-Forward Compensation < 1 % Internal 0.7-V Reference Programmable Fixed-Frequency Up to 1-MHz Voltage Mode Controller Internal Gate Drive Outputs for High-Side and Synchronous N-Channel MOSFETs 16-Pin PowerPADTM Package (JC = 25°C/W) Thermal Shutdown Externally Synchronizable Programmable High-Side Sense Short-Circuit Protection Programmable Closed-Loop Soft-Start TPS40054 TPS40054 Source Only (Product Preview) TPS40055 TPS40055 Source/Sink TPS40057 TPS40057 Source/Sink With VOUT Prebias (Product Preview) Power Modules Networking/Telecom Industrial/Servers DESCRIPTION The TPS4005x is a family of high-voltage, wide input (8 V to 40 V), synchronous, step-down converters. The TPS4005x family offers design flexibility with a variety of user programmable functions, including soft-start, UVLO, operating frequency, voltage feed-forward, high-side current limit, and loop compensation. The TPS4005x are also synchronizable to an external supply. The TPS4005x incorporates MOSFET gate drivers for external N-channel high-side and synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction. The TPS4005x uses voltage feed-forward control techniques to provide good line regulation over the wide (4:1) input voltage range and fast response to input line transients with near constant gain with input variation which eases loop compensation. The externally programmable current limit provides pulse-by-pulse current limit, as well as a hiccup mode operation utilizing an internal fault counter for longer duration overloads. Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 SIMPLIFIED APPLICATION DIAGRAM TPS4005xPWP 1 KFF ILIM 16 2 RT VIN 15 3 BP5 BOOST 14 4 SYNC HDRV 13 5 SGND SW 12 6 SS/SD BP10 11 7 VFB LDRV 10 8 COMP PGND 9 + - These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) (3) 2 PACKAGE (2) PART NUMBER Plastic HTSSOP (PWP) TPS40054MPWPREP TPS40054MPWPREP (3) SOURCE/SINK Plastic HTSSOP (PWP) TPS40055MPWPREP TPS40055MPWPREP SOURCE/SINK with prebias ­55°C to 125°C APPLICATION (1) SOURCE TA Plastic HTSSOP (PWP) TPS40057MPWPREP TPS40057MPWPREP (3) See Application Information section. The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40054PWPR TPS40054PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. Product Preview TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT VIN 45 V VFB, SS, SYNC VIN SW Input voltage range ­0.3 V to 6 V ­0.3 V to 45 V SW, transient < 50 ns ­2.5 V KFF, with IIN(max) = ­5 mA ­0.3 V to 11 V ­0.3 V to 6 V VOUT Output voltage range COMP, RT, SS IIN Input current KFF 5 mA IOUT Output current RT 200 µA TJ Operating junction temperature range ­55°C to 140°C Tstg Storage temperature (2) ­55°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds TJC TJA Thermal resistance junction-to-ambient TJP Thermal resistance junction-to-bottom of thermal pad JT Junction-to-top thermal parameter 260°C Thermal resistance junction-to-case (1) (2) (3) (4) 26.6°C/W (3) (4) 36.5°C/W (3) 2.1°C/W (3) (4) 0.848°C/W Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in reduced overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. See technical brief SLMA002 SLMA002 - PowerPAD Thermally Enhanced ). Tested in accordance with the thermal metric definitions of EIA/JESD51-5 EIA/JESD51-5. RECOMMENDED OPERATING CONDITIONS MIN VI Input voltage TA Operating free-air temperature NOM MAX UNIT 8 40 V ­55 125 °C ELECTRICAL CHARACTERISTICS TA = ­55°C to 125°C, VIN = 24 Vdc, RT = 90.9 k, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range, VIN 8 40 V 1.5 3.3 mA OPERATING CURRENT Quiescent current IDD Output drivers not switching, VFB 0.75 V Output voltage IOUT 1 mA 4.7 5 5.3 V 465 520 585 kHz BP5 VBP5 OSCILLATOR/RAMP GENERATOR (1) fOSC Accuracy 8 V VIN 40 V VRAMP PWM ramp voltage (2) VPEAK­ VVAL VIH High-level input voltage, SYNC VIL Low-level input voltage, SYNC ISYNC Input current, SYNC Pulse width, SYNC (1) (2) 2 2 V 5 5 50 V 0.8 V 11 µA ns IKFF increases with SYNC frequency, IKFF decreases with maximum duty cycle. Ensured by design. Not production tested. 3 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS (continued) TA = ­55°C to 125°C, VIN = 24 Vdc, RT = 90.9 k, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER VRT TEST CONDITIONS Maximum duty cycle Minimum duty cycle VKFF 2.5 VFB = 0 V, fSW 500 kHz 84% VFB = 0 V, 500 kHz fSW 1 MHz (2) MAX UNIT 2.59 V 80% 94% VFB 0.75 V Feed-forward voltage IKFF TYP 2.37 RT voltage MIN Feed-forward current operating range (2) 0% 3.35 3.48 3.7 V 1200 20 µA 3.6 µA SOFT START ISS Soft-start source current VSS Soft-start clamp voltage 1.2 2.35 tDSCH Discharge time CSS = 220 pF 1.4 2.2 3.4 µs tSS Soft-start time CSS = 220 pF, 0 V VSS 1.6 V 102 150 230 µs Output voltage IOUT 1 mA 8.9 9.6 10.45 V 8 V VIN 40 V, TA = 25°C 0.698 0.7 0.704 8 V VIN 40 V, 0°C TA 125°C 0.689 0.7 0.717 8 V VIN 40 V, ­55°C TA 125°C 0.719 3.7 V BP10 VBP10 VBP10 ERROR AMPLIFIER VFB Feedback input voltage V 0.689 0.7 GBW Gain bandwidth (3) 2.8 5 MHz AVOL Open loop gain 40 80 dB IOH High-level output source current 1.85 4 IOL Low-level output source current 1.95 4 VOH High-level output voltage ISOURCE = 500 µA 3.1 3.5 VOL Low-level output voltage ISINK = 500 µA 0.2 0.37 IBIAS Input bias current VFB = 0.7 V 100 220 nA 10 12.2 µA mA V CURRENT LIMIT ISINK Current limit sink current Propagation delay to output tON VILIM = 23.7 V, VSW = (VILIM­ 0.5 V) 300 VILIM = 23.7 V, VSW = (VILIM­ 2 V) 200 Switch leading-edge blanking pulse time (3) tOFF 7.5 Off time during a fault ns 100 ns 7 VILIM = 23.6 V, TA = 25°C ­155 ­38 VILIM = 23.6 V, ­55°C TA 125°C ­155 ­10 VILIM = 11.6 V, TA = 25°C ­118 ­43 VILIM = 11.6 V, 0°C TA 125°C ­160 ­45 VILIM = 11.6 V, TA = ­55°C to 125°C Offset voltage SW vs ILIM ­115 VILIM = 23.6 V, 0°C TA 125°C VOS ­70 cycle s ­50 ­160 ­15 mV OUTPUT DRIVER tLRISE Low-side driver rise time tLFALL Low-side driver fall time tHRISE High-side driver rise time tHFALL High-side driver fall time VOH High-level output voltage, HDRV (3) 4 Ensured by design. Not production tested. CLOAD = 2200 pF CLOAD = 2200 pF, (HDRV ­ SW) IHDRV = ­0.1 A (HDRV - SW) 48 110 24 58 48 105 36 82 BOOST BOOST ­1.9 ­1 ns ns V TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS (continued) TA = ­55°C to 125°C, VIN = 24 Vdc, RT = 90.9 k, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS VOL Low-level output voltage, HDRV High-level output voltage, LDRV ILDRV = ­0.1 A VOL Low-level output voltage, LDRV TYP BP10 ­1.8 BP10 ­1 IHDRV = 0.1 A (HDRV - SW) VOH MIN ILDRV = 0.1 A MAX UNIT 0.85 V V 0.6 V 100 Minimum controllable pulse width 160 ns SS/SD SHUTDOWN VSD Shutdown threshold voltage VEN Device active threshold voltage Outputs off 85 125 170 mV 180 210 260 mV 30.8 32.2 33.9 V ­10 ­5 0 mV 35 µA BOOST REGULATOR VBOOST Output voltage VIN = 24 V RECTIFIER ZERO CURRENT COMPARATOR (TPS40054 TPS40054 ONLY) VSW Switch voltage LDRV output OFF SW NODE ILEAK Leakage current (3) THERMAL SHUTDOWN TSD Shutdown temperature (3) 165 Hysteresis (3) °C 20 UVLO VDD KFF programmable threshold voltage RKFF = 28.7 k UVLO, hysteresis 6.85 7.5 7.95 7.05 UVLO, fixed 7.5 7.9 V 0.46 TYPICAL CHARACTERISTICS OFFSET VOLTAGE (VLim vs SW) vs TEMPERATURE 0 VOS - Offset Voltage (VLIM vs SW) - mV VUVLO -20 -40 -60 VLim = 23.6 V -80 VLim = 11.6 V -100 -120 -60 -40 -20 0 20 40 60 80 100 120 140 TA - Temperature - 5C Figure 1. 5 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 DEVICE INFORMATION PWP PACKAGE(1)(2) (TOP VIEW) 1 2 3 4 5 6 7 8 KFF RT BP5 SYNC SGND SS/SD VFB COMP THERMAL PAD 16 15 14 13 12 11 10 9 ILIM VIN BOOST HDRV SW BP10 LDRV PGND (1) For more information on the PWP package, see the Texas Instruments Technical Brief (SLMA002 SLMA002) (2) PowerPAD heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 14 O Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input voltage. A 0.1-µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET. BP5 3 O 5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with an external dc load of 1 mA or less. BP10 11 O 10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF ceramic capacitor. This pin may be used with an external dc load of 1 mA or less. COMP 8 O Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the VFB pin to compensate the overall loop. The COMP pin is internally clamped above the peak of the ramp to improve large signal transient response. HDRV 13 O Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW (MOSFET off). ILIM 16 I Current limit pin used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage drop (VIN -SW) across the high side MOSFET during conduction. KFF 1 I A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into this pin is internally divided and used to control the slope of the PWM ramp. LDRV 10 O Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET off). PGND 9 ­ Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the lower MOSFET(s). RT 2 I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency. SGND 5 ­ Signal ground reference for the device NAME NO. BOOST SS/SD 6 I Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V. The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive. The internal circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs cease switching and the output voltage (VOUT) decays while the internal circuitry remains active. SW 12 I This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40054 TPS40054 and TPS40057 TPS40057 versions use this pin for zero current sensing as well. SYNC 4 I Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency. If synchronization is not used, connect this pin to SGND. VFB 7 I Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage, 0.7 V. VIN 15 I Supply voltage for the device 6 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 SIMPLIFIED BLOCK DIAGRAM ILIM 16 10-V Regulator BP10 VIN 15 + CLK RT 7 2 11 BP10 14 BOOST CLK Clock Oscillator SYNC 4 1.5 VREF 7 0.7 VREF7 BP5 Ramp Generator Reference Voltages 3.5 VREF 7 KFF 1 7 CL 3-bit up/down Fault Counter N-channel Driver 1.5 VREF 7 7 7 BPN10 BPN10 Restart Fault BP5 7 BP5 3 0.7 VREF COMP 8 7 VFB 7 S Q CL R Q + + SS/SD 6 0. 7 V 0.7 VREF 7 + 7 N-channel Driver 7 SW 7 CLK S 10 LDRV Q R Q Zero Current Detector (TPS40054 TPS40054 Only) Restart 12 SW 7 BP10 7 Fault 7 + 13 HDRV 9 PGND 5 SGND UDG-05007 UDG-05007 7 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION The TPS40054/55/57 TPS40054/55/57 family of parts allows the user to optimize the PWM controller to the specific application. The TPS40055 TPS40055 is the controller of choice for synchronous buck designs, which includes most applications. It has two quadrant operations and will source or sink output current. This provides the best transient response. The TPS40054 TPS40054 operates in one quadrant and sources output current only, allowing for paralleling of converters and ensures that one converter does not sink current from another converter. This controller also emulates a standard buck converter at light loads where the inductor current goes discontinuous. At continuous output inductor currents, the controller operates as a synchronous buck converter to optimize efficiency. The TPS40057 TPS40057 operates in one quadrant as a standard buck converter during start up. After the output has reached the regulation point, the controller operates in two quadrant modes and is put in a synchronous buck configuration. This is useful for applications that have the output voltage prebiased at some voltage before the controller is enabled. When the TPS40057 TPS40057 controller is enabled it does not sink current during start up, which would pull current from the prebiased voltage supply. SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS4005x has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by a single resistor RT) to ground. The clock frequency is related to RT, in k by Equation 1 and the relationship is charted in Figure 3. RT + f SW 1 17.82 10 *6 * 17 kW (1) PROGRAMMING THE RAMP GENERATOR CIRCUIT The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 2 ). VIN SW RAMP COMP UDG-02131 UDG-02131 Figure 2. Voltage Feed-Forward Effect on PWM Duty Cycle The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The PWM ramp time is programmed via a single resistor RKFF) pulled up to VIN. RKFF is related to RT and the minimum input voltage (VIN(min) through the following: 8 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) 58.14 R KFF + VIN (min) * 3.5 RT ) 1340 W (2) where: VIN(min) is the ensured minimum start-up voltage. The actual start-up voltage is nominally about 10% lower at 25°C. RT is the timing resistance in k. The curve showing the RKFF required for a given switching frequency (fSW) is shown in Figure 4. For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltage. For more information on large duty cycle operation, see the application note (SLUA310 SLUA310). FEED-FORWARD IMPEDANCE vs SWITCHING FREQUENCY SWITCHING FREQUENCY vs TIMING RESISTANCE 600 RKFF - Feed-Forward Impedance - k 700 RT - Timing Resistance - k 500 400 300 200 100 600 500 400 VIN = 9 V 300 VIN = 15 V VIN = 25 V 200 100 0 100 200 300 400 500 600 700 800 900 1000 fSW - Switching Frequency - kHz Figure 3. 0 100 200 300 400 500 600 700 800 900 1000 fSW - Switching Frequency - kHz Figure 4. UVLO OPERATION The TPS4005x uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start low until the input voltage has exceeded the user programmable undervoltage threshold. The TPS4005x uses the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable low-line TPS4005x uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start low until the input voltage has exceeded the user programmable undervoltage threshold. UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage condition exists if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor can be referenced to the oscillator frequency as described in Equation 3: 58.14 R KFF + VIN (min) * 3.5 RT ) 1340 W (3) where: VIN is the desired start-up (UVLO) input voltage 9 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) RT is the timing resistance in kW The variable UVLO function uses a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter than the clock cycle a power-good signal is asserted and a soft-start initiated and the upper and lower MOSFETS are turned off. Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 5 ). UVLO Threshold VIN Clock PWM RAMP 1 2 3 4 5 6 7 1 2 1 2 3 4 5 6 7 PowerGood Figure 5. Undervoltage Lockout Operation The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at the nominal start up voltage. The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen to select the start-up voltage, the approximate amount of hysteresis voltage is shown in Figure 6. 10 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) UNDERVOLTAGE LOCKOUT THRESHOLD vs HYSTERESIS 1.2 VUVLO - Hysteresis - V 1.0 0.8 0.6 0.4 0.2 0 10 15 20 25 30 35 40 VUVLO - Undevoltage Lockout Threshold - V Figure 6. BP5 AND BP10 INTERNAL VOLTAGE REGULATORS Start-up characteristics of the BP5 and BP10 regulators over different temperature ranges are shown in Figure 7 and Figure 8. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs. 11 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) INPUT VOLTAGE vs BP5 VOLTAGE 6 10 8 VBP10 VBP10 - BP10 Voltage - V 5 VBP5 - BP5 Voltage - V INPUT VOLTAGE vs BP10 VOLTAGE 110°C 4 -55°C 3 25°C 6 110°C 25°C 4 -55°C 2 2 0 1 2 4 6 8 VIN- Input Voltage - V 10 12 Figure 7. 2 4 6 8 VIN- Input Voltage - V 10 12 Figure 8. SELECTING THE INDUCTOR VALUE The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good compromise is to select the inductance value such that the converter does not enter discontinuous mode until the load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in Equation 4. L+ V IN * V O VIN DI VO f SW (Henries) (4) where: VO is the output voltage I is the peak-to-peak inductor current CALCULATING THE OUTPUT CAPACITANCE The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any output voltage deviation requirement during a load transient. The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output ripple is described in Equation 5. DV + DI ESR ) 8 1 CO f SW VP*P The output ripple voltage is typically between 90% and 95% due to the ESR component. 12 (5) TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) The output capacitance requirement typically increases in the presence of a load transient requirement. During a step load, the output capacitance must provide energy to the load (light-to-heavy load step) or absorb excess inductor energy (heavy-to-light load step) while maintaining the output voltage within acceptable limits. The amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the inductor. Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in Equation 6. E L + 1 L I 2 (Joules) 2 (6) where: I2 + I OH 2 * I OL 2 (Amperes)2 (7) IOH is the output current under heavy load conditions IOL is the output current under light load conditions Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This applies to applications which have high impedance on the input voltage line or which have excessive ringing on the VIN line. The input voltage impedance can cause the input voltage to sag enough at start-up to cause a UVLO shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and cause a UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to prevent the nuisance UVLO shutdown. Assuming a hysteresis current of 10% IKFF and the peak detector charges to 8 V and VIN(min) = 10 V, the value of RA is calculated by Equation 8 using a RKFF = 71.5 k. RKFF (8 * 3.5) RA + + 495 kW ^ 499 kW 0.1 V IN(min) * 3.5 (8) CA is chosen to maintain the peak voltage between switching cycles. To keep the capacitor charge from drooping 0.1 V, or from 8 V to 7.9 V. (8 * 3.5) CA + RA 7.9 f SW (9) The value of CA may calculate to less than 10 pF, but some standard value up to 47 pF works adequately. The diode can be a small signal switching diode or Schottky rated for more then 20 V. Figure 9 illustrates a typical implementation using a small switching diode. The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at the nominal start up voltage. 13 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) + VIN RA 499 kW - RKFF 71.5 kW 1 KFF 2 RT CA 47 pF ILIM 16 VIN 15 3 BP5 BOOST 14 4 SYNC HDRV 13 5 SGND SW 12 6 SS BP10 11 7 VFB LDRV 10 8 COMP PGND 9 PWP DA 1N914 1N914, 1N4150 1N4150 Type Signal Diode UDG-03034 UDG-03034 Figure 9. Hysteresis for Programmable UVLO Energy in the capacitor is described in Equation 10. E C + 1 C V2 (Joules) 2 (10) where: V2 + V * V 2 2 f Volts2 i (11) where: Vf is the final peak capacitor voltage VI is the initial capacitor voltage Substituting Equation 7 into Equation 6, then substituting Equation 11 into Equation 10, then setting Equation 10 equal to Equation 6, and then solving for CO yields the capacitance described in Equation 12. L CO + I * I V * V 2 2 OH OL 2 f (Farads) 2 i (12) PROGRAMMING SOFT START TPS4005x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by charging an external capacitor CSS) via an internally generated current source. The voltage on CSS minus 0.85 V is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V VREF). The loop is closed on the lower of the CSS­ 0.85 V) voltage or the internal reference voltage (0.7-V VREF). Once the CSS­ 0.85 V) voltage rises above the internal reference voltage, regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-CO time constant as described in Equation 13. 14 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) t START w 2p L CO (seconds) (13) There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the higher the input current required during start-up. This relationship is describe in more detail in the section titled, Programming the Current Limit which follows. The soft-start capacitance, CSS, is described in Equation 14. 2.3 mA C SS + t START (Farads) 0.7 V (14) For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO tripping. The soft-start time should be longer than the time that the VIN supply transitions between 6 V and 7 V. PROGRAMMING CURRENT LIMIT The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven, a restart is issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present, the counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 10 for typical overcurrent protection waveforms. The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at turn-on (IL). I LIM + C O V O t START ) I L (Amperes) (15) HDRV CLOCK tBLANKING VILIM VVIN-VSW SS 7 CURRENT LIMIT TRIPS (HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP) 7 SOFT-START CYCLES UDG-02136 UDG-02136 Figure 10. Typical Current Limit Protection Waveforms 15 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) The current limit programming resistor RILIM) is calculated using Equation 16. Care must be taken in choosing the values used for VOS and ISINK in the equation. In order to assure the output current at the overcurrent level, the minimum value of ISINK and the maximum value of VOS must be used. I OC RDS(on)[max] V R ILIM + ) OS (W) I SINK I SINK (16) where: ISINK is the current into the ILIM pin and is 8.5 µA, minimum IOC is the overcurrent setpoint which is the dc output current plus one-half of the peak inductor current VOS is the overcurrent comparator offset and is ­20 mV, maximum SYNCHRONIZING TO AN EXTERNAL SUPPLY The TPS4005x can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4005x to freely run at the frequency programmed by RT. The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a dummy value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the design. R T(dummy) + f SYNC 1 17.82 10 *6 * 17 kW (17) Use the value of RT(dummy) to calculate the value for RKFF. R KFF + VIN(min) * 3.5 V 58.14 RT(dummy) ) 1340 W (18) This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency. RT(dummy) is in k Loop Compensation Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be included. The modulator gain is described in Figure 10, with VIN being the minimum input voltage required to cause the ramp excursion to cover the entire switching period as described in Equation 19. V V IN A MOD + IN or A MOD(dB) + 20 log VS VS (19) Duty cycle (D) varies from 0 to 1 as the control voltage (VC) varies from the minimum ramp voltage to the maximum ramp voltage (VS). Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage: V V VO V D + O + C or + IN V IN VS VC VS (20) 16 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) Calculate the Poles and Zeros For a buck converter using voltage mode control, there is a double pole due to the output L-CO. The double pole is located at the frequency calculated in Equation 21. 1 f LC + (Hertz) 2p L CO (21) There is also a zero created by the output capacitance CO) and its associated ESR. The ESR zero is located at the frequency calculated in Equation 22. 1 fZ + (Hertz) 2p ESR CO (22) Calculate the value of RBIAS to set the output voltage (VOUT). R BIAS + 0.7 R1 W VOUT * 0.7 (23) The maximum crossover frequency (0 dB loop gain) is calculated in Equation 24. f f C + SW (Hertz) 4 (24) Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this frequency, the control to output gain has a -2 slope (­40 dB/decade), while the Type III topology has a +1 slope (20 dB/decade), resulting in an overall closed loop ­1 slope (­20 dB/decade). Figure 12 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated. PWM MODULATOR RELATIONSHIPS MODULATOR GAIN vs SWITCHING FREQUENCY ESR Zero, + 1 Modulator Gain - dB AMOD = VIN / VS VS VC Resultant, - 1 D = VC / VS LC Filter, - 2 100 Figure 11. 1k 10 k fSW - Switching Frequency - Hz 100 k Figure 12. A Type III topology, shown in Figure 13, has 2 zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 14. The two zeros are used to compensate the L-CO double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off. In many cases, the second pole can be eliminated and the amplifier's gain roll-off used to roll-off the overall gain at higher frequencies. Figure 13. 17 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) C2 (optional) C1 R3 -1 +1 0 dB R2 -1 GAIN -90° C3 VFB R1 180° 7 8 VOUT PHASE COMP + RBIAS -270° VREF UDG-02189 UDG-02189 Figure 13. Type III Compensation Configuration Figure 14. Type III Compensation Gain and Phase The poles and zeros for a Type III network are described in Equation 25. 1 1 f Z1 + (Hertz) f Z2 + (Hertz) 2p R2 C1 2p R1 C3 f P1 + 2p 1 R2 (Hertz) C2 f P2 + 2p 1 R3 C3 (Hertz) (25) The value of R1 is somewhat arbitrary, but influences other component values. A value between 50 k and 100 k usually yields reasonable values. The unity gain frequency is described in Equation 26. 1 fC + (Hertz) 2p R1 C2 G (26) where G is the reciprocal of the modulator gain at fC. The modulator gain as a function of frequency at fC, is described in Equation 27. AMOD(f) + AMOD f LC fC 2 and G+ 1 AMOD(f) (27) Minimum Load Resistance Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current, which must be considered when sizing R2. Too small a value does not allow the output to swing over its full range. VC (max) R2 (MIN) + + 3.5 V + 1750 W I SOURCE (min) 2 mA (28) CALCULATING THE BOOST AN BP10 BYPASS CAPACITOR The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance is described in Equation 29. Qg C BOOST + (Farads) DV (29) 18 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) The 10-V reference pin, BP10V BP10V provides energy for both the synchronous MOSFET and the high-side MOSFET via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V BP10V capacitance is described in Equation 30. C BP10 + QgHS ) QgSR DV (Farads) (30) dv/dt INDUCED TURN-ON MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through currents. Therefore, the SR MOSFET should be chosen so that the CGD capacitance is smaller than the CGS capacitance. HIGH SIDE MOSFET POWER DISSIPATION The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The high-side MOSFET conduction losses are defined by Equation 31. P COND + I RMS 2 R DS(on) 1 ) TCR T J * 25 C O (Watts) (31) where: TCR is the temperature coefficient of the MOSFET RDS(on) The TCR varies depending on MOSFET technology and manufacturer, but typically ranges between 0.0035 ppm/°C and 0.01 ppm/°C. The IRMS current for the high side MOSFET is described in Equation 32. d A I +I (32) The switching losses for the high-side MOSFET are described in Equation 33. P SW(fsw) + VIN I OUT t SW f SW (Watts) (33) RMS OUT RMS where: IO is the dc-output current tSW is the switching rise time, typically < 20 ns fSW is the switching frequency Typical switching waveforms are shown in Figure 15. 19 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) ID2 IO ID1 d } I 1-d BODY DIODE CONDUCTION BODY DIODE CONDUCTION SW 0 ANTI-CROSS CONDUCTION SYNCHRONOUS RECTIFIER ON HIGH SIDE ON UDG-02139 UDG-02139 Figure 15. Inductor Current and SW Node Waveforms The maximum allowable power dissipation in the MOSFET is determined by Equation 34. PT + TJ * TA q JA (Watts) (34) where: P T + PCOND ) PSW(fsw) (Watts) (35) and JA is the package thermal impedance. SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be found using Equation 31 and the RMS current through the synchronous rectifier MOSFET is described in Equation 36. 1 * d Amperes I +I RMS O RMS (36) The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross conduction delay time. The body diode conduction losses are described by Equation 37. P DC + 2 I O V F t DELAY f SW (Watts) (37) where: VF is the body diode forward voltage tDELAY is the delay time just before the SW node rises The 2-multiplier is used because the body diode conducts twice during each cycle (once on the rising edge and once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a reverse blocking state. The reverse recovery losses are described in Equation 38. P RR + 0.5 Q RR V IN f SW (Watts) (38) where: QRR is the reverse recovery charge of the body diode. 20 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 APPLICATION INFORMATION (continued) The QRR is not always described in a MOSFET's data sheet, but may be obtained from the MOSFET vendor. The total synchronous rectifier MOSFET power dissipation is described in Equation 39. P SR + PDC ) PRR ) PCOND (Watts) (39) TPS4005x POWER DISSIPATION The power dissipation in the TPS4005x is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance)[2] can be calculated from Equation 40. P D + Q g VDR f SW (Wattsdriver) (40) And the total power dissipation in the TPS4005x, assuming the same MOSFET is selected for both the high-side and synchronous rectifier is described in Equation 41. 2 PD PT + ) IQ V IN (Watts) V DR (41) or P T + 2 f SW ) I Q Qg V IN (Watts) (42) where: IQ is the quiescent operating current (neglecting drivers) The maximum power capability of the device's PowerPad package is dependent on the layout as well as air flow. The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow. q JA + 36.515 CW (43) O The maximum allowable package power dissipation is related to ambient temperature by Equation 44. T * TA PT + J (Watts) q JA (44) Substituting Equation 45 into Equation 41 and solving for fSW yields the maximum operating frequency for the TPS4005x. The result is described in Equation 45. f SW + T J*T A q JA V DD 2 Q g * IQ (Hz) (45) LAYOUT CONSIDERATIONS PowerPADTM PACKAGE The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package, dimensions of the circuit board pad area are 5 mm x 3,4 mm [2]. The dimensions of the package pad are shown in Figure 16. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0,33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not 21 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 LAYOUT CONSIDERATIONS (continued) plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0,1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. See the PowerPAD Thermally Enhanced Package and the mechanical illustration at the end of this document for more information on the PowerPAD package. 5,10 mm 4,90 mm Thermal Pad 4,50 mm 6,60 mm 4,30 mm 6,20 mm 2,46 mm 1,86 mm 1 8 2,31 mm 1,75 mm Figure 16. PowerPAD Dimensions MOSFET PACKAGING MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (JA) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on proper layout and thermal management. The JA specified in the MOSFET data sheet refers to a given copper area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch of 2-ounce copper on a G-10/FR-4 G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. See the selected MOSFET's data sheet for more information regarding proper mounting. GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor. Sensitive nodes such as the FB resistor divider RT) and ILIM should be connected to the SGND plane. The SGND plane should only make a single point connection to the PGND plane. Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT, and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). 22 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 DESIGN EXAMPLE · · · · · · · Input Voltage: 10 Vdc to 24 Vdc Output voltage: 3.3 V +2% (3.234 VO 3.366) Output current: 8 A (maximum, steady state), 10 A (surge, 10-ms duration, 10% duty cycle maximum) Output ripple: 33 mVP-P at 8 A Output load response: 0.3 V => 10% to 90% step load change, from 1 A to 7 A Operating temperature: -40°C to 85°C fSW = 300 kHz 1. Calculate maximum and minimum duty cycles V O(min) V O(max) d MIN + + 3.324 + 0.135 d MAX + + 3.366 + 0.337 24 10 VIN(max) V IN(min) (46) 2. Select switching frequency The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit comparator. In order to maintain current limit capability, the on time of the upper MOSFET (tON) must be greater than 300 ns (see the Electrical Characteristics table). Therefore, V O(min) t + ON or V IN(max) T SW (47) VO(min) VIN(max) 1 +f SW + T SW TON (48) Using 400 ns to provide margin, f SW + 0.135 + 337 kHz 400 ns (49) Since the oscillator can vary by 10%, decrease fSW by 10% f SW + 0.9 337 kHz + 303 kHz (50) and therefore choose a frequency of 300 kHz. 3. Select I In this case I is chosen so that the converter enters discontinuous mode at 20% of nominal load. DI + I O 2 0.2 + 8 2 0.2 + 3.2 A (51) 4. Calculate the power losses Power losses in the high-side MOSFET (Si7860DP Si7860DP) at 24-VIN 24-VIN where switching losses dominate can be calculated from Equation 52. d + 8 0.135 + 2.93 A I +I RMS O (52) substituting Equation 34 into Equation 33 yields P COND + 2.932 0.008 (1 ) 0.007 (150 * 25) + 0.129 W (53) and from Equation 33, the switching losses can be determined. P SW(fsw) + VIN I O t SW f SW + 24 V 8 A 20 ns (54) 300 kHz + 1.152 W 23 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 DESIGN EXAMPLE (continued) The MOSFET junction temperature can be found by substituting Equation 35 into Equation 34 T J + PCOND ) PSW q JA ) T A + (0.129 ) 1.152) 40 ) 85 + 136 C O (55) 5. Calculate synchronous rectifier losses The synchronous rectifier MOSFET has two loss components: conduction and diode reverse recovery losses. The conduction losses are due to IRMS losses, as well as body diode conduction losses during the dead time associated with the anti-cross conduction delay. The IRMS current through the synchronous rectifier from Equation 38 1 * d + 8 1 * 0.135 + 7.44 A I +I RMS O RMS (56) The synchronous MOSFET conduction loss from Equation 33 is: P COND + I RMS 2 R DS(on) + 7.44 2 0.008 (1 ) 0.007(150 * 25) + 0.83 W The body diode conduction loss from Equation 39 is: P DC + 2 I O V FD t DELAY f SW + 2 8.0 A 0.8 V The body diode reverse recovery loss from Equation 40 is: P RR + 0.5 Q RR V IN f SW + 0.5 30 nC 24 V 100 ns 300 kHz + 0.384 W 300 kHz + 0.108 W (57) (58) (59) The total power dissipated in the synchronous rectifier MOSFET from Equation 41 is: P SR + PRR ) PCOND ) PDC + 0.108 ) 0.83 ) 0.384 + 1.322 W (60) The junction temperature of the synchronous rectifier at 85°C is: T J + PSR q JA ) T A + (1.322) 40 ) 85 + 139 oC (61) In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode conduction and reverse recovery periods. 6. Calculate the inductor value The inductor value is calculated from Equation 62. (24 * 3.3 V) 3.3 V L+ + 2.96 mH 24 V 3.2 A 300 kHz (62) A 2.9-µH Coev DXM1306-2R9 DXM1306-2R9 or 2.6-µH Panasonic ETQ-P6F2R9LFA can be used. 7. Setting the switching frequency The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be found from Equation 63, with fSW in kHz. RT + f SW 1 17.82 10 *6 * 17 kW + 170 kW N use 169 kW (63) 8. Programming the ramp generator circuit The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also controls the input UVLO voltage. For an undervoltage level of 10 V, RKFF can be calculated from Equation 64. R KFF + VIN(min) * 3.5 58.14 R T ) 1340 kW + 72.5 kW N use 71.5 kW (64) 9. Calculating the output capacitance (CO) In this example the output capacitance is determined by the load response requirement of V = 0.3 V for a 1-A to 8-A step load. CO can be calculated using Equation 65. 24 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 DESIGN EXAMPLE (continued) (8 A)2 * (1 A)2 + 97 mF (3.3)2 * (3.0)2 2.9 m CO + (65) Using Equation 66, we can calculate the ESR required to meet the output ripple requirements. 33 mV + 3.2 A ESR ) 1 8 73 mF 300 kHz (66) ESR + 10.3 mW * 3.33 mW + 6.97 mW (67) For this design example, two Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 m) are used. 10. Calculate the soft-start capacitor (CSS) This design requires a soft-start time (tSTART) of 1 ms. CSS can be calculated on Equation 68 2.3 mA C SS + 1 ms + 3.29 nF + 3300 pF 0.7 V (68) 11. Calculate the current limit resistor (RILIM) The current limit set point depends on tSTART, VO, CO, and ILOAD at start-up as shown in Equation 69. For this design, 360 mF 3.3 V I LIM u ) 8.0 A + 9.2 A 1 ms (69) For this design, set ILIM for 11 ADC minimum. From Equation 70, with IOC equal to the dc-output surge current plus one-half the ripple current of 3.2 A and RDS(on) is increased 30% (1.3 × 0.008) to allow for MOSFET heating. (* 0.02) R ILIM + 12.6 A 0.0104W ) + 15.2 kW * 2.3 kW + 12.9 kW ^ 13 kW 8.6 mA 8.6 mA (70) 12. Calculate loop compensation values Calculate the dc modulator gain (AMOD) from Equation 71 A MOD + 10 + 5.0 AMOD(dB) + 20 log (5) + 14 dB 2 (71) Calculate the output filter L-CO poles and CO ESR zeros from Equation 72 and Equation 73 1 1 f LC + + + 4.93 kHz 2p L C O 2p 2.9 mH 360 mF (72) and fZ + 2p 1 ESR CO + 2p 1 0.006 360 mF + 73.7 kHz (73) Select the close-loop 0 dB crossover frequency (fC). For this example, fC = 20 kHz. Select the double zero location for the Type III compensation network at the output filter double pole at 4.93 kHz. Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7 kHz. The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain AMOD at the crossover frequency from Equation 74. A MOD(f) + AMOD f LC fC 2 +5 kHz 4.93kHz 20 2 + 0.304 (74) And also from Equation 75. 25 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 DESIGN EXAMPLE (continued) G+ 1 + 1 + 3.29 0.304 A MOD(f) (75) Choose R1 = 100 k The poles and zeros for a type III network are described in Equation 25 and Equation 26. 1 1 f Z2 + N C3 + + 323 pF, choose 330 pF 2p R1 C3 2p 100 kW 4.93 kHz 1 1 f P2 + N R3 + + 6.55 kW, choose 6.49 kW 2p R3 C3 2p 330 pF 73.3 kHz fC + 1 2p f P1 + f Z1 + 2p R1 1 R2 2p 1 R2 C2 C2 C1 G N C2 + N R2 + N C1 + (76) (77) 1 2p + 24.2 pF, choose 22 pF 100 kW 3.29 20 kHz 1 + 98.2 kW, choose 97.6 kW 22 pF 73.3 kHz 2p 1 97.6 kW 2p 4.93 kHz + 331 pF, choose 330 pF Calculate the value of RBIAS from Equation 81 with R1 = 100 k. R BIAS + 0.7 V R1 + 0.7 V 100kW + 26.9 kW, choose 26.7 kW VO * 0.7 V 3.3 V * 0.7 V (78) (79) (80) (81) CALCULATING THE BOOST AND BP10V BP10V BYPASS CAPACITANCE The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount of droop allowed on the bypass cap. The BOOST capacitance for the Si7860DP Si7860DP, allowing for a 0.5-V droop on the BOOST pin from Equation 29 is: Qg C BOOST + + 18 nC + 36 nF DV 0.5 V (82) and the BP10V BP10V capacitance from Equation 32 is Q gHS ) Q gSR 2 Qg C BP(10 V) + + + 36 nC + 72 nF DV DV 0.5 V (83) For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1-µF capacitor is used for the BP10V BP10V bypass. 26 TPS40054-EP TPS40054-EP, TPS40055-EP TPS40055-EP, TPS40057-EP TPS40057-EP www.ti.com SGLS310A SGLS310A ­ JULY 2005 ­ REVISED AUGUST 2005 DESIGN EXAMPLE (continued) DESIGN EXAMPLE SUMMARY Figure 17 shows component selection for the 10-V to 24-V to 3.3-V at 8 A dc-to-dc converter specified in the design example. For an 8-V input application, it may be necessary to add a Schottky diode from BP10 to BOOST to get sufficient gate drive for the upper MOSFET. As seen in Figure 8, the BP10 output is about 6 V with the input at 8 V, so the upper MOSFET gate drive may be less than 5 V. A Schottky diode is shown connected across the synchronous rectifier MOSFET as an optional device that may be required if the layout causes excessive negative SW node voltage, greater than or equal to 2 V. + RKFF 71.5 k VIN 330 µF 13 k 330 µF TPS4005xPWP - 1N4150 1N4150 499 k 1 KFF 2 RT RT 169 k 100 pF ILIM 16 VIN 15 0.1 µF 47 pF 3 BP5 1.0 µF BOOST 14 22 µF 50 V 22 µF 50 V 1.0 k Optional Hysteresis for UVLO 4 SYNC 1.0 µF HDRV 13 Si7860 CSS 3300 pF 5 SGND 6 SS + SW 12 R3 6.49 k BP10 11 Si7860 C1 330 pF 7 VFB R2 97.6 k 2.9 µH LDRV 10 R1 100 k 180 µF VOUT 180 µF C3 330 pF 8 COMP C2 22 pF PGND 9 PWP 1.0 µF *optional - RBIAS 26.7 k UDG-03180 UDG-03180 Figure 17. 24 V to 3.3 V at 8-A DC-to-DC Converter Design Example REFERENCES 1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 SEM-1400 Topic 2. 2. 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