TPIC5401 SLIS024A TPIC5401DW TPIC5401NE MPDI003 MS-001 - Datasheet Archive

 

H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 D D D D D Low rDS(on) . . . 0.3

 

TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 D D D D D Low rDS(on) . . . 0.3 Typ High Voltage Output . . . 60 V Extended ESD Capability . . . 4000 V Pulsed Current . . . 10 A Per Channel Fast Commutation Speed description The TPIC5401 TPIC5401 is a monolithic gate-protected power DMOS array that consists of four N-channel enhancement-mode DMOS transistors, two of which are configured with a common source. Each transistor features integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-k resistor. The TPIC5401 TPIC5401 is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature range of ­ 40°C to 125°C. NE PACKAGE (TOP VIEW) DRAIN2 SOURCE2/GND GATE2 GND GND GATE4 SOURCE4/GND DRAIN4 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DW PACKAGE (TOP VIEW) SOURCE1 DRAIN1 GATE1 GND GND GATE3 DRAIN3 SOURCE3 GND SOURCE4/GND GATE4 NC DRAIN4 SOURCE3 DRAIN3 GATE3 NC NC 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 SOURCE2/GND GATE2 NC NC DRAIN2 SOURCE1 DRAIN1 GATE1 NC NC NC ­ No internal connection schematic DRAIN1 DRAIN3 Q1 Q3 Z1 GATE1 D1 D2 Z3 GATE3 ZC1b ZC3b ZC1a SOURCE1 ZC3a SOURCE3 DRAIN4 DRAIN2 Q2 GATE2 Q4 Z2 GATE4 Z4 ZC2b ZC4b ZC2a ZC4a GND, SOURCE2, SOURCE4 NOTE: For correct operation, no terminal pin may be taken below GND. Copyright © 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 absolute maximum ratings over operating case temperature range (unless otherwise noted) Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Source-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage (Q2, Q4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 9 V to 18 V Continuous drain current, each output, TC = 25°C: DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 A NE package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . 10 A Continuous gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Pulsed gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4, 15, and 16) . . . . . . . . . . . . . . . . . . . . . . 21 mJ Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 40°C to 125°C Storage temperature range, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2% DISSIPATION RATING TABLE PACKAGE DERATING FACTOR ABOVE TC = 25°C TC = 125°C POWER RATING DW NE 2 TC 25°C POWER RATING 1389 mW 2075 mW 11.1 mW/°C 16.6 mW/°C 279 mW 415 mW POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 electrical characteristics, TC = 25°C (unless otherwise noted) PARAMETER V(BR)DSX VGS(th) Gate-to-source threshold voltage V(BR)GS V(BR)SG TEST CONDITIONS ID = 250 µA, ID = 1 mA, See Figure 5 Drain-to-source breakdown voltage Gate-to-source breakdown voltage VGS = 0 VDS = VGS, IGS = 250 µA ISG = 250 µA Source-to-gate breakdown voltage MIN TYP MAX 60 1.5 UNIT V 1.85 2.2 V 18 V 9 V 100 V V(BR) Reverse drain-to-GND breakdown voltage (across D1, D2) Drain-to-GND current = 250 µA VDS(on) Drain-to-source on-state voltage ID = 2 A, See Notes 2 and 3 VF(SD) Forward on-state voltage, source-to-drain IS = 2 A, VGS = 0 (Z1, Z2, Z3, Z4), See Notes 2 and 3 and Figure 12 VF Forward on-state voltage, GND-to-drain ID = 2 A (D1, D2), See Notes 2 and 3 IDSS Zero-gate-voltage Zero gate voltage drain current VDS = 48 V, , VGS = 0 TC = 25°C TC = 125°C IGSSF IGSSR Forward-gate current, drain short circuited to source Reverse-gate current, drain short circuited to source VGS = 15 V, VSG = 5 V, VDS = 0 VDS = 0 Ilk lkg Leakage current, drain-to-GND current drain to GND VDGND = 48 V TC = 25°C TC = 125°C 0.05 1 0.5 10 0.3 0.35 Static drain-to-source on-state resistance drain to source on state VGS = 10 V, ID = 2 A, , See Notes 2 and 3 and Figures 6 and 7 TC = 25°C rDS( ) DS(on) TC = 125°C 0.47 0.5 VGS = 10 V, Forward transconductance Ciss Short-circuit output capacitance, common source Crss Short-circuit reverse-transfer capacitance, common source V 1 1.2 V V 0.05 1 0.5 10 20 200 nA 10 100 nA 1.6 1.9 µA S 220 120 VGS = 0, See Figure 11 275 150 100 VDS = 25 V, f = 1 MHz, µA Short-circuit input capacitance, common source Coss 0.7 7.5 VDS = 15 V, ID = 1 A, See Notes 2 and 3 and Figure 9 gfs 0.6 125 pF F NOTES: 2. Technique should limit TJ ­ TC to 10°C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP Z1 and Z3 trr Z2 and Z4 QRR VDS = 48 V, A/µs, di/dt = 100 A/µs Total diode charge POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 280 Z1 and Z3 0.12 0.9 UNIT 260 D1 and D2 IS = 1 A, 0, VGS = 0 See Figures 1 and 14 D1 and D2 Z2 and Z4 Reverse-recovery time MAX 120 2.2 ns µC 3 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX 32 65 40 80 15 30 Fall time 25 50 Total gate charge 6.6 8 0.8 1 2.6 3.2 td(on) td(off) Turn-on delay time tr tf Rise time Qg Qgs(th) Threshold gate-to-source charge Qgd Gate-to-drain charge Ld Ls Internal drain inductance 5 Internal source inductance 5 Rg Internal gate resistance Turn-off delay time VDD = 25 V, , t dis = 10 ns, VDS = 48 V, V See Figure 3 RL = 25 , , See Figure 2 ID = 1 A, A ten = 10 ns, , VGS = 10 V, V UNIT ns nC nH 0.25 thermal resistances PARAMETER TEST CONDITIONS RJA Junction to ambient thermal resistance (see Note 4) Junction-to-ambient RJB Junction-to-board thermal resistance RJP Junction-to-pin Junction to pin thermal resistance MIN TYP DW 60 All outputs with equal power 30 NE 25 PARAMETER MEASUREMENT INFORMATION I S ­ Source-to-Drain Diode Current ­ A 2 Reverse di/dt = 100 A/µs VDS = 48 V VGS = 0 TJ = 25°C Z1 and Z3 0 25% of IRM ­1 Shaded Area = QRR ­2 IRM trr(SD) ­4 0 200 400 600 Time ­ ns 800 1000 1200 IRM = maximum recovery current The above waveform is representative of Z2, Z4, D1, and D2 in shape only. Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode 4 53 DW NOTE 4: Package mounted on an FR4 printed-circuit board with no heatsink. ­3 UNIT 90 NE DW 1 MAX POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 °C/W TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 PARAMETER MEASUREMENT INFORMATION VDD = 25 V ten RL Pulse Generator 10 V VDS VGS 0V VGS 50 tr tf CL 30 pF (see Note A) 50 td(off) td(on) DUT Rgen tdis VDD VDS VDS(on) VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms Current Regulator 12-V Battery 0.2 µF Qg Same Type as DUT 50 k 10 V 0.3 µF Qgs(th) VDD VDS 0V VGS Gate Voltage DUT IG = 100 µA Qgd Time WAVEFORM IG CurrentSampling Resistor ID CurrentSampling Resistor TEST CIRCUIT Figure 3. Gate-Charge Test Circuit and Waveform POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 PARAMETER MEASUREMENT INFORMATION VDD = 25 V 354 µH Pulse Generator (see Note A) 15 V VGS VDS ID tav tw 0V IAS (see Note B) VGS 50 ID DUT 0V Rgen 50 V(BR)DSX = 60 V Min VDS 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration (tw) is increased until peak current IAS = 10 A. I V t av AS (BR)DSX Energy test level is defined as E 21 mJ. AS 2 + + Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 2.5 0.5 VDS = VGS ID = 2 A ID = 1 mA 1.5 ID = 100 µA 1 0.5 0 ­ 40 ­ 20 0 20 40 60 80 100 120 140 160 On-State Resistance ­ 2 r DS(on) ­ Static Drain-to-Source VGS(th) ­ Gate-to-Source Threshold Voltage ­ V GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS = 10 V 0.4 0.3 0.2 0.1 0 ­ 40 ­ 20 TJ ­ Junction Temperature ­ °C 0 20 40 60 Figure 6 POST OFFICE BOX 655303 80 100 120 140 160 TJ ­ Junction Temperature ­ °C Figure 5 6 VGS = 15 V · DALLAS, TEXAS 75265 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 TYPICAL CHARACTERISTICS DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 5 TJ = 25°C 0.5 0.4 VGS = 10 V 0.3 VGS = 15 V 0.2 TJ = 25°C (unless otherwise noted) VGS = 15 V 4 0.6 3 VGS = 4 V 2 1 VGS = 3 V 0.1 0.01 0 0.10 1 ID ­ Drain Current ­ A 10 2 0 4 6 8 10 12 14 16 18 VDS ­ Drain-to-Source Voltage ­ V Figure 7 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE 10 30 Total Number of Units = 1040 VDS = 15 V ID = 1 A TJ = 25°C TJ = 25°C 9 TJ = 75°C 8 I D ­ Drain Current ­ A 25 20 Figure 8 DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 20 15 10 TJ = 125°C 7 6 5 4 3 2 TJ = 150°C 5 1 2 1.975 1.95 1.925 1.9 1.875 1.85 1.825 TJ = ­ 40°C 0 1.8 Percentage of Units ­ % nVGS = 0.2 V VGS = 10 V I D ­ Drain Current ­ A On-State Resistance ­ r DS(on) ­ Static Drain-to-Source 1 0.9 0.8 0.7 0 0 1 2 3 4 5 6 7 8 9 10 VGS ­ Gate-to-Source Voltage ­ V gfs ­ Forward Transconductance ­ S Figure 9 Figure 10 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 TYPICAL CHARACTERISTICS CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 500 400 I SD ­ Source-to-Drain Diode Current ­ A 450 Capacitance ­ pF 10 f = 1 MHz VGS = 0 TJ = 25°C 350 300 Ciss 250 200 Coss 150 100 Crss 50 VGS = 0 6 4 2 1 0.6 TJ = 125°C TJ = 150°C TJ = 25°C 0.2 TJ = 75°C 0 0 10 20 30 0.1 40 0.1 VDS ­ Drain-to-Source Voltage ­ V 1 VSD ­ Source-to-Drain Voltage ­ V Figure 11 REVERSE-RECOVERY TIME vs REVERSE di/dt VDD = 20 V VDD = 30 V 40 VDS = 48 V VGS = 0 IS = 1 A TJ = 25°C See Figure 1 350 10 8 30 6 20 4 VDD = 48 V 2 10 trr ­ Reverse-Recovery Time ­ ns 50 400 12 ID = 1 A TJ = 25°C See Figure 3 VGS ­ Gate-to-Source Voltage ­ V 60 10 Figure 12 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE VDS ­ Drain-to-Source Voltage ­ V TJ = ­ 40°C 0.4 300 250 Z2 and Z4 200 150 Z1 and Z3 100 50 VDD = 20 V 0 0 0 1 2 3 4 5 6 7 0 0 Qg ­ Gate Charge ­ nC Figure 13 8 100 200 300 400 Reverse di/dt ­ A/µs Figure 14 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 500 600 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE MAXIMUM PEAK-AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 30 100 I AS ­ Maximum Peak Avalanche Current ­ A I D ­ Maximum Drain Current ­ A TC = 25°C 1 µs 10 10 ms 1 ms 500 µs 1 ÁÁ ÁÁ ÁÁ 0.1 0.1 DW Pkg NE Pkg DC Conditions 1 10 VDS ­ Drain-to-Source Voltage ­ V 100 See Figure 4 10 TC = 25°C TC = 125°C 1 0.01 0.1 1 10 100 tav ­ Time Duration of Avalanche ­ ms Less than 2% duty cycle Figure 15 Figure 16 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 9 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 THERMAL INFORMATION NE PACKAGE NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE vs PULSE DURATION RJA ­ Normalized Junction-to-Ambient Thermal Resistance ­ °C/W 10 DC Conditions 1 d = 0.5 d = 0.2 d = 0.1 0.1 d = 0.05 d = 0.02 d = 0.01 0.01 Single Pulse 0.001 tc tw ID 0 0.0001 0.0001 0.001 0.1 0.01 tw ­ Pulse Duration ­ s Device mounted on FR4 printed-circuit board with no heatsink. NOTE A: ZJA(t) = r(t) RJA tw = pulse duration tc = cycle time d = duty cycle = tw/tc Figure 17 10 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 10 TPIC5401 TPIC5401 H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY SLIS024A SLIS024A ­ DECEMBER 1993 ­ REVISED MARCH 1994 THERMAL INFORMATION DW PACKAGE JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION 100 RJB ­ Junction-to-Board Thermal Resistance ­ °C/W DC Conditions d = 0.5 d = 0.2 10 d = 0.1 d = 0.05 d = 0.02 1 d = 0.01 tc Single Pulse tw ID 0 0.1 0.0001 0.001 0.01 0.1 1 10 tw ­ Pulse Duration ­ s Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink. NOTE B: ZJB(t) = r(t) RJB tw = pulse duration tc = cycle time d = duty cycle = tw/tc Figure 18 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPIC5401DW TPIC5401DW OBSOLETE SOIC DW 20 TBD Call TI Call TI TPIC5401NE TPIC5401NE OBSOLETE PDIP NE 16 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDI003 MPDI003 ­ OCTOBER 1994 NE (R-PDIP-T*) PLASTIC DUAL-IN-LINE PACKAGE 20 PIN SHOWN 0.070 (1,78) MAX 11 20 PINS * DIM A C 16 0.914 (23,22) MIN MAX 20 0.780 (19,80) 0.975 (24,77) 1 MIN 0.930 (23,62) MAX B 1.000 (25,40) 10 MIN 0.240 (6,10) 0.260 (6,61) MAX C 0.260 (6,60) 0.280 (7,11) 0.020 (0,51) MIN A 0.200 (5,08) MAX Seating Plane 0.155 (3,94) 0.125 (3,17) 0.100 (2,54) 0.021 (0,533) 0.015 (0,381) 0.010 (0,25) M 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN B 0.200 (5,08) MAX Seating Plane 0.155 (3,94) 0.125 (3,17) 0.100 (2,54) 0.021 (0,533) 0.015 (0,381) 0.010 (0,25) M 0°­ 15° 0.010 (0,25) NOM 4040054 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 MS-001 (16 pin only) POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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