TPIC1021 SLIS113C SAEJ2602 TMS430 TMS470 TPIC1021D TPIC1021DG4 TPIC1021DR - Datasheet Archive

 

LIN Physical Interface www.ti.com SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 · FEATURES · ·

 

TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 · FEATURES · · · · · · · · · · LIN Physical Layer Specification Revision 2.0 compliant. Conforms to SAEJ2602 SAEJ2602 Recommended Practice for LIN LIN Bus Speed up to 20 kbps ESD Protection to 12 kV (Human Body Model) on LIN Pin LIN Pin Handles Voltage from -40 V to +40 V Survives Transient Damage in Automotive Environment (ISO 7637) Operation with Supply from 7 V to 27 V DC Two Operation Modes: Normal and Low Power (Sleep) Mode Low Current Consumption in Low Power Mode Wake-Up Available from LIN Bus, Wake-Up Input (External Switch) or Host MCU Interfaces to MCU with 5 V or 3.3 V I/O Pins Dominant State Timeout Protection on TXD Pin Wake-Up Request on RXD Pin Control of External Voltage Regulator (INH Pin) Integrated Pull-Up Resistor and Series Diode for LIN Slave Applications Low EME (Electromagnetic Emissions), High EMI (Electromagnetic Immunity) Bus Terminal Short-Circuit Protected for Short to Battery or Short to Ground Thermally Protected Ground Disconnection Fail Safe at System Level Ground Shift Operation at System Level Unpowered Node Does Not Disturb the Network · · · · · · · · · D PACKAGE (TOP VIEW) RXD EN NWake TXD 1 8 2 7 3 6 4 5 INH VSUP LIN GND DESCRIPTION The TPIC1021 TPIC1021 is the LIN (Local Interconnect Network) physical interface, which integrates the serial transceiver with wake up and protection features. The LIN bus is a single wire, bi-directional bus typically used for low-speed in-vehicle networks using baud rates between 2.4 kbps and 20 kbps. The LIN bus has two logical values: the dominant state (voltage near ground) represents a logic `0' and the recessive state (voltage near battery) and represents logic `1'. In the recessive state the LIN bus is pulled high by the TPIC1021 TPIC1021's internal pull-up resistor (30k) and series diode, so no external pull-up components are required for slave applications. Master applications require an external pull-up resistor (1k) plus a series diode. The LIN Protocol output data stream on the TXD pin is converted by the TPIC1021 TPIC1021 into the LIN bus signal through a current limited, wave-shaping low-side driver with control as outlined by the LIN Physical Layer Specification Revision 2.0. The receiver converts the data stream from the LIN bus and outputs the data stream via the RXD pin. In Low Power mode, the TPIC1021 TPIC1021 requires very low quiescent current even though the wake-up circuits remain active allowing for remote wake up via the LIN bus or local wake ups via NWake or EN pins. The TPIC1021 TPIC1021 has been designed for operation in the harsh automotive environment. The device can handle LIN bus voltage swing from +40 V down to ground and survive -40 V. The device also prevents back feed current through the LIN pin to the supply input in case of a ground shift or supply voltage disconnection. It also features under-voltage, over temperature, and loss of ground protection. In the event of a fault condition the output is immediately switched off and remains off until the fault condition is removed. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004­2005, Texas Instruments Incorporated TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 TERMINAL FUNCTIONS Terminal Assignments PIN NO. PIN TYPE RXD PIN NAME 1 O RXD output (open drain) pin interface reporting state of LIN bus voltage DESCRIPTION EN 2 I Enable input pin NWake 3 I High voltage input pin for device wake up TXD 4 I TXD input pin interface to control state of LIN output GND 5 I Ground connection LIN 6 I/O VSUP 7 Supply INH 8 O LIN bus pin single wire transmitter and receiver Device supply pin (connected to battery in series with external reverse blocking diode) Inhibit pin controls external voltage regulator with inhibit input LIN Bus Pin This I/O pin is the single-wire LIN bus transmitter and receiver. Transmitter Characteristics The driver is a low side transistor with internal current limitation and thermal shutdown. There is an internal 30-k pull-up resistor with a serial diode structure to Vsup so no external pull-up components are required for LIN slave mode applications. An external pull-up resistor of 1 k plus a series diode to Vsup must be added when the device is used for master node applications. Voltage on the LIN pin can go from -40 V to +40 V DC without any currents other than through the pull-up resistance. There are no reverse currents from the LIN bus to supply (Vsup), even in the event of a ground shift or loss of supply (Vsup). The LIN thresholds and ac parameters are compatible LIN Protocol Specification Revision 2.0. During a thermal shut down condition the driver is disabled. Receiver Characteristics The receiver's characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%, with a hysteresis between 5% and 17.5% of supply. Transmit Input Pin (TXD) This pin is the interface to the MCU's LIN Protocol Controller or SCI/UART used to control the state of the LIN output. When TXD is low, LIN output is dominant (near ground). When TXD is high, LIN output is recessive (near battery). TXD input structure is compatible with microcontrollers with 3.3 V and 5.0 V I/O. This pin has an internal pull-down resistor. TXD Dominant State Timeout If the TXD pin is inadvertently driven permanently low by a hardware or software application failure, the LIN bus is protected by TPIC1021 TPIC1021's Dominant State Timeout Timer. This timer is triggered by a falling edge on the TXD pin. If the low signal remains on the TXD pin for longer than tDST, the transmitter is disabled thus allowing the LIN bus to return to the recessive state and communication to resume on the bus. The timer is reset by a rising edge on TXD pin. Receive Output Pin (RXD) This pin is the interface to the MCU's LIN Protocol Controller or SCI/UART, which reports the state of the LIN bus voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground) is represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the TPIC1021 TPIC1021 to be used with 3.3 V and 5 V I/O microcontrollers. If the microcontroller's RXD pin does not have an integrated pull-up, an external pull-up resistor to the microcontroller I/O supply voltage is required. 2 www.ti.com TPIC1021 TPIC1021 LIN Physical Interface SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 RXD Wake-up Request When the TPIC1021 TPIC1021 has been in low power mode and encounters a wake-up event from the LIN bus or NWake pin the RXD pin will go LOW while the device enters and remains in Standby Mode (until EN is re-asserted high and the device enters Normal Mode). Supply Voltage (VSUP) The TPIC1021 TPIC1021 device power supply pin. This pin is connected to the battery through an external reverse battery blocking diode. The continuous DC operating voltage range for the TPIC1021 TPIC1021 is from 7 V to +27 V. The VSUP is protected to for harsh automotive conditions of up to + 40 V. The device contains a reset circuit to avoid false bus messages during under-voltage conditions when VSUP is less than VSUP_UNDER. Ground (GND) TPIC1021 TPIC1021 device ground connection. The TPIC1021 TPIC1021 can operate with a ground shift as long as the ground shift does not reduce VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the TPIC1021 TPIC1021 will not have a significant current consumption on the LIN pin while in the recessive state ( VSUP_unde, EN = 0 C:VSUP > VSUP_unde, EN = 1 VSUP < VSUP_under A A A C EN = 1 Standby Mode TXD: off RXD: LOW IHN: HIGH (high side switched on) Term: 30 kW B LIN Bus Wake-UP or NWake Pin Wake-Up Low Power Mode Normal Mode TXD: on RXD: LIN bus data IHN: HIGH (high side switched on) Term: 30 kW EN = 0 EN = 1 TXD: off RXD: floating IHN: high impedance (high side switched off) Term: highW Figure 1. Operating States Diagram 4 TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 OPERATING STATES (continued) Operating Modes MODE EN RXD LIN BUS TERMINATION INH TRANSMITTER Low Power 0 Floating High impedance High impedance Off Standby 0 Low 30 k (typical) High Off Normal 1 LIN bus data 30 k (typical) High COMMENTS On Wake-up event detected, waiting on MCU to set EN Normal Mode This is the normal operational mode where the receiver and driver are active. The receiver detects the data stream on the LIN bus and outputs it on the RXD pin for the LIN controller where recessive on the LIN bus is a digital high and dominate on the LIN bus is digital low. The driver will transmit input data on the TXD pin to the LIN bus. Low Power Mode The power saving mode for the TPIC1021 TPIC1021 and the default state after power-up (assuming EN=0). Even with the extremely low current consumption in this mode, the TPIC1021 TPIC1021 can still wake-up from LIN bus activity, a falling edge on the NWake pin or if EN is set high. The LIN bus and NWake pins are filtered to prevent false wake-up events. The wake-up events must be active for their respective time periods: tLINBUS, tNWake. The low power mode is entered by setting the EN pin low. While the device is in low power mode the following conditions exist: · The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if LIN is short-circuited to ground). · The normal receiver is disabled. · The INH pin is high impedance. · EN input, NWake input and the LIN wake-up receiver are active. Wake-Up Events There are three ways to wake-up the TPIC1021 TPIC1021 from Low Power Mode. · Remote wake-up via recessive (high) to dominant (low) state transition on LIN Bus where dominant bus state of 50% threshold is detected. The dominant state must be held for tLINBUS filter time (to eliminate false wake ups from disturbances on the LIN Bus). · Local wake-up via falling edge on NWake pin which is held low for filter time tNWake (to eliminate false wake ups from disturbances on NWake). · Local wake-up via EN being set high Standby Mode This mode is entered whenever a wake-up event occurs via the LIN bus or NWake pin while the TPIC1021 TPIC1021 is in low power mode. The LIN bus slave termination circuit and the INH pin are turned on when standby mode is entered. The application system will power up once the INH pin is turn assuming it is using a voltage regulator connected via INH pin. Standby Mode is signaled via a low level on RXD pin. When EN pin is set high while the TPIC1021 TPIC1021 is in Standby Mode the device returns to Normal Mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are turned on. 5 TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 LIN tLINBUS VSUP INH High Impedance EN System Wake-Up Time (Vreg + MCU) RXD MODE Floating Low Power Standby Normal Figure 2. Wake-Up Via LIN Bus Timing Diagram Falling Edge on NWake NWake tNWake VSUP INH High Impedance EN System Wake-Up Time (Vreg + MCU) RXD MODE Floating Low Power Standby Figure 3. Wake-Up Via NWake Timing Diagram 6 Normal TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER RATING UNIT Supply line supply voltage (continuous) 0 to 27 V Supply line supply voltage (transient) VSUP (2) 0 to 40 V NWake DC and transient input voltage (through 33-k serial resistor) -1 to 40 V Logic pin input voltage (RXD, TXD, EN) -0.3 to 5.5 V LIN DC input voltage -40 to 40 V Electrostatic discharge: Human Body Model: LIN pin (3) -12 to 12 kV Electrostatic discharge: Human Body Model: NWake pin (3) -9 to 9 kV Electrostatic discharge: Human Body Model: All other pins (3) -3 to 3 kV -400 to 400 V Electrostatic discharge: Machine Model: LIN and NWake pins (4) Electrostatic discharge: Machine Model: All other pins (4) -200 to 200 V TA Operational free-air temperature -40 to 125 °C TJ Junction temperature -40 to 150 °C Tstg Storage temperature -40 to 165 °C RJA Thermal resistance, junction-to-ambient 145 °C/W Thermal shutdown 200 °C Thermal shutdown hysteresis 25 °C (1) (2) (3) (4) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. The human body model is a 100-pF capacitor discharged through a 1.5-k resistor into each pin. The machine model is a 200-pF capacitor through a 10- resistor and a 0.75-µH coil. 7 TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 ELECTRICAL CHARACTERISTICS VSUP = 7 V to 27 V, TA = -40°C to 125°C (unless otherwise noted) MIN TYP (1) MAX 7 14 27 V 14 18 V 1.2 2.5 mA 1 2.1 mA Normal Mode, EN = 1, Bus recessive 300 500 µA Standby Mode, EN = 0, Bus recessive 300 500 µA Low Power Mode, EN = 0, VSUP < 14 V, NWake = VSUP, LIN = VSUP 20 50 µA Low Power Mode, EN = 0, 14 V < VSUP < 27 V, NWake = VSUP, LIN = VSUP PARAMETER 50 100 µA TEST CONDITIONS UNIT SUPPLY Operational supply voltage (2) Nominal supply line voltage (2) 7 VSUP undervoltage threshold (2) ICC Supply Current 4.5 Normal Mode, EN = 1, Bus dominant (total bus load > 500 ) (3) Standby Mode, EN = 0, Bus dominant (total bus load > 500 ) (3) V RXD OUTPUT PIN VO Output voltage IOL Low-level output current, open drain LIN = 0 V, RXD = 0.4 V -0.3 3.5 IIKG Leakage current, high-level LIN = VSUP, RXD = 5 V -5 5.5 V mA 0 5 µA 0.8 V TXD INPUT PIN VIL Low-level input voltage (2) VIH High-level input voltage (2) VIT Input threshold hysteresis voltage (2) -0.3 2 Pull-down resistor IIL Low-level input current 5.5 V 30 500 mV 125 TXD = 0 350 800 k -5 0 5 µA LIN PIN (Referenced to VSUP) VOH High-level output voltage (2) LIN recessive, TXD = High, IO = 0 mA VSUP-1V VOL Low-level output voltage (2) LIN dominant, TXD = Low, IO = 40 mA 0 Pull-up resistor to VSUP V 0.2×VSUP V 20 30 60 k IL Limiting current TXD = Low 50 150 250 mA IIKG Leakage current LIN = VSUP -5 0 5 µA VIL Low-level input voltage (2) LIN dominant 0×VSUP 0.4×VSUP V VIH High-level input voltage (2) LIN recessive 0.6×VSUP VSUP V VIT Input threshold voltage (2) Vhys Hysteresis voltage (2) VIL Low-level input voltage for wake-up (2) 0.6×VSUP V 0.05×VSUP 0.4×VSUP 0.5×VSUP 0.175×VSUP V 0 0.4×VSUP V -0.3 0.8 V EN PIN VIL Low-level input voltage (2) VIH High-level input voltage (2) Vhys Hysteresis voltage (2) (1) (2) (3) 8 2 5.5 V 30 500 mV Typical values are give for VSUP = 14 V at 25°C. All voltages are defined with respect to ground; positive currents flow into the TPIC1021 TPIC1021 device. In the dominant state the supply current increases as the supply voltage increases due to the integrated LIN slave termination resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN slave termination is 20 k so the maximum supply current attributed to the termination is: ISUP (dom) max termination (VSUP­ (VLIN_Dominant+0.7V) / 20 k. TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 ELECTRICAL CHARACTERISTICS (continued) VSUP = 7 V to 27 V, TA = -40°C to 125°C (unless otherwise noted) TEST CONDITIONS Pull-down resistor IIL MIN TYP (1) MAX UNIT 125 PARAMETER 350 800 k -5 0 5 µA Low-level input current EN = 0 V Vo DC output voltage Transient voltage IO Ouptut current Ron On state resistance Between VSUP and INH, INH = 2 mA drive, Normal or Standby Mode 25 40 100 IIKG Leakage current Low Power mode, 0 < INH < VSUP -5 0 5 µA V INH PIN -0.3 VSUP+0.3 -50 2 V mA NWake PIN VIL (4) -0.3 VSUP-3.3 voltage (4) VSUP-1 VSUP+0.3 V Low-level input voltage VIH High-level input Pull-up current Leakage current IIKG NWake = 0 V VSUP = NWake -40 -10 -4 µA -5 0 5 µA THERMAL SHUTDOWN Shutdown junction thermal temperature 185 °C AC CHARACTERISTICS D1 Duty cycle 1 (5) (6) THREC(max) = 0.744×VSUP, THDOM(max) = 0.581×VSUP, VSUP = 7.0 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 4 D2 Duty cycle 2 (5) (6) THREC(max) = 0.284×VSUP, THDOM(max) = 0.422×VSUP, VSUP = 7.6 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 4 D3 Duty cycle 3 (5) (6) THREC(max) = 0.778×VSUP, THDOM(max) = 0.616×VSUP, VSUP = 7.0 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 4 D4 Duty cycle 4 (5) (6) THREC(max) = 0.251×VSUP, THDOM(max) = 0.389×VSUP, VSUP = 7.6 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 4 trx_pdr Receiver rising propagation delay time RL = 2.4 k, CL = 20 pF, See Figure 4 6 µs trx_pdf Receiver falling propagation delay time RL = 2.4 k, CL = 20 pF, See Figure 4 6 µs trx_sym Symmetry of receiver propagation delay time (rising edge) wrt falling edge, See Figure 4 -2 2 µs tNWake NWake filter time for local wake-up See Figure 4 25 50 100 µs tLINBUS LIN wake-up filter time (dominant time for wake-up via LIN bus) See Figure 4 25 50 100 µs tDST Dominant state timeout (7) See Figure 4 6 9 14 ms (4) (5) (6) (7) 0.396 0.581 0.417 0.590 All voltages are defined with respect to ground; positive currents flow into the TPIC1021 TPIC1021 device. Duty cycle = tBUS_rec(min)/ (2×tBIT) Duty Cycles: LIN Driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 k; Load2 = 6.8 nF, 660 ; Load3 = 10 nF, 500 . Duty Cycles 3 and 4 are defined for 10.4 kbps operation. The TPIC1021 TPIC1021 also meets these lower speed requirements, while it is capable of of the higher speed 20.0 kbps operation as specified by Duty Cycles 1 and 2. SAEJ2602 SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details please refer to the SAEJ2602 SAEJ2602 specification. Dominant state timeout will limit the minimum data rate to 2.4 kbps. 9 TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 TIMING DIAGRAMS tBit tBit tBit RECESSIVE TXD (Input) DOMINANT tBus_dom(max) tBus_rec(min) THRec(max) THDom(max) Thresholds of receiving node 1 VSUP LIN Bus Signal (Transceiver supply of transmitting node) Thresholds of receiving node 2 THRec(min) THDom(min) tBus_dom(min) tBus_rec(max) RXD (Output of receiving node 1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving node 2) trx_pdr(2) trx_pdf(2) Figure 4. Definition of Bus Timing Parameters 10 TPIC1021 TPIC1021 LIN Physical Interface www.ti.com SLIS113C SLIS113C ­ OCTOBER 2004 ­ REVISED JULY 2005 APPLICATION INFORMATION VBAT VSUP MASTER NODE TPIC7xxxx VSUP VDD NWake VDD INH Master Node Pull-Up3 VSUP EN 2 8 3 7 MCU w/o pull-up2 MCU V 1 k VDD I/O TPIC1021 TPIC1021 TMS430 TMS430 TMS470 TMS470 GND VSUP LIN Controller or SCI/UART1 bat RXD TXD LIN 1 6 4 220 pF 5 LIN Bus VDD SLAVE NODE TPIC7xxxx VSUP VDD NWake INH VSUP VDD EN 2 8 3 7 MCU w/o pull-up2 VDD I/O MCU TPIC1021 TPIC1021 TMS430 TMS430 TMS470 TMS470 LIN Controller or SCI/UART1 GND RXD TXD LIN 1 4 6 5 (1) RXD on MCU or LIN Slave has internal pull-up, no external pull-up resistor is needed. (2) RXD on MCU or LIN Slave without internal pull-up, requires external pull-up resistor. (3) 220 pF Master Node applications require an external 1-k pull-up resistor and serial diode. Figure 5. 11 PACKAGE OPTION ADDENDUM www.ti.com 4-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TPIC1021D TPIC1021D ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-235C-UNLIM TPIC1021DG4 TPIC1021DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC1021DR TPIC1021DR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-1-235C-UNLIM TPIC1021DRG4 TPIC1021DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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