TN1074 IPC7351 BN256 UMN64 MN100 MN132 MN144 4000ZE LC4064ZEMN64 LC4064ZEUMN64 - Datasheet Archive

 

for BGA Packages September 2010 Technical Note TN1074 Introduction As Ball Grid Array (BGA) packages become increasingly popular

 

PCB Layout Recommendations for BGA Packages September 2010 Technical Note TN1074 TN1074 Introduction As Ball Grid Array (BGA) packages become increasingly popular and become more populated across the array with higher pin count and smaller pitch, it is important to understand how they are affected by various board layout techniques. This document provides a brief overview of PCB layout considerations when working with BGA packages. It outlines some of the most common problems and provides tips for avoiding them at the design stage. A key challenge of adopting fine-pitch (0.8 mm or less) BGA packages is the design of a route fanout pattern that maximizes I/O utilization while minimizing fabrication cost. This technical note provides an overview of PCB design examples provided by Lattice Semiconductor. For more information and design examples see the PCB Design Support page at the Lattice Semiconductor web site (www.latticesemi.com/support/pcbdesignsupport.cfm). BGA Board Layout Recommendations All Lattice BGA packages have Solder Mask Defined (SMD) pads. In order to evenly balance the stress in the solder joints, Lattice recommends PCB solder pads be SMD with dimensions as similar to the applicable BGA as possible. If Non Solder Mask Defined Pads (NSMD) are used, the optimum pad dimensions will result in an equivalent surface contact area on the PCB as on the BGA component. Table 19-1. Lattice Semiconductor SMD/NSMD Pad Recommendations1 0.4 mm Ball Pitch 64, 132 ucBGA Nominal BGA package pad opening diameter (mm) - SMD 0.5 mm Ball Pitch 0.8 mm Ball Pitch 56, 64, 100, 132, 144 csBGA 49, 100, 256 caBGA 0.20 0.27 1.0 mm Ball Pitch 0.40 1.27 mm Ball Pitch 256 ftBGA (Option 23), 324 ftBGA, 144, 208, 272, 388 PBGA, 100 fpBGA, 256, 388, 416, 484, 516, 1020, 1152, 672, 676, 900, 1152, 1704 Organic 256, 320, 256 ftBGA 1156 fpBGA fcBGA 352 SBGA (Option 12) 0.40 0.45 0.50 0.60 0.40 0.45 0.50 0.60 0.40 0.45 0.55 PCB Solder Mask Defined (SMD) Pad Recommendations Optimum solder mask opening 0.22 0.30 0.40 PCB Non Solder Mask Defined (NSMD) Pad Recommendations Optimum solder land diameter 0.17 0.25 0.35 0.35 1. These Lattice-recommended PCB design values will result in optimum Board Level Reliability (BLR) performance for each corresponding package. Those who use PCB design values which deviate from these recommendations should understand that the BLR performance may be reduced. 2. ispMACH 4000, MachXO, LatticeXP2. 3. LatticeECP3. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 19-1 tn1074_01.9 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Table 19-2. Lattice Semiconductor BGA Package Types Package Type Description PBGA Plastic BGA with 1.27 mm solder ball pitch. Die up configuration. fpBGA Fine Pitch BGA ­ Plastic BGA with 1.0 mm solder ball pitch. Die up configuration. ftBGA Fine Pitch Thin BGA ­ Thin plastic BGA with 1.0 mm solder ball pitch. Die up configuration. caBGA Chip Array BGA ­ Plastic BGA with 0.8 mm solder ball pitch. Die up configuration. csBGA Chip Scale BGA ­ Plastic BGA with 0.5 mm solder ball pitch. Die up configuration. fcBGA Flip-Chip BGA with 1.0 mm solder ball pitch. Die down configuration. May have a ceramic or plastic substrate. SBGA Super BGA ­ Similar to PBGA, but with an integrated heatsink plate. This package has 1.27 mm solder ball pitch and die down configuration. SBGA packages offer enhanced thermal dissipation capability. fpSBGA Fine Pitch SBGA ­ Super BGA with 1.0 mm solder ball pitch. Die down configuration. ucBGA Ultra Chip BGA ­ Saw singulated plastic ball grid array package with 0.4 mm ball pitch. BGA Breakout and Routing Examples Lattice provides several resources and different design implementations that show BGA breakout and routing of various fine-pitch BGA packages. Different stack up and layer counts are also used to show a range of design rules and fabrication costs. It is important to consult with your board fabrication and assembly houses as to the most economical and reliable process for your application. Currently there is a wide choice of BGAs from Lattice, with many devices offered in multiple packages and pitches of BGA densities as well as non-BGA options such as TQFP, QFN and others. The BGA pitch or "center to center" ball dimensions include, 1.00 mm BGAs, space-saving 0.5 mm pitch chip scale BGA and 0.4mm pitch ultra chip scale BGA packages. Fine pitch packages offer advantages and disadvantages alike. Finer pitch means that the trace and space limits will have to be adjusted down to match the BGA. Many times a design can get away with small traces underneath the BGA then fan out with a slightly larger trace width. The PCB fabrication facility will need to be aware of your design objectives and check for the smallest trace dimensions supported. Smaller traces take more time to inspect, check and align etc. Etching needs to be closely monitored when trace and space rules reach their lower limit. The combination of fanout traces, escape vias, and escape traces that allow routing out from under the BGA pin array to the perimeter of the device are collectively referred to as the "BGA breakout". The fanout pattern will arrange the breakout via, layer, and stack-up to maximize the number of I/Os that can be routed. Fanout patterns are an important consideration for devices over 800 pins and can be follow polar (north/south/east/west) or layerbiased directions. (Source: BGA Breakouts and Routing, Charles Pfeil, Mentor Graphics). 19-2 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Figure 19-1. BGA Breakout Routing Terms Lattice provides BGA breakout and routing examples for various fine pitch packages ( ). Each package example is built to comply with IPC7351 IPC7351 (www.ipc.org) specifications and nomenclature conventions. Some examples include different layout options depending on design and cost goals. For example, the 256-ball chip array BGA (BN256 BN256) examples demonstrate a design with fully-utilized I/Os, fine trace width and pitch, on a 6-layer PCB stack-up and a less expensive design with relaxed design rules, and fewer I/O pads routed, on a 4-layer PCB stack up. Table 19-3. Package Layout Example Summary Package Example # Pitch (mm) Signal/ Power Layers Trace/ WidthSpace (mm) Ball Pad (mm) Ball Mask (mm) Via Pad (mm) Via Drill (mm) MN64 1 0.5 6 .100/.100 .23 .33 .30 .125 UMN64 UMN64 1 0.4 6 .100/.100 .18 .28 .25 .10 1 0.5 4 .085/.085 .23 .38 .45 .20 2 0.5 4 .100/.100 .23 .38 .45 .20 1 0.5 4 .085/.085 .23 .38 .40 .15 2 0.5 4 .100/.100 .23 .38 .40 .15 1 0.5 6 .100/.100 .23 .33 .30 .125 2 0.5 4 .100/.100 .23 .38 .30 .125 1 0.8 6 .100/.100 .35 .50 .40 .125 2 0.8 4 .100/.100 .35 .50 .40 .15 MN100 MN100 MN132 MN132 MN144 MN144 BN256 BN256 For mechanical dimension details on packages, see the Lattice Package Diagrams document. In order to show how some of the routing challenges are solved, examples are provided for fine-pitch BGA packages from the MachXOTM and the ispMACH® 4000ZE 4000ZE families. Principles for these apply to other Lattice BGA packaged products. 19-3 PCB Layout Recommendations for BGA Packages Lattice Semiconductor 64-ball csBGA BGA Breakout and Routing Example This example places an ispMACH 4000ZE 4000ZE CPLD in a 5x5 mm, 0.5 mm pitch, 64-ball csBGA package (LC4064ZEMN64 LC4064ZEMN64) in an 6-layer stack up with maximum I/O utilization. Figure 19-2. CAM Artwork Screen Shots 64-Ball csBGA Layer 1 Primary Layer 2 Signal Layer 3 GND Layer 4 Power Layer 5 Signal Layer 6 Secondary 19-4 PCB Layout Recommendations for BGA Packages Lattice Semiconductor 64-ball ucBGA BGA Breakout and Routing Example This example places an ispMACH 4000ZE 4000ZE CPLD in a 4x4 mm, 0.4 mm pitch, 64-ball ucBGA package (LC4064ZEUMN64 LC4064ZEUMN64) in an n-layer stack up with maximum I/O utilization. This example demonstrates a modified dogbone fanout technique to get access to all pins yet limiting number of layers and via schedules, while setting up layers to use reference planes for high-speed signal traces. Figure 19-3. CAM Artwork Screen Shots, 64-Ball ucBGA Layer 1 Primary Layer 2 GND Layer 3 Signal Layer 4 Signal Layer 5 Power Layer 6 Secondary 19-5 PCB Layout Recommendations for BGA Packages Lattice Semiconductor 100-ball csBGA BGA Breakout and Routing Examples These examples place a MachXO PLD in a 8x8 mm, 0.5 mm pitch, 100-ball csBGA package (LXMXO640M100/MN100 LXMXO640M100/MN100) into two fabrication scenarios. One for a 6-layer stack up with maximum I/O utilization and a 4-layer with about 15% fewer I/Os. The 4-layer (Example #2) design makes maximum use of via and trace geometry to reduce layer count and ease fabrication while still maintaining high I/O usage. Figure 19-4. CAM Artwork Screen Shots, Example #1, 100-ball csBGA Layer 1 Primary Layer 2 GND Layer 3 Power Layer 4 Secondary 19-6 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Figure 19-5. CAM Artwork Screen Shots, Example #2, 100-ball csBGA Layer 1 Primary Layer 2 GND Layer 3 Power Layer 4 Secondary 19-7 PCB Layout Recommendations for BGA Packages Lattice Semiconductor 132-ball csBGA BGA Breakout Examples These examples place a MachXO PLD in a 8x8 mm, 0.5 mm pitch, 132-ball csBGA package (LCMXO640M132/MN132 LCMXO640M132/MN132) into two fabrication scenarios. One for a 6-layer stack up with maximum I/O utilization and a 4-layer with about 15% fewer I/Os. Figure 19-6. CAM Artwork Screen Shots, Example #1, 132-ball csBGA Layer 1 Primary Layer 2 GND Layer 3 Power Layer 4 Secondary 19-8 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Figure 19-7. CAM Artwork Screen Shots, Example #2, 132-ball csBGA Layer 1 Primary Layer 2 GND Layer 3 Power Layer 4 Secondary 19-9 PCB Layout Recommendations for BGA Packages Lattice Semiconductor 144-ball csBGA BGA Breakout Examples These examples place an ispMACH 4000ZE 4000ZE in a 7x7 mm, 0.5 mm pitch, 144-ball csBGA package (LC4256ZEMN144 LC4256ZEMN144) into two fabrication scenarios. One for a 6-layer stack up with maximum I/O utilization and a 4-layer with about 5% fewer I/Os. The 6-layer (Example #1) design avoids uses of micro vias and takes advantage of removed pads on inner layers to route all pins out to 6 layers with good layer structure for high-speed signal integrity. Figure 19-8. CAM Artwork Screen Shots, Example #1, 144-ball csBGA Layer 1 Primary Layer 2 GND Layer 3 Signal Layer 4 Signal Layer 5 Power Layer 6 Secondary 19-10 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Figure 19-9. CAM Artwork Screen Shots, Example #2, 144-ball csBGA Layer 1 Primary Layer 2 GND Layer 3 Power Layer 4 Secondary 19-11 PCB Layout Recommendations for BGA Packages Lattice Semiconductor 256-ball caBGA BGA Breakout Examples This BGA breakout and routing example places a MachXO PLD in a 14x14 mm, 0.8 mm pitch, 256-ball caBGA package (LCMXO2280-B256/BN256 LCMXO2280-B256/BN256) into two fabrication scenarios. One for a 6-layer stack up with maximum I/O utilization and a 4-layer with about 10% fewer I/Os. The 6-layer design (Example #1), demonstrates the best use of mechanically drill blind vias to place caps near power pins to minimize layers. Figure 19-10. CAM Artwork Screen Shots, Example #1, 256-Ball caBGA Layer 1 Primary Layer 2 Signal Layer 3 GND Layer 4 Power Layer 5 Signal Layer 6 Secondary 19-12 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Figure 19-11. CAM Artwork Screen Shots, Example #2, 256-ball caBGA Layer 1 Primary Layer 2 GND Layer 3 Power Layer 4 Secondary PCB Fabrication Cost and Design Rule Considerations PCB fabrication cost is a key consideration for many electronics products. By reviewing the IC device package ball density and pitch, I/O signal requirements of your application, and the manufacturing constraints of your PCB fabrication facility you can better weigh the trade-offs between design decisions. Choosing the best package for your application involves answering a few questions: · What is the driving factor in the application? The smallest possible form factor or a low PCB cost? · How many I/O signals does the application require? · What PCB layer stack up will provide the best I/O density within budget? · What layout design rules does the printed-circuit board (PCB) vendor support? · How many PCB layers does the budget allow? As the ball pitch becomes smaller with each new BGA generation, new PCB fabrication techniques and signal via type have been developed to handle the complexities. Micro vias, laser vias, filled, buried and blind vias, even buried and plated over vias. Complex boards use a combination of most of these. 19-13 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Stack-up types, ordered by cost, high-to-low include: · High-Density Interconnect (HDI) build up with micro vias · Laminated with blind and buried vias · Laminated with through vias Figure 19-12. Stack-up Example HDI is a "sandwich" with older-style larger geometry in the middle with fully drilled through holes and then a stack of fine geometry of blind, buried or mixed via, laminated both on the top and bottom of the middle stack-up. The laminated layers are thinner than traditional layers and allow finer drilling technology. Staggered micro vias allow vias within close tolerance or connected to a BGA pad to go down to the next layer or more to route away for escape routing or underneath the BGA device for further interconnect. HDI type interconnect is used on complex boards and takes extra steps in the processing flow due to special drilling, plating an laminations. It is a mix of older technology mixed with newer technology that results in a board that is highly routable. Figure 19-13. HDI Stack-up with Staggered Micro Vias Advantages and Disadvantages of BGA Packaging As pin counts increase and board space becomes more valuable, it is important to place as many circuits per square inch as possible. BGA offer the best I/O density for a given PCB area. Lattice offers a range of packages from a 4x4 mm 64-ball csBGA to a 33x33 mm 1704-ball fcBGA. One of the greatest advantages of BGA packaging is that it can be supported with existing placement and assembly equipment. BGAs also offer significantly more misalignment tolerance and less susceptibility to co-planarity issues. Even if the solder paste is misaligned or the device is slightly offset, the BGA will self-center during the 19-14 PCB Layout Recommendations for BGA Packages Lattice Semiconductor reflow process. This is due to the surface tension of the solder and flux in its molten state pulling each ball into the center of the pad. Figure 19-14. Misalignment of BGA Balls vs. QPF Leads Controlling the oven re-flow profile is one of the most important assembly parameters for consistent and reliable BGA placement. Profiles are typically tested on a pre-run. One or two panels are run to dial in the process, then visual and X-ray inspection equipment are used for verification. BGA packages present numerous benefits previously unobtainable in surface mount packaging technology. BGAs provide higher pin counts in a much smaller area than was previous possible. No longer is the package design limited to connections along the periphery on the outside quadrants of the package edge like a PQFP or TQFP outline. Fully populated ball grid arrays with pitches as small as 0.4 mm are available. Some BGA devices are arranged with de-populated interconnect near or around the center. These are dependent on the die size and number of pins. The area void of interconnect in the middle of the array has some advantages, it can be used for escape routing vias or tying directly to the ground or power planes. Although the packages can be quite complex and densely populated, all of these packages receive strict quality and reliability testing and are widely accepted today by designers and PCB fabrication/assembly houses. All of this is due to advances in equipment and technology that have allowed a smooth transition into the assembly flow. BGA Package Test and Assembly How can a pad/ball/pin be tested that can't be seen? All connections are hidden under the substrate at the ball interconnect, making it impossible to directly probe or test. To address this limitation, Lattice programmable devices provide JTAG, BSCAN, and boundary scan cells that allow electronic test and continuity of each pin with a boundary scan tester. This can be embedded into the system itself or driven externally from a high-speed test head. The boundary scan can test the pins or board for simple continuity tests or full functional test by shifting in test patterns through the JTAG port. For debug or prototype boards it may be necessary to place test points, open vias, or pads to have access to a given set of pins in order to drive, over-drive or observe a given set of signals. These can be very small, as many 19-15 PCB Layout Recommendations for BGA Packages Lattice Semiconductor pogo pin type probes are extremely small and can handle GHz range DC frequency. Zero ohm resistors are also commonly used in first-run boards as a way to gain access to a pad or pin. After assembly, BGA solder point quality and integrity is visually inspected with X-ray technology as part of the fabrication process. A special X-ray machine can look through the plastic package, substrate and silicon to directly view the BGA solder balls, vias, traces and pads. Figure 19-15. Example of How Defects May Appear in an X-Ray Image The X-ray image in Figure 19-16 shows proper alignment; no voids or defects are noted. Balls, vias and traces are visible. Figure 19-16. X-Ray Inspection Plot of ispMACH 4000ZE 4000ZE 144-ball csBGA (Photo Courtesy of CEM, Ltd., www.cemltd.com) 19-16 PCB Layout Recommendations for BGA Packages Lattice Semiconductor PCB cross-sectioning is another method used to verify BGA and PCB quality and reliability. After a new process has been developed or changed or when qualifying a new vendor, it is a good practice to get physical information from the vendor on their BGA reflow. When trace/space and drill or laser tolerances are nearing their limits, board yield can be as be as low as 50% for the bare board fab. Cross-sections give you a good idea if the process is correct but do not guarantee each batch or each board design will behave the same way due to layout dimensions, thermal issues, flux/paste and alignment, etc. Figure 19-17 shows a BGA cross-section that uses a non-soldermask over bare copper-defined pad. (NSMD) pad. Figure 19-17. BGA Cross-Section Figure 19-18 shows "offset" micro via stack routing between layers. Figure 19-18. Cross-Section of Micro Vias High-resolution video cameras are used for edge inspection to verify ball seating, distortion, solder wetting, flow, contaminates, etc. Figure 19-19 is a video view of a side/edge shot looking at BGA balls soldered down to the ispMACH 4000ZE 4000ZE Pico Evaluation Board (www.latticesemi.com/4000ze-pico-kit), an FR4 4-layer PCB. 19-17 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Figure 19-19. Edge View Camera Inspection In the photos samples above, trained technicians and computer camera recognition equipment are used for inspection of the X-ray results, looking for voids, shorts, missing connections, contaminants, alignment or other gross failure mechanisms. For example, in Figure 19-19, the BGA ball connections appear to be squashed downward, with mild distortion, insuring that proper oven profile temperatures were achieved. These technologies help in the successful placement and long term use of BGAs in the industry's latest products. Further advancements have been made in material content to conform to environmental issues, toxic materials and recycling. Another issue that relates to board design is the physical silkscreen logos and information related to recycling, lead content and other hazardous waste components, strict adherence must be paid to these requirements. Although a documentation and silkscreen issue, it can become a challenge to fit this information on the board in some cases due to component population and must be accounted for in overall board real estate. PCB Design Support Lattice provides a collection of PCB design resources at www.latticesemi.com/support/pcbdesignsupport.cfm including schematic libraries, PCB CAM viewers, technical notes, and BGA breakout and routing examples. Technical Support Assistance Hotline: 1-800-LATTICE 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com 19-18 PCB Layout Recommendations for BGA Packages Lattice Semiconductor Revision History Date Version January 2005 01.0 Change Summary Initial release. November 2005 01.1 Figures updated. June 2006 01.2 Removed NSMD content. September 2006 01.3 Added note to BGA Board Layout Recommendations table. Reformatted BGA Package Types section in tabular format. March 2008 01.4 Revised recommended Solder Mask Defined and Non Solder Mask Defined PCB solder pad dimensions to match industry standards. May 2009 01.5 Updated BGA Board Layout Recommendations table and BGA Package Types table for 0.4 mm pitch ucBGA package. February 2010 01.6 Edits to most sections and additional links and graphics added for each example. March 2010 01.7 Replaced Lattice BGA Naming Conventions table with Lattice Semiconductor BGA Package Types table and SMD/NSMD Pad Recommendations table. August 2010 01.8 Lattice Semiconductor SMD/NSMD Pad Recommendations table: Specified nominal Solder Mask Opening for each Lattice BGA package, clarified recommended Solder Mask Opening and Solder Pad Diameters and added cautionary note. September 2010 01.9 Lattice Semiconductor SMD/NSMD Pad Recommendations table Added 64 csBGA to 0.5mm pitch column. 19-19