TN-41-05 - Datasheet Archive

 

HIDING THE LSMR COMMAND IN THE SGRAM TECHNICAL NOTE HIDING THE LOAD SPECIAL MODE REGISTER COMMAND IN THE SGRAM This article was

 

TN-41-05 TN-41-05 HIDING THE LSMR COMMAND IN THE SGRAM TECHNICAL NOTE HIDING THE LOAD SPECIAL MODE REGISTER COMMAND IN THE SGRAM This article was originally published in 1997. Register is loaded with color data for use in BLOCK WRITEs (whether masked or unmasked), or the Mask Register is loaded with mask data for use in MASKED WRITEs or MASKED BLOCK WRITEs. In either case, the data is provided on the DQ pins coincident with the LSMR command being applied on the command inputs (CS#, RAS#, CAS#, WE# and DSF). The logic values applied to the address inputs at that time are used to select either the Color Register or the Mask Register as the destination for the data. INTRODUCTION The Synchronous Graphics RAM (SGRAM) includes two features that facilitate the design of high-performance graphics subsystems. These features are known as Block Write and Masked Write (or Write-Per-Bit). Both of these features require preloading of a register internal to the SGRAM. This preloading is accomplished using the LOAD SPECIAL MODE REGISTER (LSMR) command. In most cases the use of this command is so infrequent that the effect on bus bandwidth is negligible. However, in cases where the use of the LSMR command will be more frequent, the graphics controller designer will want to issue the LSMR commands at times when the bus is otherwise idle (thereby "hiding" the command). This technical note provides several examples of hiding the LSMR command; other scenarios are also possible. NOTE: INDEPENDENT OPERATION Loading data to either of these registers is independent of reading or writing data from or to the DRAM array (except for using the same pins), meaning that as long as bus contention is avoided, these two types of operations (special register loads and memory accesses) will not interfere with each other. The DQM inputs act as masks or enables for memory accesses only and have no effect on data being loaded into the Color or Mask Registers. Because of this independence, there are several possibilities for interleaving these operations on the memory interface. Some examples follow. Not all of the cases shown in the examples are tested in production test programs, and some may not be attractive for the system designers to use; however, they were chosen to best illustrate how the device was designed to operate. LSMR COMMAND ROW ACTIVATION TIME When an LSMR command is executed, one of two registers internal to the SGRAM is loaded. Either the Color Figure 1 illustrates the application of an LSMR command during the row activation (or tRCD) time in a row access. T0 T1 T2 T3 T4 T5 , , , , , , , , CLK COMMAND ACTIVE LSMR ADDRESS BANK, ROW OPCODE NOP WRITE NOP NOP BANK, COL n DQM DQ SMR DIN DIN n DIN n+1 DIN n+2 ACTIVE = Either ACTIVE with WPB or ACTIVE without WPB WRITE command (shown) can be READ, or BLOCK WRITE, etc. Burst Length (shown) = 4 or greater Sequential burst shown LSMR = Load Special Mode Register OPCODE: A0-A4,A7-A8,BA=0; A5 = 0, A6 = 1 for Color Data A5 = 1, A6 = 0 for Mask Data SMR DIN = Input data for either the Color Register or the Mask Register, depending on OPCODE DON'T CARE Figure 1 APPLYING AN LSMR COMMAND DURING ROW ACTIVATION TIME TN-41-05 TN-41-05 GT05.p65 ­ Rev. 2/99 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. Micron is a registered trademark of Micron Technology, Inc. TN-41-05 TN-41-05 HIDING THE LSMR COMMAND IN THE SGRAM This assumes that there are no accesses in progress to the second bank. Cases where memory accesses are in progress are covered below. READ BURST Figure 3 shows the application of an LSMR command during a READ burst at a point where the read data is not needed. Here the DQM inputs are used to turn off the output drivers so that mask or color data can be applied to the DQ pins (recall that the READ DQM latency is two). READ LATENCY Figure 2 shows the application of an LSMR command during the CAS# latency period following a READ command. Here a CAS# latency of three is shown, meaning that the output drivers do not turn on until after T2. T0 T1 T2 T3 T4 T5 T6 T7 , , , , , , , , , , , CLK COMMAND READ LSMR ADDRESS BANK, COL n OPCODE NOP NOP NOP NOP NOP NOP DQM SMR DIN DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT n+4 Burst Length (shown) = 8 (or full page) Sequential burst shown CAS# Latency = 3 LSMR = Load Special Mode Register OPCODE: A0-A4,A7-A8,BA=0; A5 = 0, A6 = 1 for Color Data A5 = 1, A6 = 0 for Mask Data SMR DIN = Input data for either the Color Register or the Mask Register, depending on OPCODE DON'T CARE Figure 2 APPLYING AN LSMR COMMAND DURING THE READ LATENCY PERIOD T0 T1 T2 T3 T4 T5 T6 T7 , , , , , , , CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP LSMR NOP NOP OPCODE DQM DQ DOUT n SMR DIN DOUT n+4 Burst Length (shown) = 8 (or full page) Sequential burst shown CAS Latency (shown) = 3 LSMR = Load Special Mode Register OPCODE: A0-A4,A7-A8,BA=0; A5 = 0, A6 = 1 for Color Data A5 = 1, A6 = 0 for Mask Data SMR DIN = Input data for either the Color Register or the Mask Register, depending on OPCODE DON'T CARE Figure 3 APPLYING AN LSMR COMMAND DURING A READ BURST TN-41-05 TN-41-05 GT05.p65 ­ Rev. 2/99 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. TN-41-05 TN-41-05 HIDING THE LSMR COMMAND IN THE SGRAM WRITE BURST SUMMARY Figure 4 shows the application of an LSMR command during a WRITE burst at a point where no data needs to be written to the DRAM array. Here the DQM inputs are used to prevent the color or mask data from being written to the DRAM array (recall that the WRITE DQM latency is one). Loading of the Color or Mask Register in the SGRAM for use in BLOCK WRITEs and/or MASKED WRITEs is independent of accesses to the DRAM array, except for using the same pins. This means that as long as bus contention is avoided, there is a high level of flexibility in interleaving these operations. The examples provided in this technical note illustrate that flexibility. , , , , , , , , , , , T0 T1 T2 T3 T4 T5 T6 COMMAND WRITE NOP LSMR NOP NOP NOP NOP ADDRESS BANK, COL n CLK DQM DQ DIN n OPCODE DIN n+1 SMR DIN DIN n+3 Burst Length (shown) = 4 Sequential burst shown LSMR = Load Special Mode Register OPCODE: A0-A4,A7-A8,BA=0; A5 = 0, A6 = 1 for Color Data A5 = 1, A6 = 0 for Mask Data SMR DIN = Input data for either the Color Register or the Mask Register, depending on OPCODE DON'T CARE Figure 4 APPLYING AN LSMR COMMAND DURING A WRITE BURST 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. TN-41-05 TN-41-05 GT05.p65 ­ Rev. 2/99 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.