TMS9914A NAT9914APD NAT9914APL PD7210 NAT9914 340497B-01 NAT7210 AD15-0 A15-0 - Datasheet Archive
Drop-In Replacement for TI TMS9914A NAT9914APD NAT9914APL Features · Pin compatible with TI TMS9914A · Software
IEEE 488.2 Controller Chip Drop-In Replacement for TI TMS9914A TMS9914A NAT9914APD NAT9914APD NAT9914APL NAT9914APL Features · Pin compatible with TI TMS9914A TMS9914A · Software compatible with NEC µPD7210 PD7210 or TI TMS9914A TMS9914A controller chips · Low power consumption · Meets all IEEE 488.2 requirements Bus line monitoring Preferred implementation of requesting service Will not send messages when there are no Listeners · Performs all IEEE 488.1 interface functions · Programmable data transfer rate (T1 delays of 350 ns, 500 ns, 1.1 µs, and 2 µs) · Automatic EOS and/or NL message detection · Direct memory access (DMA) · Automatically processes IEEE 488 commands and reads undefined commands · TTL-compatible CMOS device · Programmable clock rate up to 20 MHz · Reduces driver overhead Does not lose a data byte if ATN is asserted while transmitting data NAT9914 NAT9914 Description The NAT9914 NAT9914 IEEE 488.2 controller chip can perform all the interface functions defined by that the IEEE Standard 488.1-1987, and also meets the additional requirements and recommendations of the IEEE Standard 488.2-1987. Connected between the processor and the IEEE 488 bus, the NAT9914 NAT9914 provides high-level management of the IEEE 488 bus, significantly increases the throughput of driver software, and simplifies both the hardware and software design. The NAT9914 NAT9914 performs complete IEEE 488 Talker, Listener, and Controller functions. In addition to its numerous improvements, the NAT9914 NAT9914 is also completely pin compatible with the TI TMS 9914A and software compatible with the NEC µPD7210 PD7210 and TI TMS9914A TMS9914A controller chips. IEEE 488.2 Overview The IEEE 488.2 standard removes the ambiguities of IEEE 488.1 by standardizing the way instruments and controllers operate. It defines data formats, status reporting, error handling, and common configuration commands to which all IEEE 488.2 instruments must respond in a precise manner. It also defines a set of controller requirements. The benefits of IEEE 488.2 for the test system developer are reduced development time and cost, because systems are more compatible and reliable. The NAT9914 NAT9914 brings the full power of IEEE 488.2 to the design engineer along with numerous other design and performance benefits, while retaining the 40-pin and 44-pin hardware configurations of the TI TMS 9914A. General The NAT9914 NAT9914 manages the IEEE 488 bus. You program the IEEE 488 bus by writing control words into the appropriate registers. CPU-readable status registers supply operational feedback. The NAT9914 NAT9914 mode determines the function of these registers. On power up or reset, the NAT9914 NAT9914 registers resemble the TMS9914A TMS9914A register set with additional registers that supply extra functionality and IEEE 488.2 compatibility. In this mode, the NAT9914 NAT9914 is completely pin compatible with the TI TMS9914A TMS9914A. If you enable the 7210 mode, the registers resemble the NEC µPD7210 PD7210 register set with additional registers that supply extra functionality and IEEE 488.2 compatibility. This mode is not pin compatible with the NECµPD7210 PD7210. Figure 2 shows the key components of the NAT9914 NAT9914. Note: For more details about the NAT9914 NAT9914 see the NAT9914 NAT9914 Reference Manual, Part Number 320775-01. 340497B-01 340497B-01 071596 NAT9914APD NAT9914APD NAT9914APL NAT9914APL ACCRQ ACCGR CE WE DBIN RS0 RS1 RS2 INT D7 D6 D5 D4 D3 D2 D1 D0 CLK RESET VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Pin Identification VDD TR DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 CONT SRQ ATN EOI DAV NRFD NDAC IFC REN TE Mnemonic DIP 10, 11, 12, D(7-0) 13, 14, 15, 16, 17 4 3 CE* 6 5 DBIN 5 4 WE* 3 2 ACCGR* 2 1 ACCRQ* 20 21 18 19 CLK RESET* 10 9 INT* 9, 8, 7 8, 7, 6 RS(2-0) 25 23 IFC* 24 22 REN* 31 28 ATN* 32 29 SRQ* 34, 35, 36, 37, 38, 39, 41, 42 29 31, 32, 33, DIO(8-1)* 34, 35, 36 37, 38 26 DAV* I/O 27 25 NRFD* I/O 26 24 NDAC* I/O 30 27 EOI* I/O 23 NAT9914APD NAT9914APD Pin No. PLCC 11, 12, 13, 14, 15, 16, 17, 19 21 TE O DBIN WE CE ACCGR ACCRQ NC VDD TR DIO1 DIO2 NC Figure 1. NAT9914APD NAT9914APD Pin Configuration NAT9914APL NAT9914APL DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 CONT SRQ ATN EOI DAV NC D0 CLK RESET VSS TE REN IFC NDAC NRFD NC RS0 RS1 RS2 INT D7 D6 D5 D4 D3 D2 D1 6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 Figure 2. NAT9914APL NAT9914APL Pin Configuration 2 Type Description I/O Bidirectional 3-state data bus transfers commands, data, and status between the NAT9914 NAT9914 and the CPU. D0 is the most significant bit. I Chip Enable gives access to the register selected by a read or write operation, and the register selects RS(2-0) I With the Data Bus Input, you can place the contents of the register selected by RS(2-0) and CE* onto the data bus D(7-0). The polarity of DBIN is reversed for DMA operation. I The Write input latches the contents of the data bus D(7-0) into the register selected by RS(2-0) I The Access Grant signal selects the DIR or CDOR for the current read or write cycle O The Access Request output asserts to request a DMA Acknowledge cycle I The CLK input can be up to 20 MHz I Asserting the RESET* input places the NAT9914 NAT9914 in an initial, idle state 0 The Interrupt output asserts when one of the (0C) unmasked interrupt conditions is true. The NAT9914 NAT9914 does not drive INT* high. The INT* pin must be pulled up by an external resistor. I The Register Selects determine which register to access during a read or write operation I/O, Bidirectional control line initializes the IEEE 488 (OC) interface functions I/O Bidirectional control line selects either remote or (OC) local control of devices I/O Bidirectional control line indicates whether data on the DIO lines is an interface or devicedependent message I/O I/O Bidirectional control line requests service from the controller 8-bit bidirectional IEEE 488 data bus Handshake line indicates that the data on the DIO(8-1)* lines is valid Handshake line indicates that the device is ready for data Handshake line indicates the completion of a message reception Bidirectional control line indicates the last byte of a data message or executes a parallel poll Talk Enable controls the direction of the IEEE 488 data transceiver NATIONAL INSTRUMENTS NAT9914APD NAT9914APD NAT9914APL NAT9914APL Pin No. PLCC 43 Mnemonic Type Description DIP 39 TR O 33 30 CONT* O 44 22 1, 18, 28, 40 40 20 VDD VSS NC Trigger asserts when one of the trigger conditions is satisfied Controller asserts when the NAT9914 NAT9914 is Controller-In-Charge Power pin +5 V (±5%) Ground pin 0 V No connect OC= Open collector. The pin contains an internal pull-up resistor of 25 k to 100 k. * Active low. In controller applications where the CLK signal frequency is > 8 MHz, IFC* should be pulled up with a 4.7 k resistor. D(7-0) Data-In CE* RS(2-0) DBIN WE* DIO(8-1)* Message Decoder Command Pass Through Read/ Write Control Command/Data Out ACCRQ* ACCGR* Interface Functions Address Status SH1 Address Compare Address Mode AH1 CONT* TE TR T5/TE5 L3/LE3 Interrupt Mask 0, 1, 2 Compare End-Of-String SR1 RL1 PP1/PP2 Interrupt Status 0, 1, 2 INT* CLK DC1 Internal Count Internal Count 2 DT1 C1-C5 Serial Poll RSV Gen Parallel Poll EOI Gen Aux A, B, E, F, G, I SASR RESET* STB Out SYNC Auxiliary Command Decoder Bus Status and Control GPIB Control Version Figure 3. NAT9914 NAT9914 Block Diagram NATIONAL INSTRUMENTS 3 NAT9914APD NAT9914APD NAT9914APL NAT9914APL 9914 Mode Registers Data Registers Interrupt Mask Register 0 (IMR0) In 9914 mode, the NAT9914 NAT9914 registers consist of all the TI TMS9914A TMS9914A registers and two types of additional registers newly defined registers and paged-in registers. The NAT9914 NAT9914 maps the newly defined registers into the unused portion of the 9914 address space. Each paged-in register appears at offset 2 immediately after you issue an auxiliary page-in command, and it remains there until you page another register into the same space or you issue a reset. The table below lists all the registers in the 9914 register set. Data In Register (DIR) DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01 DMAO DMAI BI IE Command/Data Out Register (CDOR) Interrupt Mask Register 1 (IMR1) DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01 The data registers transfer data and commands between the IEEE 488 bus and the CPU. The Data In Register (DIR) holds data sent from the GPIB to the CPU, and the CDOR holds information to transfer onto the IEEE 488 bus. 9914 Register Set Register Page In RS(2-0) WE* DBIN CE* ACCGR* Interrupt Status 0 U 0 0 0 1 1 0 1 Interrupt Mask 0 U 0 0 0 0 0 0 1 Interrupt Status 1 U 0 0 1 1 1 0 1 Interrupt Mask 1 U 0 0 1 0 0 0 1 Address Status U 0 1 0 1 1 0 1 Interrupt Mask 2 P 0 1 0 0 0 0 1 End-of-String P 0 1 0 0 0 0 1 Bus Control P 0 1 0 0 0 0 1 Accessory P 0 1 0 0 0 0 1 Bus Status U 0 1 1 1 1 0 1 Auxiliary Command U 0 1 1 0 0 0 1 Interrupt Status 2 P 1 0 0 1 1 0 1 Address U 1 0 0 0 0 0 1 Serial Poll Status P 1 0 1 1 1 0 1 Serial Poll Mode U 1 0 1 0 0 0 1 Command Pass Thru U 1 1 0 1 1 0 1 Parallel Poll U 1 1 0 0 0 0 1 Data-In U 1 1 1 1 1 0 1 Data-In U XXX X 0 X 0 Command/Data Out U 1 1 1 0 0 0 1 Command/Data Out U XXX 0 1 X 0 The '' symbol denotes features (such as registers and auxiliary commands) that are not available in the TMS9914A TMS9914A. Notes for the PAGE-IN column U = Page-in auxiliary commands do not affect the register offset. P = The register offset is valid only after a page-in auxiliary command. Interrupt Registers Interrupt Status Register 0 (ISR0) INT0 INT1 BI BO END SPAS RLC MAC Interrupt Status Register 1 (ISR1) GET ERR UNC APT DCAS MA SRQ IFC GET IE BO END SPAS RLC MAC IE IE IE IE IE ERR UNC APT DCAS MA IE IE IE IE IE SRQ IE IFC IE Interrupt Mask Register 2 (IMR2) GLINT STBO NLEN 0 IE LLOC ATNI IE IE 0 CIC IE The interrupt registers consist of interrupt status bits, interrupt mask bits, and some noninterrupt-related bits. Several conditions can cause an interrupt. The interrupt status sets if its condition is true and an interrupt is generated if you set the corresponding mask bit. Most interrupt status bits are cleared when read. The following tables list the individual bits in the interrupt registers, along with descriptions. Interrupt Status and/or Mask Register Bits Bits INT0 INT1 BI BO END SPAS RLC MAC GET ERR UNC APT DCAS MA SRQ IFC STBO LLOC ATNI CIC GLINT Description OR of all unmasked ISR0 bits OR of all unmasked ISR1 bits Byte In Byte Out END (EOI or EOS message received) SPAS (Serial Poll Active State) Remote/Local Change My Address Change Group Execute Trigger Data Transmission Error Unrecognized Command Address Pass Through Device Clear Active State My Address Service Request (SRQ) asserted Interface Clear (IFC) asserted Status Byte Out Request Lockout State Change Attention (ATN) asserted Controller-In-Charge Global Interrupt Enable Interrupt Status Register 2 (ISR2) nba STBO NL 4 EOS LLOC ATNI X CIC NATIONAL INSTRUMENTS NAT9914APD NAT9914APD NAT9914APL NAT9914APL Noninterrupt-Related, Readable Bits Bits nba NL EOS Noninterrupt-Related, Writable Bits Bits NLEN DMAO DMAI Description New Line character enabled for EOS Enable/Disable DMA Out Enable/Disable DMA In Poll Registers Address Registers Other Registers The NAT9914 NAT9914 contains several registers that control the GPIB address mode, store the GPIB address, and monitor the GPIB address status. Description Command or Data Byte Available New Line Received End-Of-String Command Pass Through Register (CPTR) Address Status Register (ADSR) REM LLO ATN LPAS TPAS LA TA ULPA The Address Status Register monitors the NAT9914 NAT9914 address state. The following table lists the ADSR bits, along with a description of each bit. CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0 With the Command Pass Through Register (CPTR), the CPU can read the GPIB DIO(8-1) lines in the cases of undefined commands, secondary addresses, or parallel poll responses. End-Of-String Register (EOSR) EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0 Serial Poll Status Register (SPSR) S8 PEND S6 S5 S4 S3 S2 S1 Serial Poll Mode Register (SPMR) S8 rsv/RQS S6 S5 S4 S3 S2 S1 The Serial Poll Mode Register holds the STB (status byte: S8, S6 through S1) that transmits over the GPIB when you serial poll the NAT9914 NAT9914, and also holds the local rsv message (request service). The STB automatically transmits when you serial poll the NAT9914 NAT9914 if STBO IE=0. If STBO IE=1, the STB does not transmit during serial polls until you write to the SMPR. You can read the SPMR through the SPSR. The PEND bit sets when rsv sets and clears when the NAT9914 NAT9914 enters the Negative Poll Response State. Parallel Poll Register (PPR) PP8 PP7 PP6 PP5 PP4 PP3 PP2 PP1 The PPR contains the value that the NAT9914 NAT9914 outputs on the GPIB when the Controller-In-Charge conducts a parallel poll. To participate in a parallel poll, the bit corresponding to the desired parallel poll response is set to 1. The parallel poll register is double buffered. Therefore, if it is written during a parallel poll, the register updates with the new value at the end of the parallel poll. NATIONAL INSTRUMENTS Address Status Bits Bit REM LLO ATN LPAS TPAS LA TA ULPA Description The NAT9914 NAT9914 is in a Remote state The NAT9914 NAT9914 is in a Lockout state GPIB ATN signal Listener Primary Addressed State Talker Primary Addressed State Listener Addressed Talker Addressed Stores the LSB of the last address recognized by the NAT9914 NAT9914 DAT A5 A4 A3 A2 A1 The NAT9914 NAT9914 can automatically detect the address in ADR as its MTA or MLA. The following table describes the function of each bit. Address Register Bits Bit EDPA DAL DAT A5-0 Auxiliary Command Register C/S 0 0 F4 F3 F2 F1 F0 A write to this register generates one of the following operations according to the C/S and F (4-0) values. Auxiliary Commands Address Register (ADR) EDPA DAL The EOS Register holds either the seven or eight-bit EOS message byte that the GPIB system uses to detect the end of a data block. Description Enables Dual Addressing mode, in which the least significant address bit is ignored, giving the NAT9914 NAT9914 two consecutive GPIB addresses Prohibits the Listen address from being detected Prohibits the Talk address from being detected GPIB primary address Hex values Command Operation 00/80 swrst Clear/Set software reset 01/81 dacr Invalid/valid DAC release Holdoff 02 rhdf Release RFD Holdoff 03/83 hdfa Clear/Set Holdoff on All Data 04/84 hdfe Clear/Set Holdoff on END only 05 nbaf New Byte Available False 06/86 fget Clear/Set Force Group Execute Trigger 07/87 rtl Clear/Set Return to Local (continued) 5 NAT9914APD NAT9914APD NAT9914APL NAT9914APL Hex values Command Operation 08 feoi Send EOI with next byte 09/89 lon Clear/Set Listen Only 0A/8A ton Clear/Set Talk Only OB gts Go To Standby OC tca Take Control Asynchronously OD tcs Take Control Synchronously OE/8E rpp Clear/Set Request Parallel Poll 0F/8F sic Clear/Set Send Interface Clear 10/90 sre Clear/Set Send Remote Enable 11 rqc Request Control 12 rlc Release Control 13/93 dai Clear/Set Disable All Interrupts 14 pts Pass Through Next Secondary 15/95 stdl Clear/Set Short T1 settling time 16/96 shdw Clear/Set Shadow Handshake 17/97 vstdl Clear/Set Very Short T1 delay 18/98 rsv2 Clear/Set Request Service Bit 2 99 sw7210 Switch to µPD7210 PD7210 1A 9A 1C 9C 1D/9D reqf reqt ch_rst clrpi ist 1E piimr2 9E pieosr 1F pibcr 9F piaccr 6 Mode Send Reqf Send Reqt Chip Reset Clear Page-In Registers Clear/Set Parallel Poll Flag Page-In Interrupt Mask 2 Register Page-In End-Of-String Register Page-In Board Control Register Page-In Accessory Register Accessory Register (ACCR) Accessory Register A (ACCRA) ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 The ACCR is a multipurpose register. A write to this register generates one of the following operations according to the ACC values. Auxiliary Mode Operations ACC 7 6 5 4 3 2 1 0 0 0 1 0 x x x x 1 0 0 x x x 0 0 1 0 1 x x x x 1 1 0 0 x x 0 0 1 1 0 1 x x x x 1 1 0 0 x x x x x Operation Writes to the Internal Counter Register Writes to the Accessory Register A Writes to the Accessory Register B Writes to the Accessory Register E Writes to the Accessory Register F Writes to the Accessory Register I Internal Counter Register (ICR) 0 0 1 0 T3 T2 T1 1 0 0 BIN XEOS REOS 0 0 Accessory Register A controls the usage of the EOS message, as listed in the table below. EOS Message Bit Function REOS 0 Prohibit Permits (prohibits) setting 1 Permit END bit when receiving the EOS message XEOS 0 Prohibit Permits (prohibits) automatic 1 Permit transmission of END message simultaneously with EOS message transmission while in TACS BIN 0 7-bit Selects 7 or 8 bits as the 1 8-bit valid EOS message length Accessory Registers B (ACCRB) 1 0 1 ISS INV LWC SPEOI ATCT Accessory Register B controls special NAT9914 NAT9914 operating features, as listed in the table below. T0 Special Features The Internal Counter Register tells the internal circuitry in the NAT9914 NAT9914 the clock frequency supplied to the CLK input. For proper operation, set T(3-0) and MICR as follows: Clock Frequency MICR T(3-0) 1 0 0001 2 0 0010 3 0 0011 4 0 0100 5 0 0101 6 0 0110 7 0 0111 8 0 1000 10 1 0101 16 1 1000 20 1 1010 On a hardware reset, T (3-0) and MICR are set to 5 MHz. Note: MICR may be set by switching to the µPD7210 PD7210 mode and writing to the ICR2 Register. Bit Function ATCT 0 Prohibit Permits (prohibits) the 1 Permit NAT9914 NAT9914 to automatically take control of the GPIB when control is passed to it (TCT) SPEOI 0 Prohibit Permits (prohibits) END 1 Permit message transmission when in Serial Poll Active State (SPAS) LWC 0 Prohibit Permits (prohibits) the 1 Permit NAT9914 NAT9914 to accept and respond to the GPIB commands that it sources INV 0 low Specifies the INT* pin active 1 high level. The NAT9914 NAT9914 does not drive in INT* high. The INT* pin must be pulled up with an external resistor. ISS 1 SRQS Determines if the ist local message value is equal to 0 Parallel SRQS or the Parallel Poll Poll Flag Flag NATIONAL INSTRUMENTS NAT9914APD NAT9914APD NAT9914APL NAT9914APL Accessory Register E (ACCRE) 1 1 0 0 DHADT DHADC 0 0 GPIB Control/Status Registers (BCR/BSR) ATN DAV NDAC NRFD EOI SRQ IFC REN Accessory Register F (ACCRF) 1 1 0 1 DHATA DHALA DHUNTL DHALL AUXRE and AUXRF control DAC holdoff modes, as listed in the table below. The CPU can monitor the GPIB by reading the Bus Status Register. You can assert (drive low) GPIB signals by setting the corresponding bit in the GPIB Control Register to 1. Special Features Bit DHADC DHADT DHALL DHUNTL DHALA DHATA Function DAC Holdoff on DCL or SDC DAC Holdoff on GET DAC Holdoff on all commands DAC Holdoff on UNL and UNT DAC Holdoff on all Listener addresses DAC Holdoff on all Talker addresses Accessory Register I (ACCRI) 1 1 1 0 USTD PP1 0 DMAE AUXRI controls special NAT9914 NAT9914 operational features, as listed in the table below. Special Features Bit DMAE=0 DMAE=1 PP1 USTD Function ACCRQ* is asserted if either a Byte In (BI) or Byte Out (BO) condition occurs ACCRQ* is asserted if the BI and DMAI bits are set or the BO and the DMAO bits are set When set, the NAT9914 NAT9914 responds to remote GPIB parallel poll configure commands and automatically responds to parallel polls Enables 350 ns T1 delays 7210 Mode Registers The NAT9914 NAT9914 registers include all the NEC µPD7210 PD7210 registers plus two types of additional registers extra auxiliary registers and paged-in registers. You write the extra auxiliary registers the same as standard µPD7210 PD7210 auxiliary registers. Upon issuing an auxiliary page-in command, the paged-in registers appear at the same offsets as existing µPD7210 PD7210 registers. At the end of the next CPU access, the chip pages out the paged-in registers. The following table lists all the registers in the 7210 mode register set along with their associated addressing information. See the NAT7210 NAT7210 data sheet (National Instruments part number 340488-01) for more information about 7210 mode registers. 7210 Register Set Register Data-In Data-In Command/Data Out Command/Data Out Interrupt Status 1 Interrupt Mask 1 Interrupt Status 2 Interrupt Mask 2 Serial Poll Status Serial Poll Mode Version Internal Counter 2 Address Status Address Mode Command Pass Through Auxiliary Mode Source/Acceptor Status Address 0 Address Interrupt Status 0 Interrupt Mask 0 Address 1 End-Of-String Bus Status Bus Control PAGE-IN U X U X U U U U N N P P U U N U P N N P P N N P P 0 X 0 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 A(2-0) 0 0 X X 0 0 X X 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 WE* 1 X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 DBIN 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 CE* 0 X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACCGR* 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes for the PAGE-IN Column U = The page-in auxiliary command does not affect the register. N = The register offset is alway valid except for immediately after a page-in auxiliary command. P = The register is valid only immediately after a page-in auxiliary command. NATIONAL INSTRUMENTS 7 NAT9914APD NAT9914APD NAT9914APL NAT9914APL Preliminary DC Characteristics AC Characteristics TA 0 to 70° C; VCC = 5 V ±5% Limits Test Parameter Symbol Min Max Unit Condition Voltage input low VIL -0.5 +0.8 V Voltage input high VIH +2.0 VCC V Voltage output low VOL 0 0.4 V Voltage output high VOH +2.4 VCC V Input/output -10 +10 µA without leakage current internal pull-up Input/output -200 +200 µA with internal leakage current pull-up Supply current 45 mA Output current low All pins except ACCRQ IOL 2 mA 0.4 V @ IOL ACCRQ IOL 4 mA 0.4 V @ IOL Input current low IIL - 0.5 mA Supply voltage VDD 4.75 5.25 V TA 0 to 70° C; VCC = 5 V ±5% Parameter Address hold from CE, WE,and DBIN Address setup to CE , WE, and DBIN Data float from CE or DBIN Data delay from DBIN , ACCRQ unassertion Data delay from CE CE recovery width CE pulse width Data hold from WE Data setup to WE Symbol tAH tAS tDF tDR tDU tRD tRR tRW tWH tWS Min 0 0 Limits Max 20 75 20 80 80 80 0 60 Unit ns ns ns ns ns ns ns ns ns ns Test Condition ACCGR=0 ACCGR=1 Timing Waveforms tAS tAH RS2-0 Capacitance DBIN Test Unit Condition pF tDF tRD CE D7-0 pF tRW Figure 4. CPU Read pF Property Range Supply voltage, VDD -0.5 to +7.0 V Input voltage, VI -0.5 to VDD +0.5 V Operating temperature, TOPR 0 to +70° C Storage temperature, TSTG -40 to +125° C Comment: Exposing the device to stresses above those listed could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section. Exposure to absolute maximum rating conditions for extended periods may affect reliability. tDU ACCRQ ACCGR tDR DBIN tDF D7-0 Figure 5. DMA Read Notes: · tAS is the setup time to CE or WE whichever is later. · tAH is the hold time from WE or CE whichever is earlier. Absolute Maximum Ratings tRR RS2-RS0 tAH tAS CE WE tWS TA 0 to 70° C; VCC = 5 V ±5% Limits Parameter Symbol Min Max Input CIN 10 capacitance Output COUT 10 capacitance I/O capacitance CI/O 10 tWH D7-0 Figure 6. CPU Write 8 NATIONAL INSTRUMENTS NAT9914APD NAT9914APD NAT9914APL NAT9914APL ACCRQ DAV tDF tDU ACCGR tDD NDAC tDR DBIN tNR NRFD WE tDI tWH tWS INT/ACCRQ D7-0 DBIN Figure 7. DMA Write Figure 9. Acceptor Handshake Timing Source Handshake Parameter ATN to NRFD ATN to NDAC ATN to TE INT(DOIE Bit=1) ACCGR (DMAO Bit=1) 2000 2180 2 µs T1, 5MHz 1200 1380 1.1 µs T1, 5MHz 600 780 500 ns T1, 5MHz 400 580 350 ns T1, 5MHz Response to ATN tWD tWD tWD tWD Test Condition WE to DAV WE to DAV WE to DAV WE to DAV Limits (ns) Symbol Min Max tND 40 tNI 40 Parameter NDAC to DAV NDAC to INT or ACCRQ Symbol tAF Limits (ns) Min Max 35 tAN tAT Test Condition Acceptor handshake holdoff AIDS ANRS TACS TADS 35 30 ATN WE tAT TE D7-0 tAN tNI INT/ACCGR NDAC tAF NRFD DIO 8-1 tWD Figure 10. ATN Response Timing DAV tND NDAC Parallel Poll Parameter EOI to DIO valid EOI to TE EOI to TE DAV to NRFD DBIN to NRFD Note: T=one clock period Limits (ns) Test Symbol Min Max Condition tDD 35+3T tDF 25 tDI 50+2T INT(DIIE Bit=1), ACCGR (DMAI Bit=1) tDR 20 tNR 35 Read of DIR, not in Holdoff state Acceptor Handshake Parameter DAV to NDAC DAV to NDAC DAV to INT or ACCRQ Figure 8. Source Handshake Timing Symbol tED tET tTE Limits (ns) Min Max 90 30 30 Test Condition PPSS PPAS PPSS PPAS PPAS PPSS ATN EOI tTE TE DIO tET tED Figure 11. Parallel Poll Response Timing NATIONAL INSTRUMENTS 9 NAT9914APD NAT9914APD NAT9914APL NAT9914APL GPIB +5 V CPU(80186) NAT9914APD NAT9914APD 75160 DRQ ACCRQ* RD* WR* DBIN WE* INT0 INT* RESET RESET* OSC AD15-0 AD15-0 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 D8 D7 D6 D5 D4 D3 D2 D1 CLK 74245 PE D7-0 DEN TE TE DT/R CONT* Decode 74573 A3 A2 A1 D7-0 CE* ACCGR* DC TE REN IFC NDAC NRFD DAV EOI ATN SRQ REN IFC NDAC NRFD DAV EOI ATN SRQ SC +5 V A2 A1 A0 75162 A15-0 A15-0 CPU(6800) GPIB NAT9914APD NAT9914APD 75160 WE* LDSN R/WN ASN UDSN IPL2-0 DBIN +5 V Interrupt Control DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 D8 D7 D6 D5 D4 D3 D2 D1 INT* PE TE Othe r DTA CK Sources DTACKN TE D7-0 D15-0 D15-0 Decode A23-0 A23-0 CE* A3 A2 A1 RESET A2 A1 A0 RESET* CONT* DC TE REN IFC NDAC NRFD DAV EOI ATN SRQ REN IFC NDAC NRFD DAV EOI ATN SRQ SC +5 V CLK OSC 68440 RDYN DTACKN UDSN LDSN R/WN ASN A7-A1 UAS A23/D15 A23/D15 - A8/D0 75162 ACCRQ* ACCGR* GND 74573 74573 OWN 74245 DBEN DDIR DRQ ACK A23-0 A23-0 D15-0 D15-0 Figure 12. Typical CPU Systems with NAT9914 NAT9914 APD 10 NATIONAL INSTRUMENTS NAT9914APD NAT9914APD NAT9914APL NAT9914APL NOTE: All dimensions are shown in inches. 2.050 (NOM) PIN 1 IDENTIFIER 0.625 R. (NOM) .540 (NOM) TOP VIEW .600 (NOM) .075 (NOM) .010±.0003 .055 (NOM) .150 (NOM) .200 (MAX) .030 (NOM) .125 (MIN) .020 (MIN) .018±.003 .100±.010 .650±.040 SIDE VIEW FRONT VIEW Figure 13. Mechanical Data 40-Pin Plastic DIP NOTE: All dimensions are shown in inches. PIN 1 IDENTIFIER .170 (NOM) .050 (NOM) .325 .149 (NOM) .045 x 45° CHFR .088 (NOM) .015 (NOM) .045 x 45° CHFR .325 .230 .650 SQ. .690 SQ. (NOM) (NOM) .620 SQ. (NOM) .026 (NOM) .010 x 45° CHFR (3) .072 (NOM) .021 (NOM) .098 (NOM) Figure 14. Mechanical Data 44-Pin PLCC NATIONAL INSTRUMENTS 11 NAT9914APD NAT9914APD NAT9914APL NAT9914APL Part Numbers Seminars/Training NAT9914APD NAT9914APD NAT9914APL NAT9914APL Part Number Legend a NAT b 9914 c A d P e D a. Family name NAT = 8-bit GPIB Talker/Listener/Controller interface b. Device number 9914 = TI TMS9914A TMS9914A pin-compatible part c. Revision d. Package material P = plastic e. Package type D = Dual Inline Package (DIP) L = Plastic Leaded Chip Carrier (PLCC) NAT9914 NAT9914 Programmer Reference Manual.320775-01 Warranty Free and fee-paid seminars are presented several times a year in cities around the world. Comprehensive, fee-paid training courses are available at National Instruments offices, or at customer sites. Call for training schedules. All National Instruments GPIB hardware products are covered by a two-year warranty from the date of shipment. GPIB chip-level products, DAQ boards and VXIbus and MXIbus products are covered by a one-year warranty. The warranty covers board failures, components, cables, connectors, and switches, but does not cover faults caused by misuse. The owner may return a failed assembly to National Instruments for repair during the warranty period. Extended warranties are available at an additional charge. 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