TMS320VC5505/VC5504 SPRZ281 VC5505 VC5504 TMX320VC5505 TMX320VC5504

Fixed-Point Digital Signal Processor Silicon Revision 1.4 Silicon Errata Literature Number: SPRZ281 June 2009 2 SPRZ281

TMS320VC5505/VC5504 TMS320VC5505/VC5504 Fixed-Point Digital Signal Processor Silicon Revision 1.4 Silicon Errata Literature Number: SPRZ281 SPRZ281 June 2009 2 SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback Contents 1 Introduction. 5 1.1 1.2 2 Device and Development-Support Tool Nomenclature . 5 Revision Identification . 6 Silicon Revision 1.4 Usage Notes and Known Design Exceptions to Functional Specifications . 7 2.1 2.2 . 2.1.1 Master Clock Gating with WAKEUP pin low . 2.1.2 Serial Boots Only Support 16-bit Address Mode . 2.1.3 DMA Only Supports Single-Buffering . 2.1.4 Reserved Bits in the RTC Oscillator Register (RTCOSC) [0x192C] . 2.1.5 Two 1149.1 JTAG Tap Controllers for JTAG Pins (TRST, TCK, TMS, TDI, TDO) . 2.1.6 Bootloader Disables Peripheral Clocks . Silicon Revision 1.4 Known Design Exceptions to Functional Specifications . Usage Notes for Silicon Revision 1.4 SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback Table of Contents 7 7 7 7 7 7 8 8 3 www.ti.com List of Figures 1 2 3 4 5 6 Example, Device Revision Codes for TMX320VC550x (ZCH Package) . 6 CPU, USB, and EMIF Data Paths (A)(B)(C) . 9 DMA Write and CPU Read . 10 CPU Write and DMA Read . 10 USB DMA Read . 10 CPU Read From USB . 11 List of Tables 1 2 3 4 5 4 VC5505 VC5505 and VC5504 VC5504 Device Revision Codes . 6 Silicon Revision 1.4 Advisory List . 8 Transmit Path Internal Data Delays. 15 Receive Path Internal Data Delays . 15 Feedback Path Internal Data Delays . 15 List of Figures SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback Silicon Errata SPRZ281 SPRZ281 June 2009 TMS320C55x Silicon Revision 1 Introduction This document describes the known exceptions to the functional specifications for the TMS320C55x devices (i.e., TMX320VC5505 TMX320VC5505 and TMX320VC5504 TMX320VC5504). For more detailed information on these devices, see the device-specific data manual: · TMS320VC5504 TMS320VC5504 Fixed-Point Digital Signal Processor data manual (Literature Number SPRS609 SPRS609) · TMS320VC5505 TMS320VC5505 Fixed-Point Digital Signal Processor data manual (Literature Number SPRS503 SPRS503) Throughout this document, unless otherwise specified, TMS320VC550x and VC550x, refer to the TMX320VC5505 TMX320VC5505, TMX320VC5504 TMX320VC5504, TMS320VC5505 TMS320VC5505, and TMS320VC5504 TMS320VC5504 devices. For additional peripheral information, see the latest version of the TMS320VC5505 TMS320VC5505 DSP Peripheral Overview Reference Guide (Literature Number SPRUFR9). The advisory numbers in this document are not sequential. Some advisory numbers have been moved to the next revision and others have been removed and documented in the user's guide. When items are moved or deleted, the remaining numbers remain the same and are not resequenced. 1.1 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,TMS320VC5505ZCH TMS320VC5505ZCH). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX - Experimental device that is not necessarily representative of the final device's electrical specifications. TMP - Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS - Fully-qualified production device. Support tool development evolutionary flow: TMDX - Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS - Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback TMS320C55x Silicon Revision 5 Introduction www.ti.com Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZUT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default [594-MHz DSP, 297-MHz ARM9]). 1.2 Revision Identification Figure 1 provides an example(s) of the TMX320VC550x device markings. The device revision can be determined by the symbols marked on the top of the package. TMX320 TMX320 VC5505x ####### G1 Device Revision Code Figure 1. Example, Device Revision Codes for TMX320VC550x (ZCH Package) Silicon revision is identified by a device revision code marked on the package. The code is of the format VC5505x, where "x" denotes the silicon revision. If x is "D" in the device part number, it represents TMX devices and if "x" is no letter (blank) in the device part number, it represents TMS devices. Table 1 lists the information associated with each silicon revision. Table 1. VC5505 VC5505 and VC5504 VC5504 Device Revision Codes DEVICE PART NUMBER DEVICE REVISION CODE (x) (BLANK) 1.4 This silicon revision is available as TMS only. TMS320VC5505ZCH TMS320VC5505ZCH, TMS320VC5504ZCH TMS320VC5504ZCH D 6 SILICON REVISION 1.4 This silicon revision is available as TMX only. TMX320VC5505DZCH TMX320VC5505DZCH, TMX320VC5504DZCH TMX320VC5504DZCH TMS320C55x Silicon Revision PART NUMBERS/COMMENTS SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback www.ti.com 2 Silicon Revision 1.4 Usage Notes and Known Design Exceptions to Functional Specifications Silicon Revision 1.4 Usage Notes and Known Design Exceptions to Functional Specifications This section describes the usage notes and advisories that apply to silicon revision 1.4 of the TMX320VC5505 TMX320VC5505, TMX320VC5504 TMX320VC5504, TMS320VC5505 TMS320VC5505, and TMS320VC5504 TMS320VC5504 devices. 2.1 Usage Notes for Silicon Revision 1.4 Usage notes highlight and describe particular situations where the device's behavior may not match presumed or documented behavior. This may include behaviors that affect device performance or functional correctness. These usage notes will be incorporated into future documentation updates for the device (such as the device-specific data sheet), and the behaviors they describe will not be altered in future silicon revisions. 2.1.1 Master Clock Gating with WAKEUP pin low On silicon revision 1.4, the VC550x DSP can disable the Master Clock, by clearing the bit 15 of PCGCR (0x1C02) register. Once it is disabled, only the hardware (H/W) reset and WAKEUP pins can re-enable the Master Clock. The WAKEUP pin can be configured as an input or an output. As an input, it is an active high (level sensitive) and will enable the Master Clock; therefore, while WAKEUP pin is held high, disabling Master Clock by clearing the bit 15 of PCGCR register will not work. To disable the Master Clock, the WAKEUP pin must be low when configured as an input. When configured as an output, the WAKEUP pin must be driven low to disable the Master Clock. 2.1.2 Serial Boots Only Support 16-bit Address Mode On silicon revision 1.4, the VC550x DSP supports the following boot modes: NOR Flash, NAND Flash, SPI EEPROM, and I2C EEPROM. The SPI and I2C EEPROM boot modes, only support 16-bit address mode. 2.1.3 DMA Only Supports Single-Buffering The VC550x DMA only supports single-buffer operations, the double-buffer (ping-pong) feature is not supported. To handle ping-pong buffers, the DMA needs to be reprogrammed by the CPU at the end of a transfer to the next buffer. Reprogramming the DMA during an active frame transfer will affect the current active transfer. 2.1.4 Reserved Bits in the RTC Oscillator Register (RTCOSC) [0x192C] For proper VC550x device operation on silicon revision 1.4, the "RESERVED" bits in the RTCOSC register (0x192C) should always be set to "zero". 2.1.5 Two 1149.1 JTAG Tap Controllers for JTAG Pins (TRST, TCK, TMS, TDI, TDO) The VCC550x device's have two internal 1149.1 JTAG Tap controllers but only one set of corresponding JTAG pins (TRST, TCK, TMS, TDI, TDO). One TAP controller supports emulation and the other supports JTAG 1149.1 Boundary Scan. Only one of the two TAPs is internally connected to the pins at a time and it is the latched state of the EMU0 pin that determines which TAP is connected. The EMU0 pin is latched on the rising edge of TRST and from that time forward the selected tap is connected to the pins. If the latched state of EMU0 is "0", the boundary scan tap is selected and customers may perform boundary scan testing. If the latched state of EMU0 is "1", the DSP's emulation tap is selected and customers may perform emulation with TI's Code Composer StudioTM IDE Emulation Debugger. Note:Because of the VCC550x devices internal (and recommended external) pullup on the EMU0 pin and the fact that the emulation pods (e.g., XDS560 XDS560) do not drive the EMU0 pin while TRST is driven low-to-high, the emulation tap will be selected. However, customers who wish to do boundary scan testing will need to have an external pulldown, with sufficient strength to overcome the internal pullup, so that the VCC550x boundary scan tap is connected to the JTAG pins. SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback TMS320C55x Silicon Revision 7 Silicon Revision 1.4 Usage Notes and Known Design Exceptions to Functional Specifications 2.1.6 www.ti.com Bootloader Disables Peripheral Clocks At hardware reset, all of the peripheral clocks are off to conserve power. The DSP boots into the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to determine if it can boot from the peripheral. At that time, the individual peripheral's clock will be enabled for the query and then disabled again when the bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be idled. After the boot process is complete, the user is responsible for programming the required clock configuration for the DSP. For example on the VC5505 VC5505 device, the bootloader disables both the MPORT and FFTHWA. To enable the MPORT and FFT HWA, write 0x000E to the ICR registers and issue an "idle" command. Assembly Code Example: *port(#0x0001) = #(0x000E) idle C Code Example: *(ioport volatile unsigned *)0x0001 = 0x000E; asm(" idle"); // must add at leat one blank before idle in " ". For example on the VC5504 VC5504 device, the bootloader disables both the MPORT. To enable the MPORT, write 0x0002E to the ICR registers and issue an "idle" command. Assembly Code Example: *port(#0x0001) = #(0x0002E) idle C Code Example: *(ioport volatile unsigned *)0x0001 = 0x0002E; asm(" idle"); // must add at leat one blank before idle in " ". 2.2 Silicon Revision 1.4 Known Design Exceptions to Functional Specifications Table 2. Silicon Revision 1.4 Advisory List Title . Advisory 1.4.1 Advisory 1.4.2 Advisory 1.4.3 Advisory 1.4.4 Page CPU, USB, and EMIF: Endianess Incompatibility. 9 RTC: RTC Positive Compensation Multiples of Ten Values Do Not Work . 13 I2S: Invalid I2S OUERRFL Error Report at First Frame. . 14 I2S: I2S Internal Data Delay. 15 Advisory 1.4.5 USB: USB Queue Manager Reads Only 16-bit Address of USB Descriptors . 16 8 TMS320C55x Silicon Revision SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback Advisory 1.4.1 - CPU, USB, and EMIF: Endianess Incompatibility www.ti.com Advisory 1.4.1 CPU, USB, and EMIF: Endianess Incompatibility Revision(s) Affected 1.4 Details The VC550x CPU is word addressable and is a big endian architecture. The CPU interfaces to the rest of the system through several ports: MPORT, XPORT, DPORT, and IPORT. The DMA transfers data from peripherals to on-chip memory through the MPORT in 32-bit packets. The CPU accesses the peripherals through the XPORT in 8or 16-bit packets. The CPU accesses external memory through the DPORT in 8-bit (for the EMIF through a system register setting) , 16-bit (single-word access) or 32-bit (dual-word access) packets. The CPU fetches code from external memory through the IPORT in 32-bit packets. Accesses through the MPORT are big endian. Accesses through the XPORT are just 8-bit (for the USB through a system register setting) or 16-bits. 32-bit accesses through the DPORT are word swapped (MSW and LSW of a 32-bit access are swapped). Some VC550x peripherals (e.g., EMIF, USB, LCD, and MMC/SD) have sensitivity to the data endianness. MMC/SD and LCD endianness is controlled through software. On the other hand, USB and EMIF, are hardcoded to little endian. Data transfers between incompatible endianess systems could result in swapped bytes/words based on the size of the data. For example, if the CPU writes data to external memory, the transfer occurs through the DPORT which swaps the MSW and LSW. If the DMA transfers the data from external memory to on-chip memory, the transfer occurs through the MPORT. The MPORT does not swap words; therefore, if the CPU compares the original values it wrote to external memory with those written by the DMA, they will be word swapped. Figure 2 shows data paths that could create byte/word swaps. USB (Byte Addressable) 32 Bits 32 Bits MPORT USB DMA EMIF (Packs and Unpack Requests to the Native Memory Width) NAND, SRAM, or NOR 32 Bits Word Swap LCD 32 Bits 32 Bits 8 or 16 Bits 32 Bits MPORT MMC/SD 8, 16 or 32 Bits 32 Bits MPORT CPU DMA XPORT SARAM and DARAM A 8 or 16 Bits I/DPORT PC (Byte Addressable) IPORT DPORT C55x CPU The "SARAM and DARAM" and C55x CPU blocks are big endian architecture. B The "LCD" and "MMC/SD" blocks are software configurable for endianess. C The "PC", "USB", "EMIF", and "NAND, SRAM, or NOR" blocks are little endian architecture. Figure 2. CPU, USB, and EMIF Data Paths (A)(B)(C) SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback TMS320C55x Silicon Revision 9 Advisory 1.4.1 - CPU, USB, and EMIF: Endianess Incompatibility www.ti.com Example Case 1: Data transfer between the EMIF and CPU (see Figure 3 and Figure 4). Data can be written to or read from the EMIF by the DMA or CPU. The DMA uses the MPORT and does only a 32-bit read/write while the CPU can do a read/write as either 32-bit or 16-bit through the DPORT. The CPU can fetch instructions from the EMIF via the IPORT. The word/byte swap occurs only if the DMA and CPU are combined in the reading and writing (writing with the DMA and reading with the CPU or vice-versa). In a case where the DMA or CPU is used for both writing and reading, no word/byte swap will occur. Data in CPU RAM 0x1234 Data in EMIF DMA write (32-bit) 0x5678 0x5678 0x1234 0x5678 0x1234 CPU read Figure 3. DMA Write and CPU Read Data in CPU RAM Data in EMIF 0x1234 0x5678 CPU write (16-bit) 0x5678 0x1234 0x1234 0x5678 DMA read (32-bit) Figure 4. CPU Write and DMA Read Example Case 2: Data transfer between the USB and CPU (see Figure 5 and Figure 6). If the PC host (little endian) writes data to the VC550x through the USB, the USB peripheral transfers the data to on-chip memory through MPORT. If the CPU reads data from on-chip memory, the data will be byte and word swapped. If instead of using the USB peripheral's DMA to read the data, the CPU reads the data from the USB (using XPORT), the data is byte swapped at word boundaries. Data can be read from the USB by the USB DMA or CPU. The USB DMA uses the MPORT and does only a 32-bit read while CPU can do only a 16-bit read via the XPORT. The bytes/words of data will be out-of-order based on the size of original data. Data in PC (byte address) Data in USB (byte address) 0x12 0x12 0x34 0x56 0x34 0x56 0x78 Data in CPU RAM Read by DMA 0x78 0x7856 0x3412 (byte swap) Figure 5. USB DMA Read 10 TMS320C55x Silicon Revision SPRZ281 SPRZ281 June 2009 Submit Documentation Feedback Advisory 1.4.1 - CPU, USB, and EMIF: Endianess Incompatibility www.ti.com Data in PC (byte address) Data in USB (byte address) 0x12 0x12 0x34 0x56 0x34 0x56 0x78 Data in CPU RAM Read by CPU 0x78 0x3412 0x7856 (inter byte swap) Figure 6. CPU Read From USB Workaround(s) To correct this issue, it requires software to perform a word/byte swap on the data prior to processing on the C550x CPU. Two software examples are given for correcting word swapped data from/to the EMIF. For USB data read/write, it is recommended to do the correction in the PC side because the PC is byte addressable and more flexible to move data. Workaround #1 Software example to correct word/byte swap between the EMIF and CPU (DMA Write and CPU Read): Uint16 buff_in_RAM[N]; // buffer in CPU RAM Uint16 buff_in_EMIF[N]; // buffer in EMIF Uint16 i; . // read from EMIF after writing data with DMA to EMIF for(i=0;i