TMS320VC5502 SPRS166G SPRS166F TMS320VC5502PGF SPRU371 XDS510 TMS320VC5501 - Datasheet Archive

 

Digital Signal Processor Data Manual Literature Number: SPRS166G April 2001 - Revised June 2004 PRODUCTION DATA information is

 

TMS320VC5502 TMS320VC5502 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS166G SPRS166G April 2001 - Revised June 2004 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated Revision History REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS166F SPRS166F device-specific data sheet to make it an SPRS166G SPRS166G revision. Scope: This document is now Production Data. PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS Global changes: - removed the following Notes: - Information/data on the TMS320VC5502 TMS320VC5502 GZZ device is Production Data. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - Information/data on the TMS320VC5502 TMS320VC5502 PGF device is Product Preview. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. - removed all references to the Control Mode Register (CMR) Title Page: - changed Status Statement to that of Production Data 19 Section 2.2.2, Low-Profile Quad Flatpack (PGF): - added Note about TMS320VC5502PGF TMS320VC5502PGF completing Temp Cycle reliability qualification testing 34 Table 2-4, Signal Descriptions: - GPIO[7:0], Function column, Input clock source selection: - changed "An external crystal or ceramic resonator must be attached to the X1 and X2/CLKIN pins ." to "An external crystal must be attached to the X1 and X2/CLKIN pins ." 88 Updated Section 3.10.7, IDLE Control and Status Registers 89 Table 3-28, IDLE Configuration Register Bit Field Description: - deleted footnote about ICR and IDLE mode 119 Table 3-57, Peripheral Bus Controller Configuration Registers: - 0x0000: changed "CMR" (Control Mode Register) to "Reserved" 120 Table 3-58, External Memory Interface Registers: - added EMIF CE Size Control Register 1 at 0x0840 - added EMIF CE Size Control Register 2 at 0x0841 139 Updated Section 5, Device and Development-Support Tool Nomenclature 201 Section 7.2, Low-Profile Quad Flatpack Mechanical Data: - added Note about TMS320VC5502PGF TMS320VC5502PGF completing Temp Cycle reliability qualification testing April 2001 - Revised June 2004 SPRS166G SPRS166G 3 Revision History 4 SPRS166G SPRS166G April 2001 - Revised June 2004 Contents Contents Section Page 1 TMS320VC5502 TMS320VC5502 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Ball Grid Array (GZZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Low-Profile Quad Flatpack (PGF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 17 19 21 3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.5 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Configurable External Ports and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Parallel Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Host Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Serial Port 2 Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 External Bus Selection Register (XBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.5 Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Timer Signal Selection Register (TSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Inter-Integrated Circuit (I2C) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Host-Port Interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 DMA Channel 0 Control Register (DMA_CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 Input Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 Clock Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 EMIF Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.4 Changing the Clock Group Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.5 PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.6 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Idle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 IDLE Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.3 Module Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.4 Wake-Up Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.5 Auto-Wakeup/Idle Function for McBSP and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 42 42 43 43 44 45 45 46 46 47 48 49 51 53 54 55 56 57 59 60 61 61 63 64 66 67 68 70 80 81 81 81 84 85 88 April 2001 - Revised June 2004 SPRS166G SPRS166G 5 Contents Section Page 3.10.6 Clock State of Multiplexed Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.7 IDLE Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.1 General-Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.2 Parallel Port General-Purpose I/O (PGPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 External Bus Control Register (XBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Ports and System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 XPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 DPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 IPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.4 System Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.5 Time-Out Control Register (TOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.1 IFR and IER Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.3 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notice Concerning TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 88 97 97 99 106 107 108 108 111 113 114 115 116 119 133 134 135 135 135 4 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Electrical Characteristics Over Recommended Operating Case Temperature Range . . . . . . . 6.5 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.3 Clock Generation in Bypass Mode (APLL Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.4 Clock Generation in Lock Mode (APLL Synthesis Enabled) . . . . . . . . . . . . . . . . . . . 6.7.5 EMIF Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 Asynchronous Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 Programmable Synchronous Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 Synchronous DRAM Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 HOLD/HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 External Interrupt and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 140 140 140 141 143 144 145 145 146 147 148 150 152 152 155 159 164 165 167 3.11 3.12 3.13 3.14 3.15 3.16 3.17 6 SPRS166G SPRS166G April 2001 - Revised June 2004 Contents Section 6.12 6.13 6.14 6.15 XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input/Output (GPIOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel General-Purpose Input/Output (PGPIOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.1 TIM0/TIM1/WDTOUT Timer Pin Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.2 TIM0/TIM1/WDTOUT General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.3 TIM0/TIM1/WDTOUT Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.1 McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.2 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.3 McBSP as SPI Master or Slave Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host-Port Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.1 HPI Read and Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.2 HPI General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.3 HPI.HAS Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-Integrated Circuit (I2C) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver/Transmitter (UART) Timings . . . . . . . . . . . . . . . . . . . . . . . . . 168 169 170 171 171 172 174 175 175 178 179 187 187 194 196 197 199 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Low-Profile Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 200 201 6.16 6.17 6.18 6.19 7 Page April 2001 - Revised June 2004 SPRS166G SPRS166G 7 Figures List of Figures Figure Page 2-1 201-Terminal GZZ Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2-2 176-Pin PGF Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3-1 TMS320VC5502 TMS320VC5502 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3-2 TMS320VC5502 TMS320VC5502 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3-3 External Bus Selection Register Layout (0x6C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3-4 Configuration Example A (GPIO6 = 1 and GPIO7 = 1 at Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3-5 Configuration Example B (GPIO6 = 0 and GPIO7 = 0 at Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3-6 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3-7 Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3-8 3-9 Timer Signal Selection Register Layout (0x8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 58 3-10 I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3-11 DMA Channel 0 Control Register Layout (0x0C01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3-12 System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3-13 Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3-14 Clock Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3-15 PLL Control/Status Register Layout (0x1C80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3-16 3-17 PLL Multiplier Control Register Layout (0x1C88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 0 Register Layout (0x1C8A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 73 3-18 PLL Divider 1 Register Layout (0x1C8C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3-19 PLL Divider 2 Register Layout (0x1C8E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3-20 PLL Divider 3 Register Layout (0x1C90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3-21 Oscillator Divider1 Register Layout (0x1C92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3-22 Oscillator Wakeup Control Register Layout (0x1C98) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3-23 CLKOUT3 Select Register Layout (0x1C82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3-24 3-25 CLKOUT Selection Register Layout (0x8400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Control Register Layout (0x8C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 79 3-26 IDLE Configuration Register Layout (0x0001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3-27 IDLE Status Register Layout (0x0002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3-28 Peripheral IDLE Control Register Layout (0x9400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3-29 Peripheral IDLE Status Register Layout (0x9401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3-30 Master IDLE Control Register Layout (0x9402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3-31 Master IDLE Status Register Layout (0x9403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3-32 3-33 GPIO Direction Register Layout (0x3400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Layout (0x3401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 98 3-34 Parallel GPIO Enable Register 0 Layout (0x4400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3-35 Parallel GPIO Direction Register 0 Layout (0x4401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3-36 Parallel GPIO Data Register 0 Layout (0x4402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8 SPRS166G SPRS166G April 2001 - Revised June 2004 Figures Figure Page 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 Parallel GPIO Enable Register 1 Layout (0x4403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 1 Layout (0x4404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 1 Layout (0x4405) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 2 Layout (0x4406) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 2 Layout (0x4407) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 2 Layout (0x4408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register Layout (0x8800) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Configuration Register Layout (0x0100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Bus Error Register Layout (0x0102) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Configuration Register Layout (0x0200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Bus Error Register Layout (0x0202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPORT Bus Error Register Layout (0x0302) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register Layout (0x07FD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Out Control Register Layout (0x9000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFR0, IER0, DBIFR0, and DBIER0 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFR1, IER1, DBIFR1, and DBIER1 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bad TCK Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Good TCK Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Noise Filtering Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 102 103 104 104 105 107 109 110 111 112 113 114 115 134 134 136 136 137 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass Mode Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Multiply-by-N Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKIN Timings for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKOUT1 Timings for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKOUT2 Timings for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Read Timings (With Read Latency = 2) . . . . . . . . . . . . . . . . Programmable Synchronous Interface Write Timings (With Write Latency = 0) . . . . . . . . . . . . . . . . Programmable Synchronous Interface Write Timings (With Write Latency = 1) . . . . . . . . . . . . . . . . SDRAM Read Command (CAS Latency 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM ACTV Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DEAC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM REFR Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM MRS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Self-Refresh Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF.HOLD/HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 145 147 149 150 150 151 153 154 156 157 158 160 160 161 161 162 162 163 163 164 166 April 2001 - Revised June 2004 SPRS166G SPRS166G 9 Figures Figure Page 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 6-42 6-43 6-44 6-45 6-46 6-47 6-48 6-49 External Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Acknowledge Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input/Output (GPIOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel General-Purpose Input/Output (PGPIOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . Non-Multiplexed Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Read Timings Using HPI.HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Read Timings With HPI.HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Write Timings Using HPI.HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Write Timings With HPI.HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HINT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI.HAS Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 167 168 169 170 171 171 173 174 177 177 178 180 182 184 186 189 190 191 192 193 193 195 196 197 198 199 7-1 7-2 TMS320VC5502 TMS320VC5502 201-Ball MicroStar BGA Plastic Ball Grid Array Package . . . . . . . . . . . . . . . . . . . TMS320VC5502 TMS320VC5502 176-Pin Low-Profile Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 201 10 SPRS166G SPRS166G April 2001 - Revised June 2004 Tables List of Tables Table Page 2-1 2-2 2-3 2-4 201-Terminal GZZ Ball Grid Array Thermal Ball Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201-Terminal GZZ Ball Grid Array Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 20 21 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38 3-39 On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Configuration Selection Via the BOOTM[2:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 TMS320VC5502 Routing of Parallel Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 TMS320VC5502 Routing of Host Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 TMS320VC5502 Routing of Serial Port 2 Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clocks Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control/Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 0 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 2 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 3 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Divider1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Wakeup Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT3 Select Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Number of Reference Clock Cycles Needed Until Program Flow Begins . . . . . . . . . . . . . . . . . . . . . Peripheral Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Domain Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 TMS320VC5502 PGPIO Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 43 45 47 48 48 50 56 62 65 66 70 71 72 73 74 75 75 76 77 78 79 79 80 84 87 88 89 91 92 94 95 96 97 98 99 100 100 101 April 2001 - Revised June 2004 SPRS166G SPRS166G 11 Tables Table Page 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 3-75 3-76 3-77 Parallel GPIO Enable Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins With Pullups, Pulldowns, and Bus Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Addresses Under Scope of XPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Out Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Bus Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 102 103 104 104 105 106 107 108 109 110 111 112 113 114 115 116 119 120 121 124 124 124 124 126 127 128 129 129 130 130 131 131 131 131 132 132 133 6-1 6-2 6-3 6-4 6-5 6-6 6-7 Thermal Resistance Characteristics (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Characteristics (Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKIN in Bypass Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT in Bypass Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKIN in Lock Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT in Lock Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 144 145 147 147 148 148 12 SPRS166G SPRS166G April 2001 - Revised June 2004 Tables Table 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 6-42 6-43 6-44 6-45 6-46 6-47 6-48 6-49 6-50 6-51 6-52 6-53 Page EMIF Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Switching Characteristics for ECLKOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Cycle Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous DRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous DRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF.HOLD/HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF.HOLD/HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt and Interrupt Acknowledge Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt and Interrupt Acknowledge Switching Characteristics . . . . . . . . . . . . . . . . . . . . . XF Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGPIO Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics . . . . . . . . TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . HPI Read and Write Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Read and Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI.HAS Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (SDA and SCL) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (SDA and SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . April 2001 - Revised June 2004 SPRS166G SPRS166G 150 150 151 152 152 155 155 159 159 164 164 165 165 167 167 168 169 169 170 170 171 171 172 172 174 175 176 178 178 179 179 181 181 183 183 185 185 187 188 194 194 196 197 198 199 199 13 Tables 14 SPRS166G SPRS166G April 2001 - Revised June 2004 Features 1 TMS320VC5502 TMS320VC5502 Features D High-Performance, Low-Power, Fixed-Point D D D D D D TMS320C55x Digital Signal Processor (DSP) - 3.33-/5-ns Instruction Cycle Time - 300-/200-MHz Clock Rate - 16K-Byte Instruction Cache (I-Cache) - One/Two Instructions Executed per Cycle - Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)] - Two Arithmetic/Logic Units (ALUs) - One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses Instruction Cache (16K Bytes) 32K x 16-Bit On-Chip RAM That is Composed of Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes) 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes) 8M × 16-Bit Maximum Addressable External Memory Space 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to: - Asynchronous Static RAM (SRAM) - Asynchronous EPROM - Synchronous DRAM (SDRAM) - Synchronous Burst RAM (SBRAM) Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values D Programmable Low-Power Control of Six D D D D D D Device Functional Domains On-Chip Peripherals - Six-Channel Direct Memory Access (DMA) Controller - Three Multichannel Buffered Serial Ports (McBSPs) - Programmable Analog Phase-Locked Loop (APLL) Clock Generator - General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF) - 8-Bit/16-Bit Parallel Host-Port Interface (HPI) - Four Timers - Two 64-Bit General-Purpose Timers - 64-Bit Programmable Watchdog Timer - 64-Bit DSP/BIOS Counter - Inter-Integrated Circuit (I2C) Interface - Universal Asynchronous Receiver/ Transmitter (UART) On-Chip Scan-Based Emulation Logic IEEE Std 1149.1 (JTAG) Boundary Scan Logic Packages: - 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix) - 201-Terminal MicroStar BGA (Ball Grid Array) (GZZ Suffix) 3.3-V I/O Supply Voltage 1.26-V Core Supply Voltage TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. April 2001 - Revised June 2004 SPRS166G SPRS166G 15 Introduction 2 Introduction This section describes the main features of the TMS320VC5502 TMS320VC5502 and gives a brief description of the device. NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference Guide (literature number SPRU371 SPRU371). 2.1 Description The TMS320VC5502 TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide host processor access to 32K words of internal memory on the 5502. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included. The 5502 is supported by the industry's award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX, XDS510 XDS510 emulation device drivers, and evaluation modules. The 5502 is also supported by the C55x DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries. C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 XDS510 are trademarks of Texas Instruments. 16 SPRS166G SPRS166G April 2001 - Revised June 2004 Introduction 2.2 Pin Assignments 2.2.1 Ball Grid Array (GZZ) The TMS320VC5502 TMS320VC5502 is offered in a 201-terminal ball grid array (BGA) package which includes 25 thermal balls to improve thermal dissipation. Figure 2-1 illustrates the ball locations for the 201-terminal BGA package. Table 2-1 lists the locations of the thermal balls and Table 2-2 lists the signal names and terminal numbers. NOTE: Some TMX samples were shipped in the GGW package. For more information on the GGW package, see the TMS320VC5502 TMS320VC5502 and TMS320VC5501 TMS320VC5501 Digital Signal Processors Silicon Errata (literature number SPRZ020D SPRZ020D or later). U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 2-1. 201-Terminal GZZ Ball Grid Array (Bottom View) Table 2-1. 201-Terminal GZZ Ball Grid Array Thermal Ball Locations BALL NO. BALL NO. BALL NO. BALL NO. BALL NO. G7 G8 G9 G10 G11 H7 H8 H9 H10 H11 J7 J9 J10 J11 K8 K9 K10 K11 L7 J8 K7 L8 L9 L10 L11 For best device thermal performance: - An array of 25 land pads must be added on the top layer of the PCB where the package will be mounted. - The PCB land pads should be the same diameter as the vias in the package substrate for optimal Board Level Reliability Temperature Cycle performance. - The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be connected to the ground plane for heat dissipation. - A solid internal plane is preferred for spreading the heat. Refer to the MicroStar BGAE Packaging Reference Guide (literature number SSYZ015 SSYZ015) for guidance on PCB design, surface mount, and reliability considerations. April 2001 - Revised June 2004 SPRS166G SPRS166G 17 Introduction Table 2-2. 201-Terminal GZZ Ball Grid Array Ball Assignments BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME B1 GPIO6 U2 HCNTL1 T17 A19 A16 D16 C2 GPIO4 T3 HCNTL0 R16 A18 B15 D15 C1 GPIO2 U3 VSS R17 VSS A15 D14 D3 GPIO1 R4 HR/W P15 A17 C14 D13 D2 GPIO0 T4 HDS2 P16 A16 B14 D12 D1 TIM1 U4 CVDD P17 DVDD A14 D11 E3 TIM0 R5 HDS1 N15 A15 C13 D10 E2 INT0 T5 HRDY N16 A14 B13 D9 E1 CVDD U5 DVDD N17 VSS A13 DVDD F3 INT1 R6 CLKOUT M15 A13 C12 D8 F2 INT2 T6 XF M16 A12 B12 D7 F1 DVDD U6 VSS M17 CVDD A12 VSS G4 INT3 P7 C15 L14 A11 D11 D6 G3 NMI/WDTOUT R7 C14 L15 A10 C11 D5 G2 IACK T7 HINT L16 A9 B11 D4 G1 VSS U7 PVDD L17 A8 A11 CVDD H1 CLKR0 U8 NC K17 DVDD A10 D3 H4 DR0 P8 X1 K14 A7 D10 D2 H3 FSR0 R8 X2/CLKIN K15 A6 C10 D1 H2 CLKX0 T8 EMIFCLKS K16 A5 B10 D0 J1 CVDD U9 VSS J17 VSS A9 VSS J4 DX0 P9 C13 J14 A4 D9 EMU1/OFF J3 FSX0 R9 C12 J15 A3 C9 EMU0 J2 CLKR1 T9 C11 J16 A2 B9 TDO K1 DR1 U10 C10 H17 CVDD A8 VSS K2 FSR1 T10 C9 H16 D31 B8 TDI K4 DX1 P10 C8 H14 D30 D8 TRST K3 CLKX1 R10 C7 H15 D29 C8 TCK L1 VSS U11 VSS G17 VSS A7 TMS L2 FSX1 T11 ECLKIN G16 D28 B7 RESET L3 DR2 R11 ECLKOUT2 G15 D27 C7 HPIENA L4 DX2 P11 ECLKOUT1 G14 D26 D7 HD7 M1 CVDD U12 CVDD F17 CVDD A6 CVDD M2 SP3 T12 C6 F16 D25 B6 HD6 M3 SP2 R12 C5 F15 D24 C6 HD5 N1 DVDD U13 DVDD E17 DVDD A5 DVDD N2 SP1 T13 C4 E16 D23 B5 HD4 N3 SP0 R13 C3 E15 D22 C5 HD3 P1 VSS U14 VSS D17 D21 A4 CVDD P2 SCL T14 C2 D16 D20 B4 HD2 P3 SDA R14 C1 D15 D19 C4 HD1 R1 HC1 U15 C0 C17 VSS A3 VSS R2 HC0 T15 A21 C16 D18 B3 HD0 T1 HCS U16 A20 B17 D17 A2 GPIO7 CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD . NC = No Connect 18 SPRS166G SPRS166G April 2001 - Revised June 2004 Introduction 2.2.2 Low-Profile Quad Flatpack (PGF) The TMS320VC5502 TMS320VC5502 is offered in a 176-pin low-profile quad flatpack (LQFP). Figure 2-2 illustrates the pin locations for the 176-pin LQFP. Table 2-3 lists the signal names and pin numbers. NOTE: TMS320VC5502PGF TMS320VC5502PGF has completed Temp Cycle reliability qualification testing with no failures through 1500 cycles of -55°C to 125°C following an EIA/JEDEC Moisture Sensitivity Level 4 pre-condition at 220+5/-0°C peak reflow. Exceeding this peak reflow temperature condition or storage and handling requirements may result in either immediate device failure post-reflow, due to package/die material delamination ("popcorning"), or degraded Temp cycle life performance. Please note that Texas Instruments (TI) also provides MSL, peak reflow and floor life information on a bar-code label affixed to dry-pack shipping bags. Shelf life, temperature and humidity storage conditions and re-bake instructions are prominently displayed on a nearby screen-printed label. 132 89 133 88 176 45 1 44 Figure 2-2. 176-Pin PGF Low-Profile Quad Flatpack (Top View) April 2001 - Revised June 2004 SPRS166G SPRS166G 19 Introduction Table 2-3. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME GPIO6 45 HCNTL1 89 A19 133 D16 2 GPIO4 46 HCNTL0 90 A18 134 D15 3 GPIO2 47 VSS 91 VSS 135 D14 4 GPIO1 48 HR/W 92 A17 136 D13 5 GPIO0 49 HDS2 93 A16 137 D12 6 TIM1 50 CVDD 94 DVDD 138 D11 7 TIM0 51 HDS1 95 A15 139 D10 8 INT0 52 HRDY 96 A14 140 D9 9 CVDD 53 DVDD 97 VSS 141 DVDD 10 INT1 54 CLKOUT 98 A13 142 D8 11 INT2 55 XF 99 A12 143 D7 12 DVDD 56 VSS 100 CVDD 144 VSS 13 INT3 57 C15 101 A11 145 D6 14 NMI/WDTOUT 58 C14 102 A10 146 D5 15 IACK 59 HINT 103 A9 147 D4 16 VSS 60 PVDD 104 A8 148 CVDD 17 CLKR0 61 NC 105 DVDD 149 D3 18 DR0 62 X1 106 A7 150 D2 19 FSR0 63 X2/CLKIN 107 A6 151 D1 20 CLKX0 64 EMIFCLKS 108 A5 152 D0 21 CVDD 65 VSS 109 VSS 153 VSS 22 DX0 66 C13 110 A4 154 EMU1/OFF 23 FSX0 67 C12 111 A3 155 EMU0 24 CLKR1 68 C11 112 A2 156 TDO 25 DR1 69 C10 113 CVDD 157 VSS 26 FSR1 70 C9 114 D31 158 TDI 27 DX1 71 C8 115 D30 159 TRST 28 CLKX1 72 C7 116 D29 160 TCK 29 VSS 73 VSS 117 VSS 161 TMS 30 FSX1 74 ECLKIN 118 D28 162 RESET 31 DR2 75 ECLKOUT2 119 D27 163 HPIENA 32 DX2 76 ECLKOUT1 120 D26 164 HD7 33 CVDD 77 CVDD 121 CVDD 165 CVDD 34 SP3 78 C6 122 D25 166 HD6 35 SP2 79 C5 123 D24 167 HD5 36 DVDD 80 DVDD 124 DVDD 168 DVDD 37 SP1 81 C4 125 D23 169 HD4 38 SP0 82 C3 126 D22 170 HD3 39 VSS 83 VSS 127 D21 171 CVDD 40 SCL 84 C2 128 D20 172 HD2 41 SDA 85 C1 129 D19 173 HD1 42 HC1 86 C0 130 VSS 174 VSS 43 HC0 87 A21 131 D18 175 HD0 44 PIN NO. 1 SIGNAL NAME HCS 88 A20 132 D17 176 GPIO7 CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD . NC = No Connect 20 SPRS166G SPRS166G April 2001 - Revised June 2004 Introduction 2.3 Signal Descriptions Table 2-4 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2, Pin Assignments, for exact pin locations based on package type. Table 2-4. Signal Descriptions Pin Name Multiplexed Signal Name Pin Type Other I/O/Z The A[21:18] pins of the Parallel Port serve one of two functions: parallel general-purpose input/output (PGPIO) signals PGPIO[3:0] or external memory interface (EMIF) address bus signals EMIF.A[21:18]. The function of the A[21:18] pins is determined by the state of the GPIO6 pin during reset. The A[21:18] pins are set to PGPIO[3:0] if GPIO6 is low during reset. The A[21:18] pins are set to EMIF.A[21:18] if GPIO6 is high during reset. The function of the A[21:18] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C, D, E, The A[21:18] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors F, G, H, on unused pins. When the bus goes into a high-impedance state, the bus holders keep the M address bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). PGPIO[3:0] I/O/Z Parallel general-purpose I/O. PGPIO[3:0] is selected if GPIO6 is low during reset. The PGPIO[3:0] signals are configured as inputs after reset. EMIF.A[21:18] O/Z EMIF address bus. EMIF.A[21:18] is selected if GPIO6 is high during reset. The EMIF.A[21:18] signals are in a high-impedance state during reset and are configured as outputs after reset with an output value of 0. Function Parallel Port - Address Bus A[21:18] I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup [always enabled] B - Internal pulldown [always enabled] C - Hysteresis input D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G - Pin can be configured as a general-purpose input. H - Pin can be configured as a general-purpose output. J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) April 2001 - Revised June 2004 SPRS166G SPRS166G 21 Introduction Table 2-4. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port - Address Bus (Continued) A[17:2] I/O/Z HPI.HA[15:0] I/O/Z EMIF.A[17:2] O/Z The A[17:2] pins of the Parallel Port serve one of two functions: host-port interface (HPI) address bus signals HPI.HA[15:0] or external memory interface (EMIF) address bus signals EMIF.A[17:2]. The function of the A[17:2] pins is determined by the state of the GPIO6 pin during reset. The A[17:2] pins are set to HPI.HA[15:0] if GPIO6 is low during reset. The A[17:2] pins are set to EMIF.A[17:2] if GPIO6 is high during reset. The function of the A[17:2] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The A[17:2] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the C, D, E, address bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). F, M HPI address bus. HPI.HA[15:0] is selected when GPIO6 is low during reset. The HPI.HA[15:0] signals are configured as inputs after reset. The HPI will operate in non-multiplexed mode when GPIO6 is low during reset. In non-multiplexed mode, the HPI uses separate address and data buses: a 16-bit address bus (HPI.HA[15:0]) and a 16-bit data bus (HPI.HD[15:0]). Each host cycle on the data bus consists of one 16-bit data transfer. EMIF address bus. EMIF.A[17:2] is selected when GPIO6 is high during reset. The EMIF.A[17:2] signals are in a high-impedance state during reset and are configured as outputs after reset with an output value of 0. Parallel Port - Data Bus D[31:16] I/O/Z The D[31:16] pins of the Parallel Port serve one of two functions: parallel general-purpose input/output (PGPIO) signals PGPIO[19:4] or external memory interface (EMIF) data bus signals EMIF.D[31:16]. The function of the D[31:16] pins is determined by the state of the GPIO6 pin during reset. The D[31:16] pins are set to PGPIO[19:4] if GPIO6 is low during reset. The D[31:16] pins are set to EMIF.D[31:16] if GPIO6 is high during reset. The function of the D[31:16] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C, D, E, The D[31:16] bus includes bus holders to reduce the static power dissipation caused by F, G, H, floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the M data bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). PGPIO[19:4] 22 Parallel general-purpose I/O. PGPIO[19:4] is selected when GPIO6 is low during reset. The PGPIO[19:4] signals are configured as inputs after reset. EMIF.D[31:16] I/O/Z I/O/Z EMIF data bus. EMIF.D[31:16] is selected when GPIO6 is high during reset. The EMIF.D[31:16] signals are configured as inputs after reset. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup [always enabled] B - Internal pulldown [always enabled] C - Hysteresis input D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G - Pin can be configured as a general-purpose input. H - Pin can be configured as a general-purpose output. J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) SPRS166G SPRS166G April 2001 - Revised June 2004 Introduction Table 2-4. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port - Data Bus (Continued) D[15:0] I/O/Z The D[15:0] pins of the Parallel Port serve one of two functions: host-port interface (HPI) data bus signals HPI.HD[15:0] and external memory interface (EMIF) data bus signals EMIF.D[15:0]. The function of the D[15:0] pins is determined by the state of the GPIO6 pin during reset. The D[15:0] pins are set to HPI.HD[15:0] if GPIO6 is low during reset. The D[15:0] pins are set to EMIF.D[15:0] if GPIO6 is high during reset. The function of the D[15:0] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The D[15:0] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep C, D, E, the data bus at the logic level that was most recently driven. The bus holders are enabled F, M at reset and can be enabled/disabled through the External Bus Control Register (XBCR). HPI.HD[15:0] EMIF.D[15:0] I/O/Z HPI data bus. HPI.HD[15:0] is selected when GPIO6 is low during reset. The HPI.HD[15:0] signals are configured as inputs after reset. The HPI will operate in non-multiplexed mode when GPIO6 is low during reset. In non-multiplexed mode, the HPI uses separate address and data buses: a 16-bit address bus (HPI.HA[15:0]) and a 16-bit data bus (HPI.HD[15:0]). Each host cycle on the data bus consists of one 16-bit data transfer. I/O/Z EMIF data bus. EMIF.D[15:0] is selected when GPIO6 is high during reset. The EMIF.D[15:0] signals are configured as inputs after reset. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup [always enabled] B - Internal pulldown [always enabled] C - Hysteresis input D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G - Pin can be configured as a general-purpose input. H - Pin can be configured as a general-purpose output. J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) April 2001 - Revised June 2004 SPRS166G SPRS166G 23 Introduction Table 2-4. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port - Control Pins C0 I/O/Z PGPIO20 PGPIO20 I/O/Z EMIF.ARE/SADS/ SDCAS/SRE O/Z C1 I/O/Z PGPIO21 PGPIO21 EMIF.AOE/SOE/ SDRAS 24 I/O/Z O/Z The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO20 PGPIO20 or external memory interface control signal EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the state of the GPIO6 pin during reset. The C0 pin is set to PGPIO20 PGPIO20 if GPIO6 is low during reset. The C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high during reset. The function of the C0 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C, D, E, Parallel general-purpose I/O. PGPIO20 PGPIO20 is selected when GPIO6 is low during reset. F, G, H, The PGPIO20 PGPIO20 signal is configured as an input after reset. M EMIF control pin. EMIF.ARE/SADS/SDCAS/SRE is selected when GPIO6 is high during reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used by the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and synchronous read-enable (EMIF.SRE) (selected by RENEN in the CE Secondary Control Register 1). The C1 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO21 PGPIO21 or external memory interface control signal EMIF.AOE/SOE/SDRAS. The function of the C1 pin is determined by the state of the GPIO6 pin during reset. The C1 pin is set to PGPIO21 PGPIO21 if GPIO6 is low during reset. The C1 pin is set to EMIF.AOE/SOE/SDRAS if GPIO6 is high during reset. The function of the C1 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C, D, E, F, G, H, Parallel general-purpose I/O. PGPIO21 PGPIO21 is selected when GPIO6 is low during reset. The PGPIO21 PGPIO21 signal is configured as an input after reset. M EMIF control pin. EMIF.AOE/SOE/SDRAS is selected when GPIO6 is high during reset. The EMIF.AOE/SOE/SDRAS signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.AOE/SOE/SDRAS signal serves three different functions when used by the EMIF: asynchronous memory output-enable (EMIF.AOE), synchronous memory output-enable (EMIF.SOE), and SDRAM row-address strobe (EMIF.SDRAS). I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup [always enabled] B - Internal pulldown [always enabled] C - Hysteresis input D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G - Pin can be configured as a general-purpose input. H - Pin can be configured as a general-purpose output. J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) SPRS166G SPRS166G April 2001 - Revised June 2004 Introduction Table 2-4. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port - Control Pins (Continued) C2 I/O/Z PGPIO22 PGPIO22 I/O/Z EMIF.AWE/ SWE/SDWE O/Z C3 EMIF.ARDY C, D, E, F, G, H, Parallel general-purpose I/O. PGPIO22 PGPIO22 is selected when GPIO6 is low during reset. The PGPIO22 PGPIO22 signal is configured as an input after reset. M EMIF control pin. EMIF.AWE/SWE/SDWE is selected when GPIO6 is high during reset. The EMIF.AWE/SWE/SDWE signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.AWE/SWE/SDWE signal serves three different functions when used by the EMIF: asynchronous memory write-enable (EMIF.AWE), synchronous memory write-enable (EMIF.SWE), and SDRAM write-enable (EMIF.SDWE). The C3 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO23 PGPIO23 or external memory interface control signal EMIF.ARDY. The function of the C3 pin is determined by the state of the GPIO6 pin during reset. The C3 pin is set to PGPIO23 PGPIO23 if GPIO6 is low during reset. The C3 pin is set to EMIF.ARDY if GPIO6 is high during reset. The function of the C3 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). I/O/Z PGPIO23 PGPIO23 The C2 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO22 PGPIO22 or external memory interface control signal EMIF.AWE/SWE/SDWE. The function of the C2 pin is determined by the state of the GPIO6 pin during reset. The C2 pin is set to PGPIO22 PGPIO22 if GPIO6 is low during reset. The C2 pin is set to EMIF.AWE/SWE/SDWE if GPIO6 is high during reset. The function of the C2 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). I/O/Z I F, G, H, J Parallel general-purpose I/O. PGPIO23 PGPIO23 is selected when GPIO6 is low during reset. The PGPIO23 PGPIO23 signal is configured as an input after reset. EMIF data ready pin. EMIF.ARDY is selected when GPIO6 is high during reset. The EMIF.ARDY signal indicates that an external device is ready for a bus transaction to be completed. If the device is not ready (EMIF.ARDY is low), the processor extends the memory access by one cycle and checks EMIF.ARDY again. An internal pullup is included to disable this feature if not used. The internal pullup can be disabled through the External Bus Control Register (XBCR). I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup [always enabled] B - Internal pulldown [always enabled] C - Hysteresis input D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G - Pin can be configured as a general-purpose input. H - Pin can be configured as a general-purpose output. J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) April 2001 - Revised June 2004 SPRS166G SPRS166G 25 Introduction Table 2-4. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port - Control Pins (Continued) C4 I/O/Z PGPIO24 PGPIO24 I/O/Z EMIF.CE0 O/Z C5 I/O/Z PGPIO25 PGPIO25 I/O/Z EMIF.CE1 O/Z C6 I/O/Z PGPIO26 PGPIO26 EMIF.CE2 26 I/O/Z O/Z The C4 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO24 PGPIO24 or external memory interface control signal EMIF.CE0. The function of the C4 pin is determined by the state of the GPIO6 pin during reset. The C4 pin is set to PGPIO24 PGPIO24 if GPIO6 is low during reset. The C4 pin is set to C, D, E, EMIF.CE0 if GPIO6 is high during reset. The function of the C4 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, Parallel general-purpose I/O. PGPIO24 PGPIO24 is selected when GPIO6 is low during reset. M The PGPIO24 PGPIO24 signal is configured as an input after reset. EMIF chip-select for memory space CE0. EMIF.CE0 is selected when GPIO6 is high during reset. The EMIF.CE0 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C5 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO25 PGPIO25 or external memory interface control signal EMIF.CE1. The function of the C5 pin is determined by the state of the GPIO6 pin during reset. The C5 pin is set to PGPIO25 PGPIO25 if GPIO6 is low during reset. The C5 pin is set to EMIF.CE1 if GPIO6 is high during reset. The function of the C5 pin will be set once the C, D, E, device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, Parallel general-purpose I/O. PGPIO25 PGPIO25 is selected when GPIO6 is low during reset. M The PGPIO25 PGPIO25 signal is configured as an input after reset. EMIF chip-select for memory space CE1. EMIF.CE1 is selected when GPIO6 is high during reset. The EMIF.CE1 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C6 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO26 PGPIO26 or external memory interface control signal EMIF.CE2. The function of the C6 pin is determined by the state of the GPIO6 pin during reset. The C6 pin is set to PGPIO26 PGPIO26 if GPIO6 is low during reset. The C6 pin is set to EMIF.CE2 if GPIO6 is high during reset. The function of the C6 pin will be set once the C, D, E, device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, Parallel general-purpose I/O. PGPIO26 PGPIO26 is selected when GPIO6 is low during reset. M The PGPIO26 PGPIO26 signal is configured as an input after reset. EMIF chip-select for memory space CE2. EMIF.CE2 is selected when GPIO6 is high during reset. The EMIF.CE2 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup [always enabled] B - Internal pulldown [always enabled] C - Hysteresis input D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G - Pin can be configured as a general-purpose input. H - Pin can be configured as a general-purpose output. J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) SPRS166G SPRS166G April 2001 - Revised June 2004 Introduction Table 2-4. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port - Control Pins (Continued) C7 I/O/Z PGPIO27 PGPIO27 I/O/Z EMIF.CE3 O/Z C8 I/O/Z PGPIO28 PGPIO28 I/O/Z EMIF.BE0 O/Z C9 I/O/Z PGPIO29 PGPIO29 EMIF.BE1 I/O/Z O/Z The C7 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO27 PGPIO27 or external memory interface control signal EMIF.CE3. The function of the C7 pin is determined by the state of the GPIO6 pin during reset. The C7 pin is set to PGPIO27 PGPIO27 if GPIO6 is low during reset. The C7 pin is set to EMIF.CE3 if GPIO6 is high during reset. The function of the C7 pin will be set once the C, D, E, device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, Parallel general-purpose I/O. PGPIO27 PGPIO27 is selected when GPIO6 is low during reset. M The PGPIO27 PGPIO27 signal is configured as an input after reset. EMIF chip-select for memory space CE3. EMIF.CE3 is selected when GPIO6 is high during reset. The EMIF.CE3 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C8 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO28 PGPIO28 or external memory interface control signal EMIF.BE0. The function of the C8 pin is determined by the state of the GPIO6 pin during reset. The C8 pin is set to PGPIO28 PGPIO28 if GPIO6 is low during reset. The C8 pin is set to EMIF.BE0 if GPIO6 is high during reset. The function of the C8 pin will be set once the C, D, E, device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, Parallel general-purpose I/O. PGPIO28 PGPIO28 is selected when GPIO6 is low during reset. M The PGPIO28 PGPIO28 signal is configured as an input after reset. EMIF byte-enable 0 control. EMIF.BE0 is selected when GPIO6 is high during reset. The EMIF.BE0 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C9 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO29 PGPIO29 or external memory interface control signal EMIF.BE1. The function of the C9 pin is determined by the state of the GPIO6 pin during reset. The C9 pin is set to PGPIO29 PGPIO29 if GPIO6 is low during reset. The C9 pin is set to EMIF.BE1 if GPIO6 is high during reset. The function of the C9 pin will be set once the C, D, E, device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, Parallel general-purpose I/O. PGPIO29 PGPIO29 is selected when GPIO6 is low during reset. M The PGPIO29 PGPIO29 signal is configured as an input after reset. EMIF byte-enable 1 control. EMIF.BE1 is selected when GPIO6 is high during reset. The EMIF.BE1 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup [always enabled] B - Internal pulldown [always enabled] C - Hysteresis input D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G - Pin can be configured as a general-purpose input. H - Pin can be configured as a general-purpose output. J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) April 2001 - Revised June 2004 SPRS166G SPRS166G 27 Introduction Table 2-4. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port - Control Pins (Continued) C10 I/O/Z PGPIO30 PGPIO30 I/O/Z EMIF.BE2 O/Z C11 I/O/Z PGPIO31 PGPIO31 I/O/Z EMIF.BE3 O/Z C12 I/O/Z PGPIO32 PGPIO32 EMIF.SDCKE 28 I/O/Z O/Z The C10 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO30 PGPIO30 or external memory interface control signal EMIF.BE2. The function of the C10 pin is determined by the state of the GPIO6 pin during reset. The C10 pin is set to PGPIO30 PGPIO30 if GPIO6 is low during reset. The C10 pin is set to EMIF.BE2 if GPIO6 is high during reset. The function of the C10 pin will be set once the C, D, E, device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, Parallel general-purpose I/O. PGPIO30 PGPIO30 is selected when GPIO6 is low during reset. M The PGPIO30 PGPIO30 signal is configured as an input after reset. EMIF byte-enable 2 control. EMIF.BE2 is selected when GPIO6 is high during reset. The EMIF.BE2 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The C11 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO31 PGPIO31 or external memory interface control signal EMIF.BE3. The function of the C11 pin is determined by the state of the GPIO6 pin during reset. The C11 pin is set to PGPIO31 PGPIO31 if GPIO6 is low during reset. The C11 pin is set to EMIF.BE3 if GPIO6 is high during reset. The function of the C11 pin will be set once the C, D, E, device is taken out of reset (RESET pin transitions from a low to high state). F, G, H, Parallel general-purpose I/O. PGPIO31 PGPIO31 is selected when GPIO6 is low during reset. M The PGPIO31 PGPIO31 signal is configured as an input after reset. EMIF byte-enable 3 control. EMIF.BE3 is selected when GPIO6 is high during rese