TMS320VC5501 SPRS206B SPRS206A SPRU312 SPRU371 XDS510 PGPIO20 PGPIO21 PGPIO22 - Datasheet Archive

 

Digital Signal Processor Data Manual Literature Number: SPRS206B December 2002 ­ Revised June 2003 PRODUCT PREVIEW

 

TMS320VC5501 TMS320VC5501 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS206B SPRS206B December 2002 ­ Revised June 2003 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third­party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated Revision History REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS206A SPRS206A device-specific data sheet to make it an SPRS206B SPRS206B revision. Scope: EMIF changed from 16-bit to 32-bit. PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS Section 1, TMS320VC5501 TMS320VC5501 Features: ­ changed size of Maximum Addressable External Memory Space from "4M x 16-Bit" to "8M x 16-Bit" ­ changed External Parallel Bus Memory from "16-Bit" to "32-Bit" 4 Table 2­1, 176-Terminal GGW Ball Grid Array Ball Assignments: ­ changed PGPIO[19:4] to D[31:16] 6 Table 2­2, 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments: ­ changed PGPIO[19:4] to D[31:16] 7 Table 2­3, Signal Descriptions: ­ added description of D[31:16] ­ changed description of C10 ­ changed description of C11 ­ deleted description of PGPIO[19:4] 22 Updated Figure 3­1, Block Diagram of the TMS320VC5501 TMS320VC5501 26 Section 3.1.5, Boot Configuration: ­ updated "External memory boot (via EMIF)" bulleted item ­ updated "Direct execution (no boot)" bulleted item 26 Table 3­3, Boot Configuration Selection Via the BOOTM[2:0] Pins: ­ changed boot process of BOOTM[2:0] = 100 26 Section 3.2, Peripherals: ­ updated EMIF bulleted item ­ updated footnote about 5501 configuration 27 Updated Section 3.3.1, Parallel Port Mux 28 Table 3­4, TMS320VC5501 TMS320VC5501 Routing of Parallel Port Mux Signals: ­ added D[31:16] 30 Section 3.3.3, External Bus Selection Register (XBSR): ­ changed "16-bit EMIF" to "32-bit EMIF" 31 Table 3­6, External Bus Selection Register Bit Field Description: ­ changed description of Bit 0, Parallel/Host Port Mux Mode 73 Updated Section 3.11.2, Parallel Port General-Purpose I/O (PGPIO) 73 Table 3­33, TMS320VC5501 TMS320VC5501 PGPIO Cross-Reference: ­ changed "PGPIO[19:4]" row 80 Updated Table 3­43, Pins With Pullups, Pulldowns, and Bus Holders 81 Updated Table 3­44, External Bus Control Register Bit Field Description 102 Table 3­65, Device Revision ID: ­ removed row for Word Address 0x3807 December 2002 ­ Revised June 2003 PRODUCT PREVIEW 1 SPRS206B SPRS206B iii Revision History PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS Figure 6­7, Asynchronous Memory Read Timing: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 120 Figure 6­8, Asynchronous Memory Write Timing: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 122 Figure 6­9, Programmable Synchronous Interface Read Timing (With Read Latency = 2): ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 123 Figure 6­10, Programmable Synchronous Interface Write Timing (With Write Latency = 0): ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 124 Figure 6­11, Programmable Synchronous Interface Write Timing (With Write Latency = 1): ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 125 Figure 6­12, SDRAM Read Command (CAS Latency 3): ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 126 Figure 6­13, SDRAM Write Command: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 126 Figure 6­14, SDRAM ACTV Command: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 127 Figure 6­15, SDRAM DCAB Command: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 127 Figure 6­16, SDRAM DEAC Command: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 128 Figure 6­17, SDRAM REFR Command: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 128 Figure 6­18, SDRAM MRS Command: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 129 Figure 6­19, SDRAM Self-Refresh Timing: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 130 iv Table 6­11, Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1: ­ changed "BE[1:0]" to "BE[3:0]" in footnote about EMIF signals ­ changed "D[15:0]" to "D[31:0]" in footnote about EMIF signals 119 PRODUCT PREVIEW 118 Table 6­17, EMIF HOLD/HOLDA Switching Characteristics: ­ changed "BE[1:0]" to "BE[3:0]" in footnote about EMIF Bus ­ changed "D[15:0]" to "D[31:0]" in footnote about EMIF Bus SPRS206B SPRS206B December 2002 ­ Revised June 2003 Revision History PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS Figure 6­20, HOLD/HOLDA Timing: ­ changed "BE[1:0]" to "BE[3:0]" ­ changed "D[15:0]" to "D[31:0]" 131 Table 6­19, Reset Switching Characteristics: ­ changed "BE[1:0]" to "BE[3:0]" in footnote ­ changed "D[15:0]" to "D[31:0]" in footnote PRODUCT PREVIEW 130 December 2002 ­ Revised June 2003 SPRS206B SPRS206B v Contents Contents Section Page 1 TMS320VC5501 TMS320VC5501 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Ball Grid Array (GGW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Low-Profile Quad Flatpack (PGF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3 3 5 7 3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.5 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Configurable External Ports and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Parallel Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Host Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 External Bus Selection Register (XBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Timer Signal Selection Register (TSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Inter-Integrated Circuit (I2C) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Host-Port Interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 DMA Channel 0 Control Register (DMA_CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 Input Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 Clock Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 EMIF Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.4 Changing the Clock Group Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.5 PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.6 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Idle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 IDLE Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.3 Module Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.4 Wake-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.5 Auto-Wakeup/Idle Function for McBSP and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.6 Clock State of Multiplexed Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.7 IDLE Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 23 23 24 24 25 26 26 27 27 29 30 31 32 33 34 35 37 38 39 39 41 41 43 43 44 46 56 57 57 57 60 61 64 64 64 December 2002 ­ Revised June 2003 SPRS206B SPRS206B vii Contents Section 3.11 Page General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.1 General-Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.2 Parallel Port General-Purpose I/O (PGPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 External Bus Control Register (XBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Ports and System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 XPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 DPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 IPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.4 System Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.5 Time-Out Control Register (TOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.1 IFR and IER Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 73 80 81 82 82 85 87 88 89 90 92 105 106 107 4 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Clock Generation in Bypass Mode (APLL Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 Clock Generation in Lock Mode (APLL Synthesis Enabled) . . . . . . . . . . . . . . . . . . . 6.7.3 EMIF Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 Programmable Synchronous Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 Synchronous DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 External Interrupt and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 XF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 General-Purpose Input/Output (GPIOx)Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.1 TIM0/TIM1/WDTOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.1 McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.2 McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.3 McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 110 110 110 3.12 3.13 3.14 3.15 3.16 viii SPRS206B SPRS206B 111 112 113 114 114 115 116 118 118 121 125 130 131 132 133 134 135 136 136 139 140 December 2002 ­ Revised June 2003 Contents Section 6.15 6.16 6.17 7 Page HPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 150 152 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Low-Profile Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 153 154 December 2002 ­ Revised June 2003 SPRS206B SPRS206B ix Figures List of Figures Figure Page 2­1 2­2 176-Terminal GGW Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176-Pin PGF Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 3­1 3­2 3­3 3­4 3­5 3­6 3­7 3­8 3­9 3­10 3­11 3­12 3­13 3­14 3­15 3­16 3­17 3­18 3­19 3­20 3­21 3­22 3­23 3­24 3­25 3­26 3­27 3­28 3­29 3­30 3­31 3­32 3­33 3­34 3­35 3­36 3­37 Block Diagram of the TMS320VC5501 TMS320VC5501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5501 TMS320VC5501 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection Register Layout (0x6C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register Layout (0x8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Channel 0 Control Register Layout (0x0C01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL and Clock Generator Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal System Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generator (PLL) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control/Status Register Layout (0x1C80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Control Register Layout (0x1C88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 0 Register Layout (0x1C8A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 1 Register Layout (0x1C8C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 2 Register Layout (0x1C8E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 3 Register Layout (0x1C90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Divider1 Register Layout (0x1C92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Wakeup Control Register Layout (0x1C98) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT3 Select Register Layout (0x1C82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selection Register Layout (0x8400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Control Register Layout (0x8C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Configuration Register Layout (0x0001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Status Register Layout (0x0002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Control Register Layout (0x9400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Status Register Layout (0x9401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Control Register Layout (0x9402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Status Register Layout (0x9403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register Layout (0x3400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Layout (0x3401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 0 Layout (0x4400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 0 Layout (0x4401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 0 Layout (0x4402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 1 Layout (0x4403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 1 Layout (0x4404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 1 Layout (0x4405) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 25 30 32 33 34 36 37 39 41 42 44 46 48 49 50 50 51 52 53 54 54 55 64 66 67 69 70 71 72 72 74 74 75 76 76 77 x SPRS206B SPRS206B December 2002 ­ Revised June 2003 Figures Figure Page 3­38 3­39 3­40 3­41 3­42 3­43 3­44 3­45 3­46 3­47 3­48 3­49 3­50 Parallel GPIO Enable Register 2 Layout (0x4406) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 2 Layout (0x4407) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 2 Layout (0x4408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register Layout (0x8800) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Configuration Register Layout (0x0100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Bus Error Register Layout (0x0102) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Configuration Register Layout (0x0200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Bus Error Register Layout (0x0202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPORT Bus Error Register Layout (0x0302) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register Layout (0x07FD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Out Control Register Layout (0x9000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFR0, IER0, DBIFR0, and DBIER0 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFR1, IER1, DBIFR1, and DBIER1 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 78 79 81 83 84 85 86 87 88 89 106 107 6­1 6­2 6­3 6­4 6­5 6­6 6­7 6­8 6­9 6­10 6­11 6­12 6­13 6­14 6­15 6­16 6­17 6­18 6­19 6­20 6­21 6­22 6­23 6­24 6­25 6­26 6­27 6­28 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass Mode Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Multiply-by-N Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKIN Timing for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKOUT1 Timing for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKOUT2 Timing for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Read Timing (With Read Latency = 2) . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Write Timing (With Write Latency = 0) . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Write Timing (With Write Latency = 1) . . . . . . . . . . . . . . . . . SDRAM Read Command (CAS Latency 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM ACTV Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DEAC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM REFR Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM MRS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input/Output (GPIOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings When Configured as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings When Configured as Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 114 115 116 116 117 119 120 122 123 124 125 126 126 127 127 128 128 129 130 131 132 132 133 134 135 135 138 December 2002 ­ Revised June 2003 SPRS206B SPRS206B xi Figures Figure Page 6­29 6­30 6­31 6­32 6­33 6­34 6­35 6­36 6­37 6­38 6­39 6­40 6­41 6­42 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Read Timings Using HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Read Timings With HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Write Timings Using HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Write Timings With HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 139 141 142 143 144 146 147 148 149 149 150 151 152 7­1 7­2 TMS320VC5501 TMS320VC5501 176-Ball MicroStar BGA Plastic Ball Grid Array Package . . . . . . . . . . . . . . . . . . . TMS320VC5501 TMS320VC5501 176-Pin Low-Profile Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 154 xii SPRS206B SPRS206B December 2002 ­ Revised June 2003 Tables List of Tables Table Page 2­1 2­2 2­3 176-Terminal GGW Ball Grid Array Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 7 3­1 3­2 3­3 3­4 3­5 3­6 3­7 3­8 3­9 3­10 3­11 3­12 3­13 3­14 3­15 3­16 3­17 3­18 3­19 3­20 3­21 3­22 3­23 3­24 3­25 3­26 3­27 3­28 3­29 3­30 3­31 3­32 3­33 3­34 3­35 3­36 3­37 3­38 3­39 3­40 3­41 3­42 On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Configuration Selection Via the BOOTM[2:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5501 TMS320VC5501 Routing of Parallel Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5501 TMS320VC5501 Routing of Host Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control/Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 0 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 2 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider3 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Divider1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Wakeup Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT3 Select Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Number of Reference Clock Cycles Needed Until Program Flow Begins . . . . . . . . . . . . . . . . . . . . . Peripheral Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Domain Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5501 TMS320VC5501 PGPIO Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 26 28 29 31 34 40 46 47 48 49 50 51 51 52 53 54 55 55 56 60 63 64 65 66 67 69 70 71 72 72 73 74 74 75 76 76 77 78 78 79 December 2002 ­ Revised June 2003 SPRS206B SPRS206B xiii Tables Table Page 3­43 3­44 3­45 3­46 3­47 3­48 3­49 3­50 3­51 3­52 3­53 3­54 3­55 3­56 3­57 3­58 3­59 3­60 3­61 3­62 3­63 3­64 3­65 3­66 3­67 3­68 3­69 3­70 3­71 3­72 3­73 Pins With Pullups, Pulldowns, and Bus Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Addresses Under Scope of XPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Out Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Bus Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I 2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 81 82 83 84 85 86 87 88 89 90 92 93 94 97 97 97 97 99 100 101 101 102 102 103 103 103 103 104 104 105 6­1 6­2 6­3 6­4 6­5 6­6 6­7 6­8 6­9 6­10 6­11 6­12 6­13 6­14 6­15 Thermal Resistance Characteristics (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Characteristics (Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKIN in Bypass Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT in Bypass Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKIN in Lock Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT in Lock Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Switching Characteristics for ECLKOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Cycle Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous DRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous DRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 112 114 114 115 115 116 116 117 118 118 121 121 125 125 xiv SPRS206B SPRS206B December 2002 ­ Revised June 2003 Tables Table 6­16 6­17 6­18 6­19 6­20 6­21 6­22 6­23 6­24 6­25 6­26 6­27 6­28 6­29 6­30 6­31 6­32 6­33 6­34 6­35 6­36 6­37 6­38 6­39 6­40 6­41 6­42 6­43 6­44 Page EMIF HOLD/HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF HOLD/HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt and Interrupt Acknowledge Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt and Interrupt Acknowledge Switching Characteristics . . . . . . . . . . . . . . . . . . . . . XF Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins Configured as Inputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . HPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (SDA and SCL) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (SDA and SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . December 2002 ­ Revised June 2003 SPRS206B SPRS206B 130 130 131 131 132 132 133 134 134 135 135 136 137 139 139 140 140 142 142 143 143 144 144 145 145 150 151 152 152 xv Features TMS320VC5501 TMS320VC5501 Features D High-Performance, Low-Power, Fixed-Point D D D D D D TMS320C55x Digital Signal Processor (DSP) ­ 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate ­ 16K-Byte Instruction Cache (I-Cache) ­ One/Two Instructions Executed per Cycle ­ Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)] ­ Two Arithmetic/Logic Units (ALUs) ­ One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses Instruction Cache (16K Bytes) 16K x 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (32K Bytes) 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes) 8M × 16-Bit Maximum Addressable External Memory Space 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to: ­ Asynchronous Static RAM (SRAM) ­ Asynchronous EPROM ­ Synchronous DRAM (SDRAM) ­ Synchronous Burst RAM (SBRAM) Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values D Programmable Low-Power Control of Six D D D D D D Device Functional Domains On-Chip Peripherals ­ Six-Channel Direct Memory Access (DMA) Controller ­ Two Multichannel Buffered Serial Ports (McBSPs) ­ Programmable Analog Phase-Locked Loop (APLL) Clock Generator ­ General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF) ­ 8-Bit Parallel Host-Port Interface (HPI) ­ Four Timers ­ Two 64-Bit General-Purpose Timers ­ 64-Bit Programmable Watchdog Timer ­ 64-Bit DSP/BIOS Counter ­ Inter-Integrated Circuit (I2C) Interface ­ Universal Asynchronous Receiver/ Transmitter (UART) On-Chip Scan-Based Emulation Logic IEEE Std 1149.1 (JTAG) Boundary Scan Logic Packages: ­ 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix) ­ 176-Terminal MicroStar BGA (Ball Grid Array) (GGW Suffix) 3.3-V I/O Supply Voltage 1.26-V Core Supply Voltage PRODUCT PREVIEW 1 TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. December 2002 ­ Revised June 2003 SPRS206B SPRS206B 1 Introduction 2 Introduction This section describes the main features of the TMS320VC5501 TMS320VC5501 and gives a brief description of the device. NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP Functional Overview (literature number SPRU312 SPRU312) and the TMS320C55x DSP CPU Reference Guide (literature number SPRU371 SPRU371). 2.1 Description The TMS320VC5501 TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity. PRODUCT PREVIEW The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5501 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Two full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is an 8-bit parallel interface used to provide host processor access to 16K words of internal memory on the 5501. The HPI operates in multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included. The 5501 is supported by the industry's award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX, XDS510 XDS510 emulation device drivers, and evaluation modules. The 5501 is also supported by the C55x DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries. C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 XDS510 are trademarks of Texas Instruments. 2 SPRS206B SPRS206B December 2002 ­ Revised June 2003 Introduction 2.2 Pin Assignments 2.2.1 Ball Grid Array (GGW) Figure 2­1 illustrates the ball locations for the 176-pin ball grid array (BGA) package and Table 2­1 lists the signal names and terminal numbers. 1 3 2 5 4 7 6 9 8 11 10 13 12 15 14 PRODUCT PREVIEW U T R P N M L K J H G F E D C B A 17 16 Figure 2­1. 176-Terminal GGW Ball Grid Array (Bottom View) December 2002 ­ Revised June 2003 SPRS206B SPRS206B 3 Introduction Table 2­1. 176-Terminal GGW Ball Grid Array Ball Assignments BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME B1 GPIO6 U2 HCNTL1 T17 A19 A16 D16 C2 GPIO4 T3 HCNTL0 R16 A18 B15 D15 C1 GPIO2 U3 R17 D14 GPIO1 R4 P15 VSS A17 A15 D3 VSS HR/W C14 D13 D2 GPIO0 T4 HDS2 P16 A16 B14 D12 D1 TIM1 U4 P17 DVDD A14 D11 E3 TIM0 R5 CVDD HDS1 N15 A15 C13 D10 E2 INT0 T5 HRDY N16 A14 B13 D9 E1 CVDD U5 N17 DVDD INT1 R6 M15 VSS A13 A13 F3 DVDD CLKOUT C12 D8 INT2 T6 XF M16 A12 B12 D7 F1 DVDD U6 CVDD A12 INT3 P7 VSS C15 M17 G4 L14 A11 D11 VSS D6 G3 NMI/WDTOUT R7 C14 L15 A10 C11 D5 G2 IACK T7 HINT L16 A9 B11 D4 G1 PRODUCT PREVIEW F2 VSS CLKR0 U7 PVDD PSENSE L17 A8 A11 CVDD K17 DVDD A10 D3 H1 U8 H4 DR0 P8 X1 K14 A7 D10 D2 H3 FSR0 R8 X2/CLKIN K15 A6 C10 D1 H2 CLKX0 T8 EMIFCLKS K16 A5 B10 D0 J1 CVDD U9 P9 J14 VSS A4 A9 DX0 VSS C13 J17 J4 D9 VSS EMU1/OFF J3 FSX0 R9 C12 J15 A3 C9 EMU0 J2 CLKR1 T9 C11 J16 A2 B9 TDO K1 DR1 U10 C10 H17 CVDD A8 K2 FSR1 T10 C9 H16 D31 B8 VSS TDI K4 DX1 P10 C8 H14 D30 D8 TRST K3 CLKX1 R10 C7 H15 D29 C8 TCK L1 U11 TMS G16 VSS D28 A7 T11 VSS ECLKIN G17 L2 VSS FSX1 B7 RESET L3 TEST R11 ECLKOUT2 G15 D27 C7 HPIENA L4 NC P11 ECLKOUT1 G14 D26 D7 HD7 M1 CVDD U12 F17 CVDD A6 CVDD M2 RX T12 CVDD C6 F16 D25 B6 HD6 M3 GPIO5 R12 C5 F15 D24 C6 HD5 N1 DVDD U13 E17 DVDD A5 DVDD N2 TX T13 DVDD C4 E16 D23 B5 HD4 N3 GPIO3 R13 C3 E15 D22 C5 HD3 P1 VSS SCL U14 D21 A4 CVDD T14 VSS C2 D17 P2 D16 D20 B4 HD2 P3 SDA R14 C1 D15 D19 C4 HD1 R1 HC1 U15 C0 C17 HC0 T15 A21 C16 VSS D18 A3 R2 B3 VSS HD0 T1 HCS U16 A20 B17 D17 A2 GPIO7 CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD . PSENSE must be connected to ground. NC indicates "no connect". 4 SPRS206B SPRS206B December 2002 ­ Revised June 2003 Introduction 2.2.2 Low-Profile Quad Flatpack (PGF) Figure 2­2 illustrates the pin locations for the 176-pin low-profile quad flatpack (LQFP) and Table 2­2 provides a numerical list (by pin number) of the pin assignments. 132 89 88 176 45 1 PRODUCT PREVIEW 133 44 Figure 2­2. 176-Pin PGF Low-Profile Quad Flatpack (Top View) December 2002 ­ Revised June 2003 SPRS206B SPRS206B 5 Introduction Table 2­2. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME 1 GPIO6 45 HCNTL1 89 A19 133 D16 2 GPIO4 46 HCNTL0 90 A18 134 D15 3 GPIO2 47 91 D14 GPIO1 48 92 VSS A17 135 4 VSS HR/W 136 D13 5 GPIO0 49 HDS2 93 A16 137 D12 6 TIM1 50 94 DVDD 138 D11 7 TIM0 51 CVDD HDS1 95 A15 139 D10 8 INT0 52 HRDY 96 A14 140 D9 9 CVDD 53 97 DVDD INT1 54 VSS A13 141 10 DVDD CLKOUT 142 D8 98 INT2 55 XF 99 A12 143 D7 DVDD 56 CVDD 144 INT3 57 VSS C15 100 13 101 A11 145 VSS D6 14 NMI/WDTOUT 58 C14 102 A10 146 D5 15 IACK 59 HINT 103 A9 147 D4 16 VSS CLKR0 60 PVDD PSENSE 104 A8 148 CVDD 105 DVDD 149 D3 18 DR0 62 X1 106 A7 150 D2 19 FSR0 63 X2/CLKIN 107 A6 151 D1 20 CLKX0 64 EMIFCLKS 108 A5 152 D0 21 CVDD 65 66 110 VSS A4 153 DX0 VSS C13 109 22 154 VSS EMU1/OFF 23 FSX0 67 C12 111 A3 155 EMU0 24 CLKR1 68 C11 112 A2 156 TDO 25 DR1 69 C10 113 CVDD 157 26 FSR1 70 C9 114 D31 158 VSS TDI 27 DX1 71 C8 115 D30 159 TRST 28 CLKX1 72 C7 116 D29 160 TCK 29 VSS FSX1 73 TMS 118 VSS D28 161 74 VSS ECLKIN 117 30 162 RESET 31 TEST 75 ECLKOUT2 119 D27 163 HPIENA 32 NC 76 ECLKOUT1 120 D26 164 HD7 33 CVDD 77 CVDD 165 CVDD RX 78 CVDD C6 121 34 122 D25 166 HD6 35 GPIO5 79 C5 123 D24 167 HD5 36 DVDD 80 DVDD 168 DVDD TX 81 DVDD C4 124 37 125 D23 169 HD4 38 GPIO3 82 C3 126 D22 170 HD3 39 VSS SCL 83 D21 171 CVDD 84 VSS C2 127 40 128 D20 172 HD2 41 SDA 85 C1 129 D19 173 HD1 42 HC1 86 C0 130 HC0 87 A21 131 VSS D18 174 43 175 VSS HD0 44 PRODUCT PREVIEW 11 12 HCS 88 A20 132 D17 176 GPIO7 17 61 CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD . PSENSE must be connected to ground. NC indicates "no connect". 6 SPRS206B SPRS206B December 2002 ­ Revised June 2003 Introduction 2.3 Signal Descriptions Table 2­3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2, Pin Assignments, for exact pin locations based on package type. Table 2­3. Signal Descriptions Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port ­ Address Bus I/O/Z C, D, F, G, H, M PGPIO[3:0] I/O/Z Parallel general-purpose I/O. PGPIO[3:0] is selected if GPIO6 is low during reset. The PGPIO[3:0] signals are configured as inputs during and after reset. EMIF.A[21:18] O/Z EMIF address bus. EMIF.A[21:18] is selected if GPIO6 is high during reset. The EMIF.A[21:18] signals are in a high-impedance state during reset and are configured as outputs after reset with an output value of 0. I/O/Z The A[17:2] pins of the Parallel Port serve one of two functions: external memory interface (EMIF) address bus signals EMIF.A[17:2] or reserved pins. The function of the A[17:2] pins is determined by the state of the GPIO6 pin during reset. The A[17:2] pins are reserved if GPIO6 is low during reset. The A[17:2] pins are set to EMIF.A[17:2] if GPIO6 is high during reset. The function of the A[17:2] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The A[17:2] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the address bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). A[17:2] C, D, F, M Reserved EMIF.A[17:2] I O/Z Reserved pins. These pins are reserved when GPIO6 is low during reset. EMIF address bus. EMIF.A[17:2] is selected when GPIO6 is high during reset. The EMIF.A[17:2] signals are in a high-impedance state during reset and are set to outputs after reset with an output value of 0. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input D ­ Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E ­ Pin is high impedance in HOLD mode (due to HOLD pin). F ­ Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G ­ Pin can be configured as a general-purpose input. H ­ PIn can be configured as a general-purpose output. J ­ Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K ­ Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L ­ Fail-safe pin M ­ Pin is in high-impedance during reset (RESET pin is low) December 2002 ­ Revised June 2003 SPRS206B SPRS206B 7 PRODUCT PREVIEW A[21:18] The A[21:18] pins of the Parallel Port serve one of two functions: parallel general-purpose input/output (PGPIO) signals PGPIO[3:0] or external memory interface (EMIF) address bus signals EMIF.A[21:18]. The function of the A[21:18] pins is determined by the state of the GPIO6 pin during reset. The A[21:18] pins are set to PGPIO[3:0] if GPIO6 is low during reset. The A[21:18] pins are set to EMIF.A[21:18] if GPIO6 is high during reset. The function of the A[21:18] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The A[21:18] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the address bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). Introduction Table 2­3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port ­ Data Bus D[31:16] I/O/Z C, D, F, G, H, M The D[31:16] pins of the Parallel Port serve one of two functions: parallel general-purpose input/output (PGPIO) signals PGPIO[19:4] or external memory interface (EMIF) data bus signals EMIF.D[31:16]. The function of the D[31:16] pins is determined by the state of the GPIO6 pin during reset. The D[31:16] pins are set to PGPIO[19:4] if GPIO6 is low during reset. The D[31:16] pins are set to EMIF.D[31:16] if GPIO6 is high during reset. The function of the D[31:16] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The D[31:16] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the data bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). I/O/Z Parallel general-purpose I/O. PGPIO[19:4] is selected when GPIO6 is low during reset. The PGPIO[19:4] signals are configured as inputs during and after reset. EMIF.D[31:16] PRODUCT PREVIEW PGPIO[19:4] I/O/Z EMIF data bus. EMIF.D[31:16] is selected when GPIO6 is high during reset. The EMIF.D[31:16] signals are set as inputs during and after reset. D[15:0] I/O/Z C, D, F, M The D[15:0] pins of the Parallel Port serve one of two functions: external memory interface (EMIF) data bus signals EMIF.D[15:0] or reserved pins. The function of the D[15:0] pins is determined by the state of the GPIO6 pin during reset. The D[15:0] pins are reserved if GPIO6 is low during reset. The D[15:0] pins are set to EMIF.D[15:0] if GPIO6 is high during reset. The function of the D[15:0] pins will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The D[15:0] bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the bus goes into a high-impedance state, the bus holders keep the data bus at the logic level that was most recently driven. The bus holders are enabled at reset and can be enabled/disabled through the External Bus Control Register (XBCR). Reserved I/O/Z Reserved pins. These pins are reserved when GPIO6 is low during reset. EMIF.D[15:0] I/O/Z EMIF data bus. EMIF.D[15:0] is selected when GPIO6 is high during reset. The EMIF.D[15:0] signals are set as inputs during and after reset. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input D ­ Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E ­ Pin is high impedance in HOLD mode (due to HOLD pin). F ­ Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G ­ Pin can be configured as a general-purpose input. H ­ PIn can be configured as a general-purpose output. J ­ Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K ­ Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L ­ Fail-safe pin M ­ Pin is in high-impedance during reset (RESET pin is low) 8 SPRS206B SPRS206B December 2002 ­ Revised June 2003 Introduction Table 2­3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port ­ Control Pins I/O/Z PGPIO20 PGPIO20 I/O/Z C, D, F, G, H G H, M Parallel general-purpose I/O. PGPIO20 PGPIO20 is selected when GPIO6 is low during reset. The PGPIO20 PGPIO20 signal is configured as an input during and after reset. C1 PGPIO21 PGPIO21 EMIF.AOE/SOE/ SDRAS O/Z I/O/Z EMIF.ARE/SADS/ SDCAS/SRE EMIF control pin. EMIF.ARE/SADS/SDCAS/SRE is selected when GPIO6 is high during reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used by the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and synchronous read-enable (EMIF.SRE) (selected by RENEN in the CE Secondary Control Register 1). The C1 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO21 PGPIO21 or external memory interface control signal EMIF.AOE/SOE/SDRAS. The function of the C1 pin is determined by the state of the GPIO6 pin during reset. The C1 pin is set to PGPIO21 PGPIO21 if GPIO6 is low during reset. The C1 pin is set to EMIF.AOE/SOE/SDRAS if GPIO6 is high during reset. The function of the C1 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). I/O/Z O/Z C, D, F, G, H, M Parallel general-purpose I/O. PGPIO21 PGPIO21 is selected when GPIO6 is low during reset. The PGPIO21 PGPIO21 signal is configured as an input during and after reset. EMIF control pin. EMIF.AOE/SOE/SDRAS is selected when GPIO6 is high during reset. The EMIF.AOE/SOE/SDRAS signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.AOE/SOE/SDRAS signal serves three different functions when used by the EMIF: asynchronous memory output-enable (EMIF.AOE), synchronous memory output-enable (EMIF.SOE), and SDRAM row-address strobe (EMIF.SDRAS). I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input D ­ Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E ­ Pin is high impedance in HOLD mode (due to HOLD pin). F ­ Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G ­ Pin can be configured as a general-purpose input. H ­ PIn can be configured as a general-purpose output. J ­ Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K ­ Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L ­ Fail-safe pin M ­ Pin is in high-impedance during reset (RESET pin is low) December 2002 ­ Revised June 2003 SPRS206B SPRS206B 9 PRODUCT PREVIEW C0 The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO20 PGPIO20 or external memory interface control signal EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the state of the GPIO6 pin during reset. The C0 pin is set to PGPIO20 PGPIO20 if GPIO6 is low during reset. The C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high during reset. The function of the C0 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Introduction Table 2­3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port ­ Control Pins (Continued) C2 I/O/Z PGPIO22 PGPIO22 I/O/Z C, D, F, G, H, M Parallel general-purpose I/O. PGPIO22 PGPIO22 is selected when GPIO6 is low during reset. The PGPIO22 PGPIO22 signal is configured as an input during and after reset. C3 PGPIO23 PGPIO23 O/Z EMIF control pin. EMIF.AWE/SWE/SDWE is selected when GPIO6 is high during reset. The EMIF.AWE/SWE/SDWE signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.AWE/SWE/SDWE signal serves three different functions when used by the EMIF: asynchronous memory write-enable (EMIF.AWE), synchronous memory write-enable (EMIF.SWE), and SDRAM write-enable (EMIF.SDWE). I/O/Z EMIF.AWE/ SWE/SDWE PRODUCT PREVIEW The C2 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO22 PGPIO22 or external memory interface control signal EMIF.AWE/SWE/SDWE. The function of the C2 pin is determined by the state of the GPIO6 pin during reset. The C2 pin is set to PGPIO22 PGPIO22 if GPIO6 is low during reset. The C2 pin is set to EMIF.AWE/SWE/SDWE if GPIO6 is high during reset. The function of the C2 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The C3 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO23 PGPIO23 or external memory interface control signal EMIF.ARDY. The function of the C3 pin is determined by the state of the GPIO6 pin during reset. The C3 pin is set to PGPIO23 PGPIO23 if GPIO6 is low during reset. The C3 pin is set to EMIF.ARDY if GPIO6 is high during reset. The function of the C3 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). I/O/Z D, F, G, H, J Parallel general-purpose I/O. PGPIO23 PGPIO23 is selected when GPIO6 is low during reset. The PGPIO23 PGPIO23 signal is configured as an input during and after reset. C4 I I/O/Z EMIF.ARDY EMIF data ready pin. EMIF.ARDY is selected when GPIO6 is high during reset. The EMIF.ARDY signal indicates that an external device is ready for a bus transaction to be completed. If the device is not ready (EMIF.ARDY is low), the processor extends the memory access by one cycle and checks EMIF.ARDY again. An internal pullup is included to disable this feature if not used. The internal pullup can be disabled through the External Bus Control Register (XBCR). The C4 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO24 PGPIO24 or external memory interface control signal EMIF.CE0. The function of the C4 pin is determined by the state of the GPIO6 pin during reset. The C4 pin is set to PGPIO24 PGPIO24 if GPIO6 is low during reset. The C4 pin is set to EMIF.CE0 if GPIO6 is high during reset. The function of the C4 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). PGPIO24 PGPIO24 I/O/Z EMIF.CE0 O/Z C, D, F, , , , G, H, M Parallel general-purpose I/O. PGPIO24 PGPIO24 is selected when GPIO6 is low during reset. The PGPIO24 PGPIO24 signal is configured as an input during and after reset. EMIF chip-select for memory space CE0. EMIF.CE0 is selected when GPIO6 is high during reset. The EMIF.CE0 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input D ­ Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E ­ Pin is high impedance in HOLD mode (due to HOLD pin). F ­ Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G ­ Pin can be configured as a general-purpose input. H ­ PIn can be configured as a general-purpose output. J ­ Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K ­ Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L ­ Fail-safe pin M ­ Pin is in high-impedance during reset (RESET pin is low) 10 SPRS206B SPRS206B December 2002 ­ Revised June 2003 Introduction Table 2­3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port ­ Control Pins (Continued) C5 I/O/Z C, D, F, G, H, M The C5 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO25 PGPIO25 or external memory interface control signal EMIF.CE1. The function of the C5 pin is determined by the state of the GPIO6 pin during reset. The C5 pin is set to PGPIO25 PGPIO25 if GPIO6 is low during reset. The C5 pin is set to EMIF.CE1 if GPIO6 is high during reset. The function of the C5 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO25 PGPIO25 is selected when GPIO6 is low during reset. The PGPIO25 PGPIO25 signal is configured as an input during and after reset. I/O/Z EMIF.CE1 O/Z EMIF chip-select for memory space CE1. EMIF.CE1 is selected when GPIO6 is high during reset. The EMIF.CE1 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I/O/Z The C6 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO26 PGPIO26 or external memory interface control signal EMIF.CE2. The function of the C6 pin is determined by the state of the GPIO6 pin during reset. The C6 pin is set to PGPIO26 PGPIO26 if GPIO6 is low during reset. The C6 pin is set to EMIF.CE2 if GPIO6 is high during reset. The function of the C6 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C6 C, D, F, G, H, M Parallel general-purpose I/O. PGPIO26 PGPIO26 is selected when GPIO6 is low during reset. The PGPIO26 PGPIO26 signal is configured as an input during and after reset. PGPIO26 PGPIO26 I/O/Z EMIF.CE2 O/Z EMIF chip-select for memory space CE2. EMIF.CE2 is selected when GPIO6 is high during reset. The EMIF.CE2 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I/O/Z The C7 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO27 PGPIO27 or external memory interface control signal EMIF.CE3. The function of the C7 pin is determined by the state of the GPIO6 pin during reset. The C7 pin is set to PGPIO27 PGPIO27 if GPIO6 is low during reset. The C7 pin is set to EMIF.CE3 if GPIO6 is high during reset. The function of the C7 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C7 PGPIO27 PGPIO27 I/O/Z EMIF.CE3 O/Z C, D, F, G, H, M Parallel general-purpose I/O. PGPIO27 PGPIO27 is selected when GPIO6 is low during reset. The PGPIO27 PGPIO27 signal is configured as an input during and after reset. EMIF chip-select for memory space CE3. EMIF.CE3 is selected when GPIO6 is high during reset. The EMIF.CE3 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input D ­ Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E ­ Pin is high impedance in HOLD mode (due to HOLD pin). F ­ Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G ­ Pin can be configured as a general-purpose input. H ­ PIn can be configured as a general-purpose output. J ­ Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K ­ Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L ­ Fail-safe pin M ­ Pin is in high-impedance during reset (RESET pin is low) December 2002 ­ Revised June 2003 SPRS206B SPRS206B 11 PRODUCT PREVIEW PGPIO25 PGPIO25 Introduction Table 2­3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port ­ Control Pins (Continued) C8 I/O/Z C, D, F, G, H, M The C8 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO28 PGPIO28 or external memory interface control signal EMIF.BE0. The function of the C8 pin is determined by the state of the GPIO6 pin during reset. The C8 pin is set to PGPIO28 PGPIO28 if GPIO6 is low during reset. The C8 pin is set to EMIF.BE0 if GPIO6 is high during reset. The function of the C8 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO28 PGPIO28 is selected when GPIO6 is low during reset. The PGPIO28 PGPIO28 signal is configured as an input during and after reset. PGPIO28 PGPIO28 I/O/Z EMIF.BE0 O/Z EMIF byte-enable 0 control. EMIF.BE0 is selected when GPIO6 is high during reset. The EMIF.BE0 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I/O/Z The C9 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO29 PGPIO29 or external memory interface control signal EMIF.BE1. The function of the C9 pin is determined by the state of the GPIO6 pin during reset. The C9 pin is set to PGPIO29 PGPIO29 if GPIO6 is low during reset. The C9 pin is set to EMIF.BE1 if GPIO6 is high during reset. The function of the C9 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). PRODUCT PREVIEW C9 C, D, F, G, H, M Parallel general-purpose I/O. PGPIO29 PGPIO29 is selected when GPIO6 is low during reset. The PGPIO29 PGPIO29 signal is configured as an input during and after reset. PGPIO29 PGPIO29 I/O/Z EMIF.BE1 O/Z EMIF byte-enable 1 control. EMIF.BE1 is selected when GPIO6 is high during reset. The EMIF.BE1 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I/O/Z The C10 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO30 PGPIO30 or external memory interface control signal EMIF.BE2. The function of the C10 pin is determined by the state of the GPIO6 pin during reset. The C10 pin is set to PGPIO30 PGPIO30 if GPIO6 is low during reset. The C10 pin is set to EMIF.BE2 if GPIO6 is high during reset. The function of the C10 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C10 PGPIO30 PGPIO30 I/O/Z EMIF.BE2 O/Z C, D, F, G, H, M Parallel general-purpose I/O. PGPIO30 PGPIO30 is selected when GPIO6 is low during reset. The PGPIO30 PGPIO30 signal is configured as an input during and after reset. EMIF byte-enable 2 control. EMIF.BE2 is selected when GPIO6 is high during reset. The EMIF.BE2 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input D ­ Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E ­ Pin is high impedance in HOLD mode (due to HOLD pin). F ­ Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G ­ Pin can be configured as a general-purpose input. H ­ PIn can be configured as a general-purpose output. J ­ Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K ­ Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L ­ Fail-safe pin M ­ Pin is in high-impedance during reset (RESET pin is low) 12 SPRS206B SPRS206B December 2002 ­ Revised June 2003 Introduction Table 2­3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port ­ Control Pins (Continued) C11 I/O/Z C, D, F, G, H, M The C11 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO31 PGPIO31 or external memory interface control signal EMIF.BE3. The function of the C11 pin is determined by the state of the GPIO6 pin during reset. The C11 pin is set to PGPIO31 PGPIO31 if GPIO6 is low during reset. The C11 pin is set to EMIF.BE3 if GPIO6 is high during reset. The function of the C11 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). Parallel general-purpose I/O. PGPIO31 PGPIO31 is selected when GPIO6 is low during reset. The PGPIO31 PGPIO31 signal is configured as an input during and after reset. I/O/Z EMIF.BE3 O/Z EMIF byte-enable 3 control. EMIF.BE3 is selected when GPIO6 is high during reset. The EMIF.BE3 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I/O/Z The C12 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO32 PGPIO32 or external memory interface control signal EMIF.SDCKE. The function of the C12 pin is determined by the state of the GPIO6 pin during reset. The C12 pin is set to PGPIO32 PGPIO32 if GPIO6 is low during reset. The C12 pin is set to EMIF.SDCKE if GPIO6 is high during reset. The function of the C12 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C12 C, D, F, G, H, M Parallel general-purpose I/O. PGPIO32 PGPIO32 is selected when GPIO6 is low during reset. The PGPIO32 PGPIO32 signal is configured as an input during and after reset. PGPIO32 PGPIO32 I/O/Z EMIF.SDCKE O/Z EMIF SDRAM clock-enable. EMIF.SDCKE is selected when GPIO6 is high during reset. The EMIF.SDCKE signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. I/O/Z The C13 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO33 PGPIO33 or external memory interface control signal EMIF.SOE3. The function of the C13 pin is determined by the state of the GPIO6 pin during reset. The C13 pin is set to PGPIO33 PGPIO33 if GPIO6 is low during reset. The C13 pin is set to EMIF.SOE3 if GPIO6 is high during reset. The function of the C13 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). C13 PGPIO33 PGPIO33 I/O/Z EMIF.SOE3 O/Z C D F C, D, F, G, H, M Parallel general-purpose I/O. PGPIO33 PGPIO33 is selected when GPIO6 is low during reset. The PGPIO33 PGPIO33 signal is configured as an input during and after reset. EMIF synchronous memory output-enable for CE3. EMIF.SOE3 is selected when GPIO6 is high during reset. The EMIF.SOE3 signal is in a high-impedance state during reset and is set to output after reset with an output value of 1. The EMIF.SOE3 signal is intended for glueless FIFO interface. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input D ­ Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E ­ Pin is high impedance in HOLD mode (due to HOLD pin). F ­ Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G ­ Pin can be configured as a general-purpose input. H ­ PIn can be configured as a general-purpose output. J ­ Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K ­ Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L ­ Fail-safe pin M ­ Pin is in high-impedance during reset (RESET pin is low) December 2002 ­ Revised June 2003 SPRS206B SPRS206B 13 PRODUCT PREVIEW PGPIO31 PGPIO31 Introduction Table 2­3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Parallel Port ­ Control Pins (Continued) C14 I/O/Z PGPIO34 PGPIO34 Parallel general-purpose I/O. PGPIO34 PGPIO34 is selected when GPIO6 is low during reset. The PGPIO34 PGPIO34 signal is configured as an input during and after reset. C15 PGPIO35 PGPIO35 EMIF.HOLDA I EMIF hold request. EMIF.HOLD is selected when GPIO6 is high during reset. EMIF.HOLD is asserted by an external host to request control of the address, data, and control signals. I/O/Z EMIF.HOLD PRODUCT PREVIEW I/O/Z F, G, H, J, M The C14 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO34 PGPIO34 or external memory interface control signal EMIF.HOLD. The function of the C14 pin is determined by the state of the GPIO6 pin during reset. The C14 pin is set to PGPIO34 PGPIO34 if GPIO6 is low during reset. The C14 pin is set to EMIF.HOLD if GPIO6 is high during reset. The function of the C14 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). The C15 pin of the Parallel Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO35 PGPIO35 or external memory interface control signal EMIF.HOLDA. The function of the C15 pin is determined by the state of the GPIO6 pin during reset. The C15 pin is set to PGPIO35 PGPIO35 if GPIO6 is low during reset. The C15 pin is set to EMIF.HOLDA if GPIO6 is high during reset. The function of the C15 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). I/O/Z C, D, F, C D F G, H, M Parallel general-purpose I/O. PGPIO35 PGPIO35 is selected when GPIO6 is low during reset. The PGPIO35 PGPIO35 signal is configured as an input during and after reset. O/Z EMIF hold acknowledge. EMIF.HOLDA is selected when GPIO6 is high during reset. EMIF.HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state and that the EMIF address, data, and control signals are in a high-impedance state, allowing the external memory interface to be accessed by other devices. I C, L External EMIF input clock. ECLKIN is selected as the input clock to the EMIF when EMIFCLKS is high during reset. O/Z F, M EMIF output clock. ECLKOUT1 drives the EMIF input clock by default. ECLKOUT1 can be held low or set to a high-impedance state through the EMIF Global Control Register 1 (EGCR1). F EMIF output clock. ECLKOUT2 can be enabled to drive the EMIF input clock divided by a factor of 1, 2, or 4 through the EMIF Global Control Register 2 (EGCR2). ECLKOUT2 can be held low or set to a high-impedance state through the EGCR1 register. This pin is in a high-impedance state by default. C, L EMIF input clock source select. The clock source for the EMIF is determined by the state of the EMIFCLKS pin during reset. The EMIF uses an internal clock (SYSCLK3) if EMIFCLKS is low during reset. ECLKIN is used as the clock source if EMIFCLKS is high during reset. EMIF ­ Clock Pins ECLKIN ECLKOUT1 ECLKOUT2 EMIFCLKS O/Z I I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input D ­ Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E ­ Pin is high impedance in HOLD mode (due to HOLD pin). F ­ Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G ­ Pin can be configured as a general-purpose input. H ­ PIn can be configured as a general-purpose output. J ­ Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K ­ Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L ­ Fail-safe pin M ­ Pin is in high-impedance during reset (RESET pin is low) 14 SPRS206B SPRS206B December 2002 ­ Revised June 2003 Introduction Table 2­3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Function Host Port ­ Data Bus I/O/Z C, D, F, G, H, M PGPIO[43:36] HPI.HD[7:0] I/O/Z Parallel general-purpose I/O. PGPIO[43:36] is selected when GPIO6 is low during reset. The PGPIO[43:36] signals are configured as inputs during and after reset. O/Z Host data bus. HPI.HD[7:0] is selected when GPIO6 is high during reset. The HPI.HD[7:0] signals are configured as inputs during and after reset. The HPI will operate in multiplexed mode when GPIO6 is high during reset. In multiplexed mode, an 8-bit data bus (HPI.HD[7:0]) carries both address and data. Each host cycle on the bus consists of two consecutive 8-bit transfers. Host Port ­ Control Pins HC0 The HC0 pin of the Host Port serves one of two functions: parallel general-purpose input/output (PGPIO) signal PGPIO44 PGPIO44 or host-port interface (HPI) signal HPI.HAS. The function of the HC0 pin is determined by the state of the GPIO6 pin during reset. The HC0 pin is set to PGPIO44 PGPIO44 if GPIO6 is low during reset. The HC0 pin is set to HPI.HAS if GPIO6 is high during reset. The function of the HC0 pin will be set once the device is taken out of reset (RESET pin transitions from a low to high state). I/O/Z PGPIO44 PGPIO44 HPI.HAS I/O/Z I C, F, G, H, J, M Parallel general-purpose I/O. PGPIO44 PGPIO44 is selected when GPIO6 is low during reset. The PGPIO44 PGPIO44 signal is configured as an input during and after reset. Host address strobe. HPI.HAS is selected when GPIO6 is high during reset. The HPI.HAS signal is configured as an input during and after reset. Hosts with multiplexed address and data pins may require HPI.HAS to latch the address in the HPIA register. HPI.HAS is only available when the HPI is operating in multiplexed mode. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A ­ Internal pullup [always enabled] B ­ Internal pulldown [always enabled] C ­ Hysteresis input