TMS320VC5402A SPRS015E SPRS015D HPI8/16 HPI16 HPI-16 SPRZ018 TMS320C5000 C5000 - Datasheet Archive

 

Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS015E September 2001 ­ Revised January 2005 PRODUCTION

 

TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS015E SPRS015E September 2001 ­ Revised January 2005 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Revision History This data sheet revision history highlights the technical changes made to the SPRS015D SPRS015D device-specific data sheet to make it an SPRS015E SPRS015E revision. Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date with the following corrections. SECTION Table 2-2 ADDITIONS/CHANGES/DELETIONS Added Note 5. Section 5.2 Changed IOH from -2 to -8 mA and IOL from 2 to 8 mA. Changed Note 2 to read "These output current limits are used for the test conditions on VOL and VOH, except where noted otherwise." Section 5.3 Changed test conditions for VOH from "DVDD = 2.7 V to 3.0 V, IOH = MAX" to "DVDD = 2.7 V to 3.0 V, IOH = ­ 2 mA". Table 5-1 In Note 1, changed symbol for Infinity from "" to "". Figure 5-29 Updated figure to reduce confusion caused by unnecessary information. Section 6.1 Moved the Package Thermal Resistance Characteristics to this section. Global 2 Revision History A font substitution caused some symbols to display incorrectly in the D revisions of this document. This error has been corrected and validated in the E revision including the Electrical Specifications. TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Contents Revision History . 2 1 TMS320VC5402A TMS320VC5402A DSP . 9 1.1 2 Introduction . 10 2.1 2.2 2.3 3 Features . 9 Description . Pin Assignments. 2.2.1 Terminal Assignments for the GGU Package . 2.2.2 Pin Assignments for the PGE Package . Signal Descriptions . 10 10 11 12 13 Functional Overview . 17 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 Memory . 3.1.1 Data Memory . 3.1.2 Program Memory . 3.1.3 Extended Program Memory . On-Chip ROM With Bootloader. On-Chip RAM . On-Chip Memory Security . Memory Map . 3.5.1 Relocatable Interrupt Vector Table . On-Chip Peripherals . 3.6.1 Software-Programmable Wait-State Generator . 3.6.2 Programmable Bank-Switching . 3.6.3 Bus Holders . Parallel I/O Ports . 3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16 HPI8/16) . 3.7.2 HPI Nonmultiplexed Mode. Multichannel Buffered Serial Ports (McBSPs) . Hardware Timer . Clock Generator . Enhanced External Parallel Interface (XIO2) . DMA Controller . 3.12.1 Features . 3.12.2 DMA External Access . 3.12.3 DMPREC Issue . 3.12.4 DMA Memory Map . 3.12.5 DMA Priority Level. 3.12.6 DMA Source/Destination Address Modification . 3.12.7 DMA in Autoinitialization Mode . 3.12.8 DMA Transfer Counting. 3.12.9 DMA Transfer in Doubleword Mode . 3.12.10 DMA Channel Index Registers . 3.12.11 DMA Interrupts . 3.12.12 DMA Controller Synchronization Events . General-Purpose I/O Pins . 3.13.1 McBSP Pins as General-Purpose I/O. 3.13.2 HPI Data Pins as General-Purpose I/O . Memory-Mapped Registers . McBSP Control Registers and Subaddresses . DMA Subbank Addressed Registers . Contents 17 17 18 18 18 19 19 20 21 23 23 25 26 27 27 28 29 32 32 34 38 38 38 40 41 42 42 43 43 44 44 44 45 46 46 46 47 49 50 3 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 3.17 4 4.1 4.2 5 Interrupts . Documentation Support . 53 Device and Development-Support Tool Nomenclature. 54 Specifications . 55 Absolute Maximum Ratings . Recommended Operating Conditions . Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) . 5.3.1 Test Load Circuit . 5.3.2 Timing Parameter Symbology . 5.3.3 Internal Oscillator With External Crystal. 5.3.4 Clock Options . 5.3.4.1 Divide-By-Two and Divide-By-Four Clock Options . 5.3.4.2 Multiply-By-N Clock Option (PLL Enabled) . 5.3.5 Memory and Parallel I/O Interface Timing . 5.3.5.1 Memory Read . 5.3.5.2 Memory Write . 5.3.5.3 I/O Read . 5.3.5.4 I/O Write . 5.3.6 Ready Timing for Externally Generated Wait States . 5.3.7 HOLD and HOLDA Timings. 5.3.8 Reset, BIO, Interrupt, and MP/MC Timings . 5.3.9 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . 5.3.10 External Flag (XF) and TOUT Timings . 5.3.11 Multichannel Buffered Serial Port (McBSP) Timing . 5.3.11.1 McBSP Transmit and Receive Timings . 5.3.11.2 McBSP General-Purpose I/O Timing . 5.3.11.3 McBSP as SPI Master or Slave Timing. 5.3.12 Host-Port Interface Timing. 5.3.12.1 HPI8 Mode. 5.3.12.2 HPI16 HPI16 Mode . 5.1 5.2 5.3 6 55 55 56 56 57 58 59 59 61 62 62 65 67 69 70 73 74 76 77 78 78 81 82 86 86 90 Mechanical Data . 93 6.1 4 52 Support . 53 Package Thermal Resistance Characteristics . 93 Contents TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 List of Figures 2-1 2-2 3-1 3-2 3-3 3-4 . 144-Pin PGE Low-Profile Quad Flatpack (Top View) . TMS320VC5402A TMS320VC5402A Functional Block Diagram . Program and Data Memory Map . Extended Program Memory Map . Processor Mode Status Register (PMST) . 144-Ball GGU MicroStar BGATM (Bottom View) 10 12 17 20 21 21 3-5 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] . 23 3-6 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] . 24 3-7 Bank-Switching Control Register (BSCR) [MMR Address 0029h] . 25 3-8 Host-Port Interface - Nonmultiplexed Mode 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 . HPI Memory Map . Pin Control Register (PCR) . Multichannel Control Register 1x (MCR1x) . Multichannel Control Register 2x (MCR2x) . Receive Channel Enable Registers Bit Layout for Partitions A to H . Transmit Channel Enable Registers Bit Layout for Partitions A to H. Nonconsecutive Memory Read and I/O Read Bus Sequence . Consecutive Memory Read Bus Sequence (n = 3 reads) . Memory Write and I/O Write Bus Sequence. Transfer Mode Control Register (DMMCRn) . DMA Channel Enable Control Register (DMCECTL). On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) . On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) . DMPREC Register . General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] . General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] . IFR and IMR . Tester Pin Electronics . Internal Divide-By-Two Clock Option With External Crystal . External Divide-By-Two Clock Timing . Multiply-By-One Clock Timing . Nonconsecutive Mode Memory Reads . Consecutive Mode Memory Reads . Memory Write (MSTRB = 0) . Parallel I/O Port Read (IOSTRB = 0) . Parallel I/O Port Write (IOSTRB = 0) . Memory Read With Externally Generated Wait States. Memory Write With Externally Generated Wait States . I/O Read With Externally Generated Wait States . List of Figures 28 29 30 31 31 31 32 35 36 37 39 40 41 42 43 46 46 52 56 58 60 61 63 64 66 68 69 70 71 71 5 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 5-13 I/O Write With Externally Generated Wait States . 72 5-14 HOLD and HOLDA Timings (HM = 1) . 73 5-15 Reset and BIO Timings. 74 5-16 Interrupt Timing . 75 5-17 MP/MC Timing . 75 5-18 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . 76 5-19 External Flag (XF) Timing . 77 5-20 TOUT Timing . 77 5-21 McBSP Receive Timings . 79 5-22 McBSP Transmit Timings . 80 5-23 McBSP General-Purpose I/O Timings. 81 5-24 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . 82 5-25 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . 83 5-26 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . 84 5-27 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . 85 5-28 HPI-8 Mode Timing, Using HDS to Control Accesses (HCS Always Low) . 88 5-29 HPI-8 Mode Timing, Using HCS to Control Accesses 5-30 5-31 5-32 5-33 5-34 6 . HPI-8 Mode, HINT Timing . GPIOx Timings . HPI-16 HPI-16 Mode, Nonmultiplexed Read Timings . HPI-16 HPI-16 Mode, Nonmultiplexed Write Timings . HPI-16 HPI-16 Mode, HRDY Relative to CLKOUT . List of Figures 89 89 89 91 92 92 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 List of Tables 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 . Signal Descriptions . Standard On-Chip ROM Layout . Processor Mode Status Register (PMST) Field Descriptions . Software Wait-State Register (SWWSR) Field Descriptions . Software Wait-State Control Register (SWCR) Field Descriptions . Bank-Switching Control Register (BSCR) Field Descriptions . Bus Holder Control Bits . Sample Rate Generator Clock Source Selection . Receive Channel Enable Registers for Partitions A to H Field Descriptions . Transmit Channel Enable Registers for Partitions A to H Field Descriptions . Clock Mode Settings at Reset . DMD Section of the DMMCRn Register. DMA Channel Enable Control Register (DMCECTL) Descriptions . DMA Reload Register Selection . DMA Interrupts . DMA Synchronization Events. DMA Channel Interrupt Selection . CPU Memory-Mapped Registers. Peripheral Memory-Mapped Registers for Each DSP Subsystem . McBSP Control Registers and Subaddresses. DMA Subbank Addressed Registers . Interrupt Locations and Priorities. Input Clock Frequency Characteristics . Clock Mode Pin Settings for the Divide-By-2 and Divide-By-4 Clock Options . Divide-By-2 and Divide-By-4 Clock Options Timing Requirements . Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics . Multiply-By-N Clock Option Timing Requirements . Multiply-By-N Clock Option Switching Characteristics . Memory Read Timing Requirements . Memory Read Switching Characteristics. Memory Write Switching Characteristics . I/O Read Timing Requirements . I/O Read Switching Characteristics . I/O Write Switching Characteristics . Ready Timing Requirements for Externally Generated Wait States . Ready Switching Characteristics for Externally Generated Wait States . HOLD and HOLDA Timing Requirements . HOLD and HOLDA Switching Characteristics . Terminal Assignments List of Tables 11 13 19 22 24 24 25 26 30 32 32 33 39 40 43 44 45 45 47 48 49 50 52 58 59 59 59 61 61 62 62 65 67 67 69 70 70 73 73 7 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 6-1 8 . Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics . External Flag (XF) and TOUT Switching Characteristics . McBSP Transmit and Receive Timing Requirements . McBSP Transmit and Receive Switching Characteristics . McBSP General-Purpose I/O Timing Requirements . McBSP General-Purpose I/O Switching Characteristics . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . HPI8 Mode Timing Requirements. HPI8 Mode Switching Characteristics . HPI16 HPI16 Mode Timing Requirements . HPI16 HPI16 Mode Switching Characteristics. Thermal Resistance Characteristics . Reset, BIO, Interrupt, and MP/MC Timing Requirements List of Tables 74 76 77 78 79 81 81 82 82 83 83 84 84 85 85 86 87 90 91 93 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 1 TMS320VC5402A TMS320VC5402A DSP 1.1 Features · · · · · · · · · · · · · · · Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Data Bus With a Bus Holder Feature Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space 16K x 16-Bit On-Chip RAM Composed of: ­ Two Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM 16K × 16-Bit On-Chip ROM Configured for Program Memory Enhanced External Parallel Interface (XIO2) Single-Instruction-Repeat and Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better Program and Data Management Instructions With a 32-Bit Long Word Operand Instructions With Two- or Three-Operand Reads · · · · · · · · · · · · (1) (2) Arithmetic Instructions With Parallel Store and Parallel Load Conditional Store Instructions Fast Return From Interrupt On-Chip Peripherals ­ Software-Programmable Wait-State Generator and Programmable Bank-Switching ­ On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source (1) ­ One 16-Bit Timer ­ Six-Channel Direct Memory Access (DMA) Controller ­ Three Multichannel Buffered Serial Ports (McBSPs) ­ 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16 HPI8/16) Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic (2) 144-Pin Ball Grid Array (BGA) [GGU Suffix] 144-Pin Low-Profile Quad Flatpack (LQFP)(PGE Suffix) 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS) 3.3-V I/O Supply Voltage 1.6-V Core Supply Voltage The on-chip oscillator is not available on all 5402A devices. For applicable devices, see the TMS320VC5402A TMS320VC5402A Digital Signal Processor Silicon Errata (literature number SPRZ018 SPRZ018). IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. TMS320C54x, BGA, C54x, TMS320C5000 TMS320C5000, C5000 C5000, TMS320 TMS320 are trademarks of Texas Instruments. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001­2005, Texas Instruments Incorporated TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 2 Introduction This data manual also provides a detailed description, functional overview, electrical specifications, parameter measurement information, and mechanical data about the available packaging. This section describes the main features of the TMS320VC5402A TMS320VC5402A, lists the pin assignments, and describes the function of each pin. NOTE This data manual is designed to be used in conjunction with the TMS320C54xTM DSP Functional Overview (literature number SPRU307 SPRU307). 2.1 Description The TMS320VC5402A TMS320VC5402A fixed-point, digital signal processor (DSP) (hereafter referred to as the device unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls. 2.2 Pin Assignments Figure 2-1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. Figure 2-2 provides the pin assignments for the 144-pin low-profile flatpack (LQFP) package. 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N Figure 2-1. 144-Ball GGU MicroStar BGATM (Bottom View) 10 Introduction TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 2.2.1 Terminal Assignments for the GGU Package Table 2-1 lists each signal name and BGA ball number for the 144-pin TMS320VC5402AGGU TMS320VC5402AGGU package. Table 2-1. Terminal Assignments SIGNAL QUADRANT 1 BGA BALL # SIGNAL QUADRANT 2 BGA BALL # SIGNAL QUADRANT 3 BGA BALL # SIGNAL QUADRANT 4 BGA BALL # CVSS A1 BFSX1 N13 CVSS N1 A19 A13 A22 B1 BDX1 M13 BCLKR1 N2 A20 A12 CVSS C2 DVDD L12 HCNTL0 M3 CVSS B11 DVDD C1 DVSS L13 DVSS N3 DVDD A11 A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10 HD7 D3 CLKMD2 K11 BCLKR2 L4 D7 C10 A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10 A12 D1 HPI16 HPI16 K13 BFSR2 N4 D9 A10 A13 E4 HD2 J10 BDR0 K5 D10 D9 A14 E3 TOUT J11 HCNTL1 L5 D11 C9 A15 E2 EMU0 J12 BDR2 M5 D12 B9 CVDD E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9 HAS F4 TDO H10 BCLKX2 K6 D13 D8 DVSS F3 TDI H11 CVSS L6 D14 C8 CVSS F2 TRST H12 HINT M6 D15 B8 CVDD F1 TCK H13 CVDD N6 HD5 A8 HCS G2 TMS G12 BFSX0 M7 CVDD B7 HR/W G1 CVSS G13 BFSX2 N7 CVSS A7 READY G3 CVDD G11 HRDY L7 HDS1 C7 PS G4 HPIENA G10 DVDD K7 DVSS D7 DS H1 DVSS F13 DVSS N8 HDS2 A6 IS H2 CLKOUT F12 HD0 M8 DVDD B6 R/W H3 HD3 F11 BDX0 L8 A0 C6 MSTRB H4 X1 F10 BDX2 K8 A1 D6 IOSTRB J1 X2/CLKIN E13 IACK N9 A2 A5 MSC J2 RS E12 HBIL M9 A3 B5 XF J3 D0 E11 NMI L9 HD6 C5 HOLDA J4 D1 E10 INT0 K9 A4 D5 A4 IAQ K1 D2 D13 INT1 N10 A5 HOLD K2 D3 D12 INT2 M10 A6 B4 BIO K3 D4 D11 INT3 L10 A7 C4 MP/MC L1 D5 C13 CVDD N11 A8 A3 DVDD L2 A16 C12 HD1 M11 A9 B3 CVSS L3 DVSS C11 CVSS L11 CVDD C3 BDR1 M1 A17 B13 BCLKX1 N12 A21 A2 BFSR1 M2 A18 B12 DVSS M12 DVSS B2 Introduction 11 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 2.2.2 Pin Assignments for the PGE Package 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 DVSS A21 CV DD A9 A8 A7 A6 A5 A4 HD6 A3 A2 A1 A0 DV DD HDS2 DV SS HDS1 CVSS CVDD HD5 D15 D14 D13 HD4 D12 D11 D10 D9 D8 D7 D6 DV DD CV SS A20 A19 The TMS320VC5402APGE TMS320VC5402APGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-2. 108 107 106 4 5 6 7 105 104 103 102 8 9 10 11 101 100 99 98 12 13 14 15 97 96 95 94 16 17 18 19 20 93 92 91 90 89 21 22 23 24 88 87 86 85 25 26 27 28 84 83 82 81 29 30 31 32 80 79 78 77 33 34 35 36 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 A18 A17 DVSS A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT DVSS HPIENA CVDD CVSS TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT HD2 HPI16 HPI16 CLKMD3 CLKMD2 CLKMD1 DVSS DVDD BDX1 BFSX1 CV SS BCLKR1 HCNTL0 DVSS BCLKR0 BCLKR2 BFSR0 BFSR2 BDR0 HCNTL1 BDR2 BCLKX0 BCLKX2 CVSS HINT CVDD BFSX0 BFSX2 HRDY DVDD DVSS HD0 BDX0 BDX2 IACK HBIL NMI INT0 INT1 INT2 INT3 CV DD HD1 CVSS BCLKX1 DVSS CVSS A22 CVSS DVDD A10 HD7 A11 A12 A13 A14 A15 CVDD HAS DVSS CVSS CVDD HCS HR/W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP/MC DVDD CVSS BDR1 BFSR1 A. DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. DVSS is the ground for the I/O pins while CVSS is the ground for the core CPU. The DVSS and CVSS pins can be connected to a common ground plane in a system. Figure 2-2. 144-Pin PGE Low-Profile Quad Flatpack (Top View) 12 Introduction TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 2.3 Signal Descriptions Table 2-2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact pin locations based on package type. Table 2-2. Signal Descriptions TERMINAL NAME I/O (1) DESCRIPTION DATA SIGNALS A22 (MSB) A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) I/O/Z (1) (2) D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) I/O/Z (1) (2) Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16 to A22, address external program space memory. A22-A0 A22-A0 is placed in the high-impedance state in the hold mode. A22-A0 A22-A0 also goes into the high-impedance state when OFF is low. A15-A0 A15-A0 are inputs in HPI16 HPI16 mode. These pins can be used to address internal memory via the host-port interface (HPI) when the HPI16 HPI16 pin is high. These pins also have Schmitt trigger inputs. The address bus has a bus holder feature that eliminates passive components and the power dissipation associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into a high-impedance state. Parallel data bus D15 (MSB) through D0 (LSB). D15-D0 D15-D0 is multiplexed to transfer data between the core CPU and external data/program memory or I/O devices or HPI in HPI16 HPI16 mode (when HPI16 HPI16 pin is high). D15-D0 D15-D0 is placed in the high-impedance state when not outputting data or when RS or HOLD is asserted. D15-D0 D15-D0 also goes into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs. The data bus has a bus holder feature that eliminates passive components and the power dissipation associated with them. The bus holder keeps the data bus at the previous logic level when the bus goes into the high-impedance state. The bus holders on the data bus can be enabled/disabled under software control. INITIALIZATION, INTERRUPT AND RESET OPERATIONS IACK INT0 INT1 INT2 INT3 NMI RS (1) (2) O/Z (1) (1) (1) (1) (1) (1) Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15-A0 A15-A0. IACK also goes into the high-impedance state when OFF is low. I External user interrupt inputs. INT0-INT3 are maskable and are prioritized by the interrupt mask register (IMR) and the interrupt mode bit. INT0 -INT3 can be polled and reset by way of the interrupt flag register (IFR). I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI is activated, the processor traps to the appropriate vector location. I Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers and status bits. I = Input, O = Output, Z = High-impedance, S = Supply This pin has an internal bus holder controlled by way of the BSCR register. Introduction 13 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Table 2-2. Signal Descriptions (continued) TERMINAL NAME I/O (1) DESCRIPTION I Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode that is selected at reset. I Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC instruction, and all other instructions sample BIO during the read phase of the pipeline. O/Z External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset. DS PS IS O/Z Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating to a particular external space. Active period corresponds to valid address information. DS, PS, and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance state when OFF is low. MSTRB O/Z Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. READY I Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states. R/W O/Z Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low. IOSTRB O/Z I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. MP/MC MULTIPROCESSING SIGNALS BIO (1) XF MEMORY CONTROL SIGNALS HOLD I Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the 5402A, these lines go into the high-impedance state. O/Z Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing them to be available to the external circuitry. HOLDA also goes into the high-impedance state when OFF is low. This pin is driven high during reset. MSC O/Z Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF is low. IAQ O/Z Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus and goes into the high-impedance state when OFF is low. HOLDA OSCILLATOR/TIMER SIGNALS O/Z Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the machine-cycle rate divided by 4. CLKMD1 (1) CLKMD2 (1) CLKMD3 (1) I Clock mode select signals. CLKMD1-CLKMD3 allow the selection and configuration of different clock modes such as crystal, external clock, and PLL mode. The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software. X2/CLKIN (1) I Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is revision-dependent, see Section 3.10 for additional information.) X1 O Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revisiondependent, see Section 3.10 for additional information.) CLKOUT 14 Introduction TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Table 2-2. Signal Descriptions (continued) TERMINAL NAME TOUT I/O (1) O/Z DESCRIPTION Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low. MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1), AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS BCLKR0 (1) BCLKR1 (1) BCLKR2 (1) I/O/Z Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following reset. BCLKR serves as the serial shift clock for the buffered serial port receiver. BDR0 BDR1 BDR2 I BFSR0 BFSR1 BFSR2 I/O/Z Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured as an input following reset. The BFSR pulse initiates the receive data process over BDR. BCLKX0 (1) BCLKX1 (1) BCLKX2 (1) I/O/Z Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when OFF goes low. BDX0 BDX1 BDX2 O/Z Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted, or when OFF is low. BFSX0 BFSX1 BFSX2 I/O/Z Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes into the high-impedance state when OFF is low. Serial data receive input HOST-PORT INTERFACE SIGNALS I/O/Z Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the HPI registers. These pins can also be used as general-purpose I/O pins. HD0-HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the 5402A, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs. HCNTL0 (3) HCNTL1 (3) I Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 HPI16 = 1. HBIL (3) I Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 HPI16 = 1. I Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input has an internal pullup resistor that is only enabled when HPIENA = 0. I Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0. I Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0. I Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only enabled when HPIENA = 0. HD0-HD7 (1) (2) HCS (1) (3) HDS1 HDS2 HAS (1) (3) (1) (3) (1) (3) HR/W (3) HRDY O/Z Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host when the HPI is ready for the next transfer. HINT O/Z Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT goes into the high-impedance state when OFF is low. This pin is not used when HPI16 HPI16 = 1. HPIENA (4) I HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or connected to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus has holders set. HPIENA is provided with an internal pulldown resistor that is active only when RS is low. HPIENA is sampled when RS goes high and is ignored until RS goes low again. HPI16 HPI16 (4) I HPI16 HPI16 mode selection. This pin must be tied to DVDD to enable HPI16 HPI16 mode. The pin has an internal pulldown resistor which is always active. If HPI16 HPI16 is left open or driven low, the HPI16 HPI16 mode is disabled. CVSS S Ground. Dedicated ground for the core CPU SUPPLY PINS (3) (4) This pin has an internal pullup resistor. This pin has an internal pulldown resistor. Introduction 15 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Table 2-2. Signal Descriptions (continued) TERMINAL NAME I/O (1) DESCRIPTION CVDD S +VDD. Dedicated power supply for the core CPU DVSS S Ground. Dedicated ground for I/O pins DVDD S +VDD. Dedicated power supply for I/O pins TEST PINS TCK (1) (3) I IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI (3) I IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO O/Z IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low. I TMS (3) TRST (4) EMU0 (5) EMU1/OFF (5) (5) 16 IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. I IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. I/O/Z Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. I/O/Z Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: · TRST= low, · EMU0 = high · EMU1/OFF = low This pin must be pulled up with a 4.7-k resistor to ensure the device is operable in functional mode or emulation mode. Introduction TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 3 Functional Overview The following functional overview is based on the block diagram in Figure 3-1. 16K RAM Dual Access Program/Data 54X cLEAD Pbus Ebus Cbus Dbus Pbus Ebus Cbus Pbus Dbus P, C, D, E Buses and Control Signals 16K Program ROM MBus GPIO TI BUS RHEA Bus McBSP1 Enhanced XIO HPI HPI xDMA logic McBSP2 MBus RHEA bus XIO RHEA Bridge McBSP3 RHEAbus TIMER APLL Clocks JTAG Figure 3-1. TMS320VC5402A TMS320VC5402A Functional Block Diagram 3.1 Memory The 5402A device provides both on-chip ROM and RAM memories to aid in system performance and integration. 3.1.1 Data Memory The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip RAM when addressing is within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: · Higher performance because no wait states are required · Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU) · Lower cost than external memory · Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space. Functional Overview 17 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 3.1.2 Program Memory Software can configure the memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: · Higher performance because no wait states are required · Lower cost than external memory · Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space. 3.1.3 Extended Program Memory This device uses a paged extended memory scheme in program space to allow access of up to 8192K 8192K of program memory. In order to implement this scheme, the device includes several features which are also present on C548/549/5410/5409A C548/549/5410/5409A: · Twenty-three address lines, instead of sixteen · An extra memory-mapped register, the XPC · Six extra instructions for addressing extended program space Program memory is organized into 128 pages that are each 64K in length. The value of the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0. 3.2 On-Chip ROM With Bootloader This device features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program memory space. Customers can arrange to have the ROM of the 5402A programmed with contents unique to any particular application. A bootloader is available in the standard 5402A on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard device provides different ways to download the code to accommodate various system requirements: · Parallel from 8-bit or 16-bit-wide EPROM · Parallel from I/O space, 8-bit or 16-bit mode · Serial boot from serial ports, 8-bit or 16-bit mode · Host-port interface boot · Serial EEPROM mode · Warm boot The standard on-chip ROM layout is shown in Table 3-1. 18 Functional Overview TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Table 3-1. Standard On-Chip ROM Layout ADDRESS RANGE DESCRIPTION C000h­D4FFh ROM tables for the GSM EFR speech codec D500h­F7FFh Reserved F800h­FBFFh Bootloader FC00h­FCFFh µ-Law expansion table FD00h­FDFFh A-Law expansion table FE00h­FEFFh Sine look-up table FF00h­FF7Fh Reserved (1) FF80h­FFFFh Interrupt vector table (1) 3.3 In the 5402A ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h­FF7Fh in program space. On-Chip RAM The 5402A device contains 16K-word × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. Two blocks of DARAM are located in the address range 0080h­3FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one. 3.4 On-Chip Memory Security The TMS320VC5402A TMS320VC5402A device has a maskable option to protect the contents of on-chip memories. When the RAM/ROM security option is selected, the following restrictions apply: · Only the on-chip ROM-originating instructions can read the contents of the on-chip ROM. On-chip RAM and external RAM-originating instructions cannot read data from ROM; instead, 0FFFFh is read. Code can still branch to ROM from on-chip RAM or external program memory. · The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external memory. To protect the internal RAM, the user must never branch to external memory. · The security feature completely disables the scan-based emulation capability of the 54x to prevent the use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG boundary scan test capability. · The device is internally forced into microcomputer mode at reset (MP/MC bit forced to zero), preventing the ROM from being disabled by the external MP/MC pin. The status of the MP/MC bit in the PMST register can be changed after reset by the user application. · HPI writes have no restriction, but HPI reads are restricted to the 4000h - 5FFFh address range. Functional Overview 19 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 If the ROM-only security option is selected the following restrictions apply: · Only the on-chip ROM-originating instructions can read the contents of the on-chip ROM. On-chip RAM and external RAM-originating instructions cannot read data from ROM; instead, 0FFFFh is read. Code can still branch to ROM from on-chip RAM or external program memory. · The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external memory. To protect the internal RAM the user must never branch to external memory. · The security feature completely disables the scan-based emulation capability of the 54x to prevent the use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG boundary scan test capability. · The device can be started in either microcomputer mode or microprocessor mode at reset (depends on the MP/MC pin). · HPI reads and writes have no restriction. 3.5 Memory Map Hex Page 0 Program 0000 Reserved (OVLY = 1) External (OVLY = 0) 007F On-Chip 0080 DARAM0-1 (OVLY = 1) External 3FFF (OVLY = 0) 4000 Reserved 7FFF 8000 External FF7F FF80 FFFF FEFF FF00 FF7F Interrupts (External) FF80 Hex 0000 005F 0060 007F 0080 3FFF 4000 7FFF 8000 Memory-Mapped Registers Scratch-Pad RAM On-Chip DARAM0-1 (16K x 16-bit) Reserved External Reserved Interrupts (On-Chip) FFFF MP/MC= 0 (Microcomputer Mode) Address ranges for on-chip DARAM in data memory are: DARAM0: 0080h­1FFFh; DARAM1: 2000h­3FFFh Figure 3-2. Program and Data Memory Map 20 Data (4K x 16-bit) FFFF MP/MC= 1 (Microprocessor Mode) A. Hex Page 0 Program 0000 Reserved (OVLY = 1) External (OVLY = 0) 007F On-Chip 0080 DARAM0-1 (OVLY = 1) External 3FFF (OVLY = 0) 4000 Reserved 7FFF 8000 External BFFF C000 On-Chip ROM Functional Overview TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Hex 010000 013FFF 013FFF 014000 017FFF 017FFF 018000 Program Hex 7F0000 7F0000 Program On-Chip DARAM0-1 (OVLY=1) External (OVLY=0) 7F3FFF 7F4000 7F4000 Reserved 7F7FFF 7F8000 7F8000 On-Chip DARAM0-1 (OVLY=1) External (OVLY=0) . Reserved External External 7FFFFF 01FFFF 01FFFF Page 1 XPC=1 Page 127 XPC=7Fh Figure 3-3. Extended Program Memory Map 3.5.1 Relocatable Interrupt Vector Table The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft - meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate interrupt service routine without the overhead. At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. NOTE The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space. 15 8 IPTR R/W­1FF 7 IPTR 6 MP/MC 5 OVLY 4 AVIS 3 Reserved 2 CLKOFF 1 SMUL 0 SST R/W-0 R/W-MP/MC pin R/W-0 R/W-0 R/W-0 R/W-0 N/A N/A LEGEND: R = Read, W = Write, n = value at reset Figure 3-4. Processor Mode Status Register (PMST) Functional Overview 21 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Table 3-2. Processor Mode Status Register (PMST) Field Descriptions BIT 15­7 FIELD VALUE DESCRIPTION 1FFh Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The RESET instruction does not affect this field. IPTR Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in program memory space. 0 6 MP/MC The on-chip ROM is enabled and addressable. 1 The on-chip ROM is not available. MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also be set or cleared by software. RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are: 5 OVLY 0 The on-chip RAM is addressable in data space but not in program space. 1 The on-chip RAM is mapped into program space and data space. Data page 0 (addresses 0h to 7Fh), however, is not mapped into program space. Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins. AVIS 0 The external address lines do not change with the internal program address. Control and data lines are not affected and the address bus is driven with the last address on the bus. 1 4 This mode allows the internal program address to appear at the pins of the 5402A so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside on on-chip memory. 3 0 Reserved 2 CLKOFF 0 CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high level. 1 SMUL N/A Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1 and FRCT = 1. 0 22 Reserved SST N/A Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation. Functional Overview TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 3.6 On-Chip Peripherals The 5402A device has the following peripherals: · Software-programmable wait-state generator · Programmable bank-switching · A host-port interface (HPI8/16 HPI8/16) · Three multichannel buffered serial ports (McBSPs) · A hardware timer · A clock generator with a multiple phase-locked loop (PLL) · Enhanced external parallel interface (XIO2) · A DMA controller (DMA) 3.6.1 Software-Programmable Wait-State Generator The software wait-state generator of the 5402A can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the 5402A. The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3-5 and described in Table 3-3. 15 XPA 14 12 11 9 I/O R/W-111 R/W-111 R/W-0 7 6 DATA 8 DATA R/W-111 R/W-111 5 3 2 0 DATA PROGRAM PROGRAM R/W-111 R/W-111 R/W-111 R/W-111 R/W-111 R/W-111 LEGEND: R = Read, W = Write, n = value at reset Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] Functional Overview 23 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Table 3-3. Software Wait-State Register (SWWSR) Field Descriptions BIT FIELD 15 VALUE XPA 0 DESCRIPTION Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states. 14­12 I/O 111 I/O space. The field value (0­7) corresponds to the base number of wait states for I/O space accesses within addresses 0000­FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 11­9 Data 111 Upper data space. The field value (0­7) corresponds to the base number of wait states for external data space accesses within addresses 8000­FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 8­6 Data 111 Lower data space. The field value (0­7) corresponds to the base number of wait states for external data space accesses within addresses 0000­7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 111 Upper program space. The field value (0­7) corresponds to the base number of wait states for external program space accesses within the following addresses: · XPA = 0: xx8000 ­ xxFFFFh · XPA = 1: 400000h ­ 7FFFFFh The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 111 Program space. The field value (0­7) corresponds to the base number of wait states for external program space accesses within the following addresses: · XPA = 0: xx0000 ­ xx7FFFh · XPA = 1: 000000 ­ 3FFFFFh The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 5­3 Program 2­0 Program The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3-6 and described in Table 3-4. 15 8 Reserved R/W-0 7 Reserved 1 0 SWSM R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh] Table 3-4. Software Wait-State Control Register (SWCR) Field Descriptions BIT FIELD 15­1 Reserved VALUE DESCRIPTION These bits are reserved and are unaffected by writes. Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2. 0 SWSM Functional Overview Wait-state base values are unchanged (multiplied by 1). 1 24 0 Wait-state base values are multiplied by 2 for a maximum of 14 wait states. TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 3.6.2 Programmable Bank-Switching Programmable bank-switching logic allows the 5402A to switch between external memory banks without requiring external wait states for memories that need additional time to turn off. The bank-switching logic automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or data space. Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at address 0029h. The bit fields of the BSCR are shown in Figure 3-7 and are described in Table 3-5. 15 CONSEC 14 DIVFCT 12 IACKOFF R/W-11 R/W-11 R/W-1 13 R/W-1 7 11 8 Reserved R Reserved 3 2 HBH 1 BH 0 Reserved R R/W-0 R/W-0 R LEGEND: R = Read, W = Write, n = value at reset Figure 3-7. Bank-Switching Control Register (BSCR) [MMR Address 0029h] Table 3-5. Bank-Switching Control Register (BSCR) Field Descriptions BIT FIELD VALUE DESCRIPTION Consecutive bank-switching. Specifies the bank-switching mode. CONSEC (1) 0 Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for continuous memory reads (i.e., no starting and trailing cycles between read cycles). 1 15 Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles: starting cycle, read cycle, and trailing cycle. CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency equal to 1/(DIVFCT+1) of the DSP clock. 00 CLKOUT is not divided. CLKOUT is divided by 2 from the DSP clock. CLKOUT is divided by 3 from the DSP clock. 11 DIVFCT 01 10 14­13 CLKOUT is divided by 4 from the DSP clock (default value following reset. IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset. 12 0 The IACK signal output off function is disabled. 1 11­3 IACKOFF The IACK signal output off function is enabled. Reserved Reserved HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset. HBH The bus holder is disabled except when HPI16 HPI16=1. 1 2 0 The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous logic level. Bus holder. Controls the bus holder. BH is cleared to 0 at reset. 1 (1) Reserved 0 The bus holder is disabled. 1 0 BH The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic level. Reserved For additional information, see Section Section 3.11 of this document. Functional Overview 25 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 The DSP has an internal register that holds the MSB of the last address used for a read or write operation in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address used for the current read does not match that contained in this internal register, the memory strobe (MSTRB) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address. The contents of the internal register are replaced with the MSB for the read of the current address. If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs. In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document. The bank-switching mechanism automatically inserts one extra cycle in the following cases: · A memory read followed by another memory read from a different memory bank. · A program-memory read followed by a data-memory read. · A data-memory read followed by a program-memory read. · A program-memory read followed by another program-memory read from a different page. 3.6.3 Bus Holders The device has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of the address bus (A[15­0]), data bus (D[15­0]), and the HPI data bus (HD[7­0]). Bus keeper enabling/disabling is described in Table 3-6. Table 3-6. Bus Holder Control Bits HPI16 HPI16 PIN HBH D[15­0] A[15­0] HD[7­0] 0 0 OFF OFF OFF 0 0 1 OFF OFF ON 0 1 0 ON OFF OFF 0 1 1 ON OFF ON 1 0 0 OFF OFF ON 1 0 1 OFF ON ON 1 1 0 ON OFF ON 1 26 BH 0 1 1 ON ON ON Functional Overview TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 3.7 Parallel I/O Ports The 5402A has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5402A can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits. 3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16 HPI8/16) The 5402A host-port interface, also referred to as the HPI8/16 HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier TMS320C54xTM DSPs (542, 545, 548, and 549). The 5402A HPI can be used to interface to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface to external devices in program/data/IO spaces), the 5402A HPI can be configured as an HPI16 HPI16 to interface to a 16-bit host. This configuration can be accomplished by connecting the HPI16 HPI16 pin to logic "1". When the HPI16 HPI16 pin is connected to a logic "0", the 5402A HPI is configured as an HPI8. The HPI8 is an 8-bit parallel port for interprocessor communication. The features of the HPI8 include: Standard features: · Sequential transfers (with autoincrement) or random-access transfers · Host interrupt and C54xTM interrupt capability · Multiple data strobes and control pins for interface flexibility The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8 through three dedicated registers - the HPI address register (HPIA), the HPI data register (HPID), and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the 5402A. Enhanced features: · Access to entire on-chip RAM through DMA bus · Capability to continue transferring during emulation stop The HPI16 HPI16 is an enhanced 16-bit version of the TMS320C54xTM DSP 8-bit host-port interface (HPI8). The HPI16 HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface. Some of the features of the HPI16 HPI16 include: · 16-bit bidirectional data bus · Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts · Only nonmultiplexed address/data modes are supported · 15-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal extended address pages) · HRDY signal to hold off host accesses due to DMA latency · The HPI16 HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP. NOTE Only the nonmultiplexed mode is supported when the 5402A HPI is configured as a HPI16 HPI16 (see Figure 3-8). Functional Overview 27 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 The 5402A HPI functions as a slave and enables the host processor to access the on-chip memory. A major enhancement to the 5402A HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one cycle. Since host accesses are always synchronized to the 5402A clock, an active input clock (CLKIN) is required for HPI accesses during IDLE states, and host accesses are not allowed while the 5402A reset pin is asserted. 3.7.2 HPI Nonmultiplexed Mode In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 16-bit HA address bus. The host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16 HPI16 can stall host accesses via the HRDY signal. The HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. Figure 3-8 shows a block diagram of the HPI16 HPI16 in nonmultiplexed mode. DATA[15:0] HPI16 HPI16 PPD[15:0] HINT HPID[15:0] DMA Address[15:0] HCNTL0 VCC HCNTL1 HBIL HAS R/W HR/W Data Strobes READY HRDY HDS1, HDS2, HCS Figure 3-8. Host-Port Interface - Nonmultiplexed Mode 28 Functional Overview 54xx CPU Internal Memory HOST TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Address (Hex) 000 0000 Reserved 000 005F 000 0060 000 007F 000 0080 Scratch-Pad RAM DARAM0 DARAM1 000 3FFF 000 4000 Reserved 07F FFFF Figure 3-9. HPI Memory Map 3.8 Multichannel Buffered Serial Ports (McBSPs) The 5402A device provides high-speed, full-duplex serial ports that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. There are three multichannel buffered serial ports (McBSPs) on board (three per subsystem). The McBSP provides: · Full-duplex communication · Double-buffer data registers, which allow a continuous data stream · Independent framing and clocking for receive and transmit In addition, the McBSP has the following capabilities: · Direct interface to: ­ T1/E1 framers ­ MVIP switching-compatible and ST-BUS compliant devices ­ IOM-2 compliant device ­ AC97-compliant device ­ Serial peripheral interface (SPI) · Multichannel transmit and receive of up to 128 channels · A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits · µ-law and A-law companding · Programmable polarity for both frame synchronization and data clocks · Programmable internal clock and frame generation Functional Overview 29 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 The 5402A McBSPs have been enhanced to provide more flexibility in the choice of the sample rate generator input clock source. On previous TMS320C5000TM TMS320C5000TM DSP platform devices, the McBSP sample rate input clock can be driven from one of two possible choices: the internal CPU clock, or the external CLKS pin. However, most C5000TM C5000TM DSP devices have only the internal CPU clock as a possible source because the CLKS pin is not implemented. To accommodate applications that require an external reference clock for the sample rate generator, the 5402A McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be configured as the input clock to the sample rate generator. This enhancement is enabled through two register bits: pin control register (PCR) bit 7 - enhanced sample clock mode (SCLKME), and sample rate generator register 2 (SRGR2) bit 13 - McBSP sample rate generator clock mode (CLKSM). SCLKME is an addition to the PCR contained in the McBSPs on previous C5000 C5000 devices. The new bit layout of the PCR is shown in Figure 3-10. For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302 SPRU302). 15 Reserved 14 13 XIOEN 12 RIOEN 11 FSXM 10 FSRM 9 CLKXM 8 CLKRM R, +0 R/W,+0 R/W,+0 R/W,+0 R/W,+0 R/W,+0 R/W,+0 7 SCLKME 6 CLKS_STAT 5 DX_STAT 4 DR_STAT 3 FSXP 2 FSRP 1 CLKXP 0 CLKRP R/W, +0 R, +0 R, +0 R, +0 R/W,+0 R/W,+0 R/W,+0 R/W,+0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-10. Pin Control Register (PCR) The selection of the sample rate generator (SRG) clock input source is made by the combination of the CLKSM and SCLKME bit values as shown in Table 3-7. Table 3-7. Sample Rate Generator Clock Source Selection SCLKME CLKSM 0 0 CLKS (not available as a pin on 5402A) SRG Clock Source 0 1 CPU clock 1 0 BCLKR pin 1 1 BCLKX pin When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the BCLKX pin because the BCLKR output is automatically disabled. The McBSP supports independent selection of multiple channels for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled. The 5402A McBSPs have two working modes that are selected by setting the RMCME and XMCME bits in the multichannel control registers (MCR1x and MCR2x, respectively). See Figure 3-11 and Figure 3-12. For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302 SPRU302). 30 Functional Overview TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 · In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each containing 16 channels as shown in Figure 3-11 and Figure 3-12. This is compatible with the McBSPs used in earlier TMS320C54x devices, where only 32-channel selection is enabled (default). 15 Reserved 10 6 8 RPBBLK R, +0 7 RPBBLK 9 RMCME R/W, +0 R/W, +0 5 4 2 1 0 RPABLK RMCM R/W, +0 R/W, +0 RCBLK R, +0 R/W, +0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-11. Multichannel Control Register 1x (MCR1x) 15 Reserved 10 6 8 XPBBLK R, +0 7 XPBBLK 9 XMCME R/W, +0 R/W, +0 5 4 2 1 0 XPABLK XMCM R/W, +0 R/W, +0 XCBLK R, +0 R, +0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-12. Multichannel Control Register 2x (MCR2x) · In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128 channel selection capability. Twelve new registers (RCERCx­RCERHx and XCERCx­XCERHx) are used to enable the 128 channel selection. The subaddresses of the new registers are shown in Table 3-19. These new registers, functionally equivalent to the RCERA0­RCERB1 and XCERA0­XCERB1 registers in the 5420, are used to enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G, and H) in the128 channel stream. For example, XCERH1 is the transmit enable for channel partition H (channels 112 to 127) of MCBSP1 for each DSP subsystem. See Figure 3-13, Table 3-8, Figure 3-14, and Table 3-9 for bit layout and function of the receive and transmit registers . 15 RCERyz15 14 RCERyz14 13 RCERyz13 12 RCERyz12 11 RCERyz11 10 RCERyz10 9 RCERyz9 8 RCERyz8 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 7 RCERyz7 6 RCERyz6 5 RCERyz5 4 RCERyz4 3 RCERyz3 2 RCERyz2 1 RCERyz1 0 RCERyz0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-13. Receive Channel Enable Registers Bit Layout for Partitions A to H Functional Overview 31 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Table 3-8. Receive Channel Enable Registers for Partitions A to H Field Descriptions BIT FIELD VALUE DESCRIPTION Receive Channel Enable Register 15­0 RCERyz(15:0) 0 Disables reception of nth channel in partition y. 1 Enables reception of nth channel in partition y. 15 XCERyz15 14 XCERyz14 13 XCERyz13 12 XCERyz12 11 XCERyz11 10 XCERyz10 9 XCERyz9 8 XCERyz8 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 7 XCERyz7 6 XCERyz6 5 XCERyz5 4 XCERyz4 3 XCERyz3 2 XCERyz2 1 XCERyz1 0 XCERyz0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-14. Transmit Channel Enable Registers Bit Layout for Partitions A to H Table 3-9. Transmit Channel Enable Registers for Partitions A to H Field Descriptions BIT FIELD VALUE Description Transmit Channel Enable Register 15­0 XCERyz(15:0) 0 Disables transmit of nth channel in partition y. 1 Enables transmit of nth channel in partition y. The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface (SPI) protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave. The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum McBSP multichannel operating frequency on the 5402A is 9 MBps. Nonmultichannel operation is limited to 38 MBps. 3.9 Hardware Timer The device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits. 3.10 Clock Generator The clock generator provides clocks to the device, and consists of a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. 32 Functional Overview TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock. This clock generator allows system designers to select the clock source. The sources that drive the clock generator are: · A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins to enable the internal oscillator. · An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left unconnected. NOTE The crystal oscillator function is not supported by all die revisions of the 5402A device. See the TMS320VC5402A TMS320VC5402A Digital Signal ProcessorSilicon Errata (literature number SPRZ018 SPRZ018) to verify which die revisions support this functionality. The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes: · PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. · DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation. The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 ­ CLKMD3 pins. For more programming information, see the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131 SPRU131). The CLKMD pin configured clock options are shown in Table 3-10. Table 3-10. Clock Mode Settings at Reset CLOCK MODE (1) CLKMD1 CLKMD3 CLKMD RESET VALUE 0 0 0 0000h 1/2 (PLL and Oscillator disabled) 0 0 1 9007h PLL x 10 (Oscillator enabled) 0 1 0 4007h PLL x 5 (Oscillator enabled) 1 0 0 1007h PLL x 2(Oscillator enabled) 1 1 0 F007h PLL x 1 (Oscillator enabled) 1 1 1 0000h 1/2 (PLL disabled, Oscillator enabled) 1 0 1 F000h 1/4 (PLL disabled, Oscillator enabled) 0 (1) CLKMD2 1 1 - Reserved (Bypass mode) The external CLKMD1­CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software. However, the oscillator enable/disable selection is performed independently of the state of RS; therefore, if CLKMD1­CLKMD3 are changed following reset, the oscillator enable/disable selection may change, but other aspects of the clock generation mode will not. Functional Overview 33 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 3.11 Enhanced External Parallel Interface (XIO2) The 5402A external interface has been redesigned to include several improvements, including: simplification of the bus sequence, more immunity to bus contention when transitioning between read and write operations, the ability for external memory access to the DMA controller, and optimization of the power-down modes. The bus sequence on the 5402A still maintains all of the same interface signals as on previous 54x devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide additional immunity against bus contention when switching between read operations and write operations. To maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous 54x devices is available. 34 Functional Overview TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 Figure 3-15 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode, or single memory reads in consecutive mode. The accesses shown in Figure 3-15 always require 3 CLKOUT cycles to complete. CLKOUT td(CLKL-A) A[22:0] td(CLKL-MSL) td(CLKL-MSH) ta(A)M1 D[15:0] tsu(D)R th(D)R MSTRB R/W PS/DS Figure 3-15. Nonconsecutive Memory Read and I/O Read Bus Sequence Figure 3-16 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown in Figure 3-16 require (2+n) CLKOUT cycles to complete, where n is the number of consecutive reads performed. Functional Overview 35 TMS320VC5402A TMS320VC5402A Fixed-Point Digital Signal Processor www.ti.com SPRS015E SPRS015E ­ SEPTEMBER 2001 ­ REVISED JANUARY 2005 CLKOUT A[22:0] D[15:0] READ READ READ R/W MSTRB PS/DS Leading Cycle Read Cycle Read Cycle Read Cy