TMS320F28022 TMS320F28023 TMS320F28024 TMS320F28025 TMS320F28026 TMS320F28027 - Datasheet Archive

 

TMS320F28025, TMS320F28026, TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER

 

TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 1 TMS320F2802x (PiccoloTM) MCUs · · · · High-Efficiency 32-Bit CPU (TMS320C28xTM) ­ 60 MHz (16.67-ns Cycle Time) ­ 40 MHz (25-ns Cycle Time) ­ 16 x 16 and 32 x 32 MAC Operations ­ 16 x 16 Dual MAC ­ Harvard Bus Architecture ­ Atomic Operations ­ Fast Interrupt Response and Processing ­ Unified Memory Programming Model ­ Code-Efficient (in C/C+ and Assembly) Low Device and System Cost: ­ Single 3.3-V Supply ­ No Power Sequencing Requirement ­ Integrated Power-on Reset and Brown-out Reset ­ Small Packaging, as low as 38-pin available ­ Low Power ­ No Analog Support Pins Clocking: ­ 2 Internal Zero-pin Oscillators ­ On-chip Crystal Oscillator/External Clock Input ­ Dynamic PLL Ratio Changes Supported ­ Watchdog Timer Module ­ Missing Clock Detection Circuitry Up to 22 Individually Programmable, · · · · · · · · Multiplexed GPIO Pins With Input Filtering Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts Three 32-Bit CPU Timers On-Chip Memory ­ Flash, SARAM, OTP, Boot ROM Available 128-Bit Security Key/Lock ­ Protects Secure Memory Blocks ­ Prevents Firmware Reverse Engineering Serial Port Peripherals ­ One SCI (UART) Module ­ One SPI Module ­ One Inter-Integrated-Circuit (I2C) Bus Advanced Emulation Features ­ Analysis and Breakpoint Functions ­ Real-Time Debug via Hardware Enhanced Control Peripherals ­ Enhanced Pulse Width Modulator (ePWM) ­ High-resolution PWM (HRPWM) ­ Enhanced Capture (eCAP) ­ Analog-to-Digital Converter (ADC) ­ Comparator 2802x Packages ­ 38-Pin DA Plastic Small Outline Package (PSOP) ­ 48-Pin PT Plastic Quad Flatpack (PQFP) 1.2 Description The F2802x PiccoloTM family of microcontrollers provides the power of the C28xTM core coupled with highly integrated control peripherals in low pin-count devices. This family is code compatible with previous C28-based code, as well as providing a high level of analog integration. An internal voltage regulator allows for single rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The interface has been optimized for low overhead/latency. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. Piccolo, TMS320C28x, C28x, TMS320C2000 TMS320C2000, Code Composer Studio, XDS510 XDS510 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2008­2008, Texas Instruments Incorporated ADVANCE INFORMATION 1.1 Features TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 1.3 Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following: · Getting Started With TMS320C28xTM Digital Signal Controllers (literature number SPRAAM0). · C2000 C2000 Getting Started Website (http://www.ti.com/c2000getstarted) · TMS320F28x MCU Development and Experimenter's Kits (http://www.ti.com/f28xkits) ADVANCE INFORMATION 2 TMS320F2802x (PiccoloTM) MCUs Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 Contents Enhanced CAP Modules (eCAP1) . 55 Description . 1 4.7 JTAG Port . 56 Getting Started. 2 4.8 GPIO MUX . 4 2.1 Pin Assignments . 5 2.2 Signal Descriptions . 7 Functional Overview . 11 3.1 Block Diagram . 11 3.2 Memory Maps . 12 3.3 Brief Descriptions. 16 3.4 Register Map . 22 3.5 Device Emulation Registers . 23 3.6 Interrupts . 24 3.7 VREG/BOR/POR . 28 3.8 System Control . 30 3.9 Low-power Modes Block . 36 Peripherals. 38 4.1 Analog Block . 38 4.1 Serial Peripheral Interface (SPI) Module . 42 4.2 Serial Communications Interface (SCI) Module . 45 4.3 Inter-Integrated Circuit (I2C) . 48 4.4 Enhanced PWM Modules (ePWM1/2/3/4) . 50 Hardware Features Submit Documentation Feedback 5 Device Support . . 57 63 5.1 5.2 6 Device and Development Support Tool Nomenclature . 63 Related Documentation . 64 Electrical Specifications . 67 6.1 Absolute Maximum Ratings . 67 6.2 Recommended Operating Conditions . 67 6.3 Electrical Characteristics 6.4 6.5 Current Consumption. 68 Emulator Connection Without Signal Buffering for the MCU . 71 6.6 Timing Parameter Symbology . 73 6.7 Clock Requirements and Characteristics 6.8 Power Sequencing . 76 . . 68 75 6.9 General-Purpose Input/Output (GPIO) . 79 6.10 Enhanced Control Peripherals . 84 6.11 Detailed Descriptions . 97 7 Mechanicals . 99 Revision History . 100 Contents 3 ADVANCE INFORMATION 4 High-Resolution PWM (HRPWM) . 54 4.6 1.3 3 4.5 Features . 1 1.2 2 TMS320F2802x (PiccoloTM) MCUs . 1 1.1 1 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 2 Hardware Features Table 2-1. Hardware Features TYPE (1) 28022 (40 MHz) 28023 (40 MHz) 28024 (40 MHz) 28025 (40 MHz) 28026 (60 MHz) 28027 (60 MHz) Instruction cycle ­ 25 ns 25 ns 25 ns 25 ns 16.67 ns 16.67 ns On-chip flash (16-bit word) ­ 16K 32K 16K 32K 16K 32K On-chip SARAM (16-bit word) ­ 6K 6K 6K 6K 6K 6K Code security for on-chip flash/SARAM/OTP blocks ­ Yes Yes Yes Yes Yes Yes Boot ROM (8K X16) ­ Yes Yes Yes Yes Yes Yes One-time programmable (OTP) ROM (16-bit word) ­ 1K 1K 1K 1K 1K 1K ePWM modules 1 ePWM1/2/3/4 ePWM1/2/3/4 ePWM1/2/3/4 ePWM1/2/3/4 ePWM1/2/3/4 ePWM1/2/3/4 eCAP modules 0 eCAP1 eCAP1 eCAP1 eCAP1 eCAP1 eCAP1 Watchdog timer ­ Yes Yes Yes Yes Yes Yes 3.07 3.07 3.07 3.07 4.6 4.6 325 ns 325 ns 325 ns 325 ns 216.67 ns 216.67 ns FEATURE ADVANCE INFORMATION MSPS 12-Bit ADC Conversion Time 3 7 7 13 13 13 13 32-Bit CPU timers Channels ­ 3 3 3 3 3 3 HiRES ePWM Channels 1 4 4 4 4 4 4 Comparators w/ Integrated DACs 0 1 1 2 2 2 2 Inter-integrated circuit (I2C) 0 1 1 1 1 1 1 Serial Peripheral Interface (SPI) 1 1 1 1 1 1 1 Serial Communications Interface (SCI) 0 1 1 1 1 1 1 Digital ­ 20 20 22 22 22 22 Analog 6 I/O pins (shared) ­ 6 6 6 6 6 External interrupts ­ 3 3 3 3 3 3 Supply voltage (nominal) ­ 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Yes 48-Pin PT PQFP ­ ­ ­ Yes Yes Yes 38-Pin DA PSOP ­ Yes Yes ­ ­ ­ ­ A: - 40°C to 85°C ­ Yes Yes Yes Yes Yes Yes S: - 40°C to 125°C ­ ­ ­ Yes Yes ­ ­ ­ TMX TMX TMX TMX TMX TMX Packaging Temperature options Product status (2) (1) (2) 4 A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566 SPRU566) and in the peripheral reference guides. See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages. TMX is an experimental device that is not necessarily representative of the final device's electrical specifications. TMS is a fully qualified production device. Hardware Features Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 2.1 Pin Assignments 36 35 34 33 32 31 30 29 28 27 26 25 ADVANCE INFORMATION GPIO33/SCLA/EPWMSYNCO/ADCSOCBO GPIO33/SCLA/EPWMSYNCO/ADCSOCBO VDDIO VREGENZ VSS VDD GPIO32/SDAA/EPWMSYNCI/ADCSOCAO GPIO32/SDAA/EPWMSYNCI/ADCSOCAO TEST GPIO0/EPWM1A GPIO1/EPWM1B/COMP1OUT GPIO16/SPISIMOA/TZ2 GPIO16/SPISIMOA/TZ2 GPIO17/SPISOMIA/TZ3 GPIO17/SPISOMIA/TZ3 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 Figure 2-1 shows the 48-pin PT plastic quad flatpack (PQFP) pin assignments. Figure 2-2 shows the 38-pin DA plastic small outline package (PSOP) pin assignments. GPIO2/EPWM2A GPIO3/EPWM2B/COMP2OUT GPIO4/EPWM3A GPIO5/EPWM3B/ECAP1 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA VDD VSS 24 23 22 21 20 19 18 17 16 15 14 13 GPIO18/SPICLKA/SCITXDA/XCLKOUT GPIO18/SPICLKA/SCITXDA/XCLKOUT GPIO38/XCLKIN GPIO38/XCLKIN (TCK) GPIO37 GPIO37 (TDO) GPIO36 GPIO36 (TMS) GPIO35 GPIO35 (TDI) GPIO34/COMP2OUT GPIO34/COMP2OUT ADCINB7 ADCINB6/AIO14 ADCINB6/AIO14 ADCINB4/COMP2B/AIO12 ADCINB4/COMP2B/AIO12 ADCINB3 ADCINB2/COMP1B/AIO10 ADCINB2/COMP1B/AIO10 ADCINB1 TRST XRS ADCINA6/AIO6 ADCINA4/COMP2A/AIO4 ADCINA7 ADCINA3 ADCINA1 ADCINA2/COMP1A/AIO2 ADCINA0/VREFHI VDDA VSSA/VREFLO GPIO29/SCITXDA/SCLA/TZ3 GPIO29/SCITXDA/SCLA/TZ3 1 2 3 4 5 6 7 8 9 10 11 12 X1 X2 GPIO12/TZ1/SCITXDA GPIO12/TZ1/SCITXDA GPIO28/SCIRXDA/SDAA/TZ2 GPIO28/SCIRXDA/SDAA/TZ2 37 38 39 40 41 42 43 44 45 46 47 48 Figure 2-1. 2802x 48-Pin PT PQFP (top view) Submit Documentation Feedback Hardware Features 5 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 ADVANCE INFORMATION VDD VSS VREGENZ VDDIO GPIO2/EPWM2A GPIO3/EPWM2B/COMP2OUT GPIO4/EPWM3A GPIO5/EPWM3B/ECAP1 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA VDD VSS GPIO12/TZ1/SCITXDA GPIO12/TZ1/SCITXDA GPIO28/SCIRXDA/SDAA/TZ2 GPIO28/SCIRXDA/SDAA/TZ2 GPIO29/SCITXDA/SCLA/TZ3 GPIO29/SCITXDA/SCLA/TZ3 TRST XRS ADCINA6/AIO6 ADCINA4/COMP2A/AIO4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 www.ti.com 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 TEST GPIO0/EPWM1A GPIO1/EPWM1B/COMP1OUT GPIO16/SPISIMOA/TZ2 GPIO16/SPISIMOA/TZ2 GPIO17/SPISOMIA/TZ3 GPIO17/SPISOMIA/TZ3 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 GPIO18/SPICLKA/SCITXDA/XCLKOUT GPIO18/SPICLKA/SCITXDA/XCLKOUT GPIO38/XCLKIN GPIO38/XCLKIN (TCK) GPIO37 GPIO37 (TDO) GPIO36 GPIO36 (TMS) GPIO35 GPIO35 (TDI) GPIO34/COMP2OUT GPIO34/COMP2OUT ADCINB6/AIO14 ADCINB6/AIO14 ADCINB4/COMP2B/AIO12 ADCINB4/COMP2B/AIO12 ADCINB2/COMP1B/AIO10 ADCINB2/COMP1B/AIO10 VSSA/VREFLO VDDA ADCINA0/VREFHI ADCINA2/COMP1A/AIO2 Figure 2-2. 2802x 38-Pin DA PSOP (top view) 6 Hardware Features Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 2.2 Signal Descriptions Table 2-2. TERMINAL FUNCTIONS TERMINAL NAME PT NO. DA NO. I/O/Z DESCRIPTION JTAG I TCK See GPIO38 GPIO38 I See GPIO38 GPIO38. JTAG test clock with internal pullup () TMS See GPIO36 GPIO36 I See GPIO36 GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. () TDI See GPIO35 GPIO35 I See GPIO35 GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. () TDO See GPIO37 GPIO37 O/Z See GPIO37 GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive) I/O Test Pin. Reserved for TI. Must be left unconnected. O/Z See GPIO18 GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. I See GPIO19 GPIO19 and GPIO38 GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. Note: Designs that use the GPIO38/TCK/XCLKIN GPIO38/TCK/XCLKIN pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device. TRST 2 ADVANCE INFORMATION 16 JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is recommended on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. () FLASH TEST 30 38 CLOCK XCLKOUT XCLKIN See GPIO18 GPIO18 See GPIO19 GPIO19 and GPIO38 GPIO38 X1 45 ­ I On-chip crystal oscillator Input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND. (I) X2 46 ­ O On-chip crystal oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. (O) Submit Documentation Feedback Hardware Features 7 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL NAME PT NO. DA NO. I/O/Z DESCRIPTION RESET XRS 3 17 I/O Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the device. See the electrical section for thresholds of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, it is recommended that this pin be driven by an open-drain device An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. (I/OD) ADVANCE INFORMATION ADC, COMPARATOR, ANALOG I/O ADCINA7 6 I ADC Group A, Channel 7 input ADCINA6 AIO6 4 18 I I/O ADC Group A, Channel 6 input Digital AIO 6 ADCINA4 COMP2A AIO4 5 19 I I I/O ADC Group A, Channel 4 input Comparator Input 2A Digital AIO 4 ADCINA3 7 ­ I ADC Group A, Channel 3 input ADC Group A, Channel 2 input Comparator Input 1A Digital AIO 2 ADCINA2 COMP1A AIO2 9 20 I I I/O ADCINA1 8 ­ I ADC Group A, Channel 1 input ADCINA0 VREFHI 10 21 I I ADC Group A, Channel 0 input ADC External Reference ­ only used when in ADC external reference mode. See ADC Section. ADCINB7 18 ­ I ADC Group B, Channel 7 input ADCINB6 AIO14 AIO14 17 26 I I/O ADC Group B, Channel 6 input Digital AIO 14 ADCINB4 COMP2B AIO12 AIO12 16 25 I I I/O ADC Group B, Channel 4 input Comparator Input 2B Digital AIO12 AIO12 ADCINB3 15 ­ I ADC Group B, Channel 3 input ADC Group B, Channel 2 input Comparator Input 1B Digital AIO 10 ADC Group B, Channel 1 input ADCINB2 COMP1B AIO10 AIO10 14 24 I I I/O ADCINB1 13 ­ I CPU AND I/O POWER VDDA 11 22 VSSA VREFLO Analog Power Pin 12 23 VDD 32 1 VDD 43 11 CPU and Logic Digital Power Pins ­ no supply source needed when using internal VREG. Tie with 1.2 µF ceramic capacitor to ground when using internal VREG. VDDIO 35 4 Digital I/O and Flash Power Pin ­ Single Supply source when VREG is enabled VSS 33 2 VSS 44 12 VREGENZ 34 3 I GPIO0 29 37 I/O/Z Analog Ground Pin ADC Low Reference (always tied to ground) I Digital Ground Pins VOLTAGE REGULATOR CONTROL SIGNAL Internal VREG Enable/Disable ­ pull low to enable VREG, pull high to disable VREG GPIO AND PERIPHERAL SIGNALS 8 Hardware Features General purpose input/output 0 Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL NAME PT NO. DA NO. I/O/Z DESCRIPTION EPWM1A O Enhanced PWM1 Output A and HRPWM channel ­ ­ ­ ­ ­ ­ GPIO1 28 36 I/O/Z EPWM1B O ­ General purpose input/output 1 ­ COMP1OUT GPIO2 Enhanced PWM1 Output B O 37 5 EPWM2A Direct output of Comparator 1 I/O/Z General purpose input/output 2 O Enhanced PWM2 Output A and HRPWM channel ­ ­ ­ GPIO3 38 6 EPWM2B I/O/Z O ­ 7 Direct output of Comparator 2 I/O/Z General purpose input/output 4 O ­ Enhanced PWM3 output A and HRPWM channel ­ ­ ­ 40 8 EPWM3B I/O/Z O ­ General purpose input/output 5 Enhanced PWM3 output B ­ ECAP1 GPIO6 Enhanced PWM2 Output B O 39 EPWM3A GPIO5 General purpose input/output 3 ­ COMP2OUT GPIO4 ADVANCE INFORMATION ­ I/O 41 9 I/O/Z Enhanced Capture input/output 1 General purpose input/output 6 EPWM4A O Enhanced PWM4 output A and HRPWM channel EPWMSYNCI I External ePWM sync pulse input EPWMSYNCO O External ePWM sync pulse output GPIO7 42 10 I/O/Z General purpose input/output 7 EPWM4B O Enhanced PWM4 output B SCIRXDA I SCI-A receive data ­ GPIO12 GPIO12 ­ 47 13 I/O/Z General purpose input/output 12 TZ1 I Trip Zone input 1 SCITXDA O SCI-A transmit data ­ GPIO16 GPIO16 ­ 27 35 SPISIMOA I/O/Z I/O ­ I 26 34 SPISOMIA I/O/Z I/O ­ Trip Zone input 2 General purpose input/output 17 SPI-A slave out, master in ­ TZ3 GPIO18 GPIO18 SPI slave in, master out ­ TZ2 GPIO17 GPIO17 General purpose input/output 16 I 24 32 I/O/Z Trip zone input 3 General purpose input/output 18 SPICLKA I/O SPI-A clock input/output SCITXDA O SCI-A transmit Submit Documentation Feedback Hardware Features 9 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL NAME DA NO. XCLKOUT GPIO19 GPIO19 25 33 I/O/Z DESCRIPTION O/Z PT NO. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. I/O/Z General purpose input/output 19 External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other periperhal functions XCLKIN SPISTEA I/O SCIRXDA I ECAP1 SPI-A slave transmit enable input/output SCI-A receive ADVANCE INFORMATION I/O GPIO28 GPIO28 48 14 SCIRXDA Enhanced Capture input/output 1 I/O/Z General purpose input/output 28 I SDAA I/OC TZ2 I GPIO29 GPIO29 1 15 SCITXDA I/O/Z O SCLA I/OC TZ3 I GPIO32 GPIO32 31 - SCI receive data I2C data open-drain bidirectional port Trip zone input 2 General purpose input/output 29. SCI transmit data I2C clock open-drain bidirectional port Trip zone input 3 General purpose input/output 32 I/OC SDAA I/O/Z I2C data open-drain bidirectional port EPWMSYNCI I Enhanced PWM external sync pulse input ADCSOCAO O ADC start-of-conversion A GPIO33 GPIO33 36 ­ I/O/Z General-Purpose Input/Output 33 I/OC SCLA I2C clock open-drain bidirectional port EPWMSYNCO O Enhanced PWM external synch pulse output ADCSOCBO O ADC start-of-conversion B GPIO34 GPIO34 19 27 COMP2OUT I/O/Z O ­ General-Purpose Input/Output 34 Direct output of Comparator 2 ­ ­ ­ GPIO35 GPIO35 20 28 TDI I/O/Z I GPIO36 GPIO36 21 29 TMS I/O/Z I GPIO37 GPIO37 22 30 General-Purpose Input/Output 35 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK General-Purpose Input/Output 36 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. GPIO38 GPIO38 23 31 General-Purpose Input/Output 37 O/Z TDO I/O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive) I/O/Z General-Purpose Input/Output 38 TCK I JTAG test clock with internal pullup XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other periperhal functions. 10 Hardware Features Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 3 Functional Overview 3.1 Block Diagram Memory Bus M0 SARAM 1K x 16 (0-wait) M1 SARAM 1K x 16 (0-wait) OTP 1K x 16 Secure SARAM 4K x 16 (0-wait) Secure FLASH 16K/32K 16K/32K x 16 Secure Code Security Module Boot-ROM 8K x 16 (0-wait) ADVANCE INFORMATION OTP/Flash Wrapper PSWD Memory Bus TRST TCK TDI TMS TDO GPIO 32-bit periph eral bus COMP1OUT COMP2OUT MUX COMP1A COMP1B COMP2A COMP2B COMP C28x 32-bit CPU 3 External Interrupts PIE CPU Timer 0 AIO CPU Timer 1 MUX CPU Timer 2 OSC1, OSC2, Ext, PLL, LPM, WD XCLKIN X1 X2 LPM Wakeup XRS ADC A7:0 Memory Bus POR/ BOR B7:0 32-bit Peripheral Bus 32-Bit Peripheral Bus ECAP From COMP1OUT, COMP2OUT ECA Px ESYNCI EPWMxA EPWMxB HRPWM TZx SCLx SDAx VREG EPWM I2C (4L FIFO) SPISTEx SPICLKx SPISOMIx SPISIMOx SCITXDx SCIRXDx SPI (4L FIFO) ESYNCO 16-bit Peripheral Bus SCI (4L FIFO) GPIO Mux GPIO MUX Figure 3-1. Functional Block Diagram Submit Documentation Feedback Functional Overview 11 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.2 Memory Maps In Figure 3-2, the following apply: · Memory blocks are not to scale. · Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space. · Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order. · Certain memory ranges are EALLOW protected against spurious writes after configuration. · Locations 0x3D7C80 ­ 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These locations are not programmable by the user. Prog Space Data Space Low 64K (24x/240x Equivalent Data Space) M0 Vector RAM (Enabled if VMAP=0) 0x00 0040 ADVANCE INFORMATION 0x00 0000 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 0x00 1000 Reserved Reserved 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) 0x00 7000 0x00 8000 Reserved Peripheral Frame 2 (4K x 16, Protected) L0 SARAM (4K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) 0F00 9000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7C00 Reserved 0x3D 7C80 Calibration Data 0x3D 7CC0 0x3D 8000 High 64K (24x/240x Equivalent Program Space) Reserved 0x3F 0000 FLASH (32K x 16, 4 Sectors, Secure Zone + ECSL) 0x3F 7FF8 0x3F 8000 0x3F 9000 128-Bit Password L0 SARAM (4K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) Reserved 0x3F E000 Boot ROM (8K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP=1) Figure 3-2. 28023/28025/28027 Memory Map 12 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 Prog Space Data Space 0x00 0000 Low 64K (24x/240x Equivalent Data Space) 0x00 0040 0x00 0400 0x00 0800 M0 Vector RAM (Enabled if VMAP=0) M0 SARAM (1K x 16, 0-Wait) M1 SARAM (1K x 16, 0-Wait) Reserved Peripheral Frame 0 0x00 1000 Reserved 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) Reserved 0x00 7000 Peripheral Frame 2 (4K x 16, Protected) 0x00 8000 0F00 9000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7C00 ADVANCE INFORMATION L0 SARAM (4K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) Reserved 0x3D 7C80 0x3D 7CC0 Calibration Data 0x3D 8000 High 64K (24x/240x Equivalent Program Space) Reserved 0x3F 4000 FLASH (16K x 16, 4 Sectors, Secure Zone + ECSL) 0x3F 7FF8 0x3F 8000 0x3F 9000 128-Bit Password L0 SARAM (4K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) Reserved 0x3F E000 Boot ROM (8K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP=1) Figure 3-3. 28022/28024/28026 Memory Map Submit Documentation Feedback Functional Overview 13 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 3-1. Addresses of Flash Sectors in F28023/28025/28027 F28023/28025/28027 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 0000 - 0x3F 1FFF Sector D (8K x 16) 0x3F 2000 - 0x3F 3FFF Sector C (8K x 16) 0x3F 4000 - 0x3F 5FFF Sector B (8K x 16) 0x3F 6000 - 0x3F 7F7F Sector A (8K x 16) 0x3F 7F80 - 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 - 0x3F 7FF7 Boot-to-Flash Entry Point (program branch instruction here) 0x3F 7FF8 - 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) Table 3-2. Addresses of Flash Sectors in F28022/28024/28026 F28022/28024/28026 PROGRAM AND DATA SPACE Sector D (4K x 16) 0x3F 5000 - 0x3F 5FFF Sector C (4K x 16) 0x3F 6000 - 0x3F 6FFF ADVANCE INFORMATION ADDRESS RANGE 0x3F 4000 - 0x3F 4FFF Sector B (4K x 16) 0x3F 7000 - 0x3F 7F7F Sector A (4K x 16) 0x3F 7F80 - 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 - 0x3F 7FF7 Boot-to-Flash Entry Point (program branch instruction here) 0x3F 7FF8 - 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) NOTE When the code-security passwords are programmed, all addresses between 0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. · If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for code or data. Addresses 0x3F 7FF0 ­ 0x3F 7FF5 are reserved for data and should not contain program code. Table 3-3 shows how to handle these memory locations. · Table 3-3. Impact of Using the Code Security Module ADDRESS FLASH Code security enabled 0x3F 7F80 - 0x3F 7FEF 0x3F 7FF0 - 0x3F 7FF5 Fill with 0x0000 Code security disabled Application code and data Reserved for data only Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The CPU supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it protects the selected zones. The wait-states for the various spaces in the memory map area are listed in Table 3-4. 14 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-4. Wait-states AREA WAIT-STATES (CPU) M0 and M1 SARAMs 0-wait Peripheral Frame 0 0-wait (writes) Fixed 0-wait Peripheral Frame 1 COMMENTS Cycles can be extended by peripheral generated ready. 2-wait (reads) Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral. 2-wait (reads) L0 SARAM 0-wait data and program OTP Programmable Programmed via the Flash registers. 1-wait minimum 1-wait is minimum number of wait states allowed. Programmable Programmed via the Flash registers. FLASH Assumes no CPU conflicts 0-wait Paged min FLASH Password 16-wait fixed Boot-ROM ADVANCE INFORMATION 1-wait Random min Random Paged 0-wait Submit Documentation Feedback Wait states of password locations are fixed. Functional Overview 15 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.3 Brief Descriptions 3.3.1 CPU ADVANCE INFORMATION The 2802x (C28x) family is a member of the TMS320C2000TM TMS320C2000TM microcontroller (MCU) platform. The C28x-based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very efficient C/C+ engine, enabling users to develop not only their system control software in a high-level language, but also enabling development of math algorithms using C/C+. The device is as efficient at MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. 3.3.2 Memory Bus (Harvard Bus Architecture) As with many MCU-type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows: Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.) Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Program Reads Lowest: 3.3.3 (Simultaneous program reads and fetches cannot occur on the memory bus.) Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.) Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). 3.3.4 Real-Time JTAG and Analysis The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug. Additionally, the devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations while the processor is running and executing code and servicing interrupts. The user can also single step through non-time-critical code while enabling time-critical interrupts to be serviced without interference. The device implements the real-time mode in (1) 16 IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable break events when a match occurs. These devices do not support boundary scan; however, IDCODE and BYPASS features are available if the following considerations are taken into account. The IDCODE does not come by default. The user needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For BYPASS instruction, the first shifted DR value would be 1. Flash The F28027/25/23 F28027/25/23 devices contain 32K x 16 of embedded flash memory, segregated into four 8K x 16 sectors. The F28026/24/22 F28026/24/22 devices contain 16K x 16 of embedded flash memory, segregated into four 4K x 16 sectors. All devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 ­ 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 ­ 0x3F 7FF5 are reserved for data variables and should not contain program code. NOTE The Flash and OTP wait-states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait-states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the TMS320x2802x System Control and Interrupts Reference Guide (literature number SPRUFN3). 3.3.6 M0, M1 SARAMs All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages. 3.3.7 L0 SARAM The device contains 4K x 16 of single-access memory. This block is mapped to both program and data space. 3.3.8 Boot ROM The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Submit Documentation Feedback Functional Overview 17 ADVANCE INFORMATION 3.3.5 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 3-5. Boot Mode Selection MODE GPIO37/TDO GPIO37/TDO GPIO34/CMP2OUT GPIO34/CMP2OUT TRST 3 1 1 0 GetMode MODE 2 1 0 0 Wait (see Section 3.3.9 for description) 1 0 1 0 SCI 0 0 0 0 Parallel IO EMU x x 1 Emulation Boot 3.3.8.1 Emulation Boot When the emulator is connected, the GPIO37/TDO GPIO37/TDO pin cannot be used for boot mode selection. In this case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid, then the Wait boot option is used. All boot mode options can be accessed in emulation boot. 3.3.8.2 GetMode ADVANCE INFORMATION The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot option by programming two locations in the OTP. One of the following loaders can be specified: SCI, SPI, I2C, or OTP. If the content of either OTP location is invalid, then boot to flash is used 3.3.9 Security The devices support high levels of security to protect the user firmware from being reverse engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value that matches the value stored in the password locations within the Flash. In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0 memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory reads, the user must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the password locations are all ones (unprogrammed), then the KEY value does not need to match. When initially debugging a device with the password locations in flash programmed (i.e., secured), the CPU will start running and may execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will trip and cause the emulator connection to be cut. The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. The user can then exit this mode once the emulator is connected by using one of the emulation boot options as described in the TMS320x2802x Boot ROM Reference Guide (SPRUFN6). Piccolo devices do not support a hardware wait-in-reset mode. 18 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 NOTE When the code-security passwords are programmed, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. · If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 ­ 0x3F7FF5 are reserved for data and should not contain program code. The 128-bit password (at 0x3F 7FF8 ­ 0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device. · Disclaimer Code Security Module Disclaimer ADVANCE INFORMATION THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 3.3.10 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F2802x, 33 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12 INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block. 3.3.11 External Interrupts (XINT1-XINT3) The devices support three masked external interrupts (XINT1-XINT3). Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0 ­ GPIO31 GPIO31 pins. Submit Documentation Feedback Functional Overview 19 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.3.12 Internal Zero Pin Oscillators, Oscillator, and PLL The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to 12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode. 3.3.13 Watchdog Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either generate an interrupt or a device reset. 3.3.14 Peripheral Clocking ADVANCE INFORMATION The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to the CPU clock. 3.3.15 Low-power Modes The devices are full static CMOS devices. Three low-power modes are provided: IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode. STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event HALT: This mode basically shuts down the device and places it in the lowest possible power consumption mode. If the internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is used as the clock source, it is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPU-watchdog can wake the device from this mode. 3.3.16 Peripheral Frames 0, 1, 2 (PFn) The device segregates peripherals into three sections. The mapping of peripherals is as follows: PF0: Flash Waitstate Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers ADC: ADC Result Registers GPIO: GPIO MUX Configuration and Control Registers ePWM: Enhanced Pulse Width Modulator Module and Registers eCAP: Enhanced Capture Module and Registers Comparators: 20 PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: PF1: PIE: Comparator Modules Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 PF2: SYS: System Control Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Configuration Registers I2C: Inter-Integrated Circuit Module and Registers XINT External Interrupt Registers Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes. 3.3.18 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is connected to INT14 INT14 of the CPU. It can be clocked by any one of the following: · · · · SYSCLKOUT (default) Internal zero-pin oscillator 1 (INTOSC1) Internal zero-pin oscillator 2 (INTSOC2) External clock source CPU-Timer 1 is for general use and can be connected to INT13 INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block. 3.3.19 Control Peripherals The devices support the following peripherals that are used for embedded control and communication: ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the HRPWM high resolution duty and period features. The type 1 module found on 2802x devices also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced triggering including trip functions based on comparator outputs. eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal. ADC: The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned out, depending on the device. It contains two sample-and-hold units for simultaneous sampling. Comparator: Each comparator block consists of one analog comparator along with an internal 10-bit reference for supplying one input of the comparator. 3.3.20 Serial Port Peripherals Submit Documentation Feedback Functional Overview 21 ADVANCE INFORMATION 3.3.17 General-Purpose Input/Output (GPIO) Multiplexer TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com The devices support the following serial communication peripherals: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The SPI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. The SCI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. I2C: ADVANCE INFORMATION SPI: The inter-integrated circuit (I2C) module provides an interface between a MCU and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the MCU through the I2C module. The I2C contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. 3.4 Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3-6. Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3-7. Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 3-8. Table 3-6. Peripheral Frame 0 Registers (1) ADDRESS RANGE SIZE (×16) EALLOW PROTECTED (2) Device Emulation Registers 0x00 0880 - 0x00 09FF 384 Yes FLASH Registers (3) 0x00 0A80 - 0x00 0ADF 96 Yes Code Security Module Registers 0x00 0AE0 - 0x00 0AEF 16 Yes ADC registers 0 wait read only 0x00 0B00 - 0x00 0B0F 16 No CPU­TIMER0/1/2 Registers 0x00 0C00 - 0x00 0C3F 64 No PIE Registers 0x00 0CE0 - 0x00 0CFF 32 No PIE Vector Table 0x00 0D00 - 0x00 0DFF 256 No NAME (1) (2) (3) 22 Registers in Frame 0 support 16-bit and 32-bit accesses. If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents. The Flash Registers are also protected by the Code Security Module (CSM). Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-7. Peripheral Frame 1 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED Comparator 1 registers 0x00 6400 - 0x00 641F 32 (1) Comparator 2 registers 0x00 6420 - 0x00 643F 32 (1) EPWM1 + HRPWM1 registers 0x00 6800 - 0x00 683F 64 (1) EPWM2 + HRPWM2 registers 0x00 6840 - 0x00 687F 64 (1) EPWM3 + HRPWM3 registers 0x00 6880 - 0x00 68BF 64 (1) EPWM4 + HRPWM4 registers 0x00 68C0 - 0x00 68FF 64 (1) ECAP1 registers 0x00 6A00 - 0x00 6A1F 32 No GPIO registers 0x00 6F80 - 0x00 6FFF 128 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED System Control Registers 0x00 7010 - 0x00 702F 32 Yes SPI-A Registers 0x00 7040 - 0x00 704F 16 No SCI-A Registers 0x00 7050 - 0x00 705F 16 No NMI Watchdog Interrupt Registers 0x00 7060 - 0x00 706F 16 Yes External Interrupt Registers 0x00 7070 - 0x00 707F 16 Yes ADC Registers 0x00 7100 - 0x00 717F 32 (1) I2C-A Registers 0x00 7900 - 0x00 793F 64 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. 3.5 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-9. Table 3-9. Device Emulation Registers ADDRESS RANGE SIZE (x16) DEVICECNF 0x0880 0x0881 2 Device Configuration Register CLASSID 0x0882 1 Class ID Register NAME EALLOW PROTECTED DESCRIPTION Yes 0x00CF TMS320F28022 TMS320F28022 Submit Documentation Feedback 0x00C7 TMS320F28023 TMS320F28023 Revision ID Register 0x00CF TMS320F28024 TMS320F28024 1 0x00C7 TMS320F28025 TMS320F28025 0x0883 0x00CF TMS320F28026 TMS320F28026 REVID TMS320F28027 TMS320F28027 0x00C7 0x0000 - Silicon Rev. 0 - TMX No No Functional Overview 23 ADVANCE INFORMATION Table 3-8. Peripheral Frame 2 Registers TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.6 Interrupts Figure 3-4 shows how the various interrupt sources are multiplexed. Peripherals (SPI, SCI, EPWM, I2C, HRPWM, ECAP, ADC) WDINT WAKEINT Sync Watchdog LPMINT Low Power Modes XINT1 Interrupt Control MUX SYSCLKOUT XINT1 PIE C28 Core XINT2CTR(15:0) GPIOXINT1SEL(4:0) ADC XINT2 XINT2SOC XINT2 Interrupt Control XINT2CR(15:0) XINT3CTR(15:0) MUX ADVANCE INFORMATION INT1 to INT12 INT12 Up to 96 Interrupts XINT1CR(15:0) GPIOXINT2SEL(4:0) XINT3 Interrupt Control MUX GPIO0.int XINT3 GPIO MUX XINT3CR(15:0) GPIO31 GPIO31.int XINT3CTR(15:0) GPIOXINT3SEL(4:0) TINT0 CPU TIMER 0 INT13 INT13 TINT1 CPU TIMER 1 INT14 INT14 TINT2 CPU TIMER 2 NMI NMI interrupt with watchdog function (See the NMI watchdog section) CPUTMR2CLK CLOCKFAIL NMIRS System Control (See the system control section) Figure 3-4. External and PIE Interrupt Sources Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 3-10 shows the interrupts used by 2802x devices. The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior. When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth. 24 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 IFR(12:1) IER(12:1) INTM INT1 INT2 1 MUX INT11 INT11 INT12 INT12 INTx INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 MUX PIEACKx (Enable) From Peripherals or External Interrupts (Flag) PIEIERx(8:1) (Enable/Flag) Global Enable (Enable) ADVANCE INFORMATION (Flag) CPU 0 PIEIFRx(8:1) Figure 3-5. Multiplexing of Interrupts Using the PIE Block Submit Documentation Feedback Functional Overview 25 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 3-10. PIE MUXed Peripheral Interrupt Vector Table INTx.8 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1 (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 ­ (ADC) (ADC) 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40 Reserved Reserved Reserved Reserved EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT ­ ­ ­ ­ (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0xD5E INT3.y INTx.6 TINT0 0xD4E INT2.y INTx.7 WAKEINT (LPM/WD) INT1.y 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50 Reserved Reserved Reserved Reserved EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT (ePWM1) ­ INT4.y ­ ­ ­ (ePWM4) (ePWM3) (ePWM2) 0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60 Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAP1_INT (eCAP1) ­ INT5.y ­ ­ ­ ­ ­ ­ 0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ADVANCE INFORMATION ­ ­ ­ ­ ­ ­ 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80 Reserved Reserved Reserved Reserved Reserved Reserved SPITXINTA SPIRXINTA ­ ­ ­ ­ ­ (SPI-A) (SPI-A) 0xD9E INT7.y ­ 0xD8C ­ INT6.y ­ 0xD8E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ­ ­ ­ ­ ­ ­ 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0 Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A ­ ­ ­ ­ ­ (I2C-A) (I2C-A) 0xDBE INT9.y ­ 0xDAC ­ INT8.y ­ 0xDAE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0 Reserved Reserved Reserved Reserved Reserved Reserved SCITXINTA SCIRXINTA (SCI-A) ­ INT10 INT10.y ­ ­ ­ ­ ­ (SCI-A) 0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 (ADC) (ADC) (ADC) (ADC) (ADC) 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ­ ­ ­ ­ ­ ­ ­ 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved XINT3 ­ ­ ­ ­ ­ ­ ­ Ext. Int. 3 0xDFE 26 (ADC) 0xDDA 0xDEE INT12 INT12.y (ADC) 0xDDC ­ INT11 INT11.y (ADC) 0xDDE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-11. PIE Configuration and Control Registers DESCRIPTION (1) ADDRESS SIZE (x16) PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 PIEIER10 0x0CF4 1 PIE, INT10 INT10 Group Enable Register PIEIFR10 PIEIFR10 0x0CF5 1 PIE, INT10 INT10 Group Flag Register PIEIER11 PIEIER11 0x0CF6 1 PIE, INT11 INT11 Group Enable Register PIEIFR11 PIEIFR11 0x0CF7 1 PIE, INT11 INT11 Group Flag Register PIEIER12 PIEIER12 0x0CF8 1 PIE, INT12 INT12 Group Enable Register PIEIFR12 PIEIFR12 0x0CF9 1 PIE, INT12 INT12 Group Flag Register Reserved 0x0CFA 0x0CFF 6 Reserved (1) 3.6.1 ADVANCE INFORMATION NAME The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. External Interrupts Table 3-12. External Interrupt Registers NAME ADDRESS SIZE (x16) XINT1CR 0x00 7070 1 XINT1 configuration register XINT2CR 0x00 7071 1 XINT2 configuration register XINT3CR 0x00 7072 1 XINT3 configuration register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register XINT3CTR 0x00 707A 1 XINT3 counter register Submit Documentation Feedback DESCRIPTION Functional Overview 27 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge. For more information, see the TMS320x2802x System and Interrupts Reference Guide (literature number SPRUFN3). 3.7 VREG/BOR/POR Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and space of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode, eliminating a need for any external voltage supervisory circuits. 3.7.1 On-chip Voltage Regulator (VREG) ADVANCE INFORMATION A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the application. 3.7.1.1 Using the On-chip VREG To utilize the on-chip VREG, the VREGENZ pin should be pulled low and the appropriate recommended operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 µF capacitance for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. 3.7.1.2 Disabling the On-chip VREG To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be pulled high. 3.7.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled (VREGENZ pin is pulled low). Both functions pull the XRS pin low when one of the voltages is below their respective trip point. See the Section 6 for the various trip points as well as the delay time from the voltage rising past the trip point and the release of the XRS pin. Figure 3-6 shows the VREG, POR, and BOR. 28 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 In I/O Pin Out (Force HI-Z When High) DIR (0 = Input, 1 = Output) SYSRS Internal Weak PU XRS Sync RS MCLKRS PLL + Clocking Logic XRS Pin ADVANCE INFORMATION SYSCLKOUT Deglitch Filter C28 Core JTAG TCK Detect Logic VREGHALT (A) WDRST (B) PBRS POR/BOR Generating Module A. VREGENZ WDRST is the reset signal from the CPU-watchdog. B. On-Chip Voltage Regulator (VREG) PBRS is the reset signal from the POR/BOR module. Figure 3-6. VREG + POR + BOR + Reset Signal Connectivity Submit Documentation Feedback Functional Overview 29 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.8 System Control This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. Figure 3-7 shows the various clock domains that are discussed. Figure 3-8 shows the various clock sources (both internal and external) that can provide a clock for device operation. SYSCLKOUT LOSPCP (System Ctrl Regs) PCLKCR0/1/3 (System Ctrl Regs) Clock Enables I/O SPI-A, SCI-A C28x Core CLKIN LSPCLK Peripheral Registers PF2 Peripheral Registers PF1 Peripheral Registers PF1 Peripheral Registers PF2 Clock Enables ADVANCE INFORMATION I/O GPIO Mux eCAP1 Clock Enables I/O ePWM1/./4 Clock Enables I/O I2C-A Clock Enables 16 Ch ADC Registers PF2 PF0 Analog GPIO Mux Clock Enables 6 A. 12-Bit ADC COMP1/2 COMP Registers PF1 CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT). Figure 3-7. Clock and Reset Domains 30 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 CLKCTL[WDCLKSRCSEL] INTOSC1TRIM Reg Internal OSC 1 (10 MHz) (A) 0 OSC1CLK OSCCLKSRC1 WDCLK CPU-watchdog (OSC1CLK on XRS reset) OSCE 1 CLKCTL[INTOSC1OFF] 1 = Turn OSC Off CLKCTL[OSCCLKSRCSEL] WAKEOSC ADVANCE INFORMATION CLKCTL[INTOSC1HALT] 1 = Ignore HALT INTOSC2TRIM Reg Internal OSC2CLK OSC 2 (10 MHz) (A) 0 OSCCLK PLL/Missing Clock-detect circuit (OSC1CLK on XRS reset) (B) 1 OSCE CLKCTL[TRM2CLKPRESCALE] CLKCTL[TMR2CLKSRCSEL] 1 = Turn OSC Off 10 CLKCTL[INTOSC2OFF] 11 1 = Ignore HALT 1 Prescale /1, /2, /4, /8, /16 01, 10, 11 CPUTMR2CLK 01 00 CLKCTL[INTOSC2HALT] SYSCLKOUT OSCCLKSRC2 0 0 = GPIO38 GPIO38 1 = GPIO19 GPIO19 XCLK[XCLKINSEL] SYNC Edge Detect CLKCTL[OSCCLKSRC2SEL] CLKCTL[XCLKINOFF] 0 XCLKIN GPIO19 GPIO19 or GPIO38 GPIO38 1 0 XCLKIN X1 (Crystal) OSC XTAL EXTCLK WAKEOSC (Oscillators enabled when this signal is high) X2 CLKCTL[XTALOSCOFF] 0 = OSC on (default on reset) 1 = Turn OSC off A. Register loaded from TI OTP-based calibration function. B. See Section 3.8.4 for details on missing clock detection. Figure 3-8. Clock Tree Submit Documentation Feedback Functional Overview 31 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 3.8.1 www.ti.com Internal Zero Pin Oscillators The F2802x devices contain two independent internal zero pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user. The center frequency of these oscillators is determined by their respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See the electrical section for more information on these oscillators. 3.8.2 External Reference Oscillator Clock Option ADVANCE INFORMATION The typical specifications for the external quartz crystal for a frequency of 10 MHz are listed below: · Fundamental mode, parallel resonant · CL (load capacitance) = 12 pF · CL1 = CL2 = 24 pF · Cshunt = 6 pF · ESR range = 30 to 60 TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range. Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers NAME ADDRESS SIZE (x16) DESCRIPTION (1) XCLK 0x00 7010 1 XCLKOUT Control PLLSTS 0x00 7011 1 PLL Status Register CLKCTL 0x00 7012 1 Clock Control Register PLLLOCKPRD 0x00 7013 1 PLL Lock Period INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register WDKEY 0x00 7025 1 Watchdog Reset Key Register WDCR 0x00 7029 1 Watchdog Control Register (1) All registers in this table are EALLOW protected. XCLKIN/GPIO19/38 XCLKIN/GPIO19/38 External Clock Signal (Toggling 0-VDDIO) X1 X2 NC Figure 3-9. Using a 3.3-V External Oscillator 32 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 XCLKIN/GPIO19/38 XCLKIN/GPIO19/38 X1 Turn off CL1 XCLKIN path in CLKCTL register A. X2 CL2 Crystal X1/X2 pins are available in 48-pin package only. Figure 3-10. Using the On-chip Crystal Oscillator PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is at least 50 MHz. Table 3-14. PLL Settings SYSCLKOUT (CLKIN) PLLCR[DIV] VALUE (1) (2) PLLSTS[DIVSEL] = 0 or 1 (3) OSCCLK (OSCCLK * 1)/4 (OSCCLK * 1)/2 ­ (OSCCLK * 2)/4 (OSCCLK * 2)/2 ­ 0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 ­ 0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 ­ 0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 ­ 0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 ­ 0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 ­ 1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 ­ 1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 ­ 1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 ­ 1011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 ­ 1100 (3) OSCCLK/2 0010 (2) PLLSTS[DIVSEL] = 3 OSCCLK/4 (Default) (1) 0001 (1) PLLSTS[DIVSEL] = 2 0000 (PLL bypass) (OSCCLK * 12)/4 (OSCCLK * 12)/2 ­ The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic has no effect. This register is EALLOW protected. See the TMS320x2802x System and Interrupts Reference Guide (literature number SPRUFN3 ) for more information. By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. Table 3-15. CLKIN Divide Options PLLSTS [DIVSEL] CLKIN DIVIDE 0 /4 1 /4 2 (1) Submit Documentation Feedback /2 3 /1 (1) This mode can be used only when the PLL is bypassed or off. Functional Overview 33 ADVANCE INFORMATION 3.8.3 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com ADVANCE INFORMATION The PLL-based clock module provides four modes of operation: · INTOSC1 (Internal zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock for the Watchdog block, core and CPU-Timer 2 · INTOSC2 (Internal zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen for the Watchdog block, core and CPU-Timer 2. · Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 2-2 for details. · External clock source operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. Note that the XCLKIN is multiplexed with GPIO19 GPIO19 or GPIO38 GPIO38 pin. The XCLKIN input can be selected as GPIO19 GPIO19 or GPIO38 GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input (forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable at boot time. Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock source must be disabled (using the CLKCTL register) before switching clocks. Table 3-16. Possible PLL Configuration Modes REMARKS PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT PLL Off Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block is disabled in this mode. This can be useful to reduce system noise and for low power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is derived directly from the input clock on either X1/X2, X1 or XCLKIN. 0, 1 2 3 OSCCLK/4 OSCCLK/2 OSCCLK/1 PLL Bypass PLL Bypass is the default PLL configuration upon power-up or after an external reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or while the PLL locks to a new frequency after the PLLCR register has been modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. 0, 1 2 3 OSCCLK/4 OSCCLK/2 OSCCLK/1 PLL Enable Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the PLLCR the device will switch to PLL Bypass mode until the PLL locks. 0, 1 2 OSCCLK*n/4 OSCCLK*n/2 PLL MODE 3.8.4 Loss of Input Clock (NMI watchdog function) The 2802x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1-5 MHz. When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt. Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a shut-down procedure for the system. If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a preprogrammed time interval. Figure 3-11 shows the interrupt mechanisms involved. 34 Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 NMIFLG[NMINT] NMIFLGCLR[NMINT] Clear Latch Set Clear XRS NMINT Generate Interrupt Pulse When Input = 1 1 0 NMIFLG[CLOCKFAIL] Clear Latch Clear Set 0 NMIFLGCLR[CLOCKFAIL] CLOCKFAIL SYNC? SYSCLKOUT NMICFG[CLOCKFAIL] NMIFLGFRC[CLOCKFAIL] SYSCLKOUT SYSRS NMIWDPRD[15:0] NMIWDCNT[15:0] NMI Watchdog NMIRS See System Control Section Figure 3-11. NMI-watchdog 3.8.5 CPU-Watchdog Module The CPU-watchdog module on the 2802x device is similar to the one used on the 281x/280x/283xx devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter. Figure 3-12 shows the various functional blocks within the watchdog module. Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). NOTE The CPU-watchdog counter is different from the NMI watchdog. It is the legacy watchdog counter that is present in all 28x devices. NOTE Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory. Submit Documentation Feedback Functional Overview 35 ADVANCE INFORMATION XRS TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com WDCR (WDPS[2:0]) WDCR (WDDIS) WDCNTR(7:0) WDCLK Watchdog Prescaler /512 WDCLK 8-Bit Watchdog Counter CLR Clear Counter Internal Pullup WDKEY(7:0) Watchdog 55 + AA Key Detector WDRST Generate Output Pulse WDINT (512 OSCCLKs) Good Key XRS ADVANCE INFORMATION Bad WDCHK Key Core-reset WDCR (WDCHK[2:0]) 1 WDRST(A) A. 0 SCSR (WDENINT) 1 The WDRST signal is driven low for 512 OSCCLK cycles. Figure 3-12. CPU-watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.9, Low-Power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset. 3.9 Low-power Modes Block Table 3-17 summarizes the various modes. Table 3-17. Low-power Modes EXIT (1) MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT IDLE 00 On On On XRS, CPU-watchdog interrupt, any enabled interrupt STANDBY 01 On (CPU-watchdog still running) Off Off XRS, CPU-watchdog interrupt, GPIO Port A signal, debugger (2) 1X Off (on-chip crystal oscillator and PLL turned off, zero-pin oscillator and CPU-watchdog state dependent on user code.) Off Off XRS, GPIO Port A signal, debugger (2), CPU-watchdog HALT (1) (2) (3) 36 (3) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power mode will not be exited and the device will go back into the indicated low power mode. The JTAG port can still function even if the CPU clock (CLKIN) is turned off. The WDCLK must be active for the device to go into HALT mode. Functional Overview Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register. Submit Documentation Feedback Functional Overview ADVANCE INFORMATION NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x2802x System and Interrupts Reference Guide (literature number SPRUFN3) for more details. 37 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 4 Peripherals 4.1 Analog Block A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x. The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing control of start of conversions. 38-Pin 48-Pin VDDA VDDA (3.3 V) VDDA (Agnd) VSSA VREFLO VREFLO VREFLO Tied To Tied To VSSA VSSA Interface Reference Diff VREFHI VREFHI Tied To Tied To A0 A0 VREFHI A0 B0 A1 A2 A1 B1 A2 A4 A6 A6 A7 B1 B2 B2 B4 B4 B6 B6 B3 B7 COMP1OUT A2 A4 AIO2 AIO10 AIO10 B2 Simultaneous Sampling Channels ADVANCE INFORMATION A3 10-Bit DAC Comp1 A3 B3 ADC COMP2OUT A4 AIO4 AIO12 AIO12 B4 10-Bit DAC Comp2 B5 A5 A6 Signal Pinout AIO6 AIO14 AIO14 B6 A7 B7 Figure 4-1. Analog Pin Configurations Figure 4-2 shows the interaction of the analog module with the rest of the F2802x system. 4.1.1 ADC Table 4-1. ADC Configuration and Control Registers REGISTER NAME ADDRESS SIZE (x16) ADCCTL1 0x7100 1 Yes Control 1 Register ADCINTFLG 0x7104 1 No Interrupt Flag Register ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register ADCINTOVF 0x7106 1 No Interrupt Overflow Register ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register ADCINTSEL1AND2 0x7108 1 Yes Interrupt 1 and 2 Selection Register ADCINTSEL3AND4 0x7109 1 Yes Interrupt 3 and 4 Selection Register ADCINTSEL5AND6 0x710A 1 Yes Interrupt 5 and 6 Selection Register ADCINTSEL7AND8 0x710B 1 Yes Interrupt 7 and 8 Selection Register ADCINTSEL9AND10 ADCINTSEL9AND10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection) ADCSOCPRIORITYCTL 0x7110 1 Yes SOC Priority Control Register ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels) ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels) 38 Peripherals EALLOW DESCRIPTION PROTECTED Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 Table 4-1. ADC Configuration and Control Registers (continued) REGISTER NAME ADDRESS SIZE (x16) 0x7118 1 No SOC Flag 1 Register (for 16 channels) ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels) ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels) ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels) ADCSOC0CTL to ADCSOC15CTL ADCSOC15CTL 0x7120 0x712F 1 Yes SOC0 Control Register to SOC15 SOC15 Control Register ADCREFTRIM 0x7140 1 Yes Reference Trim Register ADCOFFTRIM 0x7141 1 Yes Offset Trim Register ADCREV 0x714F 1 No Revision Register ADCSOCFLG1 EALLOW DESCRIPTION PROTECTED Address Size (x16) EALLOW Protected ADCRESULT0 to ADCRESULT15 ADCRESULT15 0xB00 0xB0F 1 No 0-Wait Result Registers ADVANCE INFORMATION Table 4-2. ADC Result Registers (mapped to PF0) Name Description ADC Result 0 Register to ADC Result 15 Register PF0 (CPU) PF2 (CPU) SYSCLKOUT ADCENCLK ADCINT 1 PIE ADCINT 9 AIO MUX ADC Channels ADC Core 12-Bit ADCTRIG 1 ADCTRIG 2 ADCTRIG 3 ADCTRIG 4 ADCTRIG 5 ADCTRIG 6 ADCTRIG 7 ADCTRIG 8 ADCTRIG 9 ADCTRIG 10 ADCTRIG 11 ADCTRIG 12 TINT 0 TINT 1 TINT 2 XINT 2SOC CPUTIMER 0 CPUTIMER 1 CPUTIMER 2 XINT 2 SOCA 1 SOCB 1 EPWM 1 SOCA 2 SOCB 2 EPWM 2 SOCA 3 SOCB 3 EPWM 3 SOCA 4 SOCB 4 EPWM 4 Figure 4-2. ADC Connections Submit Documentation Feedback Peripherals 39 TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 4.1.2 www.ti.com ADC MUX To COMPy A or B input To ADC Channel X Logic implemented in GPIO MUX block AIOx Pin SYSCLK AIOxIN 1 AIOxINE AIODAT Reg (Read) SYNC ADVANCE INFORMATION 0 AIOxDIR (1 = Input, 0 = Output) AIODAT Reg (Latch) AIOSET, AIOCLEAR, AIOTOGGLE Regs AIOMUX 1 Reg AIODIR Reg (Latch) 1 1 (0 = Input, 1 = Output) IORS 0 0 Figure 4-3. ADC MUX The ADC channel and Comparator functions are always available. The digital I/O function is available only when the respective bit in the AIOMUX1 register is set to 1. In this mode, reading the AIODAT register reflects the actual pin state. The digital I/O function is disabled when the respective bit in the AIOMUX1 register is cleared to 0. In this mode, reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer is disabled to prevent analog signals from generating noise. On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO function disabled for that pin. 4.1.3 Comparator Block Figure 4-4 shows the interaction of the Comparator modules with the rest of the system 40 Peripherals Submit Documentation Feedback TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers www.ti.com SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 COMP x A COMP x B + COMP - GPIO MUX TZ1/2/3 COMP x + DAC x Wrapper AIO MUX EPWM COMPxOUT Figure 4-4. Comparator Block Diagram Table 4-3. Comparator Control Registers REGISTER NAME COMP1 ADDRESS COMP2 ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION COMPCTL 0x6400 0x6420 1 Yes Comparator Control Register COMPSTS 0x6402 0x6422 1 No Comparator Status Register DACVAL 0x6406 0x6426 1 Yes DAC Value Register Submit Documentation Feedback Peripherals 41 ADVANCE INFORMATION DAC Core 10-Bit TMS320F28022 TMS320F28022, TMS320F28023 TMS320F28023, TMS320F28024 TMS320F28024 TMS320F28025 TMS320F28025, TMS320F28026 TMS320F28026, TMS320F28027 TMS320F28027 Piccolo Microcontrollers SPRS523A SPRS523A ­ NOVEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 4.1 Serial Peripheral Interface (SPI) Module The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. ADVANCE INFORMATION The SPI module features include: · Four external pins: ­ SPISOMI: SPI slave-output/master-input pin ­ SPISIMO: SPI slave-input/master-output pin ­ SPISTE: SPI slave transmit-enable pin ­ SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO if the SPI module is not used. · Two operational modes: master and slave Baud rate: 125 different programmable rates. Baud rate = Baud rate = · · · · · LSPCLK (SPIBRR ) 1) LSPCLK 4 when SPIBRR = 3 to 127 when SPIBRR = 0,1, 2 Data word length: one to sixteen data bits Four clocking schemes (controlled by clock polarity and clock phase bits) include: ­ Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. ­ Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. ­ Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. ­ Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver oper