TMS320DM6443 SPRS282E ARM926EJ-STM ARM926EJ-S ETB11TM AIC12 IEEE-1149 DM6443 - Datasheet Archive

 

Digital Media System-on-Chip www.ti.com SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 1 Digital Media System-on-Chip

 

TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 1 Digital Media System-on-Chip (DMSoC) 1.1 Features · · · · High-Performance Digital Media SoC ­ 594-MHz C64x+TM Clock Rate ­ 297-MHz ARM926EJ-STM ARM926EJ-STM Clock Rate ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 4752 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) ­ 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) ­ 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) · · · · · · · ARM926EJ-S ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 16K-Byte RAM ­ 8K-Byte ROM Emulation Trace BufferTM (ETB11TM ETB11TM) With 4-KB Memory for ARM9 Debug Endianness: Little Endian for ARM and DSP Video Processing Subsystem ­ Resize Engine Provides: · Resize Images From 1/4x to 4x · Separate Horizontal and Vertical Control ­ Back End Provides: · Hardware On-Screen Display (OSD) · 4 - 54 MHz DACs for a Combination of · Composite NTSC/PAL Video · Luma/Chroma Separate Video (S-video) · Component (YPbPr or RGB) Video (Progressive) · Digital Output · 8-/16-Bit YUV or up to 24-Bit RGB · HD Resolution · Up to 2 Video Windows External Memory Interfaces (EMIFs) ­ 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O) ­ Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) Flash Card Interfaces ­ Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) ­ Compact Flash Controller With True IDE Mode Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005­2007, Texas Instruments Incorporated TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 · · · · · · · · · · ­ SmartMedia Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) One 64-Bit Watch Dog Timer Three UARTs (One with RTS and CTS Flow Control) One Serial Port Interface (SPI) with Two Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Audio Serial Port (ASP) ­ I2S ­ AC97 Audio Codec Interface ­ Standard Voice Codec Interface (AIC12 AIC12) 10/100 Mb/s Ethernet MAC (EMAC) ­ IEEE 802.3 Compliant ­ Media Independent Interface (MII) VLYNQTM Interface (FPGA Interface) Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data · · · · · · · · · · · · USB Port With Integrated 2.0 PHY ­ USB 2.0 High-/Full-Speed (480 Mbps) Client ­ USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) Three Pulse Width Modulator (PWM) Outputs On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART ATA/ATAPI I/F (ATA/ATAPI-6 Specification) Individual Power-Saving Modes for ARM/DSP Flexible PLL Clock Generators IEEE-1149 IEEE-1149.1 (JTAG) BoundaryScan-Compatible Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch 0.09-µm/6-Level Cu Metal Process (CMOS) 3.3-V and 1.8-V I/O, 1.2-V Internal Applications: ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging 1.2 Description The TMS320DM6443 TMS320DM6443 (also referenced as DM6443 DM6443) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM6443 DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the DM6443 DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S ARM926EJ-S core. The ARM926EJ-S ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates: · A coprocessor 15 (CP15) and protection module · Data and program Memory Management Units (MMUs) with table look-aside buffers. · Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The TMS320C64x+TM DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000TM TMS320C6000TM DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000TM C6000TM DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set. 2 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback www.ti.com TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 SPRU732). The DM6443 DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 C6000 DSP platform devices. The DM6443 DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6443 DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N 256/N, where N is between 64 and 1024. The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and the network. The DM6443 DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses. The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 DM6443 also provides multimedia card support, MMC/SD, with SDIO support. Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) 3 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6443 DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution. 4 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the device. Video-Imaging Coprocessor (VICP) JTAG Interface System Control Input Clock(s) ARM Subsystem ARM926EJ-S ARM926EJ-S CPU Video Processing Subsystem (VPSS) DSP Subsystem PLLs/Clock Generator BT.656, Y/C, Raw (Bayer) C64x+ t DSP CPU Power/Sleep Controller 16 KB I-Cache 64 KB L2 RAM 8 KB D-Cache 32 KB L1 Pgm 16 KB RAM Pin Multiplexing 80 KB L1 Data 16 KB ROM Front End Back End Resizer CCD Controller Histogram/ 3A Video Preview Interface 8b BT.656, Y/C, 24b RGB On-Screen Video 10b DAC Display Encoder 10b DAC (OSD) (VENC) 10b DAC 10b DAC NTSC/ PAL, S-Video, RGB, YPbPr Switched Central Resource (SCR) Peripherals Serial Interfaces Audio Serial Port EDMA I2 C SPI System UART VLYNQ EMAC With MDIO Watchdog Timer PWM Program/Data Storage Connectivity USB 2.0 PHY GeneralPurpose Timer HPI DDR2 Mem Ctlr (16b/32b) Async EMIF/ NAND/ SmartMedia ATA/ Compact Flash MMC/ SD/ SDIO Figure 1-1. TMS320DM6443 TMS320DM6443 Functional Block Diagram Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) 5 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Contents 6.1 6.2 Parameter Information . 87 Recommended Clock and Control Signal Transition Behavior . 88 Functional Block Diagram . 5 6.3 Power Supplies . 88 Revision History . 7 2 Device Overview . 9 6.4 Reset . 98 6.5 External Clock Input From MXI/CLKIN Pin 2.1 Device Characteristics . 9 6.6 Clock PLLs . 104 2.2 Device Compatibility. 10 6.7 Interrupts . 111 6.8 6.9 General-Purpose Input/Output (GPIO). 118 Enhanced Direct Memory Access (EDMA) Controller . 121 6.10 External Memory Interface (EMIF) . 133 6.11 ATA/CF 6.12 MMC/SD/SDIO . 154 6.13 Video Processing Sub-System (VPSS) Overview . 157 6.14 Host-Port Interface (HPI). 173 6.15 6.16 USB 2.0 . 176 Universal Asynchronous Receiver/Transmitter (UART) . 185 64 6.17 Serial Port Interface (SPI). 188 67 6.18 Inter-Integrated Circuit (I2C) . 192 80 6.19 Audio Serial Port (ASP) . 196 82 6.20 Ethernet Media Access Controller (EMAC) . 200 83 6.21 Management Data Input/Output (MDIO) . 206 84 6.22 Timer . 208 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) . 84 6.23 Pulse Width Modulator (PWM). 210 6.24 VLYNQ . 212 Recommended Operating Conditions . 85 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) . 86 6.25 IEEE 1149.1 JTAG 1 Digital Media System-on-Chip (DMSoC) . 1 1.1 Features . 1 1.2 Description . 2 1.3 . 2.4 DSP Subsystem . 2.5 Memory Map Summary . 2.6 Pin Assignments . 2.7 Terminal Functions . 2.8 Device Support . Device Configurations. 3.1 System Module Registers . 3.2 Power Considerations . 3.3 Bootmode . 3.4 Configurations at Reset . 3.5 Configurations After Reset . 3.6 Emulation Control . System Interconnect . 4.1 System Interconnect Block Diagram . Device Operating Conditions . 2.3 3 4 5 5.1 5.2 5.3 6 6 ARM Subsystem 10 15 19 22 27 56 59 59 59 60 Peripheral and Electrical Specifications. 87 Contents 7 . . . 101 141 216 Mechanical Packaging and Orderable Information . 218 7.1 Thermal Data for ZWT . 218 7.2 Packaging Information . 218 Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Revision History This data manual revision history highlights the technical changes made to the SPRS282D SPRS282D device-specific data manual to make it an SPRS282E SPRS282E revision. Scope: Applicable updates to the DM64x device family, specifically relating to the TMS320DM6443 TMS320DM6443 device, have been incorporated. TMS320DM6443 TMS320DM6443 Revision History SEE Global ADDITIONS/MODIFICATIONS/DELETIONS Changed instances of MMC/SD to MMC/SD/SDIO to indicate secure data I/O support Section 1.1 Features: Added Secure Data I/O (SDIO) under Flash Card Interfaces Added Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data Section 1.2 Description: Updated paragraph, The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 DM6443 . . . Section 1.3 Functional Block Diagram: Added HPI and SDIO to Figure 1-1, TMS320DM6443 TMS320DM6443 Functional Block Diagram Table 2-1 Section 2.5 Section 2.6.1 Characteristics of the Processor: Updated description for Peripherals Flash Cards Added row for HPI Peripheral Added row for C64x+ Megamodule Revision feature Memory Map Summary: Added HPI column to Table 2-3, Memory Map Summary Deleted AET Registers from address 0x01BC 0000 and replaced with Reserved in Table 2-4, Configuration Memory Map Summary Added HPI to address 0x01C6 7800 in Table 2-4, Configuration Memory Map Summary Pin Map (Bottom View): Updated Figure 2-5, Pin Map [Quadrant D] Section 2.7 Terminal Functions: Added HPI Signal Names and Descriptions for multiplexed pins in Table 2-9, EMIFA Terminal Functions Updated Descriptions in Table 2-6, Oscillator/PLL Terminal Functions Updated Descriptions in Table 2-17, USB Terminal Functions Updated Descriptions in Table 2-20, DAC [Part of VPBE] Terminal Functions Changed title of Table 2-24 to MMC/SD/SDIO Terminal Functions Added Table 2-25, HPI Terminal Functions Section 3.1 System Module Registers: Changed address 0x01C4 0028 to JTAGID register Added HPI_CTL register and description to address 0x01C4 0030 in Table 3-1, System Module Register Memory Map Section 3.3.1.1 BOOTCFG Register Description: Changed bit field BTSEL description for value 10 in Table 3-4, BOOTCFG Register Description Section 3.3.2 ARM Boot: Updated paragraphs Updated Table 3-6, ARM Boot Modes Section 3.3.3 DSP Boot: Added row for HPI to Table 3-7, DSP Boot Modes Section 3.4.1 Device Configuration at Device Reset: Changed description for value 10 in Table 3-8, Device Configurations (Input Pins Sampled at Reset) Section 3.5.1 Switched Central Resource (SCR) Bus Priorities: Added row for HPI in Table 3-12, DM6443 DM6443 Default Bus Master Priorities Section 3.5.2 Multiplexed Pin Configurations: Added HPI pin information to Table 3-13, DM6443 DM6443 Multiplexed Peripheral Pins and Multiplexing Controls Section 3.5.4 PINMUX0 Register Description: Added HPIEN to bit field 29 in Figure 3-7, PINMUX0 Register Added HPIEN description to Table 3-14, PINMUX0 Register Description Section 3.5.6 Pin Multiplexing Register Field Details Added new Section 3.5.6.10, HPI and EMIFA/ATA Pin Multiplexing Section 3.6 Submit Documentation Feedback Emulation Control: Added HPISRC to bit field 12 in Figure 3-9, Emulation Suspend Source Register (SUSPSRC) Added bit field HPISRC description to Table 3-33, SUSPSRC Register Description Revision History 7 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 TMS320DM6443 TMS320DM6443 Revision History (continued) SEE Section 4 Section 5.3 ADDITIONS/MODIFICATIONS/DELETIONS Added new section, System Interconnect Added Footnotes (5) and (6) to Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Section 6.3.1.3 DM6443 DM6443 Power and Clock Domains: Added row for HPI to Table 6-3, DM6443 DM6443 Power and Clock Domains Added HPI box to Figure 6-6, PLL1 and PLL2 Clock Domain Block Diagram Section 6.3.1.4 Power and Sleep Controller (PSC) Module: Added HPI to Table 6-5, DM6443 DM6443 LPSC Assignments Added HPI registers to Table 6-6, PSC Register Memory Map Section 6.4.1 Reset Electrical Data/Timing: Updated Parameter 1 Description inTable 6-8, Timing Requirements for Reset Updated Parameter 26 Description and MAX value in Table 6-9, Switching Characteristics Over Recommended Operating Conditions During Reset Section 6.5 Changed section title to External Clock Input From MXI/CLKIN Pin Updated entire section Section 6.6 Clock PLLs: Added new Section 6.6.1, PLL1 and PLL2 Section 6.7.1 ARM CPU Interrupts: Added Interrupt 23, HPINT, to Table 6-20, DM6443 DM6443 ARM Interrupts Section 6.7.2 DSP Interrupts: Deleted AEGMUX0 and AEGMUX1 registers and replaced with Reserved in Table 6-23, C64x+ Interrupt Controller Registers Section 6.9 Section 6.9.2 Enhanced Direct Memory Access (EDMA) Controller: Added paragraph EDMA Peripheral Register Descriptions: Updated Global Registers Hex Addresses for Reserved registers (0x01c0 0264 - 0x01c0 0283 and 0x01c0 0288 - 0x01c0 02FF) Section 6.10.1.1 NAND (NAND, SmartMedia, xD): Changed CS0 to CS2 in the last bulleted item Section 6.10.1.2 EMIFA Electrical Data/Timing : Updated Table 6-35, Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module Updated Figure 6-21, Asynchronous Memory Read Timing for EMIF Updated Figure 6-22, Asynchronous Memory Write Timing for EMIF Section 6.13 Section 6.13.2.3 Section 6.14 Section 6.13.2.4 Section 6.16.2 Video Processing Sub-System (VPSS) Overview: Added paragraph and equations after Table 6-46 VPBE Electrical Data/Timing: Updated Parameters 18 and 19 and added Footnote (3) in Table 6-56, Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK Added new section, Host Port Interface (HPI) DAC Electrical/Data Timing: Updated Figure 6-51, Typical Output Circuit for NTSC/PAL Video From DACs UART Electrical Data/Timing: Updated Parameters 4 and 5 MIN values in Table 6-69, Timing Requirements for UARTx Receive Section 6.17.2.1 SPI Master Mode Timings (Clock Phase = 0): Updated Parameters 10 and 11 MIN values in Table 6-74, Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode [Clock Phase = 0] Section 6.17.2.2 SPI Master Mode Timings (Clock Phase = 1): Updated Parameters 19 and 20 MIN values in Table 6-76, Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode [Clock Phase = 1] Section 6.18 Section 6.18.2 8 Revision History Inter-Integrated Circuit (I2C): Added Caution I2C Electrical Data/Timing: Updated Table 6-79, Switching Characteristics for I2C Timings Updated Figure 6-62, I2C Transmit Timings Added Caution Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the TMS320DM6443 TMS320DM6443 SoC. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count. Table 2-1. Characteristics of the Processor HARDWARE FEATURES DM6443 DM6443 DDR2 Memory Controller DDR2 (16/32-bit bus width) Asynchronous EMIF (EMIFA) Asynchronous (8/16-bit bus width) RAM, Flash (NOR,NAND) Flash Cards Compact Flash MMC/SD with secure data input/output (SDIO) SmartMedia/xD EDMA 64 independent channels 8 QDMA channels Timers 2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers) 1 64-Bit Watch Dog Peripherals UART 3 (one with RTS and CTS flow control) Not all peripherals pins are available at the same time (for more detail, see the Device Configurations section). SPI 1 (supports 2 slave devices) I2C 1 (Master/Slave) Audio Serial Port [ASP] 1 10/100 Ethernet MAC with Management Data Input/Output 1 VLYNQ 1 HPI 1 (16-bit multiplexed address/data) General-Purpose Input/Output Port Up to 71 PWM 3 outputs ATA/CF 1 (ATA/ATAPI-6) Configurable Video Port Resizer 1 Output (VPBE) High Speed Device High Speed Host USB 2.0 Size (Bytes) On-Chip Memory 160KB 160KB RAM, 8KB ROM DSP · 32KB L1 Program (L1P)/Cache (up to 32KB) · 80KB L1 Data (L1D)/Cache (up to 32KB) · 64KB Unified Mapped RAM/Cache (L2) ARM · 16KB I-cache · 8KB D-cache · 16KB RAM · 8KB ROM Organization CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1000 C64x+ Megamodule Revision Revision ID Register (MM_REVID[15:0]) (address location: 0x0181 2000) 0x0000 JTAG BSDL_ID JTAGID Register (address location: 0x01C4 0028) CPU Frequency (Maximum) MHz Submit Documentation Feedback 0x0B70 002F DM6443 DM6443 -594 DSP 594 MHz ARM 297 MHz Device Overview 9 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-1. Characteristics of the Processor (continued) HARDWARE FEATURES Cycle Time (Minimum) ns DM6443 DM6443 DM6443 DM6443 -594 ARM 3.37 ns Core (V) 1.2 V (-594) I/O (V) Voltage 1.8 V, 3.3 V PLL Options CLKIN frequency multiplier (27 MHz reference) BGA Package 16 x 16 mm Process Technology µm Product Status (1) Product Preview (PP), Advance Information (AI), or Production Data (PD) (1) DSP 1.68 ns x1 (Bypass), x22 (-594) 357-Pin BGA (ZWT) 0.09 µm PD PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2.2 Device Compatibility The ARM926EJ-S ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. The C64x+ DSP core is code-compatible with the C6000TM C6000TM DSP platform and supports features of the C64x DSP family. 2.3 ARM Subsystem The ARM Subsystem is designed to give the ARM926EJ-S ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP Subsystem, the VPSS Subsystem, and a majority of the peripherals and external memories. The ARM Subsystem includes the following features: · ARM926EJ-S ARM926EJ-S RISC processor · ARMv5TEJ (32/16-bit) instruction set · Little endian · Co-Processor 15 (CP15) · MMU · 16KB Instruction cache · 8KB Data cache · Write Buffer · 16KB Internal RAM (32-bit wide access) · 8KB Internal ROM (ARM bootloader for non-EMIFA boot options) · Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) · ARM Interrupt controller · PLL Controller · Power and Sleep Controller (PSC) · System Module 2.3.1 ARM926EJ-S ARM926EJ-S RISC CPU The ARM Subsystem integrates the ARM926EJ-S ARM926EJ-S processor. The ARM926EJ-S ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The 10 Device Overview Submit Documentation Feedback www.ti.com TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 ARM926EJ-S ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. The ARM926EJ-S ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including: · ARM926EJ ARM926EJ -S integer core · CP15 system control coprocessor · Memory Management Unit (MMU) · Separate instruction and data Caches · Write buffer · Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces · Separate instruction and data AHB bus interfaces · Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S ARM926EJ-S Technical Reference Manual, available at http://www.arm.com 2.3.2 CP15 The ARM926EJ-S ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode. 2.3.3 MMU The ARM926EJ-S ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux®, Windows® CE, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are: · Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme. · Mapping sizes are: ­ 1MB (sections) ­ 64KB (large pages) ­ 4KB (small pages) ­ 1KB (tiny pages) · Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) · Hardware page table walks · Invalidate entire TLB, using CP15 register 8 · Invalidate TLB entry, selected by MVA, using CP15 register 8 · Lockdown of TLB entries, using CP15 register 10 2.3.4 Caches and Write Buffer The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following features: · Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA) Submit Documentation Feedback Device Overview 11 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 · · · · · · Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables. Critical-word first cache refilling Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address. Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory. The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry. 2.3.5 Tightly Coupled Memory (TCM) ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM and ROM memories interfaced to the ARM926EJ-S ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S ARM926EJ-S has built-in DMA support for direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers. Instruction and Data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. The instruction region at 0x0000 and data region at 0x8000 map to the same physical 16KB TCM RAM. Placing the instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000, as required by the ARM architecture. The internal 16-KB 16-KB RAM is split into two physical banks of 8KB each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks. The ARM926EJ-S ARM926EJ-S has built in DMA support for direct accesses to the ARM internal memory from a nonARM device. Furthermore, because of the time critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers. 2.3.6 Advanced High-Performance Bus (AHB) The ARM Subsystem uses the AHB port of the ARM926EJ-S ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus. 2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) To support real-time trace, the ARM926EJ-S ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J ARM926ES-J Subsystem in the DM6443 DM6443 also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts: · Trace Port provides real-time trace capability for the ARM9. · Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. 12 Device Overview Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 The DM6443 DM6443 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data. 2.3.8 ARM Memory Mapping The ARM memory map is shown in Section 2.5, Memory Map Summary of this document. The ARM has access to memories shown in the following sections. 2.3.8.1 ARM Internal Memories The ARM has access to the following ARM internal memories: · 16KB ARM Internal RAM on TCM interface, logically separated into two 8KB pages to allow simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data (D-TCM) to the different memory regions. · 8KB ARM Internal ROM 2.3.8.2 External Memories The ARM has access to the following external memories: · DDR2 Synchronous DRAM · Asynchronous EMIF / NOR Flash / NAND Flash · ATA/CF · Flash card devices: ­ MMC/SD with SDIO ­ xD ­ SmartMedia 2.3.8.3 DSP Memories The ARM has access to the following DSP memories: · L2 RAM · L1P RAM · L1D RAM 2.3.8.4 ARM-DSP Integration DM6443 DM6443 ARM and DSP integration features are as follows: · DSP visibility from ARM's memory map, see Section 2.5, Memory Map Summary, for details · Boot Modes for DSP - see Device Configurations section, Section 3.3.3, DSP Boot, for details · ARM control of DSP boot / reset - see Device Configurations section, Section 3.3.2, ARM Boot, for details · ARM control of DSP isolation and powerdown / powerup - see Section 3, Device Configurations, for details · ARM & DSP Interrupts - see Section 6.7.1, ARM CPU Interrupts, and Section 6.7.2, DSP Interrupts, for details 2.3.9 Peripherals The ARM9 has access to all of the peripherals on the DM6443 DM6443 device. 2.3.10 PLL Controller (PLLC) The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for configuring DM6443 DM6443's two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following configuration and control: · PLL Bypass Mode · Set PLL multiplier parameters Submit Documentation Feedback Device Overview 13 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 · · · Set PLL divider parameters PLL power down Oscillator power down The PLLs are briefly described in this document in the Clocking section. For more detailed information on the PLLs and PLL Controller register descriptions, see Section 2.8.3, Documentation Support, of this document for the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14 SPRUE14). 2.3.11 Power and Sleep Controller (PSC) The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating and power domain shut-off. Brief details on the PSC are given in Section 6.3, Power Supplies. For more detailed information and complete register descriptions for the PSC, see Section 2.8.3, Documentation Support, for the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14 SPRUE14). 2.3.12 ARM Interrupt Controller (AINTC) The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM's IRQ (interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see Section 2.8.3, Documentation Support for the ARM Subsystem Guide. 2.3.13 System Module The ARM Subsystem includes the System module. The System module consists of a set of registers for configuring and controlling a variety of system functions. For details and register descriptions for the System module, see Section 3, Device Configurations and see Section 2.8.3, Documentation Support, for the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14 SPRUE14). 2.3.14 Power Management DM6443 DM6443 has several means of managing power consumption. There is extensive use of clock gating, which reduces the power used by global device clocks and individual peripheral clocks. Clock management can be utilized to reduce clock frequencies in order to reduce switching power. For more details on power management techniques, see Section 3, Device Configurations, Section 6, Peripheral and Electrical Specifications, and see Section 2.8.3, Documentation Support, for the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14 SPRUE14). DM6443 DM6443 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to customize an optimal power management strategy. Several typical power management scenarios are described in the following sections. 14 Device Overview Submit Documentation Feedback www.ti.com TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 2.4 DSP Subsystem The DSP Subsystem includes the following features: 2.4.1 C64x+ DSP CPU Description The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory. The C64x+ CPU extends the performance of the C64x core through enhancements and new features. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types. The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support. Other new features include: · SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. · Compact Instructions - The native instruction size for the C6000 C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools. · Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. · Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). · Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a Submit Documentation Feedback Device Overview 15 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 · basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents: · TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 SPRU732) · TMS320C64x Technical Overview (literature number SPRU395 SPRU395) 16 Device Overview Submit Documentation Feedback Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á Á Á ÁÁ Á ÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁ www.ti.com TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 src1 Odd register file A (A1, A3, A5.A31) src2 .L1 odd dst Even register file A (A0, A2, A4.A30) (D) even dst long src ST1b ST1a 32 MSB 32 LSB long src Data path A .S1 8 8 even dst odd dst src1 (D) src2 .M1 dst2 dst1 src1 32 32 src2 LD1a 32 MSB 32 LSB DA1 DA2 LD2a LD2b Á Á Á Á Á Á Á LD1b (A) (B) (C) dst .D1 src1 src2 2x 1x Odd register file B (B1, B3, B5.B31) src2 .D2 32 LSB 32 MSB src1 dst src2 .M2 Even register file B (B0, B2, B4.B30) (C) src1 dst2 32 (B) dst1 32 (A) src2 src1 .S2 odd dst even dst long src Data path B ST2a ST2b 32 MSB 32 LSB long src even dst .L2 (D) 8 8 (D) odd dst src2 src1 Control Register A. B. C. D. On .M unit, dst2 is 32 MSB. On .M unit, dst1 is 32 LSB. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. Figure 2-1. TMS320C64x+TM CPU (DSP Core) Data Paths Submit Documentation Feedback Device Overview 17 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 2.4.2 DSP Memory Mapping The DSP memory map is shown in Section 2.5. Configuration of the control registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to memories shown in the following sections. 2.4.2.1 ARM Internal Memories The DSP has access to the 16KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only). 2.4.2.2 External Memories The DSP has access to the following External memories: · DDR2 Synchronous DRAM · Asynchronous EMIF / NOR Flash 2.4.2.3 DSP Internal Memories The DSP has access to the following DSP memories: · L2 RAM · L1P RAM · L1D RAM 2.4.2.4 C64x+ CPU The C64x+ core uses a two-level cache-based architecture. The Level 1 Program cache (L1D) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 80 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 64 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device. Table 2-2. C64x+ Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM 0x0184 0000 L2CFG 0x0184 0020 L1PCFG 0x0184 0024 L1PCC 0x0184 0040 L1DCFG 0x0184 0044 L1DCC 0x0184 0048 - 0x0184 0FFC - 0x0184 1000 EDMAWEIGHT DESCRIPTION L2 Cache configuration register L1P Size Cache configuration register L1P Freeze Mode Cache configuration register L1D Size Cache configuration register L1D Freeze Mode Cache configuration register Reserved L2 EDMA access control register 0x0184 1004 - 0x0184 1FFC - 0x0184 2000 L2ALLOC0 Reserved L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 0x0184 2010 - 0x0184 3FFF - 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register Reserved 0x0184 4018 L2 invalidate base address register L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 18 L2IBAR 0x0184 401C L1DWIBAR Device Overview L1D writeback invalidate base address register Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-2. C64x+ Cache Registers (continued) HEX ADDRESS RANGE REGISTER ACRONYM 0x0184 4034 L1DWIWC 0x0184 4038 - 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register L1D invalidate word count register 0x0184 404C L1DIWC 0x0184 4050 - 0x0184 4FFF - 0x0184 5000 L2WB 0x0184 5004 L2WBINV 0x0184 5008 L2INV 0x0184 500C - 0x0184 5027 - 0x0184 5028 L1PINV 0x0184 502C - 0x0184 5039 - 0x0184 5040 L1DWB 0x0184 5044 L1DWBINV DESCRIPTION L1D writeback invalidate word count register Reserved Reserved L2 writeback all register L2 writeback invalidate all register L2 Global Invalidate without writeback Reserved L1P Global Invalidate Reserved L1D Global Writeback L1D Global Writeback with Invalidate 0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 - 0x0184 8004 MAR0 - MAR1 Reserved 0x0000 0000 - 0x01FF FFFF 0x0184 8008 - 0x0184 8024 MAR2 - MAR9 Memory Attribute Registers for EMIFA 0x0200 0000 - 0x09FF FFFF 0x0184 8028 - 0x0184 802C MAR10 MAR10 - MAR11 MAR11 Reserved 0x0A00 0000 - 0x0BFF FFFF 0x0184 8030 - 0x0184 803C MAR12 MAR12 - MAR15 MAR15 Memory Attribute Registers for VLYNQ 0x0C00 0000 - 0x0FFF FFFF 0x0184 8040 - 0x0184 8104 MAR16 MAR16 - MAR65 MAR65 Reserved 0x1000 0000 - 0x41FF FFFF 0x0184 8108 - 0x0184 813C MAR66 MAR66 - MAR79 MAR79 Memory Attribute Registers for EMIFA/VLYNQ Shadow 0x4200 0000 0x4FFF FFFF 0x0184 8140- 0x0184 81FC MAR80 MAR80 - MAR127 MAR127 Reserved 0x5000 0000 - 0x7FFF FFFF 0x0184 8200 - 0x0184 823C MAR128 MAR128 - MAR143 MAR143 Memory Attribute Registers for DDR2 0x8000 0000 - 0x8FFF FFFF 0x0184 8240 - 0x0184 83FC MAR144 MAR144 - MAR255 MAR255 Reserved 0x9000 0000 - 0xFFFF FFFF 2.4.3 Peripherals The DSP has controllability for the following peripherals: · EDMA · ASP · 2 Timers (Timer0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers 2.4.4 DSP Interrupt Controller The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP's available interrupts. The DSP Interrupt Controller is briefly described in this document in the Interrupts section. For more detailed on the DSP Interrupt Controller, see the Documentation Support section of this document for the C64x+ CPU User's Guide. 2.5 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. Submit Documentation Feedback Device Overview 19 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-3. Memory Map Summary START ADDRESS END ADDRESS SIZE (Bytes) 0x0000 0000 0x0000 1FFF 8K ARM RAM0 (Instruction) 0x0000 2000 0x0000 3FFF 8K ARM RAM1 (Instruction) 0x0000 4000 0x0000 5FFF 8K ARM ROM (Instruction) 0x0000 6000 0x0000 7FFF 8K Reserved 0x0000 8000 0x0000 9FFF 8K ARM RAM0 (Data) 0x0000 A000 0x0000 BFFF 8K ARM RAM1 (Data) 0x0000 C000 0x0000 DFFF 8K ARM ROM (Data) 0x0000 E000 0x0000 FFFF 8K 0x0001 0000 0x000F FFFF 960K 0x0010 0000 0x001F FFFF 1M 0x0020 0000 0x007F FFFF 6M 0x0080 0000 0x0080 FFFF 64K 0x0081 0000 0x00E0 7FFF 6112K 6112K 0x00E0 8000 0x00E0 FFFF 32K L1P Cache 0x00E1 0000 0x00F0 3FFF 976K Reserved 0x00F0 4000 0x00F0 FFFF 48K L1D RAM L1D Cache ARM EDMA/ PERIPHERAL C64x+ HPI Reserved Reserved ARM RAM0 ARM RAM0 ARM RAM1 ARM RAM1 ARM ROM ARM ROM Reserved Reserved Reserved CFG Bus Peripherals (1) VPSS L2 RAM/Cache Reserved Reserved 0x00F1 0000 0x00F1 7FFF 32K 0x00F1 8000 0x017F FFFF 9120K 9120K 0x0180 0000 0x01BB FFFF 3840K 3840K 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01FF FFFF 4M Reserved CFG Space 255744 Reserved CFG Bus Peripherals CFG Bus Peripherals CFG Bus Peripherals EMIFA (Data) Reserved EMIFA (Data) 0x0200 0000 0x09FF FFFF 128M EMIFA (Code and Data) 0x0A00 0000 0x0BFF FFFF 32M Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) 0x1000 0000 0x1000 7FFF 32K 0x1000 8000 0x1000 9FFF 8K ARM RAM0 ARM RAM0 0x1000 A000 0x1000 BFFF 8K ARM RAM1 ARM RAM1 0x1000 C000 0x1000 DFFF 8K ARM ROM ARM ROM 0x1000 E000 0x1000 FFFF 8K 0x1001 0000 0x110F FFFF 17344K 17344K Reserved Reserved 0x1110 0000 0x111F FFFF 1M 0x1120 0000 0x117F FFFF 6M 0x1180 0000 0x1180 FFFF 64K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache 0x1181 0000 0x11E0 7FFF 6112K 6112K Reserved Reserved Reserved 0x11E0 8000 0x11E0 FFFF 32K L1P Cache L1P Cache L1P Cache 0x11E1 0000 0x11F0 3FFF 976K Reserved Reserved Reserved 0x11F0 4000 0x11F0 FFFF 48K L1D RAM L1D RAM L1D RAM 0x11F1 0000 0x11F1 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache 0x11F1 8000 0x1FFF FFFF 241M32K 241M32K Reserved Reserved Reserved DDR2 Control Registers DDR2 Control Registers DDR2 Control Registers Reserved Reserved Reserved Reserved VLYNQ (Remote) Reserved Reserved 0x2000 0000 0x2000 7FFF 0x2000 8000 0x41FF FFFF 32K 0x4200 0000 (2) 0x4FFF FFFF 224M Reserved EMIFA/VLYNQ Shadow EMIFA/VLYNQ Shadow 0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved Reserved 544M-32k Reserved DDR2 Control Registers Reserved 0x8000 0000 0x8FFF FFFF 256M DDR2 DDR2 DDR2 DDR2 DDR2 0x9000 0000 0xFFFF FFFF 1792M 1792M Reserved Reserved Reserved Reserved Reserved (1) (2) 20 HPI's access to the configuration bus peripherals is limited to the power and sleep controller registers, PLL1 and PLL2 registers, and HPI configuration registers. EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000 through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be used by C64x+ for both code execution and data accesses. Device Overview Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-4. Configuration Memory Map Summary START ADDRESS END ADDRESS SIZE (Bytes) ARM/EDMA C64x+ 0x0180 0000 0x0180 FFFF 64K C64x+ Interrupt Controller 0x0181 0000 0x0181 0FFF 4K C64x+ Powerdown Controller 0x0181 1000 0x0181 1FFF 4K C64x+ Security ID 0x0181 2000 0x0181 2FFF 4K 0x0182 0000 0x0182 FFFF 64K 0x0183 0000 0x0183 FFFF 64K Reserved 0x0184 0000 0x0184 FFFF 64K C64x+ Memory System 0x0185 0000 0x0187 FFFF 192K Reserved 0x0188 0000 0x01BB FFFF 3328K 3328K Reserved 0x01BC 0000 0x01BC 00FF 256 0x01BC 0100 0x01BC 01FF 256 0x01BC 0200 0x01BC 0FFF 3.5K 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers 0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher 0x01BC 1900 0x01BF FFFF 255744 Reserved 0x01C0 0000 0x01C0 FFFF 64K EDMA CC EDMA CC 0x01C1 0000 0x01C1 03FF 1K EDMA TC0 EDMA TC0 0x01C1 0400 0x01C1 07FF 1K EDMA TC1 EDMA TC1 0x01C1 8800 0x01C1 9FFF 6K 0x01C1 A000 0x01C1 FFFF 24K 0x01C2 0000 0x01C2 03FF 1K UART0 0x01C2 0400 0x01C2 07FF 1K UART1 C64x+ Revision ID Reserved C64x+ EMC Reserved ARM ETB Memory Pin Manager and Trace Reserved Reserved Reserved 0x01C2 0800 0x01C2 0BFF 1K UART2 0x01C2 0C00 0x01C2 0FFF 1K Reserved 0x01C2 1000 0x01C2 13FF 1K I2C 0x01C2 1400 0x01C2 17FF 1K Timer0 Timer0 0x01C2 1800 0x01C2 1BFF 1K Timer1 Timer1 0x01C2 1C00 0x01C2 1FFF 1K Timer2 (Watchdog) 0x01C2 2000 0x01C2 23FF 1K PWM0 0x01C2 2400 0x01C2 27FF 1K PWM1 0x01C2 2800 0x01C2 2BFF 1K PWM2 0x01C2 2C00 0x01C3 FFFF 117K 0x01C4 0000 0x01C4 07FF 2K System Module 0x01C4 0800 0x01C4 0BFF 1K PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K PLL Controller 2 0x01C4 1000 0x01C4 1FFF 4K Power and Sleep Controller Power and Sleep Controller 0x01C4 2000 0x01C4 202F 48 Reserved Reserved 0x01C4 2030 0x01C4 2033 4 DDR2 VTP Reg DDR2 VTP Reg Submit Documentation Feedback Reserved Reserved System Module Reserved Device Overview 21 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-4. Configuration Memory Map Summary (continued) START ADDRESS END ADDRESS SIZE (Bytes) 0x01C4 2034 0x01C4 23FF 1K - 52 0x01C4 2400 0x01C4 7FFF 23K ARM/EDMA C64x+ Reserved 0x01C4 8000 0x01C4 83FF 1K 0x01C4 8400 0x01C5 FFFF 95K ARM Interrupt Controller 0x01C6 0000 0x01C6 3FFF 16K 0x01C6 4000 0x01C6 5FFF 8K USB2.0 Registers / RAM 0x01C6 6000 0x01C6 67FF 2K ATA/CF 0x01C6 6800 0x01C6 6FFF 2K SPI 0x01C6 7000 0x01C6 77FF 2K GPIO 0x01C6 7800 0x01C6 7FFF 2K HPI 0x01C6 8000 0x01C6 FFFF 32K Reserved 0x01C7 0000 0x01C7 3FFF 16K VPSS Registers 0x01C7 4000 0x01C7 FFFF 48K Reserved 0x01C8 0000 0x01C8 0FFF 4K EMAC Control Registers 0x01C8 1000 0x01C8 1FFF 4K EMAC Control Module Registers 0x01C8 2000 0x01C8 3FFF 8K EMAC Control Module RAM 0x01C8 4000 0x01C8 47FF 2K MDIO Control Registers 0x01C8 4800 0x01C8 4FFF 2K 0x01C8 5000 0x01CB FFFF 236K 0x01CC 0000 0x01CD FFFF 128K 0x01CE 0000 0x01CF FFFF 128K 0x01D0 0000 0x01DF FFFF 1M 0x01E0 0000 0x01E0 0FFF 4K EMIFA Control 0x01E0 1000 0x01E0 1FFF 4K VLYNQ Control Registers Reserved Reserved HPI Reserved Reserved Reserved Reserved 0x01E0 2000 0x01E0 3FFF 8K ASP 0x01E0 4000 0x01E0 FFFF 48K Reserved ASP 0x01E1 0000 0x01E1 FFFF 64K MMC/SD/SDIO 0x01E2 0000 0x01E3 FFFF 128K 0x01E4 0000 0x01FF FFFF 1792K 1792K 0x0200 0000 0x03FF FFFF 32M EMIFA Data/Code (CS2) EMIFA Data (CS2) 0x0400 0000 0x05FF FFFF 32M EMIFA Data/Code (CS3) EMIFA Data (CS3) 0x0600 0000 0x07FF FFFF 32M EMIFA Data/Code (CS4) EMIFA Data (CS4) 0x0800 0000 0x09FF FFFF 32M EMIFA Data/Code (CS5) EMIFA Data (CS5) 0x0A00 0000 0x0BFF FFFF 32M Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved Reserved Reserved 2.6 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing, see Section 3.5.2, Multiplexed Pin Configurations, of this document. 22 Device Overview Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 2.6.1 Pin Map (Bottom View) Figure 2-2 through Figure 2-5 show the bottom view of the package pin assignments in four quadrants (A, B, C, and D). 1 2 3 4 5 6 7 8 9 10 W RSV3 DDR_D[4] DDR_D[7] DDR_D[9] DDR_D[12] DDR_D[14] DDR_CLK0 DDR_CLK0 DDR_A[12] DDR_A[11] W V DDR_D[2] DDR_D[3] DDR_D[6] DDR_D[8] DDR_D[11] DDR_D[13] DDR_D[15] DDR_CKE DDR_BS[1] DDR_A[8] V U DDR_D[0] DDR_D[1] DDR_D[5] DDR_DQS[0] DDR_D[10] DDR_DQS[1] DDR_RAS DDR_BS[0] DDR_BS[2] DDR_A[10] U T EM_CS5/ GPIO8/ VLYNQ_ CLOCK EM_CS4/ GPIO9/ VLYNQ_ SCRUN EM_A[21]/ GPIO10/ GPIO10/ VLYNQ_TXD0 DDR_ DQM[0] DVDDR2 DDR_ DQM[1] DDR_CAS DDR_WE DDR_CS DDR_VDDDLL T R EM_A[12]/ GPIO19 GPIO19 VSS VSS RSV7 DVDDR2 VSS R P EM_A[10]/ GPIO21 GPIO21 EM_A[11]/ GPIO20 GPIO20 DVDDR2 VSS DVDDR2 VSS DVDDR2 P N EM_A[6]/ GPIO25 GPIO25 EM_A[7]/ GPIO24 GPIO24 EM_A[8]/ GPIO23 GPIO23 EM_A[13]/ GPIO18 GPIO18 DVDD18 DVDD18 VSS DVDDR2 VSS DVDDR2 VSS N M MXO PLLVDD18 PLLVDD18 RSV24 RSV24 EM_A[9]/ GPIO22 GPIO22 VSS DVDD18 DVDD18 VSS CVDD VSS CVDD M L MXI/CLKIN MXV SS RSV6 RESET MXV DD VSS DVDD18 DVDD18 CVDD CVDD CVDD L K CLK_OUT0/ GPIO48 GPIO48 EM_A[3]/ GPIO28 GPIO28 EM_A[5]/ GPIO26 GPIO26 EM_A[4]/ GPIO27 GPIO27 VSS VSS CVDDDSP CVDDDSP CVDD K 1 2 3 4 5 7 8 9 10 EM_A[17]/ EM_A[20]/ EM_A[19]/ EM_A[16]/ GPIO14/ GPIO14/ GPIO11/ GPIO11/ GPIO12/ GPIO12/ GPIO15/ GPIO15/ VLYNQ_TXD2 VLYNQ_RXD0 VLYNQ_TXD1 VLYNQ_RXD2 EM_A[15]/ EM_A[14]/ EM_A[18]/ GPIO16/ GPIO16/ GPIO17/ GPIO17/ GPIO13/ GPIO13/ VLYNQ_TXD3 VLYNQ_RXD3 VLYNQ_RXD1 DVDD18 DVDD18 6 Figure 2-2. Pin Map [Quadrant A] Submit Documentation Feedback Device Overview 23 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 11 12 13 14 15 16 17 18 19 W DDR_A[6] DDR_A[5] DDR_A[0] DDR_D[16] DDR_D[18] DDR_D[21] DDR_D[27] DDR_D[29] RSV4 W V DDR_A[7] DDR_A[4] DDR_A[2] DDR_D[17] DDR_D[19] DDR_D[22] DDR_D[24] DDR_D[28] DDR_D[30] V U DDR_A[9] DDR_A[3] DDR_A[1] DDR_DQS[2] DDR_D[20] DDR_DQS[3] DDR_D[25] DDR_D[26] DDR_D[31] U T DDR_ VSSDLL DDR_ZN DDR_ZP DDR_DQM[2] DDR_VREF DDR_DQM[3] DDR_D[23] VSSA_1P1V DAC_IOUT_D T R DVDDR2 VSS DVDDR2 VSS DVDDR2 DAC_RBIAS DAC_VREF VDDA_1P8V DAC_IOUT_C R P VSS DVDDR2 VSS DVDDR2 VSS VDDA_1P1V VSSA_1P8V DAC_IOUT_B DAC_IOUT_A P N DVDDR2 VSS DVDDR2 VSS RSV12 RSV12 UART_RTS2 UART_CTS2 UART_TXD2 UART_RXD2 N M VSS CVDD VSS DVDD18 DVDD18 RSV15 RSV15 RSV14 RSV14 RSV13 RSV13 RSV11 RSV11 RSV9 M L CVDD VSS DVDD18 DVDD18 VSS RSV19 RSV19 RSV18 RSV18 RSV17 RSV17 RSV16 RSV16 RSV10 RSV10 L K CVDDDSP CVDD VSS DVDD18 DVDD18 VSS RSV23 RSV23 RSV22 RSV22 RSV21 RSV21 RSV20 RSV20 K 11 12 13 14 15 16 17 18 19 Figure 2-3. Pin Map [Quadrant B] 24 Device Overview Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 11 12 13 14 15 16 17 18 19 J CVDDDSP VSS CVDDDSP VSS DVDD18 DVDD18 USB_ID USB_VBUS USB_ VSSA3P3 USB_ VDDA3P3 J H CVDDDSP CVDDDSP VSS DVDD18 DVDD18 VSS USB_V SS1P8 USB_V DD1P8 USB_R1 USB_DM H G VSS VSS VSS VSS DVDD18 DVDD18 USB_ VSSREF USB_ VSSA1P2LD0 USB_ VDDA1P2LD0 USB_DP G F DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD18 DVDD18 CVDD M24VDD M24VDD M24VSS M24VSS M24XI M24XI M24XO M24XO F E GPIOV33 GPIOV33_10/ RXD3 GPIOV33 GPIOV33_7/ RXD0 GPIO1 GPIO5/G1 YOUT4/R4/ AEAW4 YOUT5/R5 YOUT6/R6 YOUT7/R7 CLK_OUT1/ TIM_IN/ GPIO49 GPIO49 E D GPIOV33 GPIOV33_12/ RXDV GPIOV33 GPIOV33_4/ TXD1 GPIO2/G0 GPIO38/R1 GPIO38/R1 YOUT0/G5/ AEAW0 YOUT1/G6/ AEAW1 YOUT2/G7/ AEAW2 YOUT3/R3/ AEAW3 VCLK D C GPIOV33 GPIOV33_8/ RXD1 GPIOV33 GPIOV33_6/ TXD3 GPIO0/ LCD_OE GPIO3/B0/ LCD_FIELD PWM0/ GPIO45 GPIO45 COUT7/G4 HSYNC VSYNC VPBECLK C B GPIOV33 GPIOV33_9/ RXD2 GPIOV33 GPIOV33_3/ TXD0 GPIOV33 GPIOV33_0/ TXEN GPIO4/R0 PWM1/R2/ GPIO46 GPIO46 COUT1/B4/ BTSEL1 COUT3/B6/ DSP_BT COUT5/G2 COUT6/G3 B A GPIOV33 GPIOV33_5/ TXD2 GPIOV33 GPIOV33_2/ COL GPIOV33 GPIOV33_1/ TXCLK GPIO6/B1 PWM2/ B2/GPIO47 B2/GPIO47 COUT0/B3/ BTSEL0 COUT2/B5/ EM_WIDTH COUT4/B7 RSV2 A 11 12 13 14 15 16 17 18 19 Figure 2-4. Pin Map [Quadrant C] Submit Documentation Feedback Device Overview 25 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 1 2 3 4 5 6 7 8 9 10 J EM_A[2]/ (CLE)/ HCNTL0 EM_A[1]/ (ALE)/ HHWIL EM_BA[0]/ DA0/ HINT EM_A[0]/ DA2/ HCNTL1/ GPIO53 GPIO53 GPIO50/ GPIO50/ ATA_CS0 VSS DVDD18 DVDD18 VSS CVDDDSP CVDDDSP J H GPIO51/ GPIO51/ ATA_CS1 EM_BA[1]/ DA1/ GPIO52 GPIO52 DMACK/ UART_TXD1 EM_OE/(RE)/ (IORD)/DIOR/ HDS1 EM_D14/ DD14/ DD14/ HD14 DVDD18 DVDD18 VSS CVDDDSP VSS CVDDDSP H G DMARQ/ UART_RXD1 EM_WE/(WE)/ (IOWR)/DIOW/ HDS2 EM_R/W/ INTRQ/ HR/W EM_D11/ DD11/ DD11/ HD11 EM_D10/ DD10/ DD10/ HD10 VSS DVDD18 DVDD18 VSS DVDD18 DVDD18 VSS G F EM_WAIT/ (RDY/BSY)/ IORDY/ HRDY EM_D13/ DD13/ DD13/ HD13 EM_D8/ DD8/ HD8 EM_D6/ DD6/ HD6 EM_D2/ DD2/ HD2 DVDD18 DVDD18 VSS DVDD18 DVDD18 VSS DVDD33 DVDD33 F E EM_D15/ DD15/ DD15/ HD15 EM_D9/ DD9/ HD9 EM_D3/ DD3/ HD3 EM_D4/ DD4/ HD4 EM_D0/ DD0/ HD0 TMS DVDD18 DVDD18 VSS SD_DATA1 GPIOV33 GPIOV33_15/ MDIO E D EM_D12/ DD12/ DD12/ HD12 EM_D5/ DD5/ HD5 EM_D1/ DD1/ HD1 RSV5 UART_RXD0/ GPIO35 GPIO35 EMU0 TRST SD_DATA0 SD_DATA2 GPIOV33 GPIOV33_13/ D RXER C EM_D7/ DD7/ HD7 EM_CS2/ HCS GPIO7 UART_TXD0/ GPIO36 GPIO36 EMU1 FSR/ GPIO32 GPIO32 FSX/ GPIO31 GPIO31 SD_DATA3 GPIOV33 GPIOV33_14/ C CRS B EM_CS3 SPI_EN1/ HDDIR/ GPIO42 GPIO42 SPI_DI/ GPIO40 GPIO40 SDA/GPIO44 SDA/GPIO44 TDO RTCK DX/ GPIO33 GPIO33 A RSV1 SPI_DO/ GPIO41 GPIO41 SPI_CLK/ GPIO39 GPIO39 SPI_EN0/ GPIO37 GPIO37 TDI TCK DR/ GPIO34 GPIO34 1 2 3 4 5 6 7 SCL/ GPIO43 GPIO43 CLKX/ GPIO29 GPIO29 SD_CMD GPIOV33 GPIOV33_16/ MDCLK B CLKR/ GPIO30 GPIO30 SD_CLK GPIOV33 GPIOV33_11/ RXCLK A 8 9 10 Figure 2-5. Pin Map [Quadrant D] 26 Device Overview Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 2.7 Terminal Functions The terminal functions tables (Table 2-5 through Table 2-29) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and see the Device Configurations section of this data manual. Table 2-5. BOOT Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION BOOT COUT0/ B3/ BTSEL0 A16 I/O/Z IPD DVDD18 DVDD18 These pins are multiplexed between ARM boot mode and the VPBE. At reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to determine the ARM boot configuration. See below for the boot modes set by these inputs. See the Bootmode section for more details. After reset, these are video encoder outputs COUT0 and COUT1, or RGB666/888 RGB666/888 Blue output data bits 3 and 4 B3/B4. BTSEL1 COUT2/ B5/ EM_WIDTH 0 B16 A17 I/O/Z I/O/Z IPD DVDD18 DVDD18 ARM Boot Mode ARM ROM Boot (NAND) [default] 1 ARM EMIFA Boot (NOR) 1 0 ARM ROM Boot (HPI) 1 ARM ROM Boot (UART0) IPD DVDD18 DVDD18 This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data bus, EM_WIDTH = 1. After reset, it is video encoder output COUT2 or RGB666/888 RGB666/888 Blue output data bit 5 B5. This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1. After reset, it is video encoder output COUT3 or RGB666/888 RGB666/888 Blue data bit 6 output B6. COUT3/ B6/ DSP_BT B17 I/O/Z IPD DVDD18 DVDD18 YOUT0/ G5/ AEAW0 D15 I/O/Z IPD DVDD18 DVDD18 YOUT1/ G6/ AEAW1 D16 I/O/Z IPD DVDD18 DVDD18 YOUT2/ G7/ AEAW2 D17 I/O/Z IPD DVDD18 DVDD18 YOUT3/ R3/ AEAW3 D18 I/O/Z IPD DVDD18 DVDD18 YOUT4/ R4/ AEAW4 (1) (2) (3) 0 0 1 COUT1/ B4/ BTSEL1 BTSEL0 E15 I/O/Z IPD DVDD18 DVDD18 These pins are multiplexed between EMIFA and the VPBE. At reset, the input states of AEAW[4:0] are sampled to set the EMIFA address bus width. See the Peripheral Selection at Device Reset section for details. After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 RGB666/888 Red and Green data bit outputs G5, G6, G7, R3, and R4. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 27 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-6. Oscillator/PLL Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION OSCILLATOR, PLL MXI/CLKIN I DVDD18 DVDD18 MXO M1 O DVDD18 DVDD18 Crystal output for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXO should be left as a No Connect. MXVDD L5 S (3) 1.8-V power supply for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXVDD should still be connected to the 1.8-V power supply. MXVSS L2 GND (3) Ground for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXVSS should still be connected to ground. M24XI M24XI F18 I DVDD18 DVDD18 Crystal input for M24 oscillator (24 MHz for USB). If a crystal input is not used, but instead a physical clock-in source is supplied, this is the external oscillator clock input. When the USB peripheral is not used, M24XI M24XI should be left as a No Connect. M24XO M24XO F19 O DVDD18 DVDD18 Crystal output for M24 oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, M24XO M24XO should be left as a No Connect. When the USB peripheral is not used, M24XO M24XO should be left as a No Connect. M24VDD M24VDD F16 S (3) 1.8-V power supply for M24 oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, M24VDD M24VDD should still be connected to the 1.8-V power supply. When the USB peripheral is not used, M24VDD M24VDD should be connected to the 1.8-V power supply. M24VSS M24VSS F17 GND (3) Ground for M24 oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, M24VSS M24VSS should still be connected to ground. When the USB peripheral is not used, M24VSS M24VSS should be connected to ground. PLLVDD18 PLLVDD18 (1) (2) (3) L1 Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz). If a crystal input is not used, but instead a physical clock-in source is supplied, this is the external oscillator clock input. M2 S (3) 1.8-V power supply for PLLs (system). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal For more information, see the Recommended Operating Conditions table Table 2-7. Clock Generator Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION CLOCK GENERATOR CLK_OUT0/ GPIO48 GPIO48 I/O/Z DVDD18 DVDD18 CLK_OUT1/ TIM_IN/ GPIO49 GPIO49 (1) (2) K1 This pin is multiplexed between the PLL1 clock generator and GPIO. For the PLL1 clock generator, it is clock output CLK_OUT0. This is configurable for 13.5 MHz or 27 MHz clock outputs. E19 I/O/Z DVDD18 DVDD18 This pin is multiplexed between the USB clock generator, timer, and GPIO. For the USB clock generator, it is clock output CLK_OUT1. This is configurable for 12 MHz or 24 MHz clock outputs. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Table 2-8. RESET and JTAG Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION RESET RESET L4 I IPU DVDD18 DVDD18 This is the active low global reset input. JTAG (1) (2) (3) 28 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-8. RESET and JTAG Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) E6 I IPU DVDD18 DVDD18 JTAG test-port mode select input TDO B5 O/Z ­ DVDD18 DVDD18 JTAG test-port data output TDI A5 I IPU DVDD18 DVDD18 JTAG test-port data input TCK A6 I IPU DVDD18 DVDD18 JTAG test-port clock input RTCK B6 O/Z ­ DVDD18 DVDD18 JTAG test-port return clock output TRST D7 I IPD DVDD18 DVDD18 JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG compatibility statement portion of this data manual . EMU1 C6 I/O/Z IPU DVDD18 DVDD18 Emulation pin 1 EMU0 D6 I/O/Z IPU DVDD18 DVDD18 Emulation pin 0 NAME NO. TMS DESCRIPTION Table 2-9. EMIFA Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA BOOT CONFIGURATION COUT2/ B5/ EM_WIDTH A17 I/O/Z IPD DVDD18 DVDD18 This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data bus, EM_WIDTH = 1. After reset, it is video encoder output COUT2 or RGB666/888 RGB666/888 Blue output data bit 5 B5. This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1. After reset, it is video encoder output COUT3 or RGB666/888 RGB666/888 Blue data bit 6 output B6. COUT3/ B6/ DSP_BT B17 I/O/Z IPD DVDD18 DVDD18 YOUT0/ G5/ AEAW0 D15 I/O/Z IPD DVDD18 DVDD18 YOUT1/ G6/ AEAW1 D16 I/O/Z IPD DVDD18 DVDD18 YOUT2/ G7/ AEAW2 D17 I/O/Z IPD DVDD18 DVDD18 YOUT3/ R3/ AEAW3 D18 I/O/Z IPD DVDD18 DVDD18 YOUT4/ R4/ AEAW4 E15 I/O/Z These pins are multiplexed between EMIFA and the VPBE. At reset, the input states of AEAW[4:0] are sampled to set the EMIFA address bus width. See the Peripheral Selection at Device Reset section for details. After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 RGB666/888 Red and Green data bit outputs G5, G6, G7, R3, and R4. IPD DVDD18 DVDD18 EMIFA FUNCTIONAL PINS: ASYNC / NOR EM_CS2/ HCS I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous memories (i.e., NOR flash) or NAND flash. This is the chip select for the default boot and ROM boot modes. EM_CS3 (1) (2) (3) C2 B1 I/O/Z DVDD18 DVDD18 For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous memories (i.e., NOR flash) or NAND flash. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 29 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION T2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or NAND flash. EM_CS5/ GPIO8/ VLYNQ_CLOCK T1 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or NAND flash. EM_R/W/ INTRQ/ HR/W G3 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, it is read/write output EM_R/W. EM_WAIT/ (RDY/BSY)/ IORDY/ HRDY F1 I/O/Z IPU DVDD18 DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For EMIFA, it is wait state extension input EM_WAIT. EM_OE/ (RE)/ (IORD)/ DIOR/ HDS1 H4 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For EMIFA, it is output enable output EM_OE. EM_WE (WE) (IOWR)/ DIOW/ HDS2 G2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE. IPD DVDD18 DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, this is the Bank Address 0 output (EM_BA[0]). When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of the byte address. When connected to a 16-bit asynchronous memory, this pin has the same function as EMIF address pin 22 (EM_A[22]). NAME NO. EM_CS4/ GPIO9/ VLYNQ_SCRUN EM_BA[0]/ DA0/ HINT J3 I/O/Z EM_BA[1]/ DA1/ GPIO52 GPIO52 H2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For EMIFA, this is the Bank Address 1 output EM_BA[1]. When connected to a 16 bit asynchronous memory this pin is the lowest order bit of the 16-bit word address. When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address. EM_A[21]/ GPIO10/ GPIO10/ VLYNQ_TXD0 T3 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 21 output EM_A[21]. EM_A[20]/ GPIO11/ GPIO11/ VLYNQ_RXD0 R3 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 20 output EM_A[20]. EM_A[19]/ GPIO12/ GPIO12/ VLYNQ_TXD1 R4 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 19 output EM_A[19]. EM_A[18]/ GPIO13/ GPIO13/ VLYNQ_RXD1 P5 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 18 output EM_A[18]. EM_A[17]/ GPIO14/ GPIO14/ VLYNQ_TXD2 R2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 17 output EM_A[17]. EM_A[16]/ GPIO15/ GPIO15/ VLYNQ_RXD2 R5 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 16 output EM_A[16]. EM_A[15]/ GPIO16/ GPIO16/ VLYNQ_TXD3 P3 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 15 output EM_A[15]. EM_A[14]/ GPIO17/ GPIO17/ VLYNQ_RXD3 P4 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 14 output EM_A[14]. 30 Device Overview Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) N4 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 13 output EM_A[13]. EM_A[12]/ GPIO19 GPIO19 R1 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 12 output EM_A[12]. EM_A[11]/ GPIO20 GPIO20 P2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 11 output EM_A[11]. EM_A[10]/ GPIO21 GPIO21 P1 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 10 output EM_A[10]. EM_A[9]/ GPIO22 GPIO22 M4 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 9 output EM_A[9]. EM_A[8]/ GPIO23 GPIO23 N3 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 8 output EM_A[8]. EM_A[7]/ GPIO24 GPIO24 N2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 7 output EM_A[7]. EM_A[6]/ GPIO25 GPIO25 N1 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 6 output EM_A[6]. EM_A[5]/ GPIO26 GPIO26 K3 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 5 output EM_A[5]. EM_A[4]/ GPIO27 GPIO27 K4 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 4 output EM_A[4]. EM_A[3]/ GPIO28 GPIO28 K2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 3 output EM_A[3]. EM_A[2]/ (CLE)/ HCNTL0 J1 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is the EM_A[2] address line. EM_A[1]/ (ALE)/ HHWIL J2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia.xD) and HPI. DVDD18 DVDD18 This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO. For EMIFA, this is Address output EM_A[0], which is the least significant bit on a 32-bit word address. When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the address. NAME NO. EM_A[13]/ GPIO18 GPIO18 EM_A[0]/ DA2/ HCNTL1/ GPIO53 GPIO53 J4 I/O/Z Submit Documentation Feedback DESCRIPTION Device Overview 31 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) E5 I/O/Z DVDD18 DVDD18 EM_D1/ DD1/ HD1 D3 I/O/Z DVDD18 DVDD18 EM_D2/ DD2/ HD2 F5 I/O/Z DVDD18 DVDD18 EM_D3/ DD3/ HD3 E3 I/O/Z DVDD18 DVDD18 EM_D4/ DD4/ HD4 E4 I/O/Z DVDD18 DVDD18 EM_D5/ DD5/ HD5 D2 I/O/Z DVDD18 DVDD18 EM_D6/ DD6/ HD6 F4 I/O/Z DVDD18 DVDD18 EM_D7/ DD7/ HD7 C1 I/O/Z DVDD18 DVDD18 EM_D8/ DD8/ HD8 F3 I/O/Z DVDD18 DVDD18 EM_D9/ DD9/ HD9 E2 I/O/Z DVDD18 DVDD18 EM_D10/ DD10/ DD10/ HD10 G5 I/O/Z DVDD18 DVDD18 EM_D11/ DD11/ DD11/ HD11 G4 I/O/Z DVDD18 DVDD18 EM_D12/ DD12/ DD12/ HD12 D1 I/O/Z DVDD18 DVDD18 EM_D13/ DD13/ DD13/ HD13 F2 I/O/Z DVDD18 DVDD18 EM_D14/ DD14/ DD14/ HD14 H5 I/O/Z DVDD18 DVDD18 EM_D15/ DD15/ DD15/ HD15 E1 I/O/Z DVDD18 DVDD18 NAME EM_D0/ DD0/ HD0 32 NO. Device Overview DESCRIPTION These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0]. Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA FUNCTIONAL PINS: NAND / SMARTMEDIA / xD EM_A[1]/ (ALE)/ HHWIL J2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and HPI. For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE). EM_A[2]/ (CLE)/ HCNTL0 J1 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and HPI. For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE). EM_WAIT/ (RDY/BSY)/ IORDY/ HRDY F1 I/O/Z IPU DVDD18 DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY). EM_OE/ (RE)/ (IORD)/ DIOR/ HDS1 H4 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD, it is read enable output (RE). EM_WE (WE) (IOWR)/ DIOW/ HDS2 G2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD, it is write enable output (WE). EM_CS2/ HCS C2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous memories (i.e. NOR flash) or NAND flash. This is the chip select for the default boot and ROM boot modes. EM_CS3 B1 I/O/Z DVDD18 DVDD18 For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous memories (i.e. NOR flash) or NAND flash. EM_CS4/ GPIO9/ VLYNQ_SCRUN T2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or NAND flash. EM_CS5/ GPIO8/ VLYNQ_CLOCK T1 I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or NAND flash. Submit Documentation Feedback Device Overview 33 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) E5 I/O/Z DVDD18 DVDD18 EM_D1/ DD1/ HD1 D3 I/O/Z DVDD18 DVDD18 EM_D2/ DD2/ HD2 F5 I/O/Z DVDD18 DVDD18 EM_D3/ DD3/ HD3 E3 I/O/Z DVDD18 DVDD18 EM_D4/ DD4/ HD4 E4 I/O/Z DVDD18 DVDD18 EM_D5/ DD5/ HD5 D2 I/O/Z DVDD18 DVDD18 EM_D6/ DD6/ HD6 F4 I/O/Z DVDD18 DVDD18 EM_D7/ DD7/ HD7 C1 I/O/Z DVDD18 DVDD18 EM_D8/ DD8/ HD8 F3 I/O/Z DVDD18 DVDD18 EM_D9/ DD9/ HD9 E2 I/O/Z DVDD18 DVDD18 EM_D10/ DD10/ DD10/ HD10 G5 I/O/Z DVDD18 DVDD18 EM_D11/ DD11/ DD11/ HD11 G4 I/O/Z DVDD18 DVDD18 EM_D12/ DD12/ DD12/ HD12 D1 I/O/Z DVDD18 DVDD18 EM_D13/ DD13/ DD13/ HD13 F2 I/O/Z DVDD18 DVDD18 EM_D14/ DD14/ DD14/ HD14 H5 I/O/Z DVDD18 DVDD18 EM_D15/ DD15/ DD15/ HD15 E1 I/O/Z DVDD18 DVDD18 NAME EM_D0/ DD0/ HD0 34 NO. Device Overview DESCRIPTION These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0]. Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-10. DDR2 Memory Controller Terminal Functions SIGNAL TYPE (1) OTHER (2) (3) W7 I/O/Z DVDDR2 DDR2 Clock DDR_CLK0 W8 I/O/Z DVDDR2 DDR2 Differential clock DDR_CKE V8 I/O/Z DVDDR2 DDR2 Clock Enable DDR_CS T9 I/O/Z DVDDR2 DDR2 Active low chip select NAME NO. DDR_CLK0 DESCRIPTION DDR2 Memory Controller DDR_WE T8 I/O/Z DVDDR2 DDR2 Active low Write enable DDR_DQM[3] T16 I/O/Z DVDDR2 DDR_DQM[2] T14 I/O/Z DVDDR2 DDR_DQM[1] T6 I/O/Z DVDDR2 DDR_DQM[0] T4 I/O/Z DVDDR2 DDR2 Data mask outputs DQM3: For upper byte data bus DDR_D[31:24] DQM2: For DDR_D[23:16] DQM1: For DDR_D[15:8] DQM0: For lower byte DDR_D[7:0] DDR_RAS U7 I/O/Z DVDDR2 DDR2 Row Access Signal output DDR_CAS T7 I/O/Z DVDDR2 DDR2 Column Access Signal output DDR_DQS[0] U4 I/O/Z DVDDR2 DDR_DQS[1] U6 I/O/Z DVDDR2 DDR_DQS[2] U14 I/O/Z DVDDR2 DDR_DQS[3] U16 I/O/Z DVDDR2 Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR2 memory when writing and inputs when reading. They are used to synchronize the data transfers. DQS3 : For upper byte DDR_D[31:24] DQS2: For DDR_D[23:16] DQS1: For DDR_D[15:8] DQS0: For bottom byte DDR_D[7:0] DDR_BS[0] U8 I/O/Z DVDDR2 Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories. I/O/Z DVDDR2 DDR2 address bus DDR_BS[1] V9 DDR_BS[2] U9 DDR_A[12] W9 DDR_A[11] W10 DDR_A[10] U10 DDR_A[9] U11 DDR_A[8] V10 DDR_A[7] V11 DDR_A[6] W11 DDR_A[5] W12 DDR_A[4] V12 DDR_A[3] U12 DDR_A[2] V13 DDR_A[1] (1) (2) (3) U13 DDR_A[0] W13 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal For more information, see the Recommended Operating Conditions table Submit Documentation Feedback Device Overview 35 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-10. DDR2 Memory Controller Terminal Functions (continued) SIGNAL NAME NO. DDR_D[31] TYPE (1) OTHER (2) (3) I/O/Z DVDDR2 DESCRIPTION U19 DDR_D[30] V19 DDR_D[29] W18 DDR_D[28] V18 DDR_D[27] W17 DDR_D[26] U18 DDR_D[25] U17 DDR_D[24] V17 DDR_D[23] T17 DDR_D[22] V16 DDR_D[21] W16 DDR_D[20] U15 DDR_D[19] V15 DDR_D[18] W15 DDR_D[17] V14 DDR_D[16] W14 DDR_D[15] V7 DDR_D[14] W6 DDR_D[13] V6 DDR_D[12] W5 DDR_D[11] DDR2 data bus can be configured as 32 bits wide or 16 bits wide. V5 DDR_D[10] U5 DDR_D[9] W4 DDR_D[8] V4 DDR_D[7] W3 DDR_D[6] V3 DDR_D[5] U3 DDR_D[4] W2 DDR_D[3] V2 DDR_D[2] V1 DDR_D[1] U2 DDR_D[0] U1 DDR_VREF T15 I (3) Reference voltage input for the SSTL_18 IO buffers. DDR_VSSDLL T11 GND (3) Ground for the DDR2 Digital Locked Loop. S (3) Power (1.8 Volts) for the DDR2 Digital Locked Loop. Impedance control for DDR2 outputs. This must be connected via a 200 resistor to DVDDR2. Impedance control for DDR2 outputs. This must be connected via a 200 resistor to VSS. DDR_VDDDLL T10 DDR_ZN O/Z DDR_ZP 36 T12 (3) T13 O/Z (3) Device Overview Submit Documentation Feedback TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-11. I2C Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION I2C SCL/ GPIO43 GPIO43 I/O/Z DVDD18 DVDD18 SDA/ GPIO44 GPIO44 (1) (2) C4 This pin is multiplexed between I2C and GPIO. For I2C, it is clock output SCL. B4 I/O/Z DVDD18 DVDD18 This pin is multiplexed between I2C and GPIO. For I2C, it is bi-directional data signal SDA. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Table 2-12. Audio Serial Port (ASP) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION Audio Serial Port (ASP) CLKX/ GPIO29 GPIO29 I/O/Z DVDD18 DVDD18 CLKR/ GPIO30 GPIO30 A8 I/O/Z DVDD18 DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is Receive clock IO CLKR. FSX/ GPIO31 GPIO31 C8 I/O/Z DVDD18 DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is Transmit frame synchronization IO FSX. FSR/ GPIO32 GPIO32 C7 I/O/Z DVDD18 DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is Receive frame synchronization IO FSR. DX/ GPIO33 GPIO33 B7 I/O/Z DVDD18 DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is Data Transmit output DX. DR/ GPIO34 GPIO34 (1) (2) B8 This pin is multiplexed between ASP and GPIO. For ASP, it is Transmit clock IO CLKX. A7 I/O/Z DVDD18 DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is Data Receive input DR. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Table 2-13. SPI Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION Serial Port Interface (SPI) SPI_EN0/ GPIO37 GPIO37 I/O/Z DVDD18 DVDD18 This pin is multiplexed between SPI and GPIO. When used by SPI, it is SPI slave device 0 enable output SPI_EN0. SPI_EN1/ HDDIR/ GPIO42 GPIO42 B2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between SPI, ATA, and GPIO. When used by SPI, it is SPI slave device 1 enable output SPI_EN1. SPI_CLK/ GPIO39 GPIO39 A3 I/O/Z DVDD18 DVDD18 This pin is multiplexed between SPI and GPIO. For SPI, it is clock output SPI_CLK. SPI_DI/ GPIO40 GPIO40 B3 I/O/Z DVDD18 DVDD18 This pin is multiplexed between SPI and GPIO. For SPI, it is data input SPI_DI. SPI_DO/ GPIO41 GPIO41 (1) (2) A4 A2 I/O/Z DVDD18 DVDD18 This pin is multiplexed between SPI and GPIO. For SPI it is data output SPI_DO. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 37 TMS320DM6443 TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282E SPRS282E ­ DECEMBER 2005 ­ REVISED MARCH 2007 Table 2-14. EMAC and MDIO Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION EMAC GPIOV33 GPIOV33_0/ TXEN B13 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Transmit Enable output TXEN. GPIOV33 GPIOV33_1/ TXCLK A13 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Transmit Clock input TXCLK. GPIOV33 GPIOV33_2/ COL A12 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Collision Detect input COL. GPIOV33 GPIOV33_6/ TXD3 C12 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Transmit Data 3 output TXD3. GPIOV33 GPIOV33_5/ TXD2 A11 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Transmit Data 2 output TXD2. GPIOV33 GPIOV33_4/ TXD1 D12 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Transmit Data 1 output TXD1. GPIOV33 GPIOV33_3/ TXD0 B12 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Transmit Data 0 output TXD0. GPIOV33 GPIOV33_11/ RXCLK A10 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Receive Clock input RXCLK. GPIOV33 GPIOV33_12/ RXDV D11 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Receive Data Valid input RXDV. GPIOV33 GPIOV33_13/ RXER D10 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Receive Error input RXER. GPIOV33 GPIOV33_14/ CRS C10 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Carrier Sense input CRS. GPIOV33 GPIOV33_10/ RXD3 E11 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Receive Data 3 input RXD3. GPIOV33 GPIOV33_9/ RXD2 B11 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Receive Data 2 input RXD2. GPIOV33 GPIOV33_8/ RXD1 C11 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is Receive data 1 input RXD1. GPIOV33 GPIOV33_7/ RXD0 E12 I/O/Z DVDD33 DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is R