TMS320DM6431 SPRS342C DM6431 601/BT DDR2-400 AIC12 H-100 IEEE-1149 - Datasheet Archive

 

Digital Media Processor www.ti.com SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 1 TMS320DM6431 Digital Media Processor

 

TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 1 TMS320DM6431 TMS320DM6431 Digital Media Processor 1.1 Features · · · High-Performance Digital Media Processor (DM6431 DM6431) ­ 3.33-ns Instruction Cycle Time ­ 300-MHz C64x+TM Clock Rate ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 2400 MIPS ­ Fully Software-Compatible With C64x ­ Commercial and Automotive (Q or S suffix) Grades VelociTI.2TM Extensions to VelociTITM Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units With VelociTI.2 Extensions: · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Auto-Focus Module Operation C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ VelociTI.2 Increased Orthogonality ­ C64x+ Extensions · Compact 16-bit Instructions · Additional Instructions to Support Complex Multiplies · · · · · · · · · · · C64x+ L1/L2 Memory Architecture ­ 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation] ­ 512K-Bit (64K-Byte) L1D Data RAM/Cache [Flexible Allocation] ­ 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] Supports Little Endian Mode Only Video Processing Subsystem (VPSS), VPFE Only ­ Front End Provides: · CCD and CMOS Imager Interface · BT.601/BT 601/BT.656 Digital YCbCr 4:2:2 (10-Bit) Interface · Glueless Interface to Common Video Decoders External Memory Interfaces (EMIFs) ­ 16-Bit DDR2 SDRAM Memory Controller With 128M-Byte Address Space (1.8-V I/O) · Supports up to 266-MHz (data rate) bus and interfaces to DDR2-400 DDR2-400 SDRAM ­ Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-Bit-Wide Data) ­ NAND (8-Bit-Wide Data) Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) One 64-Bit Watch Dog Timer One UART With RTS and CTS Flow Control Master/Slave Inter-Integrated Circuit (I2C BusTM) One Multichannel Buffered Serial Port (McBSP0) ­ I2S and TDM ­ AC97 Audio Codec Interface ­ SPI ­ Standard Voice Codec Interface (AIC12 AIC12) ­ Telecom Interfaces ­ ST-Bus, H-100 H-100 ­ 128 Channel Mode Multichannel Audio Serial Port (McASP0) ­ Four Serializers and SPDIF (DIT) Mode Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006­2008, Texas Instruments Incorporated TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 · · · · · · · · High-End CAN Controller (HECC) 10/100 Mb/s Ethernet MAC (EMAC) ­ IEEE 802.3 Compliant ­ Supports Media Independent Interface (MII) ­ Management Data I/O (MDIO) Module Three Pulse Width Modulator (PWM) Outputs On-Chip ROM Bootloader Individual Power-Savings Modes Flexible PLL Clock Generators IEEE-1149 IEEE-1149.1 (JTAGTM) Boundary-Scan-Compatible Up to 111 General-Purpose I/O (GPIO) Pins www.ti.com · · · · (Multiplexed With Other Device Functions) Packages: ­ 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch ­ 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch 0.09-µm/6-Level Cu Metal Process (CMOS) 3.3-V and 1.8-V I/O, 1.2-V Internal (-3/-3Q/-3S) Applications: ­ Digital Media ­ Networked Media Encode ­ Video Imaging 1.2 Description The TMS320C64x+TM DSPs (including the TMS320DM6431 TMS320DM6431 device) are the highest-performance fixed-point DSP generation in the TMS320C6000TM TMS320C6000TM DSP platform. The DM6431 DM6431 device is based on the third-generation high-performance, advanced VelociTITM very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+TM devices are upward code-compatible from previous devices that are part of the C6000TM C6000TM DSP platform. The C64xTM DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 2400 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 SPRU732). The DM6431 DM6431 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 C6000 DSP platform devices. The DM6431 DM6431 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of 32K-byte (KB) memory space that can be configured as mapped memory or direct mapped cache. The Level 1 data/memory memory/cache (L1D) consists of a 64KB memory space that can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 64KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. 2 TMS320DM6431 TMS320DM6431 Digital Media Processor Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP0); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 1 UART with hardware handshaking support; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6431 DM6431 device includes a Video Processing Subsystem (VPSS) with a Video Processing Front-End (VPFE) input used for video capture. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC). The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6431 DM6431 and the network. The DM6431 DM6431 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C port allows DM6431 DM6431 to easily control peripheral devices and/or communicate with host processors. The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6431 DM6431 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution. Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor 3 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 1.3 www.ti.com Functional Block Diagram Figure 1-1 shows the functional block diagram of the DM6431 DM6431 device. BT.656, Y/C, Raw (Bayer) JTAG Interface 10b System Control Input Clock(s) DSP Subsystem OSC C64x+ t DSP CPU PLLs/Clock Generator Video Processing Subsystem (VPSS) Front End 64 KB L2 RAM 32 KB L1 Pgm Power/Sleep Controller Pin Multiplexing 32 KB L1 Data CCD Controller Video Interface Boot ROM Switched Central Resource (SCR) Peripherals Serial Interfaces McASP McBSP I2 C System HECC UART GeneralPurpose Timer Watchdog Timer PWM GPIO EDMA Connectivity EMAC With MDIO Program/Data Storage DDR2 Mem Ctlr (16b) Async EMIF/ NAND/ (8b) Figure 1-1. TMS320DM6431 TMS320DM6431 Functional Block Diagram 4 TMS320DM6431 TMS320DM6431 Digital Media Processor Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Contents 1 TMS320DM6431 TMS320DM6431 Digital Media Processor . 1 1.1 1.2 Description . 2 1.3 Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) . 118 Features . 1 Functional Block Diagram . 4 6 Peripheral Information and Electrical Specifications . 119 6.1 6.2 Parameter Information . 119 Recommended Clock and Control Signal Transition Behavior. 120 6.3 6.4 Revision History . 6 2 Device Overview . 7 Power Supplies . 121 Enhanced Direct Memory Access (EDMA3) Controller . 128 2.1 Device Characteristics . 7 2.2 CPU (DSP Core) Description . 8 2.3 C64x+ CPU. 11 2.4 Memory Map Summary 12 6.5 Reset . 140 2.5 Pin Assignments 16 6.6 External Clock Input From MXI/CLKIN Pin 24 6.7 Clock PLLs . 151 56 Device and Development-Support Tool Nomenclature . 56 6.8 Interrupts . 156 2.6 2.7 2.8 2.9 3 . . Terminal Functions . Device Support . . 149 6.9 Documentation Support . 58 Device Configurations. 59 External Memory Interface (EMIF) . 159 6.10 6.11 Video Processing Sub-System (VPSS) Overview . 168 Universal Asynchronous Receiver/Transmitter (UART) . 173 3.1 6.12 Inter-Integrated Circuit (I2C) . 175 Power Considerations . 60 3.3 Clock Considerations . 62 6.13 6.14 3.4 Boot Sequence . 63 3.5 Configurations At Reset . 74 3.6 Configurations After Reset . 75 Multichannel Buffered Serial Port (McBSP). 179 Multichannel Audio Serial Port (McASP0) Peripheral . 188 High-End Controller Area Network Controller (HECC) . 196 3.7 Multiplexed Pin Configurations . 79 3.8 Device Initialization Sequence After Reset . 111 3.9 4 System Module Registers . 59 3.2 Debugging Considerations . 113 6.16 Device Operating Conditions. 116 5.1 5.2 5.3 Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise Noted) . 116 Recommended Operating Conditions . 117 Electrical Characteristics Over Recommended Submit Documentation Feedback Timers . 210 6.19 Pulse Width Modulator (PWM). 213 6.20 General-Purpose Input/Output (GPIO). 215 6.21 7 Management Data Input/Output (MDIO) 6.18 System Interconnect Block Diagram . 114 Ethernet Media Access Controller (EMAC) . 202 6.17 System Interconnect . 114 4.1 5 6.15 IEEE 1149.1 JTAG . 219 . 209 Mechanical Data. 221 7.1 Thermal Data for ZWT . 221 7.1.1 Thermal Data for ZDU . 222 7.1.2 Packaging Information. 222 Contents 5 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPRS342B SPRS342B device-specific data manual to make it an SPRS342C SPRS342C revision. SEE Global ADDITIONS/MODIFICATIONS/DELETIONS · · Updated/Changed signal name from "C_WE" to "C_WE" Updated/Changed signal name from "C_WEN" to "C_WE" Section 2.6 Section 6.7.1 6 Table 2-17, Multichannel Audio Serial Port (McASP0) Terminal Functions: · Updated/Changed AFSR0/DR0/GP[100] pin description from ". frame synchronization AFSX0." to ".frame synchronization AFSR0." · Updated/Changed AFSX0/DX1/GP[107] pin description from ".frame synchronization AFSR0." to ".frame synchronization AFSX0." Updated/Changed sentence from "TI requires EMI filter manufacturer Murata." to "TI recommends EMI filter manufacturer Murata." Revision History Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 2 Device Overview 2.1 Device Characteristics Table 2-1, provides an overview of the TMS320DM6431 TMS320DM6431 DSP. The tables show significant features of the DM6431 DM6431 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1. Characteristics of the DM6431 DM6431 Processor HARDWARE FEATURES DM6431 DM6431 DDR2 Memory Controller (16-bit bus width) [1.8 V I/O] Asynchronous EMIF [EMIFA] Asynchronous (8-bit bus width), RAM, Flash, (8-bit NOR or 8-bit NAND) EDMA3 1 (64 independent channels, 8 QDMA channels) Timers 2 64-bit General Purpose (configurable as 2 64-bit or 4 32-bit) 1 64-bit Watch Dog UART 1 (with RTS and CTS flow control) Peripherals Not all peripherals pins are available at the same time (For more detail, see the Device Configuration section). I2C 1 McASP 1 (4 serailizers) 10/100 Ethernet MAC (EMAC) with Management Data Input/Output (MDIO) General-Purpose Input/Output Port (GPIO) PWM Configurable Video Port HECC Size (Bytes) On-Chip Memory 1 (Master/Slave) McBSP Organization 1 Up to 111 pins 3 outputs 1 Input (VPFE) 1 128KB 128KB RAM, 64KB ROM 32K-Byte (32KB) L1 Program (L1P) RAM/Cache (Cache up to 32KB) 64KB L1 Data (L1D) RAM/Cache 64KB Unified Mapped RAM/Cache (L2) 64KB Boot ROM MegaModule Rev ID Revision ID Register (MM_REVID.[15:0]) (address location: 0x0181 2000) CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) See the TMS320DM6437/35/33/31 TMS320DM6437/35/33/31 Digital Media Processor (DMP) [Silicon Revisions 1.1 and 1.0] Silicon Errata (literature number SPRZ250 SPRZ250). JTAG BSDL_ID JTAGID register (address location: 0x01C4 0028) See Section 6.21.1, JTAG ID (JTAGID) Register Description(s) CPU Frequency MHz Cycle Time ns Core (V) Voltage I/O (V) MXI/CLKIN frequency multiplier (27 MHz reference) PLL Options BGA Package(s) Process Technology Product Status (1) (1) 300 3.33 ns (-3/-3Q/-3S) 1.2 V (-3/-3Q/-3S) 1.8 V, 3.3 V x1 (Bypass), x14 to x30 16 x 16 mm, 0.8 mm pitch 361-Pin BGA (ZWT) 23 x 23 mm, 1.0 mm pitch 376-Pin BGA (ZDU) µm Product Preview (PP), Advance Information (AI), or Production Data (PD) 0.09 µm PD PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Submit Documentation Feedback Device Overview 7 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com 2.2 CPU (DSP Core) Description The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory. The C64x+ CPU extends the performance of the C64x core through enhancements and new features. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types. The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support. Other new features include: · SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. · Compact Instructions - The native instruction size for the C6000 C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools. · · · 8 Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com · SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents: · TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 SPRU732) · TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871 SPRU871) · TMS320C64x to TMS320C64x+ CPU Migration Guide Application Report (literature number SPRAA84 SPRAA84) · TMS320C64x+ DSP Cache User's Guide (literature number SPRU862 SPRU862) Submit Documentation Feedback Device Overview 9 SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á Á Á ÁÁ Á ÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁ TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com src1 Odd register file A (A1, A3, A5.A31) src2 .L1 odd dst Even register file A (A0, A2, A4.A30) (D) even dst long src ST1b ST1a 32 MSB 32 LSB long src Data path A .S1 8 8 even dst odd dst src1 (D) src2 .M1 dst2 dst1 src1 32 32 src2 LD1a 32 MSB 32 LSB DA1 DA2 LD2a LD2b Á Á Á Á Á Á Á LD1b (A) (B) (C) dst .D1 src1 src2 2x 1x Odd register file B (B1, B3, B5.B31) src2 .D2 32 LSB 32 MSB src1 dst src2 .M2 Even register file B (B0, B2, B4.B30) (C) src1 dst2 32 (B) dst1 32 (A) src2 src1 .S2 odd dst even dst long src Data path B ST2a ST2b 32 MSB 32 LSB long src even dst .L2 (D) 8 8 (D) odd dst src2 src1 Control Register A. B. C. D. On .M unit, dst2 is 32 MSB. On .M unit, dst1 is 32 LSB. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. Figure 2-1. TMS320C64x+TM CPU (DSP Core) Data Paths 10 Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 2.3 C64x+ CPU The C64x+ core uses a two-level cache-based architecture. The Level 1 Program memory/cache (L1P) consists of 32 KB memory space that can be configured as mapped memory or direct mapped cache. The Level 1 Data memory/cache (L1D) consists of a 64 KB memory space that can be configured as mapped memory or 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 64 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device. Table 2-2. C64x+ Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM 0x0184 0000 L2CFG 0x0184 0020 L1PCFG 0x0184 0024 L1PCC 0x0184 0040 L1DCFG 0x0184 0044 L1DCC DESCRIPTION L2 Cache configuration register L1P Size Cache configuration register L1P Freeze Mode Cache configuration register L1D Size Cache configuration register L1D Freeze Mode Cache configuration register 0x0184 0048 - 0x0184 0FFC - 0x0184 1000 EDMAWEIGHT Reserved 0x0184 1004 - 0x0184 1FFC - 0x0184 2000 L2ALLOC0 L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 L2 EDMA access control register Reserved 0x0184 2010 - 0x0184 3FFF - 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 0x0184 4018 L2IBAR L2 invalidate base address register 0x0184 401C L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register 0x0184 404C L1DIWC L1D invalidate word count register 0x0184 4050 - 0x0184 4FFF - 0x0184 5000 L2WB 0x0184 5004 L2WBINV 0x0184 5008 L2INV 0x0184 500C - 0x0184 5027 - 0x0184 5028 L1PINV 0x0184 502C - 0x0184 5039 - 0x0184 5040 L1DWB 0x0184 5044 L1DWBINV 0x0184 5048 L1DINV Submit Documentation Feedback Reserved Reserved Reserved L2 writeback all register L2 writeback invalidate all register L2 Global Invalidate without writeback Reserved L1P Global Invalidate Reserved L1D Global Writeback L1D Global Writeback with Invalidate L1D Global Invalidate without writeback Device Overview 11 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-2. C64x+ Cache Registers (continued) HEX ADDRESS RANGE REGISTER ACRONYM 0x0184 8000 - 0x0184 80BC MAR0 - MAR47 MAR47 Reserved (corresponds to byte address 0x0000 0000 - 0x2FFF FFFF) DESCRIPTION 0x0184 80C0 - 0x0184 80FC MAR48 MAR48 - MAR63 MAR63 Reserved (corresponds to byte address 0x3000 0000 - 0x3FFF FFFF) 0x0184 8100 - 0x0184 8104 MAR64 MAR64 - MAR65 MAR65 Reserved (corresponds to byte address 0x4000 0000 - 0x41FF FFFF) 0x0184 8108 - 0x0184 8124 MAR66 MAR66 - MAR73 MAR73 Memory Attribute Registers for EMIFA (corresponds to byte address 0x4200 0000 - 0x49FF FFFF) 0x0184 8128 - 0x0184 812C MAR74 MAR74 - MAR75 MAR75 Reserved (corresponds to byte address 0x4A00 0000 - 0x4BFF FFFF) 0x0184 8130 - 0x0184 813C MAR76 MAR76 - MAR79 MAR79 Reserved (corresponds to byte address 0x4C00 0000 - 0x4FFF FFFF) 0x0184 8140- 0x0184 81FC MAR80 MAR80 - MAR127 MAR127 Reserved (corresponds to byte address 0x5000 0000 - 0x7FFF FFFF) 0x0184 8200 - 0x0184 823C MAR128 MAR128 - MAR143 MAR143 Memory Attribute Registers for DDR2 (corresponds to byte address 0x8000 0000 - 0x8FFF FFFF) 0x0184 8240 - 0x0184 83FC MAR144 MAR144 - MAR255 MAR255 Reserved (corresponds to byte address 0x9000 0000 - 0xFFFF FFFF) 2.4 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. 12 Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-3. Memory Map Summary START ADDRESS END ADDRESS SIZE (Bytes) C64x+ MEMORY MAP EDMA PERIPHERAL MEMORY MAP VPSS MEMORY MAP 0x0000 0000 0x000F FFFF 1M Reserved 0x0010 0000 0x0010 FFFF 64K Boot ROM 0x0011 0000 0x007F FFFF 7M-64K 7M-64K Reserved 0x0080 0000 0x0080 FFFF 64K Reserved 0x0081 0000 0x0081 FFFF 64K L2 RAM/Cache (1) 0x0082 0000 0x00E0 7FFF 6048K 6048K Reserved 0x00E0 8000 0x00E0 FFFF 32K L1P RAM/Cache (1) 0x00E1 0000 0x00F0 3FFF 976K Reserved 0x00F0 4000 0x00F0 7FFF 16K Reserved 0x00F0 8000 0x00F0 FFFF 32K L1D RAM 0x00F1 0000 0x00F1 7FFF 32K L1D RAM/Cache (1) 0x00F1 8000 0x017F FFFF 9120K 9120K Reserved 0x0180 0000 0x01BF FFFF 4M CFG Space 0x01C0 0000 0x01FF FFFF 4M CFG Bus Peripherals 0x0200 0000 0x100F FFFF 225M Reserved 0x1010 0000 0x1010 FFFF 64K Boot ROM 0x1011 0000 0x107F FFFF 7M-48K 7M-48K Reserved 0x1080 0000 0x1080 FFFF 64K Reserved Reserved 0x1081 0000 0x1081 FFFF 64K L2 RAM/Cache (1) L2 RAM/Cache (1) 0x1082 0000 0x10E0 7FFF 6048K 6048K Reserved Reserved 0x10E0 8000 0x10E0 FFFF 32K L1P RAM/Cache (1) L1P RAM/Cache (1) 0x10E1 0000 0x10F0 3FFF 976K Reserved Reserved 0x10F0 4000 0x10F0 7FFF 16K Reserved Reserved 0x10F0 8000 0x10F0 FFFF 32K L1D RAM L1D RAM 0x10F1 0000 0x10F1 7FFF 32K L1D RAM/Cache (1) L1D RAM/Cache (1) 0x10F1 8000 0x10FF FFFF 1M-96K 1M-96K Reserved Reserved 0x1100 0000 0x1FFF FFFF 240M Reserved Reserved 0x2000 0000 0x2000 7FFF 32K DDR2 Control Regs DDR2 Control Regs 0x2000 8000 0x2FFF FFFF 256M-32K 256M-32K Reserved Reserved 0x3000 0000 0x3FFF FFFF 256M Reserved Reserved 0x4000 0000 0x41FF FFFF 32M Reserved Reserved 0x4200 0000 0x42FF FFFF 16M EMIFA Data (CS2) (2) EMIFA Data (CS2) (2) 0x4300 0000 0x43FF FFFF 16M Reserved Reserved 0x4400 0000 0x44FF FFFF 16M EMIFA Data (CS3) (2) EMIFA Data (CS3) (2) 0x4500 0000 0x45FF FFFF 16M Reserved Reserved 0x4600 0000 0x46FF FFFF 16M EMIFA Data (CS4) (2) EMIFA Data (CS4) (2) 0x4700 0000 0x47FF FFFF 16M Reserved Reserved 0x4800 0000 0x48FF FFFF 16M EMIFA Data (CS5) (2) EMIFA Data (CS5) (2) 0x4900 0000 0x49FF FFFF 16M Reserved Reserved 0x4A00 0000 0x4BFF FFFF 32M Reserved Reserved 0x4C00 0000 0x4FFF FFFF 64M Reserved Reserved 0x5000 0000 0x7FFF FFFF 768M Reserved Reserved 0x8000 0000 0x8FFF FFFF 256M DDR2 Memory Controller DDR2 Memory Controller DDR2 Memory Controller 0x9000 0000 0xFFFF FFFF 1792M 1792M Reserved Reserved Reserved Reserved CFG Bus Peripherals Reserved Reserved (1) (2) For all bootmodes that default to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot, BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and L1DCFG.L1DMODE = 0h). If cache use is required, the application code must explicitly enable the cache. For more information on boot modes, see Section 3.4.1, Boot Modes. For more information on the bootloader, see the Using the TMS320DM643x Bootloader Application Report (literature number SPRAAG0). For the EMIFA ROM Direct Boot (BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader is not executed-that is, L2 RAM/Cache defaults to all RAM (L2CFG.L2MODE = 0h); L1P RAM/Cache defaults to all cache (L1PCFG.L1PMODE = 7h); and L1D RAM/Cache defaults to all cache (L1DCFG.L1DMODE = 7h). The EMIFA CS0 and CS1 are not functionally supported on the DM6431 DM6431 device, and therefore, are not pinned out. Submit Documentation Feedback Device Overview 13 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-4. Configuration Memory Map Summary START ADDRESS END ADDRESS SIZE (Bytes) C64x+ 0x0180 0000 0x0180 FFFF 64K C64x+ Interrupt Controller 0x0181 0000 0x0181 0FFF 4K C64x+ Powerdown Controller 0x0181 1000 0x0181 1FFF 4K C64x+ Security ID 0x0181 2000 0x0181 2FFF 4K C64x+ Revision ID 0x0182 0000 0x0182 FFFF 64K C64x+ EMC 0x0183 0000 0x0183 FFFF 64K Reserved 0x0184 0000 0x0184 FFFF 64K C64x+ Memory System 0x0185 0000 0x0187 FFFF 192K Reserved 0x0188 0000 0x01BB FFFF 3328K 3328K Reserved 0x01BC 0000 0x01BC 00FF 256 Reserved 0x01BC 0100 0x01BC 01FF 256 Pin Manager and Trace 0x01BC 0400 0x01BF FFFF 255K Reserved 0x01C0 0000 0x01C0 FFFF 64K EDMA CC 0x01C1 0000 0x01C1 03FF 1K EDMA TC0 0x01C1 0400 0x01C1 07FF 1K EDMA TC1 0x01C1 0800 0x01C1 0BFF 1K EDMA TC2 0x01C1 0C00 0x01C1 9FFF 5K Reserved 0x01C1 A000 0x01C1 A7FF 2K Reserved 0x01C1 A800 0x01C1 FFFF 22K Reserved 0x01C2 0000 0x01C2 03FF 1K UART0 0x01C2 0400 0x01C2 07FF 1K Reserved 0x01C2 0800 0x01C2 0FFF 2K Reserved 0x01C2 1000 0x01C2 13FF 1K I2C 0x01C2 1400 0x01C2 17FF 1K Timer0 0x01C2 1800 0x01C2 1BFF 1K Timer1 0x01C2 1C00 0x01C2 1FFF 1K Timer2 (Watchdog) 0x01C2 2000 0x01C2 23FF 1K PWM0 0x01C2 2400 0x01C2 27FF 1K PWM1 0x01C2 2800 0x01C2 2BFF 1K PWM2 0x01C2 2C00 0x01C2 2FFF 1K Reserved 0x01C2 3000 0x01C2 3FFF 4K HECC Control (1) 0x01C2 4000 0x01C2 53FF 5K HECC RAM 0x01C2 5400 0x01C3 FFFF 107K Reserved 0x01C4 0000 0x01C4 07FF 2K System Module 0x01C4 0800 0x01C4 0BFF 1K PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K PLL Controller 2 0x01C4 1000 0x01C4 1FFF 4K Power and Sleep Controller 0x01C4 2000 0x01C6 6FFF 148K Reserved 0x01C6 7000 0x01C6 77FF 2K GPIO 0x01C6 7800 0x01C6 7FFF 2K Reserved 0x01C6 8000 0x01C6 FFFF 32K Reserved 0x01C7 0000 0x01C7 3FFF 16K VPSS Registers 0x01C7 4000 0x01C7 FFFF 48K Reserved 0x01C8 0000 0x01C8 0FFF 4K EMAC Control Registers 0x01C8 1000 0x01C8 1FFF 4K EMAC Control Module Registers (1) 14 Software must not access "Reserved" locations of the HECC. Access to HECC "Reserved" locations may hang the device. Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-4. Configuration Memory Map Summary (continued) START ADDRESS END ADDRESS SIZE (Bytes) C64x+ 0x01C8 2000 0x01C8 3FFF 8K EMAC Control Module RAM 0x01C8 4000 0x01C8 47FF 2K MDIO Control Registers 0x01C8 4800 0x01CF FFFF 494K Reserved 0x01D0 0000 0x01D0 07FF 2K McBSP0 0x01D0 0800 0x01D0 0FFF 2K Reserved 0x01D0 1000 0x01D0 13FF 1K McASP0 Control 0x01D0 1400 0x01D0 17FF 1K McASP0 Data 0x01D0 1800 0x01DF FFFF 1018K 1018K Reserved 0x01E0 0000 0x01E0 0FFF 4K EMIFA Control 0x01E0 1000 0x01E0 1FFF 4K Reserved 0x01E0 2000 0x0FFF FFFF 226M-8K 226M-8K Reserved Submit Documentation Feedback Device Overview 15 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com 2.5 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing, see Section 3.7, Multiplexed Pin Configurations of this document. 2.5.1 Pin Map (Bottom View) Figure 2-2 through Figure 2-5 show the bottom view of the ZWT package pin assignments in four quadrants (A, B, C, and D). Figure 2-6 through Figure 2-9 show the bottom view of the ZDU package pin assignments in four quadrants (A, B, C, and D). 1 2 3 4 5 6 7 8 9 10 W VSS VSS DDR_D[7] DDR_D[9] DDR_D[12] DDR_D[14] DDR_CLK DDR_CLK DDR_A[12] DDR_A[11] W V DVDDR2 DDR_D[4] DDR_D[6] DDR_D[8] DDR_D[11] DDR_D[13] DDR_D[15] DDR_CKE DDR_BA[1] DDR_A[8] V U DDR_D[2] DDR_D[3] DDR_D[5] DDR_DQS[0] DDR_D[10] DDR_DQS[1] DDR_RAS DDR_BA[0] DDR_BA[2] DDR_A[10] U T DDR_D[0] DDR_D[1] RSV16 RSV16 DDR_DQM[0] DVDDR2 DDR_DQM[1] DDR_CAS DDR_WE DDR_CS DDR_ZN T R VSS TRST TMS DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS DVDDR2 R P DVDD33 DVDD33 EMU0 TDO TDI DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS P N TCK EMU1 RESETOUT POR VSS DVDD33 DVDD33 VSS CVDD VSS CVDD N M CLKOUT0/ PWM2/ GP[84] SCL SDA RESET DVDD33 DVDD33 VSS CVDD VSS CVDD VSS M L UCTS0/ GP[87] URXD0/ GP[85] URTS0/ PWM0/ GP[88] HECC_RX/ TINP1L/ GP[56] RSV3 DVDD33 DVDD33 VSS CVDD VSS CVDD L K VSS TINP0L/ GP[98] UTXD0/ GP[86] HECC_TX/ TOUT1L/ GP[55] RSV2 VSS CVDD VSS CVDD VSS K 1 2 3 4 5 6 7 8 9 10 Figure 2-2. ZWT Pin Map [Quadrant A] 16 Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 11 12 13 14 15 16 17 18 19 W DDR_A[6] DDR_A[5] DDR_A[0] RSV24 RSV24 RSV26 RSV26 RSV29 RSV29 RSV35 RSV35 DVDDR2 DVDDR2 W V DDR_A[7] DDR_A[4] DDR_A[2] RSV25 RSV25 RSV27 RSV27 RSV30 RSV30 RSV32 RSV32 RSV37 RSV37 VSS V U DDR_A[9] DDR_A[3] DDR_A[1] RSV22 RSV22 RSV28 RSV28 RSV23 RSV23 RSV33 RSV33 RSV36 RSV36 RSV38 RSV38 U T DDR_ZP RSV20 RSV20 DDR_VREF RSV21 RSV21 RSV31 RSV31 RSV34 RSV34 RSV39 RSV39 T R VSS DVDDR2 RSV5 DVDDR2 VSS DVDDR2 VSS VSS VSS R P DVDDR2 VSS DVDDR2 VSS RSV14 RSV14 RSV11 RSV11 RSV12 RSV12 RSV8 RSV7 P N VSS CVDD VSS VSS RSV13 RSV13 RSV15 RSV15 RSV10 RSV10 RSV9 RSV6 N M CVDD VSS CVDD VSS DVDD33 DVDD33 VSS VSS VSS VSS M L VSS CVDD VSS DVDDR2 RSV4 PLLPWR18 PLLPWR18 VSS MXV DD VSS L K CVDD VSS CVDD VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 MXV SS MXI/ CLKIN K 11 12 13 14 15 16 17 18 19 DDR_VDDDLL DDR_VSSDLL Figure 2-3. ZWT Pin Map [Quadrant B] Submit Documentation Feedback Device Overview 17 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com 11 12 13 14 15 16 17 18 19 J VSS CVDD VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS VSS MXO J H CVDD VSS CVDD VSS GP[29] GP[28] GP[27] DVDD33 DVDD33 VSS H G VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS GP[30] G F DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS GP[23]/ (BOOTMODE1) EM_D[6]/ GP[20] EM_D[7]/ GP[21] GP[22]/ (BOOTMODE0) EM_CS5/ GP[33] F E RSV18 RSV18 RSV19 RSV19 VSS EM_WE EM_WAIT/ (RDY/BSY) EM_D[3]/ GP[17] EM_D[5]/ GP[19] EM_D[4]/ GP[18] EM_CS4/ GP[32] E D EM_A[18]/ GP[46] C_FIELD/ EM_A[21]/ GP[34] C_WE/ EM_R/W/ GP[35] YI4(CCD4)/ GP[40] EM_OE EM_D[0]/ GP[14] EM_D[2]/ GP[16] EM_D[1]/ GP[15] GP[31] D C EM_A[16]/ GP[48] CI0(CCD8)/ EM_A[20]/ GP[44] YI5(CCD5)/ GP[41] YI2(CCD2)/ GP[38] YI0(CCD0)/ GP[36] EM_BA[1]/ GP[5]/ (AEM0) EM_BA[0]/ GP[6]/ (AEM1) EM_CS3/ GP[13] EM_CS2/ GP[12] C B EM_A[15]/ GP[49] CI1(CCD9)/ EM_A[19]/ GP[45] YI6(CCD6)/ GP[42] YI3(CCD3)/ GP[39] YI1(CCD1)/ GP[37] EM_A[2]/ (CLE)/GP[8]/ (AEAW0/ PLLMS0) EM_A[0]/ GP[7]/ (AEM2) EM_A[3]/ GP[11] VSS B A EM_A[17]/ GP[47] YI7(CCD7)/ GP[43] VD/ GP[53] PCLK/ GP[54] HD/ GP[52] EM_A[1]/ (ALE)/GP[9]/ (AEAW1/ PLLMS1) EM_A[4]/ GP[10]/ (AEAW2/ PLLMS2) DVDD33 DVDD33 VSS A 11 12 13 14 15 16 17 18 19 GP[24]/ GP[25]/ GP[26]/ (BOOTMODE2) (BOOTMODE3) (FASTBOOT) Figure 2-4. ZWT Pin Map [Quadrant C] 18 Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 1 2 3 4 J DVDD33 DVDD33 AHCLKR0/ CLKR0/ GP[101] AXR0[1]/ DX0/ GP[104] CLKS0/ TOUT0L/ GP[97] H ACLKR0/ CLKX0/ GP[99] AXR0[0]/ GP[105] AXR0[2]/ FSX0/ GP[103] AFSR0/ DR0/ GP[100] G AHCLKX0/ GP[108] AFSX0/ GP[107] AMUTE0/ GP[110] AXR0[3]/ FSR0/ GP[102] F ACLKX0/ GP[106] AMUTEIN0/ GP[109] GP[4]/ PWM1 VSS E GP[0] GP[1] GP[2] D MDIO/ GP[83] MRXD2/ GP[80] C MDCLK/ GP[81] B A 5 6 7 8 9 10 DVDD33 DVDD33 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS H DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 G DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS F GP[3] RSV1 DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS RSV17 RSV17 E MTXEN/ GP[75] MTXD0/ GP[72] MTXD2/ GP[70] GP[64] GP[59] EM_A[6]/ GP[95] EM_A[9]/ GP[92] EM_A[12]/ GP[89] D MRXD3/ GP[82] MRXD0/ GP[78] MRXDV/ GP[74] MTXD3/ GP[69] MCOL/ GP[67] GP[62] GP[58] EM_A[7]/ GP[94] EM_A[11]/ GP[90] C VSS MRXD1/ GP[79] MRXER/ GP[76] MTXD1/ GP[71] MCRS/ GP[68] GP[65] GP[61] EM_A[5]/ GP[96] EM_A[8]/ GP[93] EM_A[13]/ GP[51] B DVDD33 DVDD33 DVDD33 DVDD33 MRXCLK/ GP[77] MTXCLK/ GP[73] GP[66] GP[63] GP[57] GP[60] EM_A[10]/ GP[91] EM_A[14]/ GP[50] A 1 2 3 4 5 6 7 8 9 10 VSS DVDD33 DVDD33 VSS J Figure 2-5. ZWT Pin Map [Quadrant D] Submit Documentation Feedback Device Overview 19 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 1 AA Y W 2 VSS VSS DDR_D[6] DDR_D[8] DDR_D[12] DDR_D[15] DDR_CLK0 DDR_CLK0 DDR_BS[1] DDR_BS[2] DDR_A[10] DVDDR2 DDR_D[3] DDR_D[4] DDR_DQS[0] DDR_D[10] DDR_D[13] DDR_DQS[1] DDR_CKE DDR_BS[0] DDR_A[12] DDR_A[11] DDR_D[0] DDR_D[1] DDR_D[5] DDR_DQM[0] DDR_D[11] DDR_D[14] DDR_DQM[1] DDR_RAS DDR_CAS DDR_WE DDR_CS VSS DDR_D[2] RSV16 RSV16 DDR_D[7] DDR_D[9] VSS DVDDR2 VSS DVDDR2 VSS DVDDR2 DVDDR2 TRST DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS TCK TDO EMU0 AB 3 5 6 DVDDR2 VSS TDI VSS DVDDR2 EMU1 RESETOUT DVDD33 DVDD33 VSS CLKOUT0/ PWM2/ GP[84] POR RESET VSS DVDD33 DVDD33 UCTS0/ GP[87] SDA HECC_RX/ TINP1L/ GP[56] DVDD33 DVDD33 VSS UTXD0/ GP[86] SCL HECC_TX/ TOUT1L/ GP[55] VSS DVDD33 DVDD33 M VSS URXD0/ GP[85] URTS0/ PWM0/ GP[88] RSV3 VSS 1 2 3 4 8 9 P N 7 10 11 AB AA Y W R V U TMS 4 www.ti.com T R P 9 10 VSS CVDD CVDD N CVDD VSS VSS N M CVDD CVDD VSS M 10 11 U 6 7 V 8 11 T 5 9 P Figure 2-6. ZDU Pin Map [Quadrant A] 20 Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 12 13 14 15 16 17 18 19 20 21 22 AA DDR_A[7] DDR_A[4] DDR_A[1] DDR_A[0] RSV26 RSV26 RSV29 RSV29 RSV30 RSV30 RSV33 RSV33 RSV36 RSV36 DVDDR2 DVDDR2 AB DDR_A[9] AB DDR_A[6] DDR_A[3] RSV22 RSV22 RSV24 RSV24 RSV27 RSV27 RSV23 RSV23 RSV31 RSV31 RSV34 RSV34 RSV38 RSV38 VSS AA DDR_A[2] RSV20 RSV20 RSV25 RSV25 RSV28 RSV28 RSV21 RSV21 RSV32 RSV32 RSV35 RSV35 RSV37 RSV37 RSV39 RSV39 Y Y DDR_A[8] DDR_A[5] W DDR_ZN DDR_ZP DDR_VDDDLL DDR_VSSDLL RSV5 DVDDR2 DDR_VREF DVDDR2 VSS VSS VSS W V DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS RSV12 RSV12 RSV7 RSV6 V U VSS VSS RSV11 RSV11 RSV15 RSV15 RSV8 U T VSS RSV14 RSV14 RSV13 RSV13 RSV9 RSV10 RSV10 T VSS VSS VSS VSS VSS R 12 13 14 15 16 17 R P CVDD CVDD VSS P DVDD33 DVDD33 RSV4 DVDD33 DVDD33 VSS DVDD33 DVDD33 P N VSS VSS CVDD N VSS DVDD33 DVDD33 PLLPWR18 PLLPWR18 MXV DD MXI/ CLKIN N M VSS VSS CVDD M DVDD33 DVDD33 VSS DVDD33 DVDD33 MXV SS MXO M 12 13 14 18 19 20 21 22 Figure 2-7. ZDU Pin Map [Quadrant B] Submit Documentation Feedback Device Overview 21 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com 21 22 (BOOTMODE2) DVDD33 DVDD33 VSS GP[26]/ GP[23]/ (FASTBOOT) (BOOTMODE1) GP[29] GP[30] GP[28] EM_CS5/ GP[33] 18 19 L VSS GP[27] CVDD K DVDD33 DVDD33 VSS J VSS DVDD33 DVDD33 H DVDD33 DVDD33 VSS EM_D[7]/ GP[21] (BOOTMODE3) G VSS DVDD33 DVDD33 EM_D[1]/ GP[15] EM_D[4]/ GP[18] GP[31] G F DVDD33 DVDD33 VSS EM_D[3]/ GP[17] EM_D[6]/ GP[20] EM_D[5]/ GP[19] F 12 13 14 L VSS CVDD CVDD K VSS VSS J CVDD CVDD 20 GP[24]/ GP[22]/ (BOOTMODE0) GP[25]/ EM_CS4/ GP[32] L K J H 12 13 14 15 16 17 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 EM_BA[0]/ GP[6]/ (AEM1) EM_D[0]/ GP[14] EM_D[2]/ GP[16] E D RSV17 RSV17 RSV18 RSV18 RSV19 RSV19 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 EM_OE EM_WAIT/ (RDY/BSY) EM_A[3]/ GP[11] EM_CS3/ GP[13] D C EM_A[11]/ GP[90] EM_A[15]/ GP[49] CI1(CCD9)/ EM_A[19]/ GP[45] CI0(CCD8)/ EM_A[20]/ GP[44] C_FIELD/ EM_A[21]/ GP[34] C_WE/ EM_R/W/ GP[35] YI4(CCD4)/ GP[40] EM_WE EM_BA[1]/ GP[5[/ (AEM0) EM_A[0]/ GP[7]/ (AEM2) EM_CS2/ GP[12] C B EM_A[12]/ GP[89] EM_A[16]/ GP[48] EM_A[17]/ GP[47] YI6(CCD6)/ GP[42] YI5(CCD5)/ GP[41] YI2(CCD2) GP[38] YI1(CCD1)/ GP[37] YI0(CCD0)/ GP[36] EM_A[1]/ (ALE)/GP[9]/ (AEAW1/ PLLMS1) EM_A[4]/ GP[10]/ (AEAW2/ PLLMS2) VSS B A EM_A[13]/ GP[51] EM_A[14]/ GP[50] EM_A[18]/ GP[46] YI7(CCD7)/ GP[43] YI3(CCD3)/ GP[39] VD/ GP[53] PCLK/ GP[54] HD/ GP[52] EM_A[2]/ (CLE)/GP[8]/ (AEAW0/ PLLMS0) DVDD33 DVDD33 VSS A 12 13 14 15 16 17 18 19 20 21 22 E Figure 2-8. ZDU Pin Map [Quadrant C] 22 Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 1 2 3 4 5 9 10 11 L DVDD33 DVDD33 TINP0L/ GP[98] TOUT0L/ GP[97] RSV2 DVDD33 DVDD33 L CVDD VSS VSS L K AHCLKR0/ CLKR0/ GP[101] AXR0[1]/ DX0/ GP[104] AFSR0/ DR0/ GP[100] DVDD33 DVDD33 VSS K CVDD VSS VSS K J ACLKR0/ CLKX0/ GP[99] AXR0[2]/ FSX0/ GP[103] AXR0[3]/ FSR0/ GP[102] VSS DVDD33 DVDD33 J VSS CVDD CVDD J H AHCLKX0/ GP[108] AXR0[0]/ GP[105] AMUTE0/ GP[110] DVDD33 DVDD33 VSS H G ACLKX0/ GP[106] AFSX0/ GP[107] AMUTEIN0/ GP[109] VSS DVDD33 DVDD33 G F GP[2] GP[3] GP[4]/ PWM1 DVDD33 DVDD33 VSS F 6 7 8 9 10 11 DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 E GP[0] GP[1] DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS E D MDCLK/ GP[81] MRXD3/ GP[82] MRXDV/ GP[74] RSV1 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS DVDD33 DVDD33 VSS D C MDIO/ GP[83] MRXD0/ GP[78] MRXD2/ GP[80] MTXEN/ GP[75] MTXD2/ GP[70] MCOL/ GP[67] GP[64] GP[62] GP[59] EM_A[7]/ GP[94] EM_A[9]/ GP[92] C B DVDD33 DVDD33 MRXER/ GP[76] MRXD1/ GP[79] MTXD1/ GP[71] MTXD0/ GP[72] MCRS/ GP[68] GP[65] GP[61] GP[58] EM_A[6]/ GP[95] EM_A[10]/ GP[91] B A VSS DVDD33 DVDD33 MRXCLK/ GP[77] MTXCLK/ GP[73] MTXD3/ GP[69] GP[66] GP[63] GP[57] GP[60] EM_A[5]/ GP[96] EM_A[8]/ GP[93] A 1 2 3 4 5 6 7 8 9 10 11 Figure 2-9. ZDU Pin Map [Quadrant D] Submit Documentation Feedback Device Overview 23 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com 2.6 Terminal Functions The terminal functions tables (Table 2-5 through Table 2-26) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations, see the Device Configurations section of this data manual. All device boot and configuration pins are multiplexed configuration pins- meaning they are multiplexed with functional pins. These pins function as device boot and configuration pins only during device reset. The input states of these pins are sampled and latched into the BOOTCFG register when device reset is deasserted (see Note below). After device reset is deasserted, the values on these multiplexed pins no longer have to hold the configuration. For proper device operation, external pullup/pulldown resistors may be required on these device boot and configuration pins. Section 3.9.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldown resistors are required. Note: Internal to the chip, the two device reset pins RESET and POR are logically AND'd together for the purpose of latching device boot and configuration pins. The values on all device boot and configuration pins are latched into the BOOTCFG register when the logical AND of RESET and POR transitions from low-to-high. 24 Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-5. BOOT Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION BOOT GP[25]/ (BOOTMODE3) G16 H21 G15 L20 I/O/Z IPD DVDD33 DVDD33 Bootmode configuration bits. These bootmode functions along with the FASTBOOT function determine what device bootmode configuration is selected. The DM6431 DM6431 device supports several types of bootmodes along with a FASTBOOT option; for more details on the types/options, see Section 3.4.1, Boot Modes. F15 K20 F18 J20 GP[26]/ (FASTBOOT) G17 K19 I/O/Z IPD DVDD33 DVDD33 Fast Boot 0 = Not Fast Boot 1 = Fast Boot EM_A[4]/GP[10]/ (AEAW2/PLLMS2) A17 B21 I/O/Z IPD DVDD33 DVDD33 EM_A[1]/(ALE)/ GP[9]/ (AEAW1/PLLMS1) A16 B20 I/O/Z IPD DVDD33 DVDD33 EM_A[2]/(CLE)/ GP[8]/ (AEAW0/PLLMS0) B16 A20 I/O/Z IPD DVDD33 DVDD33 EM_A[0]/ GP[7]/(AEM2) B17 C21 I/O/Z IPD DVDD33 DVDD33 EM_BA[0]/ GP[6]/(AEM1) C17 E20 I/O/Z IPD DVDD33 DVDD33 EM_BA[1]/ GP[5]/(AEM0) C16 C20 I/O/Z IPD DVDD33 DVDD33 For proper DM6431 DM6431 device operation, if this pin is both routed and 3-stated (not driven) during device reset, it must be pulled down via an external resistor. For more detailed information on pullup/pulldown resistors, see Section 3.9.1, Pullup/Pulldown Resistors. For proper DM6431 DM6431 device operation, if this pin is both routed and 3-stated (not driven) during device reset, it must be pulled up via an external resistor. For more detailed information on pullup/pulldown resistors, see Section 3.9.1, Pullup/Pulldown Resistors. GP[24]/ (BOOTMODE2) GP[23]/ (BOOTMODE1) GP[22]/ (BOOTMODE0) GP[28] (3) J21 I/O/Z GP[27] (1) (2) H16 IPD DVDD33 DVDD33 H17 L19 I/O/Z IPU DVDD33 DVDD33 EMIFA Address Bus Width (AEAW) and Fast Boot PLL Multiplier Select (PLLMS). These configuration pins serve two purposes which are based on AEM[2:0] settings. For AEM[2:0] = 001 [8-bit EMIFA (Async) Pinout Mode 1], the AEAW/PLLMS pins serve as the AEAW function to select EMIFA Address Bus Width. For all other AEM modes, the AEAW/PLLMS pins select the PLL multiplier for fast boot. For more details, see Section 3.5.1.2, EMIFA Address Width Select (AEAW) and Fast Boot PLL Multipler Select (PLLMS). Selects EMIFA Pinout Mode The DM6431 DM6431 supports the following EMIFA Pinout Modes: AEM[2:0] = 000, No EMIFA AEM[2:0] = 001, 8-bit EMIFA (Async) Pinout Mode 1 AEM[2:0] = 101, 8-bit EMIFA (NAND) Pinout Mode 5 This signal doesn't actually affect the EMIFA module. It only affects how the EMIFA is pinned out. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 25 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-6. Oscillator/PLL Terminal Functions SIGNAL ZWT NO. NAME ZDU NO. TYPE (1) OTHER (2) DESCRIPTION OSCILLATOR, PLL MXI/ CLKIN N22 I MXVDD Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz). If the internal oscillator is bypassed, this is the external oscillator clock input. (3) MXO J19 M22 O MXVDD Crystal output for MX oscillator MXVDD L18 N21 S (4) 1.8 V power supply for MX oscillator. On the board, this pin can be connected to the same 1.8 V power supply as DVDDR2. MXVSS K18 M21 GND (4) Ground for MX oscillator PLLPWR18 PLLPWR18 (1) (2) (3) (4) K19 L16 N20 S (4) 1.8 V power supply for PLLs I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal For more information on external board connections, see Section 6.6, External Clock Input From MXI/CLKIN Pin. For more information, see the Recommended Operating Conditions table Table 2-7. Clock Generator Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION CLOCK GENERATOR CLKOUT0/ PWM2/GP[84] (1) (2) (3) 26 M1 R1 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between the System Clock generator (PLL1), PWM2, and GPIO. For the System Clock generator (PLL1), it is clock output CLKOUT0. This is configurable for 27 MHz or other 27 MHz-divided-down (/1 to /32) clock outputs. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-8. RESET and JTAG Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) Device reset DESCRIPTION RESET RESET M4 R3 I IPU DVDD33 DVDD33 RESETOUT N3 T3 O/Z ­ DVDD33 DVDD33 Reset output status pin. The RESETOUT pin indicates when the device is in reset. POR N4 R2 I IPU DVDD33 DVDD33 Power-on reset. JTAG test-port mode select input. For proper device operation, do not oppose the IPU on this pin. JTAG TMS I P3 U2 O/Z ­ DVDD33 DVDD33 JTAG test-port data output TDI P4 U3 I IPU DVDD33 DVDD33 JTAG test-port data input TCK N1 U1 I IPU DVDD33 DVDD33 JTAG test-port clock input TRST R2 V2 I IPD DVDD33 DVDD33 JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG compatibility statement portion of this data sheet EMU1 N2 T2 I/O/Z IPU DVDD33 DVDD33 Emulation pin 1 EMU0 (3) V3 TDO (1) (2) R3 IPU DVDD33 DVDD33 P2 T1 I/O/Z IPU DVDD33 DVDD33 Emulation pin 0 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 27 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-9. EMIFA Terminal Functions (Boot Configuration) SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA: BOOT CONFIGURATION EM_A[4]/GP[10]/ (AEAW2/PLLMS2) A17 B21 I/O/Z IPD DVDD33 DVDD33 EM_A[1]/(ALE)/GP[ 9]/ (AEAW1/PLLMS1) A16 B20 I/O/Z IPD DVDD33 DVDD33 EM_A[2]/(CLE)/GP [8]/ (AEAW0/PLLMS0) B16 A20 I/O/Z IPD DVDD33 DVDD33 EM_BA[1]/ GP[5]/(AEM0) C16 C20 I/O/Z IPD DVDD33 DVDD33 EM_BA[0]/ GP[6]/(AEM1) C17 E20 I/O/Z IPD DVDD33 DVDD33 EM_A[0]/ GP[7]/(AEM2) B17 C21 I/O/Z IPD DVDD33 DVDD33 (1) (2) (3) 28 These pins are multiplexed between the EMIFA and GPIO. When RESET or POR is asserted, these pins function as EMIFA configuration pins. At reset if AEM[2:0] = 001 (EMIFA in 8-bit Async mode), then the input states of AEAW[2:0] are sampled to set the EMIFA Address Bus Width. After reset, these pins function as EMIFA or GPIO pin functions based on pin mux selection. For more details on the AEAW/PLLMS functions, see Section 3.5.1.2, EMIFA Address Bus Width (AEAW) and Fast Boot PLL Multiplier Select (PLLMS). These pins are multiplexed between the EMIFA and GPIO. When RESET or POR is asserted, these pins function as EMIFA configuration pins. At reset, the input states of AEM[2:0] are sampled to set the EMIFA Pinout Mode. For more details, see Section 3.5.1, Configurations at Reset. After reset, these pins function as EMIFA or GPIO pin functions based on pin mux selection. For more details on the AEM functions, see Section 3.5.1.1, EMIFA Pinout Mode (AEM[2:0]). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA FUNCTIONAL PINS: 8-Bit ASYNC/NOR (EMIFA Pinout Mode 1, AEM[2:0] = 001) Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., AEAW[2:0], AEM[2:0], etc.). For more details, see Section 3.7, Multiplexed Pin Configurations This pin is multiplexed between EMIFA and GPIO. EM_CS2/GP[12] C19 C22 I/O/Z IPD DVDD33 DVDD33 For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous memories (i.e., NOR flash). This is the chip select for the default boot and ROM boot modes. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. This pin is multiplexed between EMIFA and GPIO. EM_CS3/GP[13] C18 D22 I/O/Z IPD DVDD33 DVDD33 For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous memories (i.e., NOR flash). Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. This pin is multiplexed between EMIFA and GPIO. EM_CS4/GP[32] E19 H22 I/O/Z IPD DVDD33 DVDD33 For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash). Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash). EM_CS5/GP[33] F19 J22 I/O/Z IPD DVDD33 DVDD33 C_WE/EM_R/W/ GP[35] C17 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO. D13 For EMIFA (ASYNC/NOR), this pin is wait state extension input EM_WAIT. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. For EMIFA, it is read/write output EM_R/W. EM_WAIT/ (RDY/BSY) E15 D20 I/O/Z IPU DVDD33 DVDD33 EM_OE D15 D19 I/O/Z IPU DVDD33 DVDD33 For EMIFA, it is output enable output EM_OE. EM_WE E14 C19 I/O/Z IPU DVDD33 DVDD33 For EMIFA, it is write enable output EM_WE. I/O/Z IPD DVDD33 DVDD33 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. EM_BA[0]/ GP[6]/(AEM1) C17 E20 For EMIFA, this is the Bank Address 0 output (EM_BA[0]). When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of the byte address. This pin is multiplexed between EMIFA and GPIO. EM_BA[1]/ GP[5]/(AEM0) (1) (2) (3) C16 C20 For EMIFA, this is the Bank Address 1 output EM_BA[1]. When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 29 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued) SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) C_FIELD/ EM_A[21]/GP[34] D12 C16 I/O/Z IPD DVDD33 DVDD33 CI0(CCD8)/ EM_A[20]/GP[44] C12 C15 I/O/Z IPD DVDD33 DVDD33 CI1(CCD9)/ EM_A[19]/GP[45] B12 C14 I/O/Z IPD DVDD33 DVDD33 EM_A[18]/GP[46] D11 A14 I/O/Z IPD DVDD33 DVDD33 EM_A[17]/GP[47] A11 B14 I/O/Z IPD DVDD33 DVDD33 EM_A[16]/GP[48] C11 B13 I/O/Z IPD DVDD33 DVDD33 EM_A[15]/GP[49] B11 C13 I/O/Z IPD DVDD33 DVDD33 EM_A[14]/GP[50] A10 A13 I/O/Z IPD DVDD33 DVDD33 EM_A[13]/GP[51] B10 A12 I/O/Z IPD DVDD33 DVDD33 D10 B12 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. EM_A[12]/GP[89] IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. DESCRIPTION This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO. For EMIFA, it is address bit 21 output EM_A[21]. This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO. For EMIFA (AEM[2:0] = 001), this pin is address bit 20 output EM_A[20] if AEAW[2:0] = 100b. This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO. For EMIFA (AEM[2:0] = 001), this pin is address bit 19 output EM_A[19] if AEAW[2:0] = 100b. This pin is multiplexed between EMIFA and GPIO. For EMIFA (AEM[2:0] = 001), this pin is address bit 18 output EM_A[18] if AEAW[2:0] = 011/100b. This pin is multiplexed between EMIFA and GPIO. For EMIFA (AEM[2:0] = 001), this pin is address bit 17 output EM_A[17] if AEAW[2:0] = 011/100b. This pin is multiplexed between EMIFA and GPIO. For EMIFA (AEM[2:0] = 001), this pin is address bit 16 output EM_A[16] if AEAW[2:0] = 010/011/100b. This pin is multiplexed between EMIFA and GPIO. For EMIFA (AEM[2:0] = 001), this pin is address bit 15 output EM_A[15] if AEAW[2:0] = 010/011/100b. This pin is multiplexed between EMIFAand GPIO. For EMIFA (AEM[2:0] = 001), this pin is address bit 14 output EM_A[14] if AEAW[2:0] = 001/010/011/100b. This pin is multiplexed between EMIFA and GPIO. EM_A[11]/GP[90] EM_A[10]/GP[91] EM_A[9]/GP[92] EM_A[8]/GP[93] EM_A[7]/GP[94] EM_A[6]/GP[95] EM_A[5]/GP[96] EM_A[4]/GP[10]/ (AEAW2/PLLMS2) 30 C10 A9 D9 B9 C9 D8 B8 A17 Device Overview C12 B11 C11 A11 C10 B10 A10 B21 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z For EMIFA (AEM[2:0] = 001), this pin is address bit 13 output EM_A[13] if AEAW[2:0] = 001/010/011/100b. For EMIFA, this pin is address bit 12 output EM_A[12]. For EMIFA, this pin is address bit 11 output EM_A[11]. For EMIFA, this pin is address bit 10 output EM_A[10]. For EMIFA, this pin is address bit 9 output EM_A[9]. For EMIFA, this pin is address bit 8 output EM_A[8]. For EMIFA, this pin is address bit 7 output EM_A[7]. For EMIFA, this pin is address bit 6 output EM_A[6]. For EMIFA, this pin is address bit 5 output EM_A[5]. For EMIFA, this pin is address bit 4 output EM_A[4]. Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued) SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) B18 D21 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. EM_A[3]/GP[11] IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. IPD DVDD33 DVDD33 This pin is multiplexed between EMIFA and GPIO. EM_A[2]/(CLE)/GP [8]/ (AEAW0/PLLMS0) B16 EM_A[1]/(ALE)/GP[ 9]/ (AEAW1/PLLMS1) A16 A20 B20 I/O/Z I/O/Z DESCRIPTION For EMIFA, this pin is address bit 3 output EM_A[3]. For EMIFA, this pin is address bit 2 output EM_A[2]. For EMIFA, this pin is address output EM_A[1]. This pin is multiplexed between EMIFA and GPIO. For EMIFA, this pin is Address output EM_A[0], which is the least significant bit on a 32-bit word address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the address. EM_A[0]/ GP[7]/(AEM2) B17 C21 I/O/Z IPD DVDD33 DVDD33 EM_D0/GP[14] D16 E21 I/O/Z IPD DVDD33 DVDD33 EM_D1/GP[15] D18 G20 I/O/Z IPD DVDD33 DVDD33 EM_D2/GP[16] D17 E22 I/O/Z IPD DVDD33 DVDD33 EM_D3/GP[17] E16 F20 I/O/Z IPD DVDD33 DVDD33 These pins are multiplexed between EMIFA and GPIO. EM_D4/GP[18] E18 G21 I/O/Z IPD DVDD33 DVDD33 For EMIFA (AEM[2:0] = 001), these pins are the 8-bit bi-directional data bus (EM_D[7:0]). EM_D5/GP[19] E17 F22 I/O/Z IPD DVDD33 DVDD33 EM_D6/GP[20] F16 F21 I/O/Z IPD DVDD33 DVDD33 EM_D7/GP[21] F17 H20 I/O/Z IPD DVDD33 DVDD33 EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 1, AEM[2:0] = 001) This pin is multiplexed between EMIFA (NAND) and GPIO. EM_A[1]/(ALE)/GP[ 9]/ (AEAW1/PLLMS1) A16 B20 I/O/Z IPD DVDD33 DVDD33 EM_A[2]/(CLE)/GP [8]/ (AEAW0/PLLMS0) B16 A20 I/O/Z IPD DVDD33 DVDD33 EM_WAIT/ (RDY/BSY) E15 D20 I/O/Z IPU DVDD33 DVDD33 When used for EMIFA (NAND), it is ready/busy input (RDY/BSY). EM_OE D15 D19 I/O/Z IPU DVDD33 DVDD33 When used for EMIFA (NAND), this pin is read enable output (RE). EM_WE E14 C19 I/O/Z IPU DVDD33 DVDD33 When used for EMIFA (NAND), this pin is write enable output (WE). When used for EMIFA (NAND) , this pin is the Address Latch Enable output (ALE). This pin is multiplexed between EMIFA (NAND) and GPIO. When used for EMIFA (NAND), this pin is the Command Latch Enable output (CLE). This pin is multiplexed between EMIFA (NAND) and GPIO. EM_CS2/GP[12] C19 C22 Submit Documentation Feedback I/O/Z IPD DVDD33 DVDD33 For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use with NAND flash. This is the chip select for the default boot and ROM boot modes. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. Device Overview 31 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued) SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION This pin is multiplexed between EMIFA (NAND) and GPIO. EM_CS3/GP[13] C18 D22 I/O/Z IPD DVDD33 DVDD33 For EMIFA (NAND), this pin is Chip Select 3 output EM_CS3 for use with NAND flash. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. This pin is multiplexed between EMIFA (NAND) and GPIO. EM_CS4/GP[32] E19 H22 I/O/Z IPD DVDD33 DVDD33 For EMIFA (NAND), it is Chip Select 4 output EM_CS4 for use with NAND flash. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. This pin is multiplexed between EMIFA (NAND) and GPIO. For EMIFA (NAND), it is Chip Select 5 output EM_CS5 for use with NAND flash. EM_CS5/GP[33] F19 J22 I/O/Z IPD DVDD33 DVDD33 EM_D0/GP[14] D16 E21 I/O/Z IPD DVDD33 DVDD33 EM_D1/GP[15] D18 G20 I/O/Z IPD DVDD33 DVDD33 EM_D2/GP[16] D17 E22 I/O/Z IPD DVDD33 DVDD33 EM_D3/GP[17] E16 F20 I/O/Z IPD DVDD33 DVDD33 These pins are multiplexed between EMIFA (NAND) and GPIO. EM_D4/GP[18] E18 G21 I/O/Z IPD DVDD33 DVDD33 For EMIFA (NAND) AEM[2:0] = 001, these are the 8-bit bi-directional data bus (EM_D[7:0]). EM_D5/GP[19] E17 F22 I/O/Z IPD DVDD33 DVDD33 EM_D6/GP[20] F16 F21 I/O/Z IPD DVDD33 DVDD33 EM_D7/GP[21] F17 H20 I/O/Z IPD DVDD33 DVDD33 32 Device Overview Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101) SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 5, AEM[2:0] = 101) Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., AEAW[2:0], AEM[2:0], etc.). For more details, see Section 3.7, Multiplexed Pin Configurations This pin is multiplexed between EMIFA (NAND) and GPIO. EM_A[1]/(ALE)/GP[ 9]/ (AEAW1/PLLMS1) A16 B20 I/O/Z IPD DVDD33 DVDD33 EM_A[2]/(CLE)/GP [8]/ (AEAW0/PLLMS0) B16 A20 I/O/Z IPD DVDD33 DVDD33 EM_WAIT/ (RDY/BSY) E15 D20 I/O/Z IPU DVDD33 DVDD33 When used for EMIFA (NAND), it is ready/busy input (RDY/BSY). EM_OE D15 D19 I/O/Z IPU DVDD33 DVDD33 When used for EMIFA (NAND), this pin is read enable output (RE). EM_WE E14 C19 I/O/Z IPU DVDD33 DVDD33 When used for EMIFA (NAND), this pin is write enable output (WE). When used for EMIFA (NAND) , this pin is the Address Latch Enable output (ALE). This pin is multiplexed between EMIFA (NAND) and GPIO. When used for EMIFA (NAND) , this pin is the Command Latch Enable output (CLE). This pin is multiplexed between EMIFA (NAND) and GPIO. EM_CS2/GP[12] C19 C22 I/O/Z IPD DVDD33 DVDD33 For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with NAND flash. This is the chip select for the default boot and ROM boot modes. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. This pin is multiplexed between EMIFA (NAND) and GPIO. EM_CS3/GP[13] C18 D22 I/O/Z IPD DVDD33 DVDD33 For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with NAND flash. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. This pin is multiplexed between EMIFA (NAND) and GPIO. EM_CS4/GP[32] E19 H22 I/O/Z IPD DVDD33 DVDD33 For EMIFA, it is Chip Select 4 output EM_CS4 for use with NAND flash. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. This pin is multiplexed between EMIFA (NAND) and GPIO. EM_CS5/GP[33] (1) (2) (3) F19 J22 I/O/Z IPD DVDD33 DVDD33 For EMIFA, it is Chip Select 5 output EM_CS5 for use with NAND flash. Note: This pin features an internal pulldown (IPD). If this pin is connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensure the EM_CSx function defaults to an inactive (high) state. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 33 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101) (continued) SIGNAL NAME ZDU NO. TYPE (1) OTHER (2) (3) EM_D0/GP[14] D16 E21 I/O/Z IPD DVDD33 DVDD33 EM_D1/GP[15] D18 G20 I/O/Z IPD DVDD33 DVDD33 EM_D2/GP[16] D17 E22 I/O/Z IPD DVDD33 DVDD33 EM_D3/GP[17] E16 F20 I/O/Z IPD DVDD33 DVDD33 These pins are multiplexed between EMIFA (NAND) and GPIO. EM_D4/GP[18] E18 G21 I/O/Z IPD DVDD33 DVDD33 For EMIFA AEM[2:0] = 101 (NAND), these are the 8-bit bi-directional data bus (EM_D[7:0]). EM_D5/GP[19] E17 F22 I/O/Z IPD DVDD33 DVDD33 EM_D6/GP[20] F16 F21 I/O/Z IPD DVDD33 DVDD33 EM_D7/GP[21] 34 ZWT NO. F17 H20 I/O/Z IPD DVDD33 DVDD33 Device Overview DESCRIPTION Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-12. DDR2 Memory Controller Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DDR_CLK W7 AB7 I/O/Z DVDDR2 DDR2 Clock Output DDR_CLK W8 AB8 I/O/Z DVDDR2 DDR2 Differential Clock Output DDR_CKE V8 AA8 I/O/Z DVDDR2 DDR2 Clock Enable Output DDR_CS T9 Y11 I/O/Z DVDDR2 DDR2 Active Low Chip Select Output DDR_WE T8 Y10 I/O/Z DVDDR2 DDR2 Active Low Write Enable Output DDR_DQM[1] T6 Y7 I/O/Z DVDDR2 DDR_DQM[0] T4 Y4 I/O/Z DVDDR2 DDR2 Data Mask Outputs DQM1: For DDR_D[15:8] DQM0: For lower byte DDR_D[7:0] DDR_RAS U7 Y8 I/O/Z DVDDR2 DDR2 Row Access Signal Output DESCRIPTION DDR2 Memory Controller DDR_CAS I/O/Z DVDDR2 DDR2 Column Access Signal Output AA4 I/O/Z DVDDR2 U6 AA7 I/O/Z DVDDR2 Data strobe input/outputs for each byte of the 16-bit data bus. They are outputs to the DDR2 memory when writing and inputs when reading. They are used to synchronize the data transfers. DQS1: For DDR_D[15:8] DQS0: For bottom byte DDR_D[7:0] DDR_BA[0] U8 AA9 DDR_BA[1] V9 AB9 I/O/Z DVDDR2 Bank Select Outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories. DDR_BA[2] U9 AB10 DDR_A[12] W9 AA10 DDR_A[11] W10 AA11 DDR_A[10] U10 AB11 DDR_A[9] U11 AA12 DDR_A[8] V10 Y12 DDR_A[7] V11 AB12 DDR_A[6] W11 AA13 I/O/Z DVDDR2 DDR2 Address Bus Output DDR_A[5] W12 Y13 DDR_A[4] V12 AB13 DDR_A[3] U12 AA14 DDR_A[2] V13 Y14 DDR_A[1] U13 AB14 DDR_A[0] (3) Y9 U4 DDR_DQS[1] (1) (2) T7 DDR_DQS[0] W13 AB15 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Fore more information, see the Recommended Operating Conditions table Submit Documentation Feedback Device Overview 35 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-12. DDR2 Memory Controller Terminal Functions (continued) SIGNAL ZWT NO. ZDU NO. DDR_D[15] V7 W6 V6 W5 V5 U5 W4 V4 AB4 DDR_D[7] W3 W4 DDR_D[6] V3 U3 V2 AA3 DDR_D[3] U2 AA2 DDR_D[2] U1 W2 DDR_D[1] T2 Y2 DDR_D[0] T1 Y1 DDR_VREF T15 W18 Ground for the DDR2 DLL Y3 DDR_D[4] Reference voltage input for the SSTL_18 I/O buffers AB3 DDR_D[5] (3) W5 DDR_D[8] I AA5 DDR_D[9] DVDDR2 Y5 DDR_D[10] I/O/Z AB5 DDR_D[11] DESCRIPTION AA6 DDR_D[12] OTHER (2) (3) Y6 DDR_D[13] TYPE (1) AB6 DDR_D[14] NAME DDR2 bi-directional data bus is configured as 16-bits wide. DDR_VSSDLL T13 W15 GND (3) DDR_VDDDLL T12 W14 S (3) Power (1.8 Volts) for the DDR2 Digital Locked Loop DDR_ZN T10 W12 (3) Impedance control for DDR2 outputs. This must be connected via a 200- resistor to DVDDR2. DDR_ZP T11 W13 (3) Impedance control for DDR2 outputs. This must be connected via a 200- resistor to VSS. 36 Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-13. EMAC and MDIO Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Transmit Enable input MTXEN. DESCRIPTION EMAC MTXEN/GP[75] D3 C4 I/O/Z IPD DVDD33 DVDD33 MTXCLK/GP[73] A4 A4 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Transmit Clock input MTXCLK. MCOL/GP[67] C6 C6 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Collision Detect input MCOL. MTXD3/GP[69] C5 A5 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Transmit Data 3 output MTXD3. MTXD2/GP[70] D5 C5 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Transmit Data 2 output MTXD2. MTXD1/GP[71] B4 B4 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Transmit Data 1 output MTXD1. MTXD0/GP[72] D4 B5 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Transmit Data 0 output MTXD0. MRXCLK/GP[77] A3 A3 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Receive Clock input MRXCLK. MRXDV/GP[74] C4 D3 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Receive Data Valid input MRXDV. MRXER/GP[76] B3 B2 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Receive Error input MRXER. MCRS/GP[68] B5 B6 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Carrier Sense input MCRS. MRXD3/GP[82] C2 D2 I/O/Z IPU DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Receive Data 3 input MRXD3. MRXD2/GP[80] D2 C3 I/O/Z IPU DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Receive Data 2 input MRXD2. MRXD1/GP[79] B2 B3 I/O/Z IPU DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Receive data 1 input MRXD1. MRXD0/GP[78] C3 C2 I/O/Z IPU DVDD33 DVDD33 This pin is multiplexed between Ethernet MAC (EMAC) and GPIO. In Ethernet MAC mode, it is Receive Data 0 input MRXD0. MDIO MDCLK/GP[81] (3) D1 I/O/Z IPU DVDD33 DVDD33 This pin is multiplexed between MDIO and GPIO. In Ethernet MAC mode, it is Management Data Clock output MDCLK. MDIO/GP[83] (1) (2) C1 D1 C1 I/O/Z IPU DVDD33 DVDD33 This pin is multiplexed between MDIO and GPIO. In Ethernet MAC mode, it is Management Data IO MDIO (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 37 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-14. VPFE Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION VIDEO/IMAGE IN (VPFE) PCLK/GP[54] VD/GP[53] HD/GP[52] A14 A13 A15 A18 A17 A19 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between the VPFE (CCDC) and GPIO. In VPFE mode, this pin is the pixel clock input (PCLK) used to load image data into the CCD Controller (CCDC) on pins CI[7:0] and YI[7:0]. I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between the VPFE (CCDC) and GPIO. In VPFE mode, this pin is the vertical synchronization signal (VD) that can be either an input (slave mode) or an output (master mode), which signals the start of a new frame to the CCDC. I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between the VPFE (CCDC) and GPIO. In VPFE mode, this pin is the horizontal synchronization signal (HD) that can be either an input (slave mode) or an output (master mode), which signals the start of a new line to the CCDC. This pin is multiplexed between the VPFE (CCDC), EMIFA, and GPIO. CI1(CCD9)/ EM_A[19]/GP[45] B12 C14 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input CI1 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD9. In 8-bit YCbCr mode, this pin should not be used. This pin is multiplexed between the VPFE (CCDC), EMIFA, and GPIO. CI0(CCD8)/ EM_A[20]//GP[44] C12 C15 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input CI0 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD8. In 8-bit YCbCr mode, this pin should not be used. This pin is multiplexed between the VPFE (CCDC) and GPIO. YI7(CCD7)/ GP[43] A12 A15 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input YI7 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD7. In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the lower 8-bit channel. This pin is multiplexed between the VPFE (CCDC) and GPIO. YI6(CCD6)/ GP[42] B13 B15 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input YI6 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD6. In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and CR6 of the lower 8-bit channel. This pin is multiplexed between the VPFE (CCDC) and GPIO. YI5(CCD5)/ GP[41] (1) (2) (3) 38 C13 B16 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input YI5 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD5. In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the lower 8-bit channel. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-14. VPFE Terminal Functions (continued) SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION This pin is multiplexed between the VPFE(CCDC) and GPIO. YI4(CCD4)/ GP[40] D14 C18 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input YI4 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD4. In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the lower 8-bit channel. This pin is multiplexed between the VPFE (CCDC) and GPIO. YI3(CCD3)/ GP[39] B14 A16 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input YI3 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD3. In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the lower 8-bit channel. This pin is multiplexed between the VPFE (CCDC) and GPIO. YI2(CCD2)/ GP[38] C14 B17 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input YI2 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD2. In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the lower 8-bit channel. This pin is multiplexed between the VPFE (CCDC) and GPIO. YI1(CCD1)/ GP[37] B15 B18 I/O/Z IPD DVDD33 DVDD33 This pin is CCDC input YI1 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD1. In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the lower 8-bit channel. This pin is multiplexed between the VPFE (CCDC) and GPIO. YI0(CCD0)/ GP[36] C15 B19 I/O/Z IPD DVDD3 This pin is CCDC input YI0 and it supports several modes: In 10-bit CCD Raw mode, it is input CCD0. In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the lower 8-bit channel. C_WE/EM_R/W/ GP[35] D13 C17 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO. In VPFE mode, it is the CCD Controller write enable input C_WE. C_FIELD/EM_A[21]/ GP[34] D12 C16 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO. In VPFE mode, it is CCDC field identification bidirectional signal C_FIELD. Submit Documentation Feedback Device Overview 39 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-15. I2C Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION I2C SCL (3) 40 N2 I/O/Z DVDD33 DVDD33 SDA (1) (2) M2 For I2C, this pin is I2C clock. In I2C master mode, this pin is an output. In I2C slave mode, this pin is an input. When the I2C module is used, for proper device operation, this pin must be pulled up via an external resistor. M3 P2 I/O/Z DVDD33 DVDD33 For I2C, this pin is the I2C bi-directional data signal. When the I2C module is used, for proper device operation, this pin must be pulled up via an external resistor. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-16. Multichannel Buffered Serial Port 0 (McBSP0) Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION Multichannel Buffered Serial Port 0 (McBSP0) For more details on pin multiplexing, see Section 3.7, Multiplexed Pin Configurations. CLKS0/TOUT0L/ GP[97] J4 L3 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McBSP0, Timer0, and GPIO. For McBSP0, it is McBSP0 external clock source (I). ACLKR0/CLKX0/ GP[99] H1 J1 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McBSP0, it is McBSP0 transmit clock CLKX0 (I/O/Z). AHCLKR0/CLKR0/ GP[101] J2 K1 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McBSP0, it is McBSP0 receive clock CLKR0 (I/O/Z). AXR0[2]/FSX0/ GP[103] H3 J2 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McBSP0, it is McBSP0 transmit frame synchronization FSX0 (I/O/Z). AXR0[3]/FSR0/ GP[102] G4 J3 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McBSP0, it is McBSP0 receive frame synchronization FSR0 (I/O/Z). AXR0[1]/DX0/ GP[104] J3 K2 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McBSP0, it is McBSP0 data transmit output DX0 (O/Z). AFSR0/DR0/ GP[100] H4 K3 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McBSP0, it is McBSP0 data receive input DR0 (I). (1) (2) (3) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 41 TMS320DM6431 TMS320DM6431 Digital Media Processor SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 www.ti.com Table 2-17. Multichannel Audio Serial Port (McASP0) Terminal Functions SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) This pin is multiplexed between McASP0 and GPIO. For McASP0, it is McASP0 mute input AMUTEIN0 (I). DESCRIPTION McASP0 AMUTEIN0/ GP[109] F2 G3 I/O/Z IPD DVDD33 DVDD33 AMUTE0/GP[110] G3 H3 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0 and GPIO. For McASP0, it is McASP0 mute output AMUTE0 (O/Z). ACLKR0/CLKX0/ GP[99] H1 J1 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McASP0, it is McASP0 receive bit clock ACLKR0 (I/O/Z). AHCLKR0/CLKR0/ GP[101] J2 K1 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McASP0, it is McASP0 receive high-frequency master clock AHCLKR0 (I/O/Z). ACLKX0/GP[106] F1 G1 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0 and GPIO. For McASP0, it is McASP0 transmit bit clock ACLKX0 (I/O/Z). AHCLKX0/GP[108] G1 H1 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0 and GPIO. For McASP0, it is McASP0 transmit high-frequency master clock AHCLKX0 (I/O/Z). AFSR0/DR0/ GP[100] H4 K3 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McASP0, it is McASP0 receive frame synchronization AFSR0 (I/O/Z). AFSX0/GP[107] G2 G2 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0 and GPIO. For McASP0, it is McASP0 transmit frame synchronization AFSX0 (I/O/Z). AXR0[3]/FSR0/ GP[102] G4 J3 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 3 AXR0[3] (I/O/Z). AXR0[2]/FSX0/ GP[103] H3 J2 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 2 AXR0[2] (I/O/Z). AXR0[1]/DX0/ GP[104] J3 K2 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0, McBSP0, and GPIO. For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 1 AXR0[1] (I/O/Z). AXR0[0]/GP[105] H2 H2 I/O/Z IPD DVDD33 DVDD33 This pin is multiplexed between McASP0 and GPIO. For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 0 AXR0[0] (I/O/Z). (1) (2) (3) 42 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Submit Documentation Feedback TMS320DM6431 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C SPRS342C ­ NOVEMBER 2006 ­ REVISED JUNE 2008 Table 2-18. High-End Controller Area Network (HECC) SIGNAL NAME ZWT NO. ZDU NO. TYPE (1) OTHER (2) (3) DESCRIPTION HECC HECC_RX/ TINP1L/ GP[56] (3) P3 I/O/Z IPU DVDD33 DVDD33 This pin is multiplexed between HECC, Timer 1, and GPIO. For HECC, this pin is HECC receive serial data HECC_RX (I). HECC_TX/ TOUT1L/ GP[55] (1) (2) L4 K4 N3 I/O/Z IPU DVDD33 DVDD33 This pin is multiplexed between HECC, Timer 1, and GPIO. For HECC, this pin is HECC transmit serial data HECC_TX (O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Submit