TMS320C6713 SPRS186C IEC60958-1 CP-430 IEEE-1149 HD14/ HD12/ HD15/ HD10/ HD13/ - Datasheet Archive

 

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 D Highest-Performance Floating-Point

 

TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 D Highest-Performance Floating-Point Digital D D D D D D Signal Processor (DSP): TMS320C6713 TMS320C6713 ­ Eight 32-Bit Instructions/Cycle ­ 32/64-Bit Data Word ­ 225-, 200-MHz (GDP), and 200-, 167-MHz (PYP) Clock Rates ­ 4.4-, 5-, 6-Instruction Cycle Times ­ 1800 /1350 , 1600 /1200 , and 1336 /1000 MIPS /MFLOPS ­ Rich Peripheral Set, Optimized for Audio ­ Highly Optimized C/C+ Compiler VelociTI Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core ­ Eight Independent Functional Units: ­ Two ALUs (Fixed-Point) ­ Four ALUs (Floating- and Fixed-Point) ­ Two Multipliers (Floating- and Fixed-Point) ­ Load-Store Architecture With 32 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional Instruction Set Features ­ Native Instructions for IEEE 754 ­ Single- and Double-Precision ­ Byte-Addressable (8-, 16-, 32-Bit Data) ­ 8-Bit Overflow Protection ­ Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture ­ 4K-Byte L1P Program Cache (Direct-Mapped) ­ 4K-Byte L1D Data Cache (2-Way) ­ 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM Device Configuration ­ Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot ­ Endianness: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) ­ Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM ­ 512M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) D 16-Bit Host-Port Interface (HPI) D Two Multichannel Audio Serial Ports D D D D D D D D D D (McASPs) ­ Two Independent Clock Zones Each (1 TX and 1 RX) ­ Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones ­ Each Clock Zone Includes: ­ Programmable Clock Generator ­ Programmable Frame Sync Generator ­ TDM Streams From 2-32 Time Slots ­ Support for Slot Size: 8, 12, 16, 20, 24, 28, 32 Bits ­ Data Formatter for Bit Manipulation ­ Wide Variety of I2S and Similar Bit Stream Formats ­ Integrated Digital Audio Interface Transmitter (DIT) Supports: ­ S/PDIF, IEC60958-1 IEC60958-1, AES-3, CP-430 CP-430 Formats ­ Up to 16 transmit pins ­ Enhanced Channel Status/User Data ­ Extensive Error Checking and Recovery Two Inter-Integrated Circuit Bus (I2C Bus) Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports: ­ Serial-Peripheral-Interface (SPI) ­ High-Speed TDM Interface ­ AC97 Interface Two 32-Bit General-Purpose Timers Dedicated GPIO Module With 16 pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149 IEEE-1149.1 (JTAG) Boundary-Scan-Compatible Package Options: ­ 208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP) ­ 272-Ball, Ball Grid Array Package (GDP) 0.13-µm/6-Level Copper Metal Process ­ CMOS Technology 3.3-V I/Os, 1.2-V Internal (PYP) 3.3-V I/Os, 1.26-V Internal (GDP) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x, VelociTI, and PowerPAD are trademarks of Texas Instruments. I2C Bus is a trademark of Philips Electronics N.V. Corporation All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 1 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 Table of Contents GDP 272-Ball BGA package (bottom view) . . . . . . . . . . . . . . 3 PYP PowerPAD QFP package (top view) . . . . . . . . . . . . . . 8 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 functional block and CPU (DSP core) diagram . . . . . . . . . . 11 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . 12 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 16 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 CPU CSR register description . . . . . . . . . . . . . . . . . . . . . . . . 65 interrupts and interrupt selector . . . . . . . . . . . . . . . . . . . . . . . 67 external interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 EDMA module and EDMA selector . . . . . . . . . . . . . . . . . . . . 70 PLL and PLL controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 multichannel audio serial port (McASP) peripherals . . . . . 80 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . 87 EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2 POST OFFICE BOX 1443 bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature . 88 89 89 90 parameter measurement information . . . . . . . . . . . . . . . 91 signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 timing parameters and board routing analysis . . . . . . . 92 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 97 synchronous-burst memory timing . . . . . . . . . . . . . . . . 100 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . 102 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 112 multichannel audio serial port (McASP) timing . . . . . . 113 inter-integrated circuits (I2C) timing . . . . . . . . . . . . . . . 116 host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . 118 multichannel buffered serial port timing . . . . . . . . . . . . 121 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 general-purpose input/output (GPIO) port timing . . . . 133 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 GDP 272-Ball BGA package (bottom view) Y VSS VSS ED18 BE2 ARDY EA2 DVDD EA7 EA9 ECLKOUT ECLKIN CLKOUT2/ GP[2] VSS EA14 EA16 EA18 DVDD EA20 VSS VSS W VSS CVDD DVDD ED17 VSS CE2 EA4 EA6 DVDD AOE/ SDRAS/ SSOE VSS DVDD EA11 EA13 EA15 VSS EA19 CE1 CVDD VSS V ED20 ED19 CVDD ED16 BE3 CE3 EA3 EA5 EA8 EA10 ARE/ SDCAS/ SSADS AWE/ SDWE/ SSWE DVDD EA12 DVDD EA17 CE0 CVDD DVDD BE0 U ED22 ED21 ED23 VSS DVDD CVDD DVDD VSS VSS CVDD CVDD DVDD VSS CVDD CVDD DVDD VSS EA21 BE1 VSS T ED24 ED25 DVDD VSS VSS ED13 ED15 ED14 R DVDD ED27 ED26 CVDD CVDD DVDD ED11 ED12 P ED28 ED29 ED30 VSS VSS ED9 VSS ED10 N SCL0 SDA0 ED31 VSS VSS ED6 ED7 ED8 M CLKR1/ AXR0[6] DR1/ SDA1 FSR1/ AXR0[7] VSS VSS VSS VSS VSS VSS DVDD ED4 ED5 L FSX1 DX1/ AXR0[5] CLKX1/ AMUTE0 CVDD VSS VSS VSS VSS CVDD ED2 ED3 CVDD K CVDD VSS CLKS0/ AHCLKR0 CVDD VSS VSS VSS VSS CVDD ED0 ED1 VSS J DR0/ AXR0[0] DVDD FSR0/ AFSR0 VSS VSS VSS VSS VSS HOLD HOLDA BUS REQ HINT/ GP[1] H FSX0/ AFSX0 DX0/ AXR0[1] CLKR0/ ACLKR0 VSS VSS DVDD HRDY/ ACLKR1 HHWIL/ AFSR1 G TOUT0/ AXR0[2] TINP0/ AXR0[3] CLKX0/ ACLKX0 VSS VSS HCNTL0/ AXR1[3] HCNTL1/ AXR1[1] HR/W/ AXR1[0] F TOUT1/ AXR0[4] TINP1/ AHCLKX0 DVDD CVDD CVDD HDS2/ AXR1[5] VSS HCS/ AXR1[2] E CLKS1/ SCL1 VSS GP[7] (EXT_INT7) VSS VSS HAS/ ACLKX1 HDS1/ AXR1[6] HD0/ AXR1[4] D DVDD GP[6] (EXT_INT6) EMU2 VSS CVDD CVDD RSV VSS EMU0 CLKOUT3 CVDD RSV VSS CVDD CVDD DVDD VSS HD2/ AFSX1 DVDD HD1/ AXR1[7] GP[5] GP[4]/ C (EXT_INT5)/ (EXT_INT4)/ AMUTEIN0 AMUTEIN1 CVDD CLK MODE0 PLLHV VSS CVDD VSS VSS DVDD EMU4 RSV NMI HD14/ HD14/ GP[14] HD12/ HD12/ GP[12] HD9/ GP[9] HD6/ AHCLKR1 CVDD HD4/ GP[0] HD3/ AMUTE1 B VSS CVDD DVDD VSS RSV TRST TMS DVDD EMU1 EMU3 RSV EMU5 DVDD HD15/ HD15/ GP[15] VSS HD10/ HD10/ GP[10] HD8/ GP[8] HD5/ AHCLKX1 CVDD VSS A VSS VSS CLKIN CVDD RSV TCK TDI TDO CVDD CVDD VSS RSV RESET VSS HD13/ HD13/ GP[13] HD11/ HD11/ GP[11] DVDD HD7/ GP[3] VSS VSS 8 9 10 11 12 13 15 16 17 18 19 20 1 2 3 4 5 6 7 Shading denotes the GDP package pin functions that drop out on the PYP package. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 14 3 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 GDP 272-Ball BGA package (bottom view) (continued) Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) BALL NO. A1 SIGNAL NAME BALL NO. SIGNAL NAME VSS VSS C1 GP[5](EXT_INT5)/AMUTEIN0 A2 C2 GP[4](EXT_INT4)/AMUTEIN1 A3 CLKIN C3 CVDD A4 CVDD RSV C4 CLKMODE0 A5 C5 PLLHV A6 TCK C6 A7 TDI C7 VSS CVDD A8 TDO C8 A9 CVDD CVDD C9 VSS VSS C10 DVDD A10 A11 C11 EMU4 A12 VSS RSV C12 RSV A13 RESET C13 NMI A14 VSS HD13/GP HD13/GP[13] C14 HD14/GP HD14/GP[14] A15 C15 HD12/GP HD12/GP[12] A16 HD11/GP HD11/GP[11] C16 HD9/GP[9] A17 DVDD HD7/GP[3] C17 HD6/AHCLKR1 C18 CVDD VSS VSS C19 HD4/GP[0] C20 HD3/AMUTE1 VSS CVDD D1 DVDD D2 GP[6](EXT_INT6) D3 EMU2 B4 DVDD VSS D4 B5 RSV D5 VSS CVDD B6 TRST D6 CVDD B7 TMS D7 RSV B8 D8 B9 DVDD EMU1 D9 VSS EMU0 B10 EMU3 D10 CLKOUT3 B11 RSV D11 CVDD B12 EMU5 D12 RSV B13 DVDD HD15/GP HD15/GP[15] D13 D14 VSS CVDD VSS HD10/GP HD10/GP[10] D15 CVDD B16 D16 DVDD B17 HD8/GP[8] D17 B18 HD5/AHCLKX1 D18 VSS HD2/AFSX1 B19 CVDD VSS D19 DVDD D20 HD1/AXR1[7] A18 A19 A20 B1 B2 B3 B14 B15 B20 Shading denotes the GDP package pin functions that drop out on the PYP package. 4 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME E1 CLKS1/SCL1 J17 HOLD E2 VSS GP[7](EXT_INT7) J18 HOLDA J19 BUSREQ J20 HINT/GP[1] E17 VSS VSS K1 CVDD E18 HAS/ACLKX1 K2 E19 HDS1/AXR1[6] K3 VSS CLKS0/AHCLKR0 E20 E3 E4 HD0/AXR1[4] K4 CVDD F1 TOUT1/AXR0[4] K9 F2 TINP1/AHCLKX0 K10 VSS VSS F3 DVDD CVDD K12 VSS VSS CVDD HDS2/AXR1[5] K17 CVDD K18 ED0 K19 ED1 F20 VSS HCS/AXR1[2] K20 G1 TOUT0/AXR0[2] L1 VSS FSX1 G2 TINP0/AXR0[3] L2 DX1/AXR0[5] G3 CLKX0/ACLKX0 L3 CLKX1/AMUTE0 G4 L4 CVDD G17 VSS VSS L9 G18 HCNTL0/AXR1[3] L10 VSS VSS G19 HCNTL1/AXR1[1] L11 G20 F4 F17 F18 F19 K11 HR/W/AXR1[0] L12 VSS VSS H1 FSX0/AFSX0 L17 CVDD H2 DX0/AXR0[1] L18 ED2 H3 CLKR0/ACLKR0 L19 ED3 H4 VSS VSS L20 CVDD M1 CLKR1/AXR0[6] M2 DR1/SDA1 H19 DVDD HRDY/ACLKR1 M3 FSR1/AXR0[7] H20 HHWIL/AFSR1 M4 J1 DR0/AXR0[0] M9 VSS VSS J2 DVDD FSR0/AFSR0 M10 VSS VSS M12 M17 VSS VSS M18 DVDD J11 VSS VSS M19 ED4 J12 VSS M20 ED5 H17 H18 J3 J4 J9 J10 M11 VSS VSS Shading denotes the GDP package pin functions that drop out on the PYP package. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 5 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME N1 SCL0 U9 N2 SDA0 U10 VSS CVDD N3 ED31 U11 CVDD N4 U12 DVDD N17 VSS VSS U13 N18 ED6 U14 VSS CVDD N19 ED7 U15 CVDD N20 ED8 U16 DVDD P1 ED28 U17 P2 ED29 U18 VSS EA21 P3 ED30 U19 BE1 P4 U20 P17 VSS VSS V1 VSS ED20 P18 ED9 V2 ED19 P19 VSS ED10 V3 CVDD V4 ED16 V5 BE3 R2 DVDD ED27 V6 CE3 R3 ED26 V7 EA3 R4 CVDD CVDD V8 EA5 V9 EA8 V10 EA10 R19 DVDD ED11 V11 ARE/SDCAS/SSADS R20 ED12 V12 AWE/SDWE/SSWE T1 ED24 V13 DVDD T2 ED25 V14 EA12 T3 DVDD VSS V15 DVDD V16 EA17 VSS ED13 V17 CE0 T18 V18 CVDD T19 ED15 V19 DVDD T20 ED14 V20 BE0 U1 ED22 W1 U2 ED21 W2 VSS CVDD U3 ED23 W3 DVDD U4 VSS DVDD W4 ED17 W5 W6 VSS CE2 U7 CVDD DVDD W7 EA4 U8 VSS W8 EA6 P20 R1 R17 R18 T4 T17 U5 U6 Shading denotes the GDP package pin functions that drop out on the PYP package. 6 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued) BALL NO. W9 SIGNAL NAME BALL NO. SIGNAL NAME DVDD AOE/SDRAS/SSOE Y5 ARDY Y6 EA2 VSS DVDD Y7 DVDD W12 Y8 EA7 W13 EA11 Y9 EA9 W14 EA13 Y10 ECLKOUT W15 EA15 Y11 ECLKIN W16 VSS EA19 Y12 CLKOUT2/GP[2] W17 Y13 W18 CE1 Y14 VSS EA14 W19 CVDD VSS Y15 EA16 Y16 EA18 VSS VSS Y17 DVDD Y2 Y18 EA20 Y3 ED18 Y19 Y4 BE2 Y20 VSS VSS W10 W11 W20 Y1 Shading denotes the GDP package pin functions that drop out on the PYP package. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 7 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 PYP PowerPAD QFP package (top view) 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 HD4/GP[0] HD2/AFSX1 HD3/AMUTE1 HAS /ACLKX1 HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] CV DD VSS HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/ W/AXR1[0] VSS DV DD HRDY/ACLKR1 HHWIL/AFSR1 HOLD HOLDA BUSREQ HINT/GP[1] VSS CV DD ED0 ED1 ED2 ED3 ED5 ED4 DV DD VSS CV DD ED8 ED7 ED6 ED10 ED9 ED12 ED11 CV DD VSS DV DD ED14 ED15 ED13 BE0 EA21 BE1 DV DD VSS CV DD PYP 208-PIN 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP) (TOP VIEW) CVDD VSS HD5/AHCLKX1 HD8/GP[8] HD6/AHCLKR1 DVDD VSS HD7/GP[3] HD9/GP[9] HD10/GP HD10/GP[10] HD11/GP HD11/GP[11] HD12/GP HD12/GP[12] CVDD VSS CVDD HD13/GP HD13/GP[13] HD14/GP HD14/GP[14] HD15/GP HD15/GP[15] NMI RESET CVDD RSV RSV RSV RSV VSS DVDD 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 GP[4](EXT_INT4)/AMUTEIN1 GP[6](EXT_INT6) CV DD VSS DV DD GP[5](EXT_INT5)/AMUTEIN0 GP[7](EXT_INT7) CLKS1/SCL1 DV DD VSS CV DD TINP1/AHCLKX0 TOUT1/AXR0[4] CV DD VSS CLKX0/ACLKX0 TINP0/AXR0[3] TOUT0/AXR0[2] CLKR0/ACLKR0 DX0/AXR0[1] FSX0/AFSX0 CV DD VSS FSR0/AFSR0 DV DD VSS DR0/AXR0[0] CLKS0/AHCLKR0 CV DD VSS FSX1 DX1/AXR0[5] CLKX1/AMUTE0 VSS CV DD CLKR1/AXR0[6] DR1/SDA1 FSR1/AXR0[7] VSS CV DD SCL0 SDA0 CV DD DV DD VSS CV DD DV DD VSS VSS CV DD CV DD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CLKOUT3 EMU1 EMU0 TDO DVDD VSS CVDD TDI TMS TCK VSS CVDD CVDD TRST RSV VSS RSV CVDD PLLHV VSS CLKIN CLKMODE0 DVDD VSS CVDD 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 8 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 CVDD CE1 CE0 EA20 EA19 EA17 DVDD VSS CVDD EA18 EA15 EA12 EA16 EA13 EA14 CVDD VSS DVDD EA11 VSS DVDD AWE/SDWE/SSWE CLKOUT2/GP[2] VSS CVDD ARE/SDCAS/SSADS ECLKIN ECLKOUT EA10 AOE/SDRAS/SSOE EA9 VSS DVDD EA8 EA7 EA6 EA5 CVDD VSS DVDD EA4 EA3 EA2 CE2 CVDD VSS DVDD CE3 ARDY DVDD VSS CVDD TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 description The TMS320C67xt DSPs (including the TMS320C6713 TMS320C6713 device) compose the floating­point DSP generation in the TMS320C6000t DSP platform. The TMS320C6713 TMS320C6713 (C6713 C6713) device is based on the high-performance, advanced VelociTIt very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Operating at 225 MHz, the C6713 C6713 delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). The C6713 C6713 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-Byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-Byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-Byte memory space that is shared between program and data space. 64K Bytes of the 256K Bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K Bytes in L2 serves as mapped SRAM. The C6713 C6713 has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713 C6713 has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958 IEC60958, AES-3, CP-430 CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The two I2C ports on the TMS320C6713 TMS320C6713 allow the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The TMS320C6713 TMS320C6713 device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet. The TMS320C67x DSP generation is supported by the TI eXpressDSPt set of industry benchmark development tools, including a highly optimizing C/C+ Compiler, the Code Composer Studiot Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOSt kernel. TMS320C6000 TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 9 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 device characteristics Table 2 provides an overview of the C6713 C6713 DSP. The table shows significant features of the C6713 C6713 device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C67x DSP device part numbers and part numbering, see Table 24 and Figure 12. Table 2. Characteristics of the C6713 C6713 Processor C6713 C6713 (FLOATING-POINT DSP) INTERNAL CLOCK SOURCE HARDWARE FEATURES GDP PYP 1 (32 bit) 1 (16 bit) Not all peripheral pins are available at the same time. (For more details, see the Device Configuration section.) Peripheral P i h l performance i f is de endent dependent on chi -level chip-level configuration. EMIF SYSCLK3 or ECLKIN EDMA (16 Channels) CPU clock frequency 1 HPI (16 bit) SYSCLK2 1 McASPs AUXCLK, SYSCLK2 2 I2Cs SYSCLK2 2 McBSPs Peri herals Peripherals SYSCLK2 2 32-Bit Timers 1/4 of SYSCLK1 2 GPIO Module SYSCLK2 1 Size (Bytes) On-Chip Memory 264K 4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified L2 Cache/Mapped RAM 192KB 192KB L2 Mapped RAM Organization CPU ID+CPU Rev ID Control Status Register (CSR.[31:16]) BSDL File For the C6713 C6713 BSDL file, contact your Field Sales Representative. Frequency MHz Cycle Time ns 225, 200 Clock Generator Options 5 ns (C6713PYP-200 C6713PYP-200) 6 ns (C6713PYPA-167 C6713PYPA-167) 1.26 V [GDP Package] 1.2 V [PYP Package] I/O (V) 3.3 V Prescaler Multiplier Postscaler 27 x 27 mm Packages 200, 167 4.4 ns (C6713GDP-225 C6713GDP-225) 5 ns (C6713GDPA-200 C6713GDPA-200) Core (V) Voltage 0x0203 /1, /2, /3, ., /32 x4, x5, x6, ., x25 /1, /2, /3, ., /32 272-Ball BGA (GDP) ­ ­ 208-Pin PowerPAD PQFP (PYP) 28 x 28 mm Process Technology µm Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) 0.13 PD PD PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock check (high-frequency) circuit. C67x is a trademark of Texas Instruments. 10 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 functional block and CPU (DSP core) diagram C6713 C6713 Digital Signal Processor 32 EMIF L1P Cache Direct Mapped 4K Bytes Total L2 Cache/ Memory 4 Banks 64K Bytes Total McASP1 C67x CPU (up to 4-Way) McASP0 Instruction Fetch Control Registers Instruction Dispatch McBSP1 Data Path A Pin Multiplexing McBSP0 I2C1 I2C0 Timer 1 Control Logic Instruction Decode Data Path B A Register File Enhanced DMA Controller (16 channel) .L1 .S1 .M1 .D1 In-Circuit Emulation .D2 .M2 .S2 .L2 Interrupt Control L1D Cache 2-Way Set Associative 4K Bytes L2 Memory 192K Bytes Clock Generator and PLL x4 through x25 Multiplier /1 through /32 Dividers Timer 0 Test B Register File Power-Down Logic GPIO 16 HPI In addition to fixed-point instructions, these functional units execute floating-point instructions. EMIF interfaces to: ­SDRAM ­SBSRAM ­SRAM, ­ROM/Flash, and ­I/O devices McBSPs interface to: ­SPI Control Port ­High-Speed TDM Codecs ­AC97 Codecs ­Serial EEPROM POST OFFICE BOX 1443 McASPs interface to: ­I2S Multichannel ADC, DAC, Codec, DIR ­DIT: Multiple Outputs · HOUSTON, TEXAS 77251­1443 11 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 CPU (DSP core) description The TMS320C6713 TMS320C6713 floating-point digital signal processor is based on the C67x CPU. The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. 12 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 CPU (DSP core) description (continued) Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁ Á Á Á ÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ ÁÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁ Á ÁÁÁ Á long src long dst dst .S1 src1 32 8 8 src2 dst src1 .M1 src2 LD1 32 LSB DA2 LD2 32 LSB Á Á Á Á DA1 .D1 .D2 dst src1 src2 1X src2 src1 dst src2 .M2 src1 dst src2 src1 dst long dst long src .S2 Data Path B Á Á LD2 32 MSB ST2 long src long dst dst .L2 src2 src1 8 8 Register File B (B0­B15) 32 32 8 8 In addition to fixed-point instructions, these functional units execute floating-point instructions. Figure 1. TMS320C67x CPU (DSP Core) Data Paths POST OFFICE BOX 1443 Register File A (A0­A15) 2X Á Á Á Á Á Data Path A 32 Á Á Á Á Á LD1 32 MSB ST1 8 8 Á Á Á Á dst long dst long src Á Á Á Á Á .L1 src2 Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ src1 · HOUSTON, TEXAS 77251­1443 Control Register File 13 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 memory map summary Table 3 shows the memory map address ranges of the C6713 C6713 device. Table 3. TMS320C6713 TMS320C6713 Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE Internal RAM (L2) 192K 0000 0000 ­ 0002 FFFF Internal RAM/Cache 64K 0003 0000 ­ 0003 FFFF Reserved 24M ­ 256K 0004 0000 ­ 017F FFFF External Memory Interface (EMIF) Registers 256K 0180 0000 ­ 0183 FFFF L2 Registers 128K 0184 0000 ­ 0185 FFFF Reserved 128K 0186 0000 ­ 0187 FFFF HPI Registers 256K 0188 0000 ­ 018B FFFF McBSP 0 Registers 256K 018C 0000 ­ 018F FFFF McBSP 1 Registers 256K 0190 0000 ­ 0193 FFFF Timer 0 Registers 256K 0194 0000 ­ 0197 FFFF Timer 1 Registers 256K 0198 0000 ­ 019B FFFF 019C 0000 ­ 019C 01FF Interrupt Selector Registers 512 Device Configuration Registers 4 019C 0200 ­ 019C 0203 Reserved 256K ­ 516 019C 0204 ­ 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 ­ 01A3 FFFF Reserved 768K 01A4 0000 ­ 01AF FFFF GPIO Registers 16K 01B0 0000 ­ 01B0 3FFF Reserved 240K 01B0 4000 ­ 01B3 FFFF I2C0 Registers 16K 01B4 0000 ­ 01B4 3FFF I2C1 Registers 16K 01B4 4000 ­ 01B4 7FFF Reserved 16K 01B4 8000 ­ 01B4 BFFF McASP0 Registers 16K 01B4 C000 ­ 01B4 FFFF McASP1 Registers 16K 01B5 0000 ­ 01B5 3FFF Reserved 160K 01B5 4000 ­ 01B7 BFFF PLL Registers 8K 01B7 C000 ­ 01B7 DFFF Reserved 264K 01B7 E000 ­ 01BB FFFF Emulation Registers 256K 01BC 0000 ­ 01BF FFFF Reserved 4M 01C0 0000 ­ 01FF FFFF QDMA Registers 52 0200 0000 ­ 0200 0033 Reserved 16M ­ 52 0200 0034 ­ 02FF FFFF Reserved 720M 0300 0000 ­ 2FFF FFFF McBSP0 Data Port 64M 3000 0000 ­ 33FF FFFF McBSP1 Data Port 64M 3400 0000 ­ 37FF FFFF Reserved 64M 3800 0000 ­ 3BFF FFFF McASP0 Data Port 1M 3C00 0000 ­ 3C0F FFFF McASP1 Data Port 1M 3C10 0000 ­ 3C1F FFFF Reserved EMIF CE0 1G + 62M 3C20 0000 ­ 7FFF FFFF 256M 8000 0000 ­ 8FFF FFFF EMIF CE1 EMIF CE2 256M 9000 0000 ­ 9FFF FFFF 256M A000 0000 ­ AFFF FFFF EMIF CE3 256M B000 0000 ­ BFFF FFFF Reserved 1G C000 0000 ­ FFFF FFFF The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB 128MB per CE space. 14 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 L2 memory structure expanded Figure 2 shows the detail of the L2 memory structure. L2 Mode 000 001 010 L2 Memory 011 Block Base Address 111 192K SRAM 208K SRAM 224K SRAM 240K SRAM 192K-Byte RAM ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ 0x0003 0000 64K 4-Way Cache 48K 3-Way Cache 32K 2-Way Cache 16K-Byte RAM 16K 1-Way Cache 256K SRAM (All) 0x0000 0000 0x0003 4000 16K-Byte RAM 0x0003 8000 16K-Byte RAM 0x0003 C000 16K-Byte RAM 0x0003 FFFF Figure 2. L2 Memory Configuration POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 15 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions Table 4 through Table 17 identify the peripheral registers for the C6713 C6713 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions for the EMIF, EDMA, HPI, and McBSP modules, see the TMS320C6000 TMS320C6000 Peripherals Reference Guide (literature number SPRU190 SPRU190). Table 4. EMIF Registers HEX ADDRESS RANGE ACRONYM 0180 0000 GBLCTL EMIF global control REGISTER NAME 0180 0004 CECTL1 EMIF CE1 space control 0180 0008 CECTL0 EMIF CE0 space control 0180 000C ­ 0180 0010 CECTL2 Reserved EMIF CE2 space control 0180 0014 CECTL3 EMIF CE3 space control 0180 0018 SDCTL EMIF SDRAM control 0180 001C SDTIM EMIF SDRAM refresh control 0180 0020 SDEXT EMIF SDRAM extension 0180 0024 ­ 0183 FFFF ­ Reserved Table 5. L2 Cache Registers HEX ADDRESS RANGE CCFG 0184 4000 L2WBAR L2 writeback base address register 0184 4004 L2WWC L2 writeback word count register 0184 4010 L2WIBAR L2 writeback-invalidate base address register 0184 4014 L2WIWC L2 writeback-invalidate word count register 0184 4020 L1PIBAR L1P invalidate base address register 0184 4024 L1PIWC L1P invalidate word count register 0184 4030 L1DWIBAR L1D writeback-invalidate base address register 0184 4034 L1DWIWC L1D writeback-invalidate word count register 0184 5000 L2WB 0184 5004 L2WBINV 0184 8200 MAR0 Controls CE0 range 8000 0000 ­ 80FF FFFF 0184 8204 MAR1 Controls CE0 range 8100 0000 ­ 81FF FFFF 0184 8208 MAR2 Controls CE0 range 8200 0000 ­ 82FF FFFF 0184 820C MAR3 Controls CE0 range 8300 0000 ­ 83FF FFFF 0184 8240 MAR4 Controls CE1 range 9000 0000 ­ 90FF FFFF 0184 8244 MAR5 Controls CE1 range 9100 0000 ­ 91FF FFFF 0184 8248 MAR6 Controls CE1 range 9200 0000 ­ 92FF FFFF 0184 824C MAR7 Controls CE1 range 9300 0000 ­ 93FF FFFF 0184 8280 MAR8 Controls CE2 range A000 0000 ­ A0FF FFFF 0184 8284 MAR9 Controls CE2 range A100 0000 ­ A1FF FFFF 0184 8288 MAR10 MAR10 Controls CE2 range A200 0000 ­ A2FF FFFF 0184 828C MAR11 MAR11 Controls CE2 range A300 0000 ­ A3FF FFFF 0184 82C0 MAR12 MAR12 Controls CE3 range B000 0000 ­ B0FF FFFF 0184 82C4 MAR13 MAR13 Controls CE3 range B100 0000 ­ B1FF FFFF 0184 82C8 MAR14 MAR14 Controls CE3 range B200 0000 ­ B2FF FFFF 0184 82CC MAR15 MAR15 Controls CE3 range B300 0000 ­ B3FF FFFF 0184 82D0 ­ 0185 FFFF 16 ACRONYM 0184 0000 REGISTER NAME ­ Cache configuration register L2 writeback all register L2 writeback-invalidate all register Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions (continued) Table 6. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10­15 (INT10 INT10­INT15 INT15) 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4­9 (INT04 INT04­INT09 INT09) 019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts (EXT_INT4­EXT_INT7) 019C 000C ­ 019F FFFF ­ Reserved Table 7. Device Registers HEX ADDRESS RANGE ACRONYM 019C 0200 DEVCFG 019C 0204 ­ 019F FFFF ­ N/A CSR REGISTER DESCRIPTION Allows the user to control peripheral selection. This register also offers the user control of the EMIF input clock source. For more detailed information on the device configuration register, see the Device Configurations section of this data sheet. Device Configuration Reserved Identifies which CPU and defines the silicon revision of the CPU. This register also offers the user control of device operation. For more detailed information on the CPU Control Status Register, see the CPU CSR Register Description section of this data sheet. CPU Control Status Register Table 8. EDMA Parameter RAM HEX ADDRESS RANGE ACRONYM 01A0 0000 ­ 01A0 0017 ­ Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event 01A0 0018 ­ 01A0 002F ­ Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event 01A0 0030 ­ 01A0 0047 ­ Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event 01A0 0048 ­ 01A0 005F ­ Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event 01A0 0060 ­ 01A0 0077 ­ Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event 01A0 0078 ­ 01A0 008F ­ Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event 01A0 0090 ­ 01A0 00A7 ­ Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event 01A0 00A8 ­ 01A0 00BF ­ Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event 01A0 00C0 ­ 01A0 00D7 ­ Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event 01A0 00D8 ­ 01A0 00EF ­ Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event 01A0 00F0 ­ 01A0 00107 ­ Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event 01A0 0108 ­ 01A0 011F ­ Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event 01A0 0120 ­ 01A0 0137 ­ Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event 01A0 0138 ­ 01A0 014F ­ Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event 01A0 0150 ­ 01A0 0167 ­ Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event 01A0 0168 ­ 01A0 017F ­ Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event 01A0 0180 ­ 01A0 0197 ­ Reload/link parameters for Event 0­15 01A0 0198 ­ 01A0 01AF ­ Reload/link parameters for Event 0­15 . REGISTER NAME . 01A0 07E0 ­ 01A0 07F7 ­ 01A0 07F8 ­ 01A0 07FF ­ Reload/link parameters for Event 0­15 Scratch pad area (2 words) The C6713 C6713 device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 17 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions (continued) For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 3. 31 0 EDMA Parameter Word 0 EDMA Channel Options Parameter (OPT) OPT Word 1 EDMA Channel Source Address (SRC) SRC Word 2 Array/Frame Count (FRMCNT) Word 3 Element Count (ELECNT) EDMA Channel Destination Address (DST) CNT DST Word 4 Array/Frame Index (FRMIDX) Element Index (ELEIDX) IDX Word 5 Element Count Reload (ELERLD) Link Address (LINK) RLD Figure 3. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event Table 9. EDMA Registers HEX ADDRESS RANGE ACRONYM 01A0 0800 ­ 01A0 FEFC ­ 01A0 FF00 ESEL0 EDMA event selector 0 01A0 FF04 ESEL1 EDMA event selector 1 01A0 FF08 ­ 01A0 FF0B ­ 01A0 FF0C ESEL3 01A0 FF1F ­ 01A0 FFDC ­ 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPR Channel interrupt pending register 01A0 FFE8 CIER Channel interrupt enable register 01A0 FFEC CCER Channel chain enable register 01A0 FFF0 ER 01A0 FFF4 EER Event enable register 01A0 FFF8 ECR Event clear register 01A0 FFFC ESR Event set register 01A1 0000 ­ 01A3 FFFF ­ 18 REGISTER NAME Reserved Reserved EDMA event selector 3 Reserved Event register Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions (continued) Table 10. Quick DMA (QDMA) and Pseudo Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0200 0000 QOPT QDMA options parameter register 0200 0004 QSRC QDMA source address register 0200 0008 QCNT QDMA frame count register 0200 000C QDST QDMA destination address register 0200 0010 QIDX QDMA index register 0200 0014 ­ 0200 001C ­ 0200 0020 QSOPT QDMA pseudo options register 0200 0024 QSSRC QDMA pseudo source address register 0200 0028 QSCNT QDMA pseudo frame count register 0200 002C QSDST QDMA pseudo destination address register 0200 0030 QSIDX Reserved QDMA pseudo index register All the QDMA and Pseudo registers are write-accessible only Table 11. PLL Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B7 C000 PLLPID Peripheral identification register (PID) 01B7 C004 ­ 01B7 C0FF ­ [C6713 C6713 value: 0x00010801 for PLL Controller] Reserved 01B7 C100 PLLCSR 01B7 C104 ­ 01B7 C10F ­ PLL control/status register 01B7 C110 PLLM 01B7 C114 PLLDIV0 PLL controller divider 0 register 01B7 C118 PLLDIV1 PLL controller divider 1 register 01B7 C11C PLLDIV2 PLL controller divider 2 register 01B7 C120 PLLDIV3 PLL controller divider 3 register 01B7 C124 OSCDIV1 Oscillator divider 1 register 01B7 C128 ­ 01B7 DFFF ­ Reserved PLL multiplier control register Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 19 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions (continued) Table 12. McASP0 and McASP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 3C10 0000 ­ 3C10 FFFF RBUF/XBUFx McASPx receive buffer or McASPx transmit buffer via the Peripheral Data Bus. (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].) 01B4 C000 01B5 0000 MCASPPIDx Peripheral Identification register [C6713 C6713 value: 0x00100101 for McASP0 and for McASP1] 01B4 C004 01B5 0004 PWRDEMUx Power down and emulation management register 01B4 C008 01B5 0008 ­ Reserved 01B4 C00C 01B5 000C ­ Reserved 01B4 C010 01B5 0010 PFUNCx Pin function register 01B4 C014 01B5 0014 PDIRx Pin direction register 01B4 C018 01B5 0018 PDOUTx Pin data out register 01B4 C01C 01B5 001C PDIN/PDSETx McASP0 McASP1 3C00 0000 ­ 3C00 FFFF Pin data in / data set register Read returns: PDIN Writes affect: PDSET 01B4 C020 01B5 0020 PDCLRx 01B4 C024 ­ 01B4 C040 01B5 0024 ­ 01B5 0040 ­ Pin data clear register 01B4 C044 01B5 0044 GBLCTLx Global control register 01B4 C048 01B5 0048 AMUTEx Mute control register 01B4 C04C 01B5 004C DLBCTLx Digital Loop-back control register 01B4 C050 01B5 0050 DITCTLx DIT mode control register 01B4 C054 ­ 01B4 C05C 01B5 0054 ­ 01B5 005C ­ 01B4 C060 01B5 0060 RGBLCTLx 01B4 C064 01B5 0064 RMASKx Reserved Reserved Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive. Receiver format unit bit mask register 01B4 C068 01B5 0068 RFMTx 01B4 C06C 01B5 006C AFSRCTLx 01B4 C070 01B5 0070 ACLKRCTLx 01B4 C074 01B5 0074 AHCLKRCTLx 01B4 C078 01B5 0078 RTDMx 01B4 C07C 01B5 007C RINTCTLx 01B4 C080 01B5 0080 RSTATx Status register ­ Receiver 01B4 C084 01B5 0084 RSLOTx Current receive TDM slot register 01B4 C088 01B5 0088 RCLKCHKx 01B4 C08C ­ 01B4 C09C 01B5 008C ­ 01B5 009C ­ 01B4 C0A0 01B5 00A0 XGBLCTLx 01B4 C0A4 01B5 00A4 XMASKx 01B4 C0A8 01B5 00A8 XFMTx 01B4 C0AC 01B5 00AC AFSXCTLx 01B4 C0B0 01B5 00B0 ACLKXCTLx 01B4 C0B4 01B5 00B4 AHCLKXCTLx 20 POST OFFICE BOX 1443 Receive bit stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive TDM slot 0­31 register Receiver interrupt control register Receiver clock check control register Reserved Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. Transmit format unit bit mask register Transmit bit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions (continued) Table 12. McASP0 and McASP1 Registers (Continued) HEX ADDRESS RANGE McASP0 McASP1 ACRONYM REGISTER NAME 01B4 C0B8 01B5 00B8 XTDMx Transmit TDM slot 0­31 register 01B4 C0BC 01B5 00BC XINTCTLx Transmit interrupt control register 01B4 C0C0 01B5 00C0 XSTATx Status register ­ Transmitter 01B4 C0C4 01B5 00C4 XSLOTx Current transmit TDM slot 01B4 C0C8 01B5 00C8 XCLKCHKx 01B4 C0D0 ­ 01B4 C0FC 01B5 00CC ­ 01B5 00FC ­ 01B4 C100 01B5 0100 DITCSRA0x Left (even TDM slot) channel status register file 01B4 C104 01B5 0104 DITCSRA1x Left (even TDM slot) channel status register file Transmit clock check control register Reserved 01B4 C108 01B5 0108 DITCSRA2x Left (even TDM slot) channel status register file 01B4 C10C 01B5 010C DITCSRA3x Left (even TDM slot) channel status register file 01B4 C110 01B5 0110 DITCSRA4x Left (even TDM slot) channel status register file 01B4 C114 01B5 0114 DITCSRA5x Left (even TDM slot) channel status register file 01B4 C118 01B5 0118 DITCSRB0x Right (odd TDM slot) channel status register file 01B4 C11C 01B5 011C DITCSRB1x Right (odd TDM slot) channel status register file 01B4 C120 01B5 0120 DITCSRB2x Right (odd TDM slot) channel status register file 01B4 C124 01B5 0124 DITCSRB3x Right (odd TDM slot) channel status register file 01B4 C128 01B5 0128 DITCSRB4x Right (odd TDM slot) channel status register file 01B4 C12C 01B5 012C DITCSRB5x Right (odd TDM slot) channel status register file 01B4 C130 01B5 0130 DITUDRA0x Left (even TDM slot) user data register file 01B4 C134 01B5 0134 DITUDRA1x Left (even TDM slot) user data register file 01B4 C138 01B5 0138 DITUDRA2x Left (even TDM slot) user data register file 01B4 C13C 01B5 013C DITUDRA3x Left (even TDM slot) user data register file 01B4 C140 01B5 0140 DITUDRA4x Left (even TDM slot) user data register file 01B4 C144 01B5 0144 DITUDRA5x Left (even TDM slot) user data register file 01B4 C148 01B5 0148 DITUDRB0x Right (odd TDM slot) user data register file 01B4 C14C 01B5 014C DITUDRB1x Right (odd TDM slot) user data register file 01B4 C150 01B5 0150 DITUDRB2x Right (odd TDM slot) user data register file 01B4 C154 01B5 0154 DITUDRB3x Right (odd TDM slot) user data register file 01B4 C158 01B5 0158 DITUDRB4x Right (odd TDM slot) user data register file 01B4 C15C 01B5 015C DITUDRB5x Right (odd TDM slot) user data register file 01B4 C160 ­ 01B4 C17C 01B5 0160 ­ 01B5 017C ­ 01B4 C180 01B5 0180 SRCTL0x Serializer 0 control register 01B4 C184 01B5 0184 SRCTL1x Serializer 1 control register Reserved 01B4 C188 01B5 0188 SRCTL2x Serializer 2 control register 01B4 C18C 01B5 018C SRCTL3x Serializer 3 control register 01B4 C190 01B5 0190 SRCTL4x Serializer 4 control register 01B4 C194 01B5 0194 SRCTL5x Serializer 5 control register 01B4 C198 01B5 0198 SRCTL6x Serializer 6 control register 01B4 C19C 01B5 019C SRCTL7x Serializer 7 control register 01B4 C1A0 ­ 01B4 C1FC 01B5 01A0 ­ 01B5 01FC ­ POST OFFICE BOX 1443 Reserved · HOUSTON, TEXAS 77251­1443 21 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions (continued) Table 12. McASP0 and McASP1 Registers (Continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B5 0200 XBUF0x 01B4 C204 01B5 0204 XBUF1x Transmit Buffer for Serializer 0 through configuration bus Transmit Buffer for Serializer 1 through configuration bus 01B4 C208 01B5 0208 XBUF2x 01B4 C20C 01B5 020C XBUF3x 01B4 C210 01B5 0210 XBUF4x 01B4 C214 01B5 0214 XBUF5x 01B4 C218 01B5 0218 XBUF6x 01B4 C21C 01B5 021C XBUF7x 01B4 C220 ­ 01B4 C27C 01B5 C220 ­ 01B5 027C ­ 01B4 C280 01B5 0280 RBUF0x 01B4 C284 01B5 0284 RBUF1x 01B4 C288 01B5 0288 RBUF2x 01B4 C28C 01B5 028C RBUF3x 01B4 C290 01B5 0290 RBUF4x 01B4 C294 01B5 0294 RBUF5x 01B4 C298 01B5 0298 RBUF6x 01B4 C29C 01B5 029C RBUF7x 01B4 C2A0 ­ 01B4 FFFF 01B5 02A0 ­ 01B5 3FFF ­ McASP0 McASP1 01B4 C200 Transmit Buffer for Serializer 2 through configuration bus Transmit Buffer for Serializer 3 through configuration bus Transmit Buffer for Serializer 4 through configuration bus Transmit Buffer for Serializer 5 through configuration bus Transmit Buffer for Serializer 6 through configuration bus Transmit Buffer for Serializer 7 through configuration bus Reserved Receive Buffer for Serializer 0 through configuration bus Receive Buffer for Serializer 1 through configuration bus Receive Buffer for Serializer 2 through configuration bus Receive Buffer for Serializer 3 through configuration bus Receive Buffer for Serializer 4 through configuration bus Receive Buffer for Serializer 5 through configuration bus Receive Buffer for Serializer 6 through configuration bus Receive Buffer for Serializer 7 through configuration bus Reserved The transmit buffers for serializers 0 ­ 7 are accessible to the CPU via the peripheral bus if the XSEL bit = 1 (XFMT register). The receive buffers for serializers 0 ­ 7 are accessible to the CPU via the peripheral bus if the RSEL bit = 1 (RFMT register). Table 13. I2C0 and I2C1 Registers HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION I2C0 01B4 0000 01B4 4000 I2COARx I2Cx own address register 01B4 0004 01B4 4004 I2CIERx I2Cx interrupt enable register 01B4 0008 01B4 4008 I2CSTRx I2Cx interrupt status register 01B4 000C 01B4 400C I2CCLKLx I2Cx clock low-time divider register 01B4 0010 01B4 4010 I2CCLKHx I2Cx clock high-time divider register 01B4 0014 01B4 4014 I2CCNTx I2Cx data count register 01B4 0018 01B4 4018 I2CDRRx I2Cx data receive register 01B4 001C 01B4 401C I2CSARx I2Cx slave address register 01B4 0020 01B4 4020 I2CDXRx I2Cx data transmit register 01B4 0024 01B4 4024 I2CMDRx I2Cx mode register 01B4 0028 01B4 4028 I2CISRCx I2Cx interrupt source register 01B4 002C 01B4 402C ­ 01B4 0030 01B4 4030 I2CPSCx I2Cx prescaler register 01B4 0034 01B4 4034 I2CPID10 I2CPID10 I2CPID11 I2CPID11 I2Cx Peripheral Identification register 1 [C6713 C6713 value: 0x0000 0101] 01B4 0038 01B4 4038 I2CPID20 I2CPID20 I2CPID21 I2CPID21 I2Cx Peripheral Identification register 2 [C6713 C6713 value: 0x0000 0005] 01B4 003C ­ 01B4 3FFF 22 I2C1 01B4 403C ­ 01B4 7FFF ­ POST OFFICE BOX 1443 Reserved Reserved · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions (continued) Table 14. HPI Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS ­ HPID HPI data register Host read/write access only ­ HPIA HPI address register Host read/write access only 0188 0000 HPIC HPI control register Both Host/CPU read/write access 0188 0004 ­ 018B FFFF ­ Reserved Table 15. Timer 0 and Timer 1 Registers HEX ADDRESS RANGE TIMER 0 TIMER 1 ACRONYM REGISTER NAME COMMENTS 0194 0000 0198 0000 CTLx Timer x control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0194 0004 0198 0004 PRDx Timer x period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 0198 0008 CNTx Timer x counter register Contains the current value of the incrementing counter. 0194 000C ­ 0197 FFFF 0198 000C ­ 019B FFFF ­ Reserved ­ Table 16. McBSP0 and McBSP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION McBSP0 McBSP1 018C 0000 0190 0000 DRRx 3000 0000 ­ 33FF FFFF 3400 0000 ­ 37FF FFFF DRRx McBSPx data receive register via Peripheral Data Bus 018C 0004 0190 0004 DXRx McBSPx data transmit register via Configuration Bus 3000 0000 ­ 33FF FFFF 3400 0000 ­ 37FF FFFF DXRx McBSPx data transmit register via Peripheral Data Bus 018C 0008 0190 0008 SPCRx 018C 000C 0190 000C RCRx McBSPx receive control register 018C 0010 0190 0010 XCRx McBSPx transmit control register 018C 0014 0190 0014 SRGRx McBSPx data receive register via Configuration Bus The CPU and EDMA controller can only read this register; they cannot write to it. McBSPx serial port control register McBSPx sample rate generator register 018C 0018 0190 0018 MCRx McBSPx multichannel control register 018C 001C 0190 001C RCERx McBSPx receive channel enable register 018C 0020 0190 0020 XCERx McBSPx transmit channel enable register 018C 0024 0190 0024 PCRx 018C 0028 ­ 018F FFFF 0190 0028 ­ 0193 FFFF ­ POST OFFICE BOX 1443 McBSPx pin control register Reserved · HOUSTON, TEXAS 77251­1443 23 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 peripheral register descriptions (continued) Table 17. GPIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B0 0000 GPIO enable register GPDIR GPIO direction register 01B0 0008 GPVAL GPIO value register 01B0 000C ­ 01B0 0010 GPDH GPIO delta high register 01B0 0014 GPHM GPIO high mask register 01B0 0018 GPDL GPIO delta low register 01B0 001C GPLM GPIO low mask register 01B0 0020 GPGC GPIO global control register 01B0 0024 GPPOL GPIO interrupt polarity register 01B0 0028 ­ 01B0 3FFF 24 GPEN 01B0 0004 ­ Reserved Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 signal groups description CLKIN CLKOUT2/GP[2] CLKOUT3 CLKMODE0 PLLHV TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 Clock/PLL Oscillator Reset and Interrupts RESET NMI GP[7](EXT_INT7)§ GP[6](EXT_INT6)§ GP[5](EXT_INT5)/AMUTEIN0§ GP[4](EXT_INT4)/AMUTEIN1§ HD4/GP[0] IEEE Standard 1149.1 (JTAG) Emulation Control/Status HD15/GP HD15/GP[15] HD14/GP HD14/GP[14] HD13/GP HD13/GP[13] HD12/GP HD12/GP[12] HD11/GP HD11/GP[11] HD10/GP HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4] HPI (Host-Port Interface) Control Data Register Select Half-Word Select HAS/ACLKX1 HR/W/AXR1[0] HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HINT/GP[1] HCNTL0/AXR1[3] HCNTL1/AXR1[1] HHWIL/AFSR1 These external pins are applicable to the GDP package only. The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. For more details, see the External Interrupt Sources section of this data sheet. For more details on interrupt sharing, see the TMS320C6000 TMS320C6000 Peripherals Reference Guide (literature number SPRU190 SPRU190). § All of these pins are external interrupt sources. For more details, see the External Interrupt Sources section of this data sheet. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 4. CPU (DSP Core) and Peripheral Signals POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 25 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 signal groups description (continued) HD15/GP HD15/GP[15] HD14/GP HD14/GP[14] HD13/GP HD13/GP[13] HD12/GP HD12/GP[12] HD11/GP HD11/GP[11] HD10/GP HD10/GP[10] HD9/GP[9] HD8/GP[8] GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0] GPIO General-Purpose Input/Output (GPIO) Port TOUT1/AXR0[4] Timer 1 Timer 0 TOUT0/AXR0[2] TINP0/AXR0[3] TINP1/AHCLKX0 Timers CLKS1/SCL1 DR1/SDA1 I2C1 I2C0 SCL0 SDA0 I2Cs The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. GP[15:0] are also external EDMA event source capable. For more details, see the External Interrupt Sources and External EDMA Event Sources sections of this data sheet. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 5. Peripheral Signals 26 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 signal groups description (continued) ED[31:16] 16 16 Data ED[15:0] CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 Memory Control ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY Memory Map Space Select 20 Address Bus Arbitration HOLD HOLDA BUSREQ Byte Enables EMIF (External Memory Interface) McBSP1 McBSP0 CLKX1/AMUTE0 FSX1 DX1/AXR0[5] Transmit Transmit CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1] CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1 Receive Receive CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0] Clock Clock CLKS1/SCL1 CLKS0/AHCLKR0 McBSPs (Multichannel Buffered Serial Ports) These external pins are applicable to the GDP package only. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 5. Peripheral Signals (Continued) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 27 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 signal groups description (continued) (Transmit/Receive Data Pins) FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF (Receive Bit Clock) CLKR0/ACLKR0 CLKS0/AHCLKR0 (Transmit Bit Clock) Receive Clock Generator Transmit Clock Generator (Receive Master Clock) TINP1/AHCLKX0 (Transmit Master Clock) Receive Clock Check Circuit FSR0/AFSR0 (Receive Frame Sync or Left/Right Clock) CLKX0/ACLKX0 Transmit Clock Check Circuit Receive Frame Sync Transmit Frame Sync Error Detect (see Note A) Auto Mute Logic FSX0/AFSX0 (Transmit Frame Sync or Left/Right Clock) CLKX1/AMUTE0 GP[5](EXT_INT5)/AMUTEIN0 McASP0 (Multichannel Audio Serial Port 0) NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 5. Peripheral Signals (Continued) 28 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 signal groups description (continued) (Transmit/Receive Data Pins) HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF (Receive Bit Clock) HRDY/ACLKR1 HD6/AHCLKR1 (Transmit Bit Clock) Receive Clock Generator Transmit Clock Generator (Receive Master Clock) HD5/AHCLKX1 (Transmit Master Clock) Receive Clock Check Circuit HHWIL/AFSR1 (Receive Frame Sync or Left/Right Clock) HAS/ACLKX1 Transmit Clock Check Circuit Receive Frame Sync Transmit Frame Sync Error Detect (see Note A) Auto Mute Logic HD2/AFSX1 (Transmit Frame Sync or Left/Right Clock) HD3/AMUTE1 GP[4](EXT_INT4)/AMUTEIN1 McASP1 (Multichannel Audio Serial Port 1) NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 5. Peripheral Signals (Continued) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 29 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS On the C6713 C6713 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset. device configurations at device reset Table 18 describes the C6713 C6713 device configuration pins, which are set up via internal or external pullup/pulldown resistors through the HPI data pins (HD[4:3] and HD8) and CLKMODE0 pin. These configuration pins must be in the desired state until reset is released. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section of this data sheet. Table 18. Device Configurations Pins at Device Reset (HD[4:3], HD8, and CLKMODE0) CONFIGURATION PIN PYP GDP HD8 160 B17 HD[4:3] (BOOTMODE) CLKMODE0 156, 154 205 C19, C20 C4 FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 ­ System operates in Big Endian mode 1 ­ System operates in Little Endian mode (default) Bootmode Configuration Pins (BOOTMODE) 00 ­ CE1 width 32-bit, HPI boot/Emulation boot 01 ­ CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 ­ CE1 width 16-bit, Asynchronous external ROM boot with default timings 11 ­ CE1 width 32-bit, Asynchronous external ROM boot with default timings For more detailed information on these bootmode configurations, see the bootmode section of this data sheet. Clock generator input clock source select 0 ­ Reserved. Do not use. 1 ­ CLKIN square wave [default] This pin must be pulled to the correct level even after reset. All other HD pins (HD [15, 13:9, 7:5, 2:0] have pullups/pulldowns (IPUs or IPDs). For proper device operation, do not oppose these pins with external pullups/pulldowns at reset. 30 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) peripheral pin selection at device reset Some C6713 C6713 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:8, 3, 1, 0] and McASP1). D HPI, McASP1, and GPIO peripherals The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral pins or McASP1 peripheral pins and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 19). Table 19. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins) PERIPHERAL PIN SELECTION HPI_EN (HD14 Pin) [173, C14] PERIPHERAL PINS SELECTED HPI 0 1 DESCRIPTION McASP1 and GP[15:8,3,1,0] HPI_EN = 0 HPI pins are disabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins are enabled. All multiplexed HPI/McASP1 and HPI/GPIO pins function as McASP1 and GPIO pins, respectively. To use the GPIO pins, the appropriate bits in the GPEN and GPDIR registers need to be configured. HPI_EN = 1 HPI pins are enabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins are disabled [default]. All multiplexed HPI/McASP1 and HPI/GPIO pins function as HPI pins. The HPI_EN (HD[14]) pin cannot be controlled via software. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 31 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) peripheral selection/device configurations via the DEVCFG control register The device configuration register (DEVCFG) allows the user to control the pin availability of the McBSP0, McBSP1, McASP0, I2C1, and Timer peripherals. The DEVCFG register also offers the user control of the EMIF input clock source and the timer output pins. For more detailed information on the DEVCFG register control bits, see Table 20 and Table 21. Table 20. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 ­ 0x019C02FF] 31 16 Reserved RW-0 5 4 3 2 1 0 Reserved EKSRC TOUT1SEL TOUT0SEL MCBSP0DIS MCBSP1DIS RW-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 Legend: R/W = Read/Write; -n = value after reset Do not write non-zero values to these bit locations. Table 21. Device Configuration (DEVCFG) Register Selection Bit Descriptions BIT # NAME 31:5 Reserved 4 3 2 1 0 32 EKSRC DESCRIPTION Reserved. Do not write non-zero values to these bit locations. EMIF input clock source bit. Determines which clock signal is used as the EMIF input clock. 0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default) 1 = ECLKIN external pin is the EMIF input clock source TOUT1SEL Timer 1 output (TOUT1) pin function select bit. Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 1 output (TOUT1) pin (default) 1 = The pin functions as the McASP0 transmit/receive data pin 4 (AXR0[4]). The Timer 1 module is still active. TOUT0SEL Timer 0 output (TOUT0) pin function select bit. Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 0 output (TOUT0) pin (default) 1 = The pin functions as the McASP0 transmit/receive data pin 2 (AXR0[2]). The Timer 0 module is still active. MCBSP0DIS Multichannel Buffered Serial Port 0 (McBSP0) disable bit. Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled. 0 = McBSP0 peripheral pins are enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default). [If the McASP0 data pins are available, the McASP0 peripheral is functional for DIT mode only.] 1 = McBSP0 peripheral pins are disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled. MCBSP1DIS Multichannel Buffered Serial Port 1 (McBSP1) disable bit. Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled. 0 = McBSP1 peripheral pins are enabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0 peripheral pins (AXR0[7:5] and AMUTE0) are disabled (default) 1 = McBSP1 peripheral pins are disabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0 peripheral pins (AXR0[7:5] and AMUTE0) are enabled. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of these pins are configured by software via the device configuration register (DEVCFG), and the others (specifically, the HPI pins) are configured by external pullup/pulldown resistors only at reset. The muxed pins that are configured by software can be programmed to switch functionalities at any time. The muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 22 summarizes the peripheral pins affected by the HPI_EN (HD14 pin) and DEVCFG register. Table 23 identifies the multiplexed pins on the C6713 C6713 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure the specific multiplexed functions. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 33 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) Table 22. Peripheral Pin Selection Matrix SELECTION BITS B I T N A M E PERIPHERAL PINS AVAILABILITY B I T M c A S P 0 V A L U E M c A S P 1 I 2 C 0 I 2 C 1 M c B S P 0 T I M E R 0 M c B S P 1 T I M E R 1 H P I 0 AHCLKX1 AHCLKR1 ACLKX1 ACLKR1 AFSX1 AFSR1 AMUTE1 AXR1[0] to AXR1[7] None 1 None All HPI_EN (boot config pin) None 1 None All 1 AMUTE0 AXR0[5] AXR0[6] AXR0[7] All None 0 NO AXR0[2] TOUT0 1 AXR0[2] NO TOUT0 0 NO AXR0[4] TOUT1 1 AXR0[4] NO TOUT1 MCBSP1DIS (DEVCFG bit) TOUT1SEL (DEVCFG bit) NO GP[0:1], GP[3], GP[8:15] None NO AMUTE0 AXR0[5] AXR0[6] AXR0[7] Plus: GP[2] ctrl'd by GP2EN bit All ACLKK0 ACLKR0 AFSX0 AFSR0 AHCLKR0 AXR0[0] AXR0[1] 0 TOUT0SEL (DEVCFG bit) P I N S E M I F GP[0:1], GP[3], GP[8:15] 0 MCBSP0DIS (DEVCFG bit) G P I O Gray blocks indicate that the peripheral is not affected by the selection bit. The McASP0 pins AXR0[3] and AHCLKX0 are shared with the timer input pins TINP0 and TINP1, respectively. See Table 23 for more detailed information. 34 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) Table 23. C6713 C6713 Device Multiplexed/Shared Pins MULTIPLEXED PINS NAME CLKOUT2/GP[2] PYP 82 GDP Y12 GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 6 1 C1 C2 CLKS0/AHCLKR0 28 27 20 H2 FSR0/AFSR0 24 J3 FSX0/AFSX0 21 H1 CLKR0/ACLKR0 19 16 8 E1 DR1/SDA1 37 M2 DX1/AXR0[5] 32 L2 FSR1/AXR0[7] 38 M3 CLKR1/AXR0[6] 36 M1 CLKX1/AMUTE0 33 No Function GPxDIR = 0 (input) GP5EN = 0 (disabled) GP4EN = 0 (disabled) [(GPEN register bits) GP[x] function disabled] G3 CLKS1/SCL1 GP[5](EXT_INT5) GP[4](EXT_INT4) When the CLKOUT2 pin is enabled , the CLK2EN bit in the EMIF global control register (GBLCTL) controls the CLKOUT2 pin. CLK2EN = 0: CLKOUT2 held high CLK2EN = 1: CLKOUT2 enabled to clock [default] H3 CLKX0/ACLKX0 GP2EN = 0 (GPEN register bit) GP[2] function disabled, CLKOUT2 enabled CLKOUT2 DESCRIPTION J1 DX0/AXR0[1] DEFAULT SETTING K3 DR0/AXR0[0] DEFAULT FUNCTION L3 McBSP0 pin function in McBSP1 pin f nction function POST OFFICE BOX 1443 MCBSP0DIS = 0 (DEVCFG register bit) i bi ) McASP0 pins disabled disabled, McBSP0 pins enabled ins MCBSP1DIS = 0 (DEVCFG register bit) I2C1 and McASP0 pins disabled, McBSP1 pins ins enabled · HOUSTON, TEXAS 77251­1443 To use these software-configurable GPIO pins, the GPxEN bits in the GP Enable Register and the GPxDIR bits in the GP Direction Register must be properly configured. GPxEN = 1: GP[x] pin enabled GPxDIR = 0: GP[x] pin is an input GPxDIR = 1: GP[x] pin is an output To use AMUTEIN0/1 pin function, the GP[5]/GP[4] pins must be configured as an input, the INEN bit set to 1, and the polarity through the INPOL bit selected in the associated McASP AMUTE register. By default, McBSP0 peripheral pins are default upon enabled u on reset (McASP0 pins are ins ) disabled). To enable the McASP0 peripheral pins pins, the MCBSP0DIS bit in the DEVCFG register must be set to 1 (disabling the McBSP0 M BSP0 peripheral pins). i h l i ) By default, McBSP1 peripheral pins are eri heral ins enabled upon reset (I2C1 and McASP0 disabled). pins are disabled) To enable the I2C1 and McASP0 peripheral pins, the MCBSP1DIS bit in pins the DEVCFG register must be set to 1 (disabling the McBSP1 peripheral pins). 35 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) Table 23. C6713 C6713 Device Multiplexed/Shared Pins (Continued) MULTIPLEXED PINS NAME PYP GDP HINT/GP[1] 135 174 173 C14 HD13/GP HD13/GP[13] 172 A15 HD12/GP HD12/GP[12] 168 C15 HD11/GP HD11/GP[11] 167 A16 HD10/GP HD10/GP[10] 166 B16 HD9/GP[9] 165 C16 HD8/GP[8] 160 B17 HD7/GP[3] 164 A18 HD4/GP[0] 156 C19 HD1/AXR1[7] 152 D20 HD0/AXR1[4] 147 E20 HCNTL1/AXR1[1] 144 G19 HCNTL0/AXR1[3] 146 G18 HR/W/AXR1[0] 143 G20 HDS1/AXR1[6] 151 E19 HDS2/AXR1[5] 150 F18 HCS/AXR1[2] 145 F20 HD6/AHCLKR1 161 C17 HD5/AHCLKX1 159 B18 HD3/AMUTE1 154 C20 HD2/AFSX1 155 D18 HHWIL/AFSR1 139 H20 HRDY/ACLKR1 140 H19 HAS/ACLKX1 153 E18 TINP0/AXR0[3] 17 G2 DESCRIPTION B14 HD14/GP HD14/GP[14] DEFAULT SETTING J20 HD15/GP HD15/GP[15] DEFAULT FUNCTION By d f lt th B default, the HPI peripheral pins are i h l i enabled at reset. McASP1 peripheral reset pins and eleven GPIO pins are ins ins disabled. To enable the McASP1 peripheral pins and the eleven GPIO pins, an external ins, pulldown resistor must be provided on the HD14 pin setting HPI EN = 0 at HPI_EN reset. HPI_EN (HD14 pin) = 1 in) (HPI enabled) HPI pin function McASP1 pins and eleven GPIO pins are disabled. ins To use these software configurable software-configurable GPIO pins, the GPxEN bits in the GP Enable Register and the GPxDIR bits in the GP Direction Register must be properly configured. configured GPxEN = 1: GP[x] pin enabled in GPxDIR = 0: GP[x] pin is an input [ ] GPxDIR = 1: GP[x] pin is an output McASP1 pin direction is controlled by y the PDIR[x] bits in the McASP1PDIR S register. register Timer 0 input function McASP0PDIR = 0 (input) [specifically AXR0[3] bit] By default, the Timer 0 input pin is enabled (and a shared input until the McASP0 peripheral forces an output). McASP0PDIR = 0 input, = 1 output By default, the Timer 0 output pin is enabled. TOUT0/AXR0[2] 36 18 G1 Timer 0 output function POST OFFICE BOX 1443 TOUT0SEL = 0 (DEVCFG register bit) [TOUT0 pin enabled and McASP0 AXR0[2] pin disabled] · HOUSTON, TEXAS 77251­1443 To enable the McASP0 AXR0[2] pin, the TOUT0SEL bit in the DEVCFG register must be set to 1 (disabling the Timer 0 peripheral output pin function). The AXR2 bit in the McASP0PDIR register controls the direction (input/output) of the AXR0[2] pin McASP0PDIR = 0 input, = 1 output TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) Table 23. C6713 C6713 Device Multiplexed/Shared Pins (Continued) MULTIPLEXED PINS NAME TINP1/AHCLKX0 PYP 12 GDP F2 DEFAULT FUNCTION Timer 1 input function DEFAULT SETTING DESCRIPTION McASP0PDIR = 0 (input) [specifically AHCLKX bit] By default, the Timer 1 input and McASP0 clock function are enabled as inputs. For the McASP0 clock to function as an output: McASP0PDIR = 1 (specifically the AHCLKX bit] By default, the Timer 1 output pin is enabled. TOUT1/AXR0[4] 13 F1 Timer 1 output function TOUT1SEL = 0 (DEVCFG register bit) [TOUT1 pin enabled and McASP0 AXR0[4] pin disabled] To enable the McASP0 AXR0[4] pin, the TOUT1SEL bit in the DEVCFG register must be set to 1 (disabling the Timer 1 peripheral output pin function). The AXR4 bit in the McASP0PDIR register controls the direction (input/output) of the AXR0[4] pin McASP0PDIR = 0 input, = 1 output configuration examples Figure 6 through Figure 11 illustrate examples of peripheral selections that are configurable on this device. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 37 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI SCL1, SDA1 I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 McASP1 8 AXR1[7:0] 8 AXR0[7:0] {TINP0/AXR0[3]} McBSP1 McASP0 TIMER0 McBSP0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F MCBSP0DIS = 1 MCBSP1DIS = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 6. Configuration Example A (2 I2C + 2 McASP + GPIO) 38 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 McASP1 8 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] 5 AXR0[4:0] {TINP0/AXR0[3]} DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McBSP1 McASP0 TIMER0 TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 McBSP0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000E MCBSP0DIS = 1 MCBSP1DIS = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 7. Configuration Example B (1 I2C + 1 McBSP + 2 McASP + GPIO) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 39 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI SCL1, SDA1 I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 McASP1 8 AXR1[7:0] 6 McBSP1 McASP0 (DIT Mode) AXR0[7:2] {TINP0/AXR0[3]} AMUTE0, TINP1/AHCLKX0 TIMER0 McBSP0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000D MCBSP0DIS = 0 MCBSP1DIS = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 8. Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO] 40 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 McASP1 8 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] 3 McBSP1 DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McASP0 (DIT Mode) AXR0[4:2] {TINP0/AXR0[3]} TINP1/AHCLKX0 TIMER0 TOUT0/AXR0[2] TIMER1 TOUT1/AXR0[4] McBSP0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000C MCBSP0DIS = 0 MCBSP1DIS = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 9. Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers] POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 41 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset CLKOUT2 GPIO and EXT_INT GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) 16 HD[15:0] HPI I2C0 I2C1 McASP1 SCL0, SDA0 HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS SCL1, SDA1 8 AXR0[7:0], {TINP0/AXR0[3]} McBSP1 McASP0 TIMER0 McBSP0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F MCBSP0DIS = 1 MCBSP1DIS = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (enabling GPEN.[2]) Figure 10. Configuration Example E (1 I2C + HPI + 1 McASP) 42 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset CLKOUT2 GPIO and EXT_INT GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) 16 HD[15:0] HPI I2C0 I2C1 McASP1 SCL0, SDA0 HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS 5 AXR0[4:0] {TINP0/AXR0[3]} DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McBSP1 McASP0 TIMER0 TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 McBSP0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000E MCBSP0DIS = 1 MCBSP1DIS = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (enabling GPEN.[2]) Figure 11. Configuration Example F (1 McBSP + HPI + 1 McASP) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 43 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 DEVICE CONFIGURATIONS (CONTINUED) debugging considerations It is recommended that external connections be provided to peripheral selection/device configuration pins, including HD[14, 8, 4, 3], and CLKMODE0. Although internal pullup resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the HPI data bus (HD[15, 13:9, 7:5, 2:0]). For proper device operation, do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors for all device pins, see the terminal functions table. 44 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 TERMINAL FUNCTIONS The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 45 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 Terminal Functions SIGNAL NAME PIN NO. TYPE IPD/ IPU DESCRIPTION PYP GDP CLKIN 204 A3 I IPD Clock Input CLKOUT2/GP[2] 82 Y12 O/Z IPD Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z) CLKOUT3 184 D10 O IPD Clock output programmable by OSCDIV1 register in the PLL controller. IPU Clock generator input clock source select 0 ­ Reserved, do not use. 1 ­ CLKIN square wave [default] For proper device operation, this pin must be either left unconnected or externally pulled up with a 1-k resistor. CLOCK/PLL CONFIGURATION CLKMODE0 205 C4 I PLLHV 202 C5 A§ Analog power (3.3 V) for PLL (PLL Filter) JTAG EMULATION TMS 192 B7 I IPU JTAG test-port mode select TDO 187 A8 O/Z IPU JTAG test-port data out TDI 191 A7 I IPU JTAG test-port data in TCK 193 A6 I IPU JTAG test-port clock TRST 197 B6 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet. EMU5 - B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 - C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 - B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 - D3 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 EMU0 185 186 B9 D9 Emulation [1:0] pins · Select the device functional mode of operation EMU[1:0] Operation 00 Boundary Scan/Functional Mode (see Note) 01 Reserved 10 Reserved 11 Emulation/Functional Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet) I/O/Z IPU The DSP can be placed in Functional mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Functional mode. For the Boundary Scan mode drive EMU[1:0] and RESET pins low. RESETS AND INTERRUPTS RESET 176 A13 I IPU Device reset NMI 175 C13 I IPD Nonmaskable interrupt · Edge-driven (rising edge) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k resistor (approximate) for the IPD or 18-k resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k and 2.0 k, respectively, should be used to pull a signal to the opposite supply rail.] § A = Analog signal 46 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186C SPRS186C ­ DECEMBER 2001 ­ REVISED MARCH 2003 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION RESETS AND INTERRUPTS (CONTINUED) GP[7](EXT_INT7) 7 E3 GP[6](EXT_INT6) 2 D2 GP[5](EXT_INT5)/ AMUTEIN0 6 C1 GP[4](EXT_INT4)/ AMUTEIN1 1 I/O/Z IPU General-purpose input/output pins (I/O/Z) which also function as external interrupts · Edge-driven · Polarit independentl selected via the E ternal Interrupt Polarity Register Polarity independently ia External Interr pt Polarit bits (EXTPOL.[3:0]), in addition to the GPIO registers. GP[4] and GP[5] pins also f d i l function as AMUTEIN1 M ASP1 mute i i McASP1 input and d AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the associated McASP AMUTE register. C2 HOST-PORT INTERFACE (HPI) HINT/GP[1] 135 J20 O/Z IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). HCNTL1/AXR1[1] 144 G19 I IPU Host control ­ selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z). HCNTL0/AXR1[3] 146 G18 I IPU Host control ­ selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z). HHWIL/AFSR1 139 H20 I IPU Host half-word select ­ first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). HR/W/AXR1[0] 143 G20 I IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z). HD15/GP HD15/GP[15] 174 B14 IPU HD14/GP HD14/GP[14] 173 C14 IPU HD13/GP HD13/GP[13] 172 A15 IPU HD12/GP HD12/GP[12] 168 C15 IPU HD11/GP HD11/GP[11] 167 A16 HD10/GP HD10/GP[10] 166 B16 IPU HD9/GP[9] 165 C16 IPU HD8/GP[8] 160 B17 IPU HD7/GP[3] 164 A18 IPU HD6/AHCLKR1 161 C17 I/O/Z 159 B18 ­ Boot mode (HD[4:3]) 00 ­ CE1 width 32-bit, HPI boot/Emulation boot 32 bit, 01 ­ CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 ­ CE1 width 16-bit, Asynchronous external ROM boot with default timings 11 ­ CE1 width 32-bit, Asynchronous external ROM boot with default timings IPU IPU I/O/Z HD5/AHCLKX1 Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z) · Used for transfer of data address and control data, address, · Also controls initialization of DSP modes at reset via pullup/pulldown resistors ­ Device Endian mode (HD8) 0 ­ Big Endian 1 ­ Little Endian IPU ­ HPI_EN (HD14) 0 ­ HPI di bl d M ASP1 enabled disabled, McASP1 bl d 1 ­ HPI enabled, McASP1 disabled (default) Other HD pins (HD [15, 13:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). For proper device operation, do not oppose these pins with external IPUs/IPDs at reset. For more details, see the Device Configurations section of this data sheet. Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k resistor (approximate) for the IPD or 18-k resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k and 2.0 k, respectively, should be used to pull a signal to the opposite suppl