TMS320C6745/6747 SPRS377B C6747 128MB 256MB C6745 TMS320C6000 C6000 TMS320 - Datasheet Archive

 

www.ti.com SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 1 TMS320C6745/6747 Floating-point Digital Signal Processor

 

TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 1 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor 1.1 Features · · · · · · Applications ­ Industrial Control ­ USB, Networking ­ High-Speed Encoding ­ Professional Audio Software Support ­ TI DSP/BIOSTM ­ Chip Support Library and DSP Library 300-MHz C674x VLIW DSP C674x Instruction Set Features ­ Superset of the C67x+TM and C64x+TM ISAs ­ 2400/1800 C674x MIPS/MFLOPS ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions C674x Two Level Cache Memory Architecture ­ 32K-Byte L1P Program RAM/Cache ­ 32K-Byte L1D Data RAM/Cache ­ 256K-Byte L2 Unified Mapped RAM/Cache ­ Flexible RAM/Cache Partition (L1 and L2) ­ 1024K-Byte L2 ROM Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Transfer Controllers ­ 32 Independent DMA Channels ­ 8 Quick DMA Channels ­ Programmable Transfer Burst Size TMS320C674x Floating Point VLIW DSP Core ­ Load-Store Architecture With Non-Aligned Support ­ 64 General-Purpose Registers (32 Bit) ­ Six ALU (32-/40-Bit) Functional Units · Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point · Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks · Supports up to Two Floating Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle ­ Two Multiply Functional Units · · · · · · · · · · Mixed-Precision IEEE Floating Point Multiply Supported up to: ­ 2 SP x SP -> SP Per Clock ­ 2 SP x SP -> DP Every Two Clocks ­ 2 SP x DP -> DP Every Three Clocks ­ 2 DP x DP -> DP Every Four Clocks · Fixed Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Hardware Support for Modulo Loop Operation ­ Protected Mode Operation ­ Exceptions Support for Error Detection and Program Redirection 128K-Byte RAM Shared Memory (C6747 C6747 Only) 3.3V LVCMOS IOs (except for USB interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128MB 128MB Address Space ­ EMIFB · 32-Bit or 16-Bit SDRAM With 256MB 256MB Address Space (C6747 C6747) · 16-Bit SDRAM With 256MB 256MB Address Space (C6745 C6745) Three Configurable 16550 type UART Modules: ­ UART0 With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option LCD Controller (C6747 C6747 Only) Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Two Master/Slave Inter-Integrated Circuit (I2C BusTM) One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth (C6747 C6747 only) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. TMS320C6000 TMS320C6000, C6000 C6000 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2008­2008, Texas Instruments Incorporated ADVANCE INFORMATION · TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 · · ADVANCE INFORMATION · · · · 2 USB 1.1 OHCI (Host) With Integrated PHY (USB1) (C6747 C6747 Only) USB 2.0 OTG Port With Integrated PHY (USB0) ­ USB 2.0 High-/Full-Speed Client (C6747 C6747) ­ USB 2.0 Full-Speed Client (C6745 C6745) ­ USB 2.0 High-/Full-/Low-Speed Host (C6747 C6747) ­ USB 2.0 Full-/Low-Speed Host (C6745 C6745) ­ High-speed Functionality Available on C6747 C6747 Device Only ­ End Point 0 (Control) ­ End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx Three Multichannel Audio Serial Ports: ­ Transmit/Receive Clocks up to 50 MHz ­ Six Clock Zones and 28 Serial Data Pins ­ Supports TDM, I2S, and Similar Formats ­ DIT-Capable (McASP2) ­ FIFO buffers for Transmit and Receive 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802.3 Compliant (3.3-V I/O Only) ­ RMII Media Independent Interface ­ Management Data I/O (MDIO) Module Real-Time Clock With 32 KHz Oscillator and Separate Power Rail (C6747 C6747 Only) One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers) TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com · · · · · · · One 64-Bit General-Purpose Timer (Watch Dog) Three Enhanced Pulse Width Modulators (eHRPWM): ­ Dedicated 16-Bit Time-Base Counter With Period And Frequency Control ­ 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs ­ Dead-Band Generation ­ PWM Chopping by High-Frequency Carrier ­ Trip Zone Input Three 32-Bit Enhanced Capture Modules (eCAP): ­ Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs ­ Single Shot Capture of up to Four Event Time-Stamps Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP) C6747 C6747 Device: ­ 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch C6745 C6745 Device ­ 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch Commercial or Automotive Temperature Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 1.2 Trademarks DSP/BIOS, TMS320C6000 TMS320C6000, C6000 C6000, TMS320 TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments. ADVANCE INFORMATION All trademarks are the property of their respective owners. Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor 3 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 1.3 Description The C6745/6747 C6745/6747 is a Low-power digital signal processor based on C674x DSP core. It provides significantly lower power than other members of the TMS320C6000TM TMS320C6000TM platform of DSPs. The C6745/6747 C6745/6747 enables OEMs and ODMs to quickly bring to market devices featuring high processing performance . ADVANCE INFORMATION The C6745/6747 C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB 256KB memory space that is shared between program and data space. L2 also has a 1024KB 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB 128KB RAM shared memory ( C6747 C6747 only) is available for use by other hosts without affecting DSP performance. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with 16/9 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) [C6747 C6747 only]; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6745/6747 C6745/6747 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. 4 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 1.4 Functional Block Diagram JTAG Interface DSP Subsystem System Control C674xTM DSP CPU PLL/Clock Generator w/OSC AET GeneralPurpose Timer GeneralPurpose Timer (Watchdog) 32 KB L1 Pgm Power/Sleep Controller 32 KB L1 RAM 256 KB L2 RAM RTC/ Pin 32-KHz Multiplexing OSC 1024 KB L2 ROM ADVANCE INFORMATION Input Clock(s) Switched Central Resource (SCR) Peripherals DMA EDMA3 McASP w/FIFO (3) I2C (2) eCAP (3) SPI (2) UART (3) LCD Ctlr Connectivity Control Timers eHRPWM (3) Display Serial Interfaces Audio Ports eQEP (2) USB2.0 OTG Ctlr PHY USB1.1 OHCI Ctlr PHY (10/100) EMAC (RMII) MDIO Internal Memory 128 KB RAM External Memory Interfaces HPI MMC/SD (8b) EMIFA(8b/16B) NAND/Flash 16b SDRAM EMIFB SDRAM Only (16b/32b) Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device components are available on each device. Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor 5 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Contents 1 1.1 1.4 6.11 External Memory Interface B (EMIFB) . 92 6.12 MMC / SD / SDIO (MMCSD) . 97 16 6.13 Ethernet Media Access Controller (EMAC) . 100 19 6.14 6.15 Management Data Input/Output (MDIO) . 106 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) . 108 38 6.16 Serial Peripheral Interface Ports (SPI0, SPI1) . 124 38 6.17 6.18 Enhanced Capture (eCAP) Peripheral . 142 Enhanced Quadrature Encoder (eQEP) Peripheral . 145 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) . 147 ADVANCE INFORMATION Device Compatibility . 9 3.3 4 DSP Subsystem . 10 21 38 38 39 Chip Configuration Registers (CFGCHIP and SUSPSRC) . 45 4.7 DSP Communication Registers . 52 4.8 5.2 5.3 Peripheral Information and Electrical Specifications . 59 6.1 6.2 6 Recommended Operating Conditions . 57 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) . 58 Parameter Information . 59 Recommended Clock and Control Signal Transition Contents USB1 Host Controller Registers (USB1.1 OHCI) . 174 6.25 USB0 OTG (USB2.0 OTG) 6.26 Host-Port Interface (UHPI) . 183 6.27 Power and Sleep Controller (PSC) 6.28 Emulation Logic . 192 6.29 7 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) . 168 Universal Asynchronous Receiver/Transmitter (UART) . 172 6.24 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) . 56 Timers . 166 6.22 6.23 Documentation Support . 54 LCD Controller . 151 6.21 Device Operating Conditions . 56 5.1 77 6.20 Device Support . 53 4.9 6 6.19 41 4.6 5 . EDMA External Memory Interface A (EMIFA) . 82 3.2 . 3.5 Pin Assignments . 3.6 Terminal Functions . Device Configuration . 4.1 Introduction . 4.2 Boot Modes Supported . 4.3 SYSCFG Module . 4.4 Pin Multiplexing Control Registers . 4.5 Bus Master Priority Configuration . General-Purpose Input/Output (GPIO) . 74 6.10 Device Characteristics . 8 Memory Map Summary Interrupts . 68 6.8 6.9 3.1 3.4 Clock PLLs . 65 6.7 Revision History . 7 Device Overview . 8 Crystal Oscillator or External Clock Input . 64 6.6 Functional Block Diagram . 5 Reset . 61 6.5 Description . 4 Power Supplies . 61 6.4 Trademarks . 3 1.3 6.3 Features . 1 1.2 2 3 Behavior . 60 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor . 1 Real Time Clock (RTC) . 194 . . 175 190 Mechanical Packaging and Orderable Information . 198 7.1 Thermal Data for ZKB. 198 7.2 Thermal Data for PTP. 199 7.3 Mechanical Drawings . 199 Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the changes made to the SPRS377A SPRS377A device-specific data manual to make it an SPRS377B SPRS377B revision. Table 2-1. Revision History ADDITIONS/MODIFICATIONS/DELETIONS Global: Document status updated from "Product Preview" To "Advance Information". Global: Updated the document to correct typos. ADVANCE INFORMATION Global: Deleted references to PLLDIV9, SYSCLK9. Global: Updates done to include RAM suppply for voltage scaling. Global: Updated "ePWM" to "eHRPWM". Global: Updates done to highlight the differences between C6745 C6745 and C6747 C6747. Global: Updated SYSCLK dividers max frequency to 400mhz. · Added the following new sections: ­ Section 6.4, Reset ­ Section 6.26, UHPI · Updated the following tables and sections for Emulation related changes : ­ Table 3-4, Reset and JTAG Terminal Function ­ Table 6-99, DSP Debug Features ­ Section 6.28.1, JTAG Port Description ­ Table 4-10, SUSPSRC Field Descriptions ­ Section 4.3, SYSCFG Module Deleted Section 4.5 ( in the earlier revision), Pin Multiplexing Control Registers since it is covered in detail in the System Reference Guide Section 1.1, Added a bullet - "3.3V LVCMOS IOs (except for USB interfaces)". Figure 3-4, Pin Map (PTP) - Updated Pin 124 to "AXR0[11]/AXR2[0]/GP3[11]" Table 3-4, Reset and JTAG Terminal Functions table - Updated TDO PULL from "IPU" to IPD" Table 3-18, Multichannel Audio Serial Ports (McASPs) Terminal Functions - Updated "UART1_TXD/AXR2[0]AXR0[11]/GP3[11]" to "UART1_TXD/AXR0[10]/GP3[10]" Section 5.2, Recommended Operating Conditions - Updated the table with values for VIH Updated Table 6-26, Timing requirements for MMCSD Updated Table 6-27, Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module Table 6-85, UART Registers - Added Modem Status Register and Scratchpad Register Submit Documentation Feedback Revision History 7 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3 Device Overview 3.1 Device Characteristics Table 3-1 provides an overview of the C6745/6747 C6745/6747 Low power digital signal processor. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Table 3-1. Characteristics of the C6745/C6747 C6745/C6747 Processor HARDWARE FEATURES ADVANCE INFORMATION C6745 C6745 C6747 C6747 EMIFB SDRAM only, 16-bit bus width SDRAM only, 16/32-bit bus width EMIFA Asynchronous (8-bit bus width) RAM, Flash, NOR, NAND Asynchronous (8/16-bit bus width) RAM, Flash, 16-bit SDRAM, NOR, NAND Flash Card Interface MMC and SD cards supported. EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers Timers 2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as Watch Dog) UART 3 (one with RTS and CTS flow control) SPI 2 (Each with one hardware chip select) I2C Peripherals Not all peripherals pins are available at the same time (for more detail, see the Device Configurations section). Multichannel Audio Serial Port [McASP] 2 (both Master/Slave) 2 (each with transmit/receive, FIFO buffer, 16/9 serializers) 10/100 Ethernet MAC with Management Data I/O eHRPWM eCAP 1 (RMII Interface) 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs eQEP UHPI 3 (each with transmit/receive, FIFO buffer, 16/9 serializers) 2 32-bit QEP channels with 4 inputs/channel - 1 (16-bit multiplexed address/data) USB 2.0 (USB0) Full Speed Host Or Device with On-Chip PHY High-Speed OTG Controller with on-chip OTG PHY USB 1.1 (USB1) - Full-Speed OHCI (as host) with on-chip PHY General-Purpose Input/Output Port 8 banks of 16-bit LCD Controller - 1 RTC - 1 (32 KHz oscillator and seperate power trail. Provides time and date tracking and alarm capability.) Size (Bytes) On-Chip Memory Organization 488KB 488KB RAM, 1088KB 1088KB ROM DSP 32KB L1 Program (L1P)/Cache (up to 32KB) 32KB L1 Data (L1D)/Cache (up to 32KB) 256KB 256KB Unified Mapped RAM/Cache (L2) 1024KB 1024KB ROM (L2) DSP Memories can be made accessible to EDMA3, and other peripherals. ADDITIONAL SHARED MEMORY 128KB 128KB RAM C674x CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1400 C674x Megamodule Revision Revision ID Register (MM_REVID[15:0]) 0x0000 JTAG BSDL_ID JTAGID Register CPU Frequency MHz Cycle Time ns 8 Device Overview 0x0B7D_F02F 674x DSP 300 MHz 674x DSP 3.33 ns Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-1. Characteristics of the C6745/C6747 C6745/C6747 Processor (continued) HARDWARE FEATURES I/O (V) 3.3 V 24 mm x 24 mm, 176-Pin, 0.5 mm pitch, TQFP (PTP) Package Product Status (1) (1) C6747 C6747 1.2 V Product Preview (PP), Advance Information (AI), or Production Data (PD) 17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB) AI ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. 3.2 Device Compatibility The C674x DSP core is code-compatible with the C6000TM C6000TM DSP platform and supports features of both the C64x+ and C67x+ DSP families. Submit Documentation Feedback Device Overview 9 ADVANCE INFORMATION Voltage C6745 C6745 Core (V) TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.3 DSP Subsystem The DSP Subsystem includes the following features: · C674x DSP CPU · 32KB L1 Program (L1P)/Cache (up to 32KB) · 32KB L1 Data (L1D)/Cache (up to 32KB) · 256KB 256KB Unified Mapped RAM/Cache (L2) · 1MB Mask-programmable ROM · Little endian ADVANCE INFORMATION 32K Bytes L1P RAM/ Cache 256K Bytes L2 RAM 256 256 256 Cache Control Memory Protect 1M Byte L2 ROM 256 Cache Control Memory Protect L1P Bandwidth Mgmt L2 Bandwidth Mgmt 256 256 256 Instruction Fetch 256 Power Down Interrupt Controller C674x Fixed/Floating Point CPU IDMA Register File A Register File B 64 64 256 CFG Bandwidth Mgmt Memory Protect Cache Control 8 x 32 EMC L1D MDMA 64 32K Bytes L1D RAM/ Cache 32 Configuration Peripherals Bus SDMA 64 64 64 High Performance Switch Fabric Figure 3-1. C674x Megamodule Block Diagram 10 Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com 3.3.1 SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 C674x DSP CPU Description The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory. The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core. Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types. The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support. Other new features include: · SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. · Compact Instructions - The native instruction size for the C6000 C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools. · Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. · Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). · Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. Submit Documentation Feedback Device Overview 11 ADVANCE INFORMATION The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 · www.ti.com Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents: · TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 SPRU732) · TMS320C64x Technical Overview (literature number SPRU395 SPRU395) ADVANCE INFORMATION 12 Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á Á Á ÁÁ Á ÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁ www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 src1 Odd register file A (A1, A3, A5.A31) src2 .L1 odd dst Even register file A (A0, A2, A4.A30) (D) even dst long src ST1b ST1a 32 MSB 32 LSB long src Data path A .S1 8 8 even dst odd dst src1 (D) .M1 dst2 dst1 src1 32 32 src2 LD1a 32 MSB 32 LSB DA1 DA2 LD2a LD2b Á Á Á Á Á Á Á LD1b ADVANCE INFORMATION src2 (A) (B) (C) dst .D1 src1 src2 2x 1x Odd register file B (B1, B3, B5.B31) src2 .D2 32 LSB 32 MSB src1 dst src2 .M2 Even register file B (B0, B2, B4.B30) (C) src1 dst2 32 (B) dst1 32 (A) src2 src1 .S2 odd dst even dst long src Data path B ST2a ST2b 32 MSB 32 LSB long src even dst .L2 (D) 8 8 (D) odd dst src2 src1 Control Register A. B. C. D. On .M unit, dst2 is 32 MSB. On .M unit, dst1 is 32 LSB. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths Submit Documentation Feedback Device Overview 13 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 3.3.2 www.ti.com DSP Memory Mapping The DSP memory map is shown in Section 3.4. 3.3.2.1 External Memories The DSP has access to the following External memories: · Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA) · SDRAM (EMIFB) 3.3.2.2 DSP Internal Memories ADVANCE INFORMATION The DSP has access to the following DSP memories: · L2 RAM · L1P RAM · L1D RAM 3.3.2.3 C674x CPU The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 3-2 shows a memory map of the C674x CPU cache registers for the device. Table 3-2. C674x Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM 0x0184 0000 L2CFG 0x0184 0020 L1PCFG 0x0184 0024 L1PCC 0x0184 0040 L1DCFG 0x0184 0044 L1DCC 0x0184 0048 - 0x0184 0FFC - 0x0184 1000 EDMAWEIGHT DESCRIPTION L2 Cache configuration register L1P Size Cache configuration register L1P Freeze Mode Cache configuration register L1D Size Cache configuration register L1D Freeze Mode Cache configuration register Reserved L2 EDMA access control register 0x0184 1004 - 0x0184 1FFC - 0x0184 2000 L2ALLOC0 Reserved L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 0x0184 2010 - 0x0184 3FFF - 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register Reserved 0x0184 4018 L2 invalidate base address register L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 14 L2IBAR 0x0184 401C L1DIBAR L1D invalidate base address register Device Overview Reserved Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-2. C674x Cache Registers (continued) REGISTER ACRONYM 0x0184 404C L1DIWC 0x0184 4050 - 0x0184 4FFF - 0x0184 5000 L2WB 0x0184 5004 L2WBINV 0x0184 5008 L2INV DESCRIPTION L1D invalidate word count register Reserved L2 writeback all register L2 writeback invalidate all register L2 Global Invalidate without writeback 0x0184 500C - 0x0184 5027 - 0x0184 5028 L1PINV Reserved 0x0184 502C - 0x0184 5039 - 0x0184 5040 L1DWB 0x0184 5044 L1DWBINV 0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 ­ 0x0184 80FF MAR0 - MAR63 MAR63 Reserved 0x0000 0000 ­ 0x3FFF FFFF 0x0184 8100 ­ 0x0184 817F MAR64 MAR64 ­ MAR95 MAR95 Memory Attribute Registers for EMIFA SDRAM Data (CS0) 0x4000 0000 ­ 0x5FFF FFFF 0x0184 8180 ­ 0x0184 8187 MAR96 MAR96 - MAR97 MAR97 Memory Attribute Registers for EMIFA Async Data (CS2) 0x6000 0000 ­ 0x61FF FFFF 0x0184 8188 ­ 0x0184 818F MAR98 MAR98 ­ MAR99 MAR99 Memory Attribute Registers for EMIFA Async Data (CS3) 0x6200 0000 ­ 0x63FF FFFF 0x0184 8190 ­ 0x0184 8197 MAR100 MAR100 ­ MAR101 MAR101 Memory Attribute Registers for EMIFA Async Data (CS4) 0x6400 0000 ­ 0x65FF FFFF 0x0184 8198 ­ 0x0184 819F MAR102 MAR102 ­ MAR103 MAR103 Memory Attribute Registers for EMIFA Async Data (CS5) 0x6600 0000 ­ 0x67FF FFFF 0x0184 81A0 ­ 0x0184 81FF MAR104 MAR104 ­ MAR127 MAR127 Reserved 0x6800 0000 ­ 0x7FFF FFFF 0x0184 8200 MAR128 MAR128 0x0184 8204 ­ 0x0184 82FF MAR129 MAR129 ­ MAR191 MAR191 Reserved 0x8200 0000 ­ 0xBFFF FFFF 0x0184 8300 ­ 0x0184 837F MAR192 MAR192 ­ MAR223 MAR223 Memory Attribute Registers for EMIFB SDRAM Data (CS2) 0xC000 0000 ­ 0xDFFF FFFF 0x0184 8380 ­ 0x0184 83FF MAR224 MAR224 ­ MAR255 MAR255 Reserved 0xE000 0000 ­ 0xFFFF FFFF L1P Global Invalidate Reserved L1D Global Writeback L1D Global Writeback with Invalidate Memory Attribute Register for Shared RAM 0x8000 0000 ­ 0x8001 FFFF Reserved 0x8002 0000 ­ 0x81FF FFFF See Table 3-3 for a detailed top level C6745/6747memory map that includes the DSP memory space. Submit Documentation Feedback Device Overview 15 ADVANCE INFORMATION HEX ADDRESS RANGE TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.4 Memory Map Summary Table 3-3. C6745/6747 C6745/6747 Top Level Memory Map Start Address End Address Size DSP Mem Map EDMA Mem Map Master Peripheral Mem Map 0x0000 0000 0x006F FFFF 6M + 1024K 1024K 0x0070 0000 0x007F FFFF 1024K 1024K DSP L2 ROM - 0x0080 0000 0x0083 FFFF 256K DSP L2 RAM - 0x0084 0000 0x00DF FFFF 5M + 768K 0x00E0 0000 0x00E0 7FFF 32K 0x00E0 8000 0x00EF FFFF 992K 0x00F0 0000 0x00F0 7FFF 32K 0x00F0 8000 0x017F FFFF 8M + 992K 0x0180 0000 0x0180 FFFF 0x0181 0000 LCDC Mem Map - - DSP L1D RAM - 64K DSP Interrupt Controller - 0x0181 0FFF 4K DSP Powerdown Controller - 0x0181 1FFF 4K DSP Security ID - 0x0181 2000 0x0181 2FFF 4K DSP Revision ID - 0x0181 3000 0x0181 FFFF 52K - - 0x0182 0000 0x0182 FFFF 64K DSP EMC - 0x0183 0000 0x0183 FFFF 64K DSP Internal Reserved - 0x0184 0000 0x0184 FFFF 64K DSP Memory System - 0x0185 0000 0x01BB FFFF 3M + 600K 0x01BC 0000 0x01BC 0FFF 4K - 0x01BC 1000 0x01BC 17FF 2K - 0x01BC 1900 0x01BC 18FF 256 - 0x01BC 0500 0x01BF FFFF 260K 0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC - 0x01C0 8000 0x01C0 83FF 1024 EDMA3 TC0 - 0x01C0 8400 0x01C0 87FF 1024 EDMA3 TC1 - 0x01C0 8800 0x01C0 FFFF 30K 0x01C1 0000 0x01C1 0FFF 4K PSC 0 - 0x01C1 1000 0x01C1 1FFF 4K PLL Controller - 0x01C1 2000 0x01C1 3FFF 8K 0x01C1 4000 0x01C1 4FFF 4K SYSCFG - 0x01C1 5000 0x01C1 5FFF 4K - 0x01C1 6000 0x01C1 6FFF 4K - 0x01C1 7000 0x01C1 7FFF 4K - 0x01C1 8000 0x01C1 FFFF 32K - 0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 - 0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 - 0x01C2 2000 0x01C2 2FFF 4K I2C 0 - 0x01C2 3000 0x01C2 3FFF 4K RTC - 0x01C2 4000 ADVANCE INFORMATION - 0x0181 1000 16 DSP L1P RAM 0x01C2 4FFF 4K Device Overview - Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-3. C6745/6747 C6745/6747 Top Level Memory Map (continued) Start Address End Address Size EDMA Mem Map Master Peripheral Mem Map LCDC Mem Map 0x01C2 5000 0x01C3 FFFF 110K 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 - 0x01C4 1000 0x01C4 1FFF 4K SPI 0 - 0x01C4 2000 0x01C4 2FFF 4K UART 0 - 0x01C4 3000 0x01CF FFFF 774K 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control - 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl - 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data - 0x01D0 3000 0x01D0 3FFF 4K 0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control - 0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Ctrl - 0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data - 0x01D0 7000 0x01D0 7FFF 4K 0x01D0 8000 0x01D0 8FFF 4K McASP 2 Control - - - ADVANCE INFORMATION DSP Mem Map - - 0x01D0 9000 0x01D0 9FFF 4K McASP 2 AFIFO Ctrl - 0x01D0 A000 0x01D0 AFFF 4K McASP 2 Data - 0x01D0 B000 0x01D0 BFFF 4K 0x01D0 C000 0x01D0 CFFF 4K UART 1 - 0x01D0 D000 0x01D0 DFFF 4K UART 2 - 0x01D0 E000 0x01D0 EFFF 4K IOPU 4 - 0x01D0 F000 0x01DF FFFF 964K 0x01E0 0000 0x01E0 FFFF 64K USB0 0x01E1 0000 0x01E1 0FFF 4K UHPI 0x01E1 1000 0x01E1 1FFF 4K 0x01E1 2000 0x01E1 2FFF 4K SPI 1 0x01E1 3000 0x01E1 3FFF 4K LCD Controller 0x01E1 4000 0x01E1 4FFF 4K - - - 0x01E1 5000 0x01E1 5FFF 4K 0x01E1 6000 0x01E1 FFFF 40K 0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM - 0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers - 0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers - 0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port - 0x01E2 5000 0x01E2 5FFF 4K USB1 - 0x01E2 6000 0x01E2 6FFF 4K GPIO - 0x01E2 7000 0x01E2 7FFF 4K PSC 1 - 0x01E2 8000 0x01E2 8FFF 4K I2C 1 - 0x01E2 9000 0x01E2 9FFF 4K 0x01E2 A000 0x01EF FFFF 856K 0x01F0 0000 0x01F0 0FFF 4K 0x01F0 1000 0x01F0 1FFF 0x01F0 2000 0x01F0 2FFF 0x01F0 3000 - eHRPWM 0 - 4K HRPWM 0 - 4K eHRPWM 1 - 0x01F0 3FFF 4K HRPWM 1 - 0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 - 0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 - 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 - Submit Documentation Feedback Device Overview 17 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 3-3. C6745/6747 C6745/6747 Top Level Memory Map (continued) Start Address End Address Size DSP Mem Map EDMA Mem Map Master Peripheral Mem Map LCDC Mem Map 0x01F0 7000 0x01F0 7FFF 4K ECAP 1 - 0x01F0 8000 0x01F0 8FFF 4K ECAP 2 - 0x01F0 9000 0x01F0 9FFF 4K EQEP 0 - 0x01F0 A000 0x01F0 AFFF 4K EQEP 1 - 0x01F0 BFFF 4K - 0x116F FFFF 247M + 976K - 0x1170 0000 0x117F FFFF 1024K 1024K DSP L2 ROM - 0x1180 0000 0x1183 FFFF 256K DSP L2 RAM - 0x1184 0000 ADVANCE INFORMATION 0x01F0 B000 0x01F0 C000 0x11DF FFFF 5M + 768K - 0x11E0 0000 0x11E0 7FFF 32K 0x11E0 8000 0x11EF FFFF 992K 0x11F0 0000 0x11F0 7FFF 32K 0x11F0 8000 0x3FFF FFFF 736M + 992K 0x4000 0000 0x5FFF FFFF 512M EMIFA SDRAM data (CS0) - 0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) - 0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) - 0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) - 0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) - EMIFA Control Regs - 0x6800 0000 0x6800 7FFF 32K 0x6800 8000 0x7FFF FFFF 383M + 992K DSP L1P RAM DSP L1D RAM - - - 0x8000 0000 0x8001 FFFF 128K 0x8002 0000 0xAFFF FFFF 767M + 896K - 0xB000 0000 0xB000 7FFF 32K EMIFB Control Regs 0xB000 8000 0xBFFF FFFF 255M + 992K - 0xC000 0000 0xDFFF FFFF 512M EMIFB SDRAM Data 0xE000 0000 0xFFFC FFFF 511M + 832K - 0xFFFD 0000 0xFFFD FFFF 64K - 0xFFFE 0000 0xFFFE DFFF 56K - 0xFFFE E000 0xFFFE FFFF 8K - 0xFFFF 0000 0xFFFF 1FFF 8K - 0xFFFF 2000 18 - - 0xFFFF FFFF 56K - Device Overview Shared RAM - Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 3.5 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 3.5.1 Pin Map (Bottom View) Figure 3-3 and Figure 3-4 show the pin assignments for BGA package and PTP package respectively.Note that micro-vias are not required. Contact your TI representative for routing recommendations. 2 4 5 6 7 8 9 10 AXR1[11]/ GP5[11] SPI0_CLK/ EQEP1I/ GP5[2]/ BOOT[2] SPI1_CLK/ EQEP1S/ GP5[7]/ BOOT[7] EMA_CS[3]/ AMUTE2/ GP2[6] EMA_CS[0]/ UHPI_HAS/ GP2[4] EMA_A[0]/ LCD_D[7]/ GP1[0] EMA_A[4]/ LCD_D[3]/ GP1[4] 3 T VSS VSS AXR1[0]/ GP4[0] R DVDD AXR1[1]/ GP4[1] UART0_RXD/ I2C0_SDA/ TM64P0 TM64P0_IN12/ IN12/ GP5[8]/ BOOT[8] P AXR1[3]/ EQEP1A/ GP4[3] AXR1[2]/ GP4[2] N AXR1[5]/ EPWM2B/ GP4[5] AXR1[4]/ EQEP1B/ GP4[4] AXR1[10]/ GP5[10] M AXR1[9]/ GP4[9] AXR1[8]/ EPWM1A/ GP4[8] AXR1[7]/ EPWM1B/ GP4[7] AXR1[6]/ EPWM2A/ GP4[6] DVDD VSS VSS L AHCLKR1/ GP4[11] ACLKR1/ ECAP2/ APWM2/ GP4[12] AFSR1/ GP4[13] AMUTE0/ RESETOUT DVDD CVDD K RTCK AHCLKX1/ EPWM0B/ GP3[14] ACLKX1/ EPWM0A/ GP3[15] AFSX1/ EPWMSYNCI/ EPWMSYNCO/ GP4[10] DVDD J TMS TDI TDO TRST H RTC_XI RTC_XO TCK G RTC_CVDD RTC_VSS F OSCOUT E SPI0_ENA/ SPIO_SOMI[0]/ EMA_OE/ SPI1_ENA/ UART0_CTS/ EQEPOI/ UHPI_HDS1/ UART2_RXD/ EQEP0A/ GP5[0]/ AXR0[13]/ GP5[3]/ GP5[12] BOOT[0] GP2[7] BOOT[3] 11 12 13 15 14 EMA_D[0]/ EMA_D[9]/ EMA_A[8]/ EMA_SDCKE/ MMCSD_DAT[0]/ UHPI_HD[9]/ UHPI_HD[0]/ LCD_PCLK/ GP2[0] LCD_D[9]/ GP0[0]/ GP1[8] GP0[9] BOOT[12] EMA_CLK/ OBSCLK/ AHCLKR2/ GP1[15] 16 VSS VSS T DVDD R EMA_A[1]/ EMA_BA[0]/ MMCSD_CLK/ LCD_D[4]/ UHPI_HCNTL0/ GP1[14] GP1[1] EMA_A[5]/ LCD_D[2]/ GP1[5] EMA_A[9]/ LCD_HSYNC/ GP1[9] EMA_D[2]/ EMA_D[10]/ EMA_D[1]/ MMCSD_DAT[2]/ UHPI_HD[10]/ MMCSD_DAT[1]/ UHPI_HD[2]/ LCD_D[10]/ UHPI_HD[1]/ GP0[2] GP0[10] GP0[1] UART0_TXD/ EMA_A[2]/ SPI1_SOMI[0]/ SPI0_SIMO[0]/ EMA_CS[2]/ EMA_BA[1]/ SPI1_SCS[0]/ I2C0_SCL/ I2C1_SCL/ EQEP0S/ UHPI_HCS/ LCD_D[5]/ MMCSD_CMD/ TM64P0 TM64P0_OUT12/ OUT12/ UART2_TXD/ UHPI_HHWIL/ UHPI_HCNTL1/ GP5[5]/ GP5[1]/ GP2[5]/ GP5[9]/ GP5[13] GP1[13] GP1[2] BOOT[5] BOOT[1] BOOT[15] BOOT[9] EMA_A[6]/ LCD_D[1]/ GP1[6] EMA_A[11]/ LCD_AC_ ENB_CS/ GP1[11] EMA_WE_ EMA_D[4]/ EMA_D[12]/ EMA_D[3]/ EMA_D[11]/ DQM[1]/ MMCSD_DAT[4]/ UHPI_HD[12]/ MMCSD_DAT[3]/ UHPI_HD[11]/ UHPI_HDS2/ UHPI_HD[4]/ LCD_D[12]/ UHPI_HD[3]/ LCD_D[11] AXR0[14]/ GP0[4] GP0[12] GP0[3] GP0[11] GP2[8] P SPI0_SCS[0]/ SPI1_SIMO[0]/ UART0_RTS/ I2C1_SDA/ EMA_WAIT[0]/ EMA_RAS/ EMA_A[10]/ UHPI_HRDY/ EMA_CS[5]/ LCD_VSYNC/ EQEP0B/ GP5[6]/ GP5[4]/ GP2[10] GP2[2] GP1[10] BOOT[6] BOOT[4] EMA_A[3]/ LCD_D[6]/ GP1[3] EMA_A[7]/ LCD_D[0]/ GP1[7] EMA_A[12]/ LCD_MCLK/ GP1[12] EMA_D[8]/ EMA_D[6]/ EMA_D[14]/ EMA_D[5]/ EMA_D[13]/ UHPI_HD[8]/ MMCSD_DAT[6]/ UHPI_HD[14]/ MMCSD_DAT[5]/ UHPI_HD[13]/ LCD_D[8]/ UHPI_HD[6]/ LCD_D[14]/ UHPI_HD[5]/ LCD_D[13]/ GP0[14] GP0[5] GP0[13] GP0[8] GP0[6] N DVDD DVDD VSS VSS DVDD EMA_WE/ UHPI_HRW/ AXR0[12]/ GP2[3]/ BOOT[14]] EMA_D[7]/ EMA_WE_ EMA_D[15]/ MMCSD_DAT[7]/ DQM[0]/ UHPI_HD[15]/ UHPI_HINT/ UHPI_HD[7]/ LCD_D[15]/ AXR0[15]/ GP0[7]/ GP0[15] GP2[9] BOOT[13] M VSS VSS VSS VSS DVDD DVDD EMB_CAS EMB_D[22] EMB_D[23] EMA_CAS/ EMA_CS[4]/ GP2[1] L CVDD CVDD VSS VSS CVDD CVDD DVDD EMB_D[20] EMB_WE_ DQM[0]/ GP5[15] EMB_WE EMB_D[21] K EMU0 CVDD CVDD VSS VSS CVDD CVDD CVDD EMB_D[5]/ GP6[5] EMB_D[19] EMB_D[6]/ GP6[6] EMB_D[7]/ GP6[7] J USB0_ VSSA33 VSSA33 USB0_ VDDA33 VDDA33 RVDD CVDD VSS VSS CVDD CVDD RVDD EMB_D[3]/ GP6[3] EMB_D[17] EMB_D[18] EMB_D[4]/ GP6[4] H RESET USB0_DM DVDD CVDD CVDD VSS VSS CVDD CVDD DVDD EMB_D[1]/ GP6[1] EMB_D[31] EMB_D[16] EMB_D[2]/ GP6[2] G OSCIN USB0_VSSA USB0_DP DVDD CVDD RSV1 VSS VSS VSS DVDD DVDD EMB_D[15]/ GP6[15] EMB_D[29] EMB_D[30] EMB_D[0]/ GP6[0] F PLL0_VSSA OSCVSS USB0_ VDDA18 VDDA18 USB0_ DRVVBUS/ GP4[15] DVDD VSS VSS DVDD DVDD VSS VSS DVDD EMB_D[13]/ GP6[13] EMB_D[27] EMB_D[28] EMB_D[14]/ GP6[14] E D PLL0_VDDA USB0_ID C USB1_ VDDA33 VDDA33 USB1_ VDDA18 VDDA18 USB0_ VDDA12 VDDA12 B RSV2 VSS A VSS 1 ADVANCE INFORMATION 1 AFSX0/ GP2[13]/ BOOT[10] AXR0[6]/ UART1_TXD/ RMII_RXER/ AXR0[10]/ ACLKR2/ GP3[10] GP3[6] AXR0[2]/ RMII_TXEN/ AXR2[3]/ GP3[2] EMB_CS[0] EMB_A[0]/ GP7[2] EMB_A[4]/ GP7[6] EMB_A[8]/ GP7[10] EMB_D[9]/ GP6[9] EMB_D[10]/ GP6[10] EMB_D[11]/ GP6[11] EMB_D[12]/ GP6[12] D AFSR0/ GP3[12] ACLKX0/ ECAP0/ APWM0/ GP2[12] AXR0[5]/ AXR0[1]/ UART1_RXD/ RMII_RXD[1]/ RMII_TXD[1]/ AXR0[9]/ AFSX2/ ACLKX2/ GP3[9] GP3[5] GP3[1] EMB_BA[0]/ GP7[1] EMB_A[1]/ GP7[3] EMB_A[5]/ GP7[7] EMB_A[9]/ GP7[11] EMB_SDCKE EMB_CLK EMB_WE_ DQM[1]/ GP5[14] EMB_D[8]/ GP6[8] C USB1_DM ACLKR0/ ECAP1/ APWM1/ GP2[15] AHLKX0/ AHCLKX2/ USB_ REFCLKIN/ GP2[11] AXR0[8]/ MDIO_D/ GP3[8] AXR0[4]/ AXR0[0]/ RMII_RXD[0]/ RMII_TXD[0]/ AXR2[1]/ AFSR2/ GP3[4] GP3[0] EMB_BA[1]/ GP7[0] EMB_A[2]/ GP7[4] EMB_A[6]/ GP7[8] EMB_A[11]/ GP7[13] EMB_WE_ DQM[2] EMB_D[25] EMB_A[12]/ GP3[13] DVDD B VSS USB1_DP AHCLKR0/ RMII_MHZ_ 50_CLK/ GP2[14]/ BOOT[11] AXR0[11]/ AXR2[0]/ GP3[11] AXR0[7]/ MDIO_CLK/ GP3[7] AXR0[3]/ RMII_CRS_DV/ AXR2[2]/ GP3[3] EMB_RAS EMB_A[10]/ GP7[12] EMB_A[3]/ GP7[5] EMB_A[7]/ GP7[9] EMB_WE_ DQM[3] EMB_D[24] EMB_D[26] VSS VSS A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AMUTE1/ USB0_VBUS EHRPWMTZ/ GP4[14] Figure 3-3. Pin Map (BGA) Submit Documentation Feedback Device Overview 19 RSV2 USB0_VDDA12 VDDA12 USB0_VDDA18 VDDA18 USB0_VSSA USB0_DP USB0_DM USB0_VSSA33 VSSA33 USB0_VDDA33 VDDA33 PLL0_VDDA PLL0_VSSA OSCIN OSCVSS OSCOUT RESET CVDD RSV4 RSV3 TRST DVDD TMS TDI CVDD TCK TDO GP7[14] DVDD RVDD AHCLKX1/EPWM0B/GP3[14] CVDD ACLKX1/EPWM0A/GP3[15] AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10] DVDD ACLKR1/ECAP2/APWM2/GP4[12] AFSR1/GP4[13] CVDD AXR1[8]/EPWM1A/GP4[8] AXR1[7]/EPWM1B/GP4[7] AXR1[6]/EPWM2A/GP4[6] AXR1[5]/EPWM2B/GP4[5] DVDD AXR1[4]/EQEP1B/GP4[4] AXR1[3]/EQEP1A/GP4[3] AXR1[2]/GP4[2] AXR1[1]/GP4[1] 20 Device Overview 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 CVDD SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] DVDD SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] EMA_WAIT[0]/GP2[10] CVDD EMA_CS[3]/GP2[6] EMA_OE//AXR0[13]/GP2[7] EMA_CS[2]/GP2[5]/BOOT[15] DVDD EMA_BA[0]/GP1[14] EMA_BA[1]/GP1[13] EMA_A[10]/GP1[10] CVDD EMA_A[0]/GP1[0] EMA_A[1]/MMCSD_CLK/GP1[1] EMA_A[2]/MMCSD_CMD/GP1[2] EMA_A[3]/GP1[3] DVDD EMA_A[4]/GP1[4] EMA_A[5]/GP1[5] EMA_A[6]/GP1[6] EMA_A[7]/GP1[7] CVDD EMA_A[8]/GP1[8] EMA_A[9]/GP1[9] EMA_A[11]/GP1[11] EMA_A[12]/GP1[12] DVDD EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 ADVANCE INFORMATION AXR1[0]/GP4[0] UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT8 UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] GP5[10] DVDD GP5[11] SPI1_ENA/UART2_RXD/GP5[12] SPI1_SCS[0]/UART2_TXD/GP5[13] SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 AMUTE1/EHRPWMTZ/GP4[14] AFSR0/GP3[12] ACLKR0/ECAP1/APWM1/GP2[15] AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] DVDD AFSX0/GP2[13]/BOOT[10] ACLKX0/ECAP0/APWM0/GP2[12] AHCLKX0/USB_REFCLKIN/GP2[11] AXR0[11]/AXR2[0]/GP3[11] UART1_TXD/AXR0[10]/GP3[10] UART1_RXD/AXR0[9]/GP3[9] AXR0[8]/MDIO_D/GP3[8] AXR0[7]/MDIO_CLK/GP3[7] DVDD AXR0[6]/RMII_RXER/GP3[6] AXR0[5]/RMII_RXD[1]/GP3[5] AXR0[4]/RMII_RXD[0]/GP3[4] AXR0[3]/RMII_CRS_DV/GP3[3] CVDD AXR0[2]/RMII_TXEN/GP3[2] AXR0[1]/RMII_TXD[1]/GP3[1] AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] EMB_RAS DVDD EMB_CS[0] EMB_BA[0]/GP7[1] EMB_BA[1]/GP7[0] EMB_A[10]/GP7[12] CVDD EMB_A[0]/GP7[2] EMB_A[1]/GP7[3] EMB_A[2]/GP7[4] EMB_A[3]/GP7[5] DVDD EMB_A[4]/GP7[6] EMB_A[5]/GP7[7] EMB_A[6]/GP7[8] EMB_A[7]/GP7[9] EMB_A[8]/GP7[10] CVDD EMB_A[9]/GP7[11] EMB_A[11]/GP7[13] DVDD EMB_A[12]/GP3[13] TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com VSS (177) Thermal Pad 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 EMB_SDCKE DVDD EMB_CLK EMB_WE_DQM[1]/GP5[14] EMB_D[8]/GP6[8] EMB_D[9]/GP6[9] EMB_D[10]/GP6[10] DVDD EMB_D[11]/GP6[11] EMB_D[12]/GP6[12] EMB_D[13]/GP6[13] CVDD EMB_D[14]/GP6[14] DVDD EMB_D[15]/GP6[15] EMB_D[0]/GP6[0] EMB_D[1]/GP6[1] DVDD EMB_D2/GP6[2] CVDD EMB_D[3]/GP6[3] RVDD EMB_D[4]/GP6[4] DVDD EMB_D[5]/GP6[5] EMB_D[6]/GP6[6] EMB_D[7]/GP6[7] CVDD EMB_WE_DQM[0]/GP5[15] EMB_WE DVDD EMB_CAS CVDD EMA_WE/AXR0[12]/GP2[3]/BOOT[14] EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] DVDD EMA_D[6]/MMCSD_DAT[6]/GP0[6] EMA_D[5]/MMCSD_DAT[5]/GP0[5] CVDD EMA_D[4]/MMCSD_DAT[4]/GP0[4] EMA_D[3]/MMCSD_DAT[3]/GP0[3] DVDD EMA_D[2]/MMCSD_DAT[2]/GP0[2] EMA_D[1]/MMCSD_DAT[1]/GP0[1] Figure 3-4. Pin Map (PTP) Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 3.6 Terminal Functions to identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description. 3.6.1 Device Reset and JTAG Table 3-4. Reset and JTAG Terminal Functions PIN NO SIGNAL NAME TYPE (1) PULL (2) DESCRIPTION PTP ZKB 146 G3 I - L4 O (3) TMS 152 J1 I IPU JTAG test mode select TDI 153 J2 I IPU JTAG test data input TDO 156 J3 O IPD JTAG test data output TCK 155 H3 I IPU JTAG test clock TRST 150 J4 I IPD JTAG test reset EMU[0] - J5 I/O IPU Miscellaneous emulation pin. GP7[14] 157 K1 I/O IPU General-Purpose IO signal. AMUTE0/RESETOUT Device reset input IPD Reset output. Multiplexed with McASP0 mute output. JTAG (1) (2) (3) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Open drain mode for RESETOUT function. 3.6.2 High-Frequency Oscillator and PLL Table 3-5. High-Frequency Oscillator and PLL Terminal Functions SIGNAL NAME EMA_CLK/OBSCLK/AHCLKR 2/GP1[15] PIN NO PTP ZKB - R12 TYPE (1) PULL (2) O IPU DESCRIPTION PLL Observation Clock 1.2-V OSCILLATOR OSCIN 143 F2 I Oscillator input OSCOUT 145 F1 O Oscillator output OSCVSS 144 E2 GND PLL0_VDDA 141 D1 PWR PLL analog VDD (1.2-V filtered supply) PLL0_VSSA 142 E1 GND PLL analog VSS (for filter) Oscillator ground (for filter only) 1.2-V PLL (1) (2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 21 ADVANCE INFORMATION RESET RESET TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 3.6.3 www.ti.com Real-Time Clock and 32-kHz Oscillator Table 3-6. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions SIGNAL NAME PIN NO TYPE (1) PULL (2) DESCRIPTION PTP ZKB RTC_CVDD - G1 RTC_XI - H1 I Low-frequency (32-kHz) oscillator receiver for real-time clock RTC_XO - H2 O Low-frequency (32-kHz) oscillator driver for real-time clock RTC_Vss - G2 GND (1) ADVANCE INFORMATION (2) PWR RTC module core power ( isolated from rest of chip CVDD) Oscillator ground (for filter) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.4 External Memory Interface A (ASYNC, SDRAM) Table 3-7. External Memory Interface A (EMIFA) Terminal Functions PIN NO TYPE (1) PULL (2) M16 I/O IPD N14 I/O IPD - N16 I/O IPD - P14 I/O IPD EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] - P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] 54 M15 I/O IPU EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] 52 N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] 51 N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] 49 P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] 48 P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] 46 R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] 45 R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU SIGNAL NAME PTP ZKB EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] - EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] - EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] (1) (2) 22 MUXED DESCRIPTION UHPI, LCD, GPIO MMC/SD, UHPI, GPIO, BOOT EMIFA data bus MMC/SD, UHPI, GPIO MMC/SD, UHPI, GPIO, BOOT I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued) PIN NO TYPE (1) PULL (2) N11 O IPU 41 P11 O IPU 27 N8 O IPU EMA_A[9]/LCD_HSYNC/GP1[9] 40 R11 O IPU EMA_A[8]/LCD_PCLK/GP1[8] 39 T11 O IPU EMA_A[7]/LCD_D[0]/GP1[7] 37 N10 O IPD EMA_A[6]/LCD_D[1]/GP1[6] 36 P10 O IPD EMA_A[5]/LCD_D[2]/GP1[5] 35 R10 O IPD EMA_A[4]/LCD_D[3]/GP1[4] 34 T10 O IPD EMA_A[3]/LCD_D[6]/GP1[3] 32 N9 O IPD EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] 31 P9 O IPU EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] 30 R9 O EMA_A[0]/LCD_D[7]/GP1[0] 29 T9 EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] 26 EMA_BA[0]/LCD_D[4]/GP1[14] SIGNAL NAME PTP ZKB EMA_A[12]/LCD_MCLK/GP1[12] 42 EMA_A[11]/LCD_AC_ENB_CS/GP1[11] EMA_A[10]/LCD_VSYNC/GP1[10] MUXED DESCRIPTION EMIFA address bus IPU MMCSD, UHPI, GPIO EMIFA address bus. O IPD LCD, GPIO P8 O IPU LCD, UHPI, GPIO 25 R8 O IPU LCD, GPIO EMA_CLK/OBSCLK/AHCLKR2/GP1[15] - R12 O IPU McASP2, GPIO EMIFA clock. EMA_SDCKE/GP2[0] - T12 O IPU GPIO EMIFA SDRAM clock enable. EMA_RAS/EMA_CS[5]/GP2[2] - N7 O IPU EMA_CAS/EMA_CS[4]/GP2[1] - EMA_RAS/EMA_CS[5]/GP2[2] EMA_CAS/EMA_CS[4]/GP2[1] EMIFA bank address EMIFA SDRAM row address strobe. EMIF A chip select, GPIO EMIFA SDRAM column address strobe. L16 O IPU - N7 O IPU - L16 O IPU EMA_CS[3]/AMUTE2/GP2[6] 21 T7 O IPU McASP2, GPIO EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] 25 P7 O IPU UHPI, GPIO, BOOT - T8 O IPU UHPI, GPIO EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] 55 M13 O IPU UHPI, EMIFA SDRAM write MCASP0, enable. GOPIO, BOOT EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8] - P12 O IPU EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9] - M14 O IPU EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] 22 R7 O IPU UHPI, McASP0, GPIO EMIFA output enable. EMA_WAIT[0]/UHPI_HRDY/GP2[10] 19 N6 I IPU UHPI, GPIO EMIFA wait input/interrupt. EMA_CS[0]/UHPI_HAS/GP2[4] Submit Documentation Feedback EMIF A SDRAM, GPIO EMIFA Async Chip Select EMIFA write enable/data mask for UHPI, McASP, EMA_D[15:8] GPIO EMIFA write enable/data mask for EMA_D[7:0]. Device Overview 23 ADVANCE INFORMATION LCD, GPIO TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 3.6.5 www.ti.com External Memory Interface B (only SDRAM ) Table 3-8. External Memory Interface B (EMIFB) Terminal Functions PIN NO TYPE (1) PULL (2) G14 I/O IPD - F15 I/O IPD - F14 I/O IPD EMB_D[28] - E15 I/O IPD EMB_D[27] - E14 I/O IPD EMB_D[26] - A14 I/O IPD EMB_D[25] - B14 I/O IPD EMB_D[24] - A13 I/O IPD EMB_D[23] - L15 I/O IPD EMB_D[22] - L14 I/O IPD EMB_D[21] - K16 I/O IPD EMB_D[20] - K13 I/O IPD EMB_D[19] - J14 I/O IPD EMB_D[18] - H15 I/O IPD EMB_D[17] - H14 I/O IPD SIGNAL NAME PTP ZKB EMB_D[31] - EMB_D[30] EMB_D[29] ADVANCE INFORMATION EMB_D[16] - G15 I/O IPD EMB_D[15]/GP6[15] 74 F13 I/O IPD EMB_D[14]/GP6[14] 76 E16 I/O 78 E13 I/O IPD EMB_D[12]/GP6[12] 79 D16 I/O IPD EMB_D[11]/GP6[11] 80 D15 I/O IPD EMB_D[10]/GP6[10] 82 D14 I/O IPD EMB_D[9]/GP6[9] 83 D13 I/O IPD EMB_D[8]/GP6[8] 84 C16 I/O IPD EMB_D[7]/GP6[7] 62 J16 I/O IPD EMB_D[6]/GP6[6] 63 J15 I/O IPD EMB_D[5]/GP6[5] 64 J13 I/O IPD EMB_D[4]/GP6[4] 66 H16 I/O IPD EMB_D[3]/GP6[3] 68 H13 I/O IPD EMB_D[2]/GP6[2] 70 G16 I/O IPD EMB_D[1]/GP6[1] 72 G13 I/O IPD EMB_D[0]/GP6[0] 73 F16 I/O IPD EMB_A[12]/GP3[13] 89 B15 O IPD EMB_A[11]/GP7[13] 91 B12 O IPD EMB_A[10]/GP7[12] 105 A9 O IPD EMB_A[9]/GP7[11] 92 C12 O IPD EMB_A[8]/GP7[10] 94 D12 O IPD EMB_A[7]/GP7[9] 95 A11 O IPD EMB_A[6]/GP7[8] 96 B11 O IPD EMB_A[5]/GP7[7] 97 C11 O DESCRIPTION IPD EMB_D[13]/GP6[13] MUXED IPD (1) (2) 24 EMIFB SDRAM data bus. GPIO GPIO EMIFB SDRAM row/column address bus. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-8. External Memory Interface B (EMIFB) Terminal Functions (continued) PIN NO TYPE (1) PULL (2) D11 O IPD 100 A10 O IPD 101 B10 O IPD EMB_A[1]/GP7[3] 102 C10 O IPD EMB_A[0]/GP7[2] 103 D10 O IPD EMB_BA[1]/GP7[0] 106 B9 O IPU EMB_BA[0]/GP7[1] 107 C9 O IPU EMIFB SDRAM band address. EMB_CLK 86 C14 O IPU EMIF SDRAM clock. EMB_SDCKE 88 C13 I/O IPU EMIFB SDRAM clock enable. EMB_WE 59 K15 O IPU EMIFB write enable EMB_RAS 110 A8 O IPU EMIFB SDRAM row address strobe. EMB_CAS 57 L13 O IPU EMIFB column address strobe. EMB_CS[0] 108 D9 O IPU EMIFB SDRAM chip select 0. EMB_WE_DQM[3] - A12 O IPU EMB_WE_DQM[2] - B13 O IPU EMB_WE_DQM[1]/GP5[14] 85 C15 O IPU EMB_WE_DQM[0]/GP5[15] 60 K14 O IPU PTP ZKB EMB_A[4]/GP7[6] 98 EMB_A[3]/GP7[5] EMB_A[2]/GP7[4] 3.6.6 MUXED DESCRIPTION EMIFB SDRAM row/column address. GPIO EMIFB write enable/data mask for EMB_D. GPIO Serial Peripheral Interface Modules (SPI0, SPI1) Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION SPI0 SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I/O IPU UART0, EQEP0B, GPIO, BOOT SPI0 chip select. SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I/O IPU UART0, EQEP0A, GPIO, BOOT SPI0 enable. SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 T5 I/O IPD eQEP1, GPIO, BOOT SPI0 clock. SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I/O IPD eQEP0, GPIO, BOOT SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I/O IPD SPI0 data slave-in-masterout. SPI0 data slave-out-masterin. SPI1 SPI1_SCS[0]/UART2_TXD/GP5[13] 8 P4 I/O IPU SPI1_ENA/UART2_RXD/GP5[12] 7 R4 I/O IPU SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 T6 I/O IPD (1) (2) UART2, GPIO SPI1 chip select. SPI1 enable. eQEP1, GPIO, BOOT SPI1 clock. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 25 ADVANCE INFORMATION SIGNAL NAME TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions (continued) SIGNAL NAME PIN NO TYPE (1) PULL (2) N5 I/O IPU P5 I/O IPU PTP ZKB SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 MUXED I2C1, GPIO, BOOT DESCRIPTION SPI1 data slave-in-masterout. SPI1 data slave-out-masterin. ADVANCE INFORMATION 26 Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com 3.6.7 SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2) The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon how the eCAP module is programmed. Table 3-10. Enhanced Capture Module (eCAP) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) I/O IPD McASP0, GPIO enhanced capture 0 input or auxiliary PWM 0 output. I/O IPD McASP0, GPIO enhanced capture 1 input or auxiliary PWM 1 output. I/O IPD McASP1, GPIO enhanced capture 2 input or auxiliary PWM 2 output. MUXED DESCRIPTION ACLKX0/ECAP0/APWM0/GP2[12] 126 C5 eCAP1 ACLKR0/ECAP1/APWM1/GP2[15] 130 B4 eCAP2 ACLKR1/ECAP2/APWM2/GP4[12] (1) (2) 165 L2 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.8 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2) Table 3-11. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION eHRPWM0 ACLKX1/EPWM0A/GP3[15] 162 K3 I/O eHRPWM0 A output (with high-resolution). IPD McASP1, GPIO eHRPWM0 B output. AHCLKX1/EPWM0B/GP3[14] 160 K2 I/O IPD AMUTE1/EPWMTZ/GP4[14] - D4 I/O IPD McASP1, eHRPWM1, GPIO, eHRPWM2 eHRPWM0 trip zone input. 163 K4 I/O IPD McASP1, eHRPWM0, GPIO Sync input to eHRPWM0 module or sync output to external PWM. AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] eHRPWM1 AXR1[8]/EPWM1A/GP4[8] 168 M2 I/O AXR1[7]/EPWM1B/GP4[7] 169 M3 I/O IPD - D4 I/O IPD eHRPWM1 A (with high-resolution). IPD McASP1, GPIO AMUTE1/EPWMTZ/GP4[14] (1) (2) eHRPWM1 B output. McASP1, eHRPWM0, GPIO, eHRPWM2 eHRPWM1 trip zone input. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 27 ADVANCE INFORMATION eCAP0 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 3-11. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions (continued) PIN NO SIGNAL NAME PTP TYPE (1) ZKB PULL (2) MUXED DESCRIPTION eHRPWM2 AXR1[6]/EPWM2A/GP4[6] 170 M4 I/O IPD AXR1[5]/EPWM2B/GP4[5] 171 N1 I/O IPD - D4 I/O IPD McASP1, GPIO AMUTE1/EPWMTZ/GP4[14] ADVANCE INFORMATION 3.6.9 McASP1, eHRPWM0, GPIO, eHRPWM2 eHRPWM2 A (with high-resolution). eHRPWM2 B output. eHRPWM2 trip zone input. Enhanced Quadrature Encoder Pulse Module (eQEP) Table 3-12. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions PIN NO SIGNAL NAME PTP TYPE (1) ZKB PULL (2) MUXED DESCRIPTION eQEP0 SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I IPU SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I IPD SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I IPD SPIO, UART0, GPIO, BOOT SPI0, GPIO, BOOT eQEP0A quadrature input. eQEP0B quadrature input. eQEP0 index. eQEP0 strobe. eQEP1 eQEP1A quadrature input. AXR1[3]/EQEP1A/GP4[3] 174 P1 I IPD AXR1[4]/EQEP1B/GP4[4] 173 N2 I IPD SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 174 T5 I IPD SPI0, GPIO, BOOT eQEP1 index. SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 T6 I IPD SPI1, GPIO, BOOT eQEP1 strobe. McASP1, GPIO (1) (2) eQEP1B quadrature input. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.10 Boot Table 3-13. Boot Terminal Functions (1) SIGNAL NAME EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] PIN NO PTP ZKB 23 P7 TYPE (2) PULL (3) MUXED I IPU EMIFA, UHPI, GPIO BOOT[15]. EMIFA, UHPI, McASP0, GPIO BOOT[14]. EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] 55 M13 I IPU EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] 54 M15 I IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I IPU (1) (2) (3) 28 EMIFA, MMC/SD, UHPI, GPIO DESCRIPTION BOOT[13]. BOOT[12]. Boot decoding will be defined in the ROM datasheet. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-13. Boot Terminal Functions (continued) SIGNAL NAME PIN NO TYPE (2) PULL (3) A4 I IPD McASP0, EMAC, GPIO BOOT[11]. D5 I IPD McASP0, GPIO BOOT[10]. BOOT[9]. PTP ZKB AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 AFSX0/GP2[13]/BOOT[10] 127 MUXED DESCRIPTION UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] 3 P3 I IPU UART0, I2C0, Timer0, GPIO UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] 2 R3 I IPU UART0, I2C0, Timer0, GPIO BOOT[8]. SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 T6 I IPD SPI1, eQEP1, GPIO BOOT[7]. SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 N5 I IPU SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 P5 I IPU BOOT[6]. ADVANCE INFORMATION SPI1, I2C1, GPIO BOOT[5]. SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I IPU SPI0, UART0, eQEP0, GPIO SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU SPI0, UART0, eQEP0, GPIO SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 T5 I IPD SPIO, eQEP1, GPIO BOOT[2]. SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I IPD SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I IPD BOOT[4]. BOOT[3]. SPI0, eQEP0, GPIO BOOT[1]. BOOT[0]. 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2) Table 3-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION UART0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] 2 R3 I IPU I2C0, BOOT, Timer0, GPIO, UART0 receive data. UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] 3 P3 O IPU I2C0, Timer0, GPIO, BOOT UART0 transmit data. SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 O IPU SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU UART0 clear-to-send input UART1 receive data. UART0 ready-to-send output SPIO, eQEP0, GPIO, BOOT UART1 UART1_RXD/AXR0[9]/GP3[9] 122 C6 I IPD UART1_TXD/AXR0[10]/GP3[10] 123 D6 O IPD UART1 transmit data. UART2 receive data. McASP0, GPIO UART2 SPI1_ENA/UART2_RXD/GP5[12] 7 R4 I IPU SPI1_SCS[0]/UART2_TXD/GP5[13] 8 P4 O IPU SPI1, GPIO (1) (2) UART2 transmit data. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 29 TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.6.12 Inter-Integrated Circuit Modules(I2C0, I2C1) Table 3-15. Inter-Integrated Circuit (I2C) Terminal Functions PIN NO SIGNAL NAME PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION I2C0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] 2 R3 I/O IPU UART0, Timer0, GPIO, BOOT I2C0 serial data. UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] 3 P3 I/O IPU UART0, Timer0, GPIO, BOOT I2C0 serial clock. SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 N5 I/O IPU SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 P5 I/O IPU I2C1 ADVANCE INFORMATION (1) (2) SPI1, GPIO, BOOT I2C1 serial Data. I2C1 serial clock. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.13 Timers Table 3-16. Timers Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION TIMER0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] 2 R3 I IPU UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] 3 P3 O IPU UART0, I2C0, GPIO, BOOT Timer0 lower input. Timer0 lower output TIMER1 (Watchdog ) No external pins. The Timer1 peripheral pins are not pinned out as external pins. (1) (2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.14 Universal Host-Port Interface (UHPI) Note: The UHPI module requires 16 data pins for the host port interface to function. Therefore on the PTP, only the GPIO pin capability is supported on the UHPI peripherals. 30 Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-17. Universal Host-Port Interface (UHPI) Terminal Functions PIN NO TYPE ( PULL (2) M16 I/O IPD N14 I/O IPD - N16 I/O IPD EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] - P14 I/O IPD EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] - P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/ BOOT[13] - M15 I/O IPU EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] - N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] - N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] - P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] - P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] - R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] - R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/ BOOT[12] - T13 I/O IPU EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] - P9 I/O IPU EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] - R9 I/O EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] - P8 EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] - EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] PTP ZKB EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] - EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] - EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] MUXED DESCRIPTION EMIFA, LCD, GPIO EMIFA, MMC/SD, GPIO, BOOT UHPI data bus. EMIFA, MMC/SD, GPIO EMIFA, MMC/SD, GPIO, BOOT IPU EMIFA, MMCSD_CMD, GPIO UHPI access control. I/O IPU EMIFA, LCD, GPIO UHPI half-word identification control. M13 I/O IPU EMIFA, McASP, GPIO, BOOT UHPI read/write. - P7 I/O IPU EMIFA, GPIO, BOOT UHPI chip select. EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8] - P12 I/O IPU EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] - R7 I/O IPU EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9] - M14 I/O IPU EMA_WAIT[0]/UHPI_HRDY/GP2[10] - N6 I/O IPU EMA_CS[0]/UHPI_HAS/GP2[4] (1) (2) - T8 I/O IPU EMIFA, McASP0, GPIO UHPI data strobe. UHPI host interrupt. UHPI ready. EMIFA, GPIO UHPI address strobe. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 31 ADVANCE INFORMATION 1) SIGNAL NAME TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2) Table 3-18. Multichannel Audio Serial Ports (McASPs) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION McASP0 - M14 I/O IPU EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8] - P12 I/O IPU EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] 24 R7 I/O IPU EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] ADVANCE INFORMATION EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9] 55 M13 I/O IPU EMIFA, UHPI, GPIO, BOOT AXR0[11]/AXR2[0]/GP3[11] 124 A5 I/O IPD McASP2, GPIO AXR0[10]/UART1_TXD/GP3[10] 123 D6 I/O IPD GPIO AXR0[9]/GP3[9] 122 C6 I/O IPD GPIO AXR0[8]/MDIO_D/GP3[8] 121 B6 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] 120 A6 I/O IPD AXR0[6]/RMII_RXER/ACLKR2/GP3[6] 118 D7 I/O IPD AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] 117 C7 I/O IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] 116 B7 I/O IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] 115 A7 I/O IPD AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] 113 D8 I/O IPD AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] 112 C8 I/O IPD AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] 111 B8 I/O IPD AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] 125 B5 I/O IPD McASP0 McASP2, USB, transmit master GPIO clock. ACLKX0/ECAP0/APWM0/GP2[12] 126 C5 I/O IPD eCAP0, GPIO McASP0 transmit bit clock. AFSX0/GP2[13]/BOOT[10] 127 D5 I/O IPD GPIO, BOOT McASP0 transmit frame sync. AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 A4 I/O IPD EMAC, GPIO, BOOT McASP0 receive master clock. ACLKR0/ECAP1/APWM1/GP2[15] 130 B4 I/O IPD eCAP1, GPIO McASP0 receive bit clock. AFSR0/GP3[12] 131 C4 I/O IPD GPIO McASP0 receive frame sync. - L4 O IPD RESETOUT McASP0 mute output. AMUTE0/RESETOUT (1) (2) 32 EMIFA, UHPI, GPIO MDIO, GPIO McASP0 serial data. EMAC, McASP2, GPIO I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-18. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued) SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION McASP1 AXR1[11]/GP5[11] - T4 I/O IPU AXR1[10]/GP5[10] - N3 I/O IPU AXR1[9]/GP4[9] - M1 I/O IPD AXR1[8]/EPWM1A/GP4[8] 168 M2 I/O IPD eHRPWM1 A, GPIO AXR1[7]/EPWM1B/GP4[7] 169 M3 I/O IPD eHRPWM1 B, GPIO AXR1[6]/EPWM2A/GP4[6] 170 M4 I/O IPD eHRPWM2 A, GPIO AXR1[5]/EPWM2B/GP4[5] 171 N1 I/O IPD eHRPWM2 B, GPIO AXR1[4]/EQEP1B/GP4[4] 173 N2 I/O IPD AXR1[3]/EQEP1A/GP4[3] 174 P1 I/O IPD AXR1[2]/GP4[2] 175 P2 I/O IPD AXR1[1]/GP4[1] 176 R2 I/O IPD AXR1[0]/GP4[0] 1 T3 I/O IPD AHCLKX1/EPWM0B/GP3[14] 160 K2 I/O IPD eHRPWM0, GPIO McASP1 transmit master clock. ACLKX1/EPWM0A/GP3[15] 162 K3 I/O IPD eHRPWM0, GPIO McASP1 transmit bit clock. AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 K4 I/O IPD eHRPWM0, GPIO McASP1 transmit frame sync. - L1 I/O IPD GPIO McASP1 receive master clock. ACLKR1/ECAP2/APWM2/GP4[12] 165 L2 I/O IPD eCAP2, GPIO McASP1 receive bit clock. AFSR1/GP4[13] 166 L3 I/O IPD GPIO McASP1 receive frame sync. eHRPWM0, eHRPWM1, GPIO, eHRPWM2 McASP1 mute output. McASP0, EMAC, GPIO McASP2 serial data. AMUTE1/EPWMTZ/GP4[14] 132 D4 O IPD McASP1 serial data. eQEP, GPIO GPIO McASP2 AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] - D8 I/O IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] - A7 I/O IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] - B7 I/O IPD AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] - B5 I/O IPD AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] - C8 I/O IPD AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] - C7 I/O IPD McASP0, EMAC, GPIO McASP2 transmit frame sync. EMA_CLK/OBSCLK/AHCLKR2/GP1[15] - R12 I/O IPU EMIFA, GPIO McASP2 receive master clock. AXR0[6]/RMII_RXER/ACLKR2/GP3[6] - D7 I/O IPD McASP0, EMAC, GPIO McASP2 receive bit clock. Submit Documentation Feedback McASP2 transmit master McASP0, USB, clock. GPIO McASP2 transmit bit clock. Device Overview 33 ADVANCE INFORMATION AHCLKR1/GP4[11] GPIO TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 www.ti.com Table 3-18. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued) PIN NO SIGNAL NAME PTP - TYPE (1) PULL (2) ZKB T7 EMA_CS[3]/AMUTE2/GP2[6] O IPU MUXED DESCRIPTION McASP2 mute output. EMIFA, GPIO 3.6.16 Universal Serial Bus Modules (USB0, USB1) Table 3-19. Universal Serial Bus (USB) Terminal Functions SIGNAL NAME PIN NO PTP TYPE (1) PULL (2) ZKB DESCRIPTION ADVANCE INFORMATION USB0 2.0 OTG (USB0) USB0_DM 138 USB0_DP 137 USB0_VDDA33 VDDA33 140 USB0_VSSA33 VSSA33 139 USB0_VDDA18 VDDA18 A USB0 PHY data minus F4 A USB0 PHY data plus H5 PWR USB0 PHY 3.3-V supply H4 PWR USB0 PHY 3.3-V supply reference 135 E3 PWR USB0 PHY 1.8-V supply input 134 C3 PWR USB0 PHY 1.2-V LDO output for bypass cap 136 F3 PWR USB0 PHY 1.8-V and 1.2-V supply reference USB0_ID - D2 A USB0 PHY identification (mini-A or mini-B plug) USB0_VBUS - D3 A USB0 bus voltage USB0_DRVVBUS/GP4[15] - E4 0 IPD USB0 controller VBUS control output. Multiplexed with GPIO bank 4 pin 15. 125 B5 I IPD USB_REFCLKIN. Optional clock input. USB0_VDDA12 VDDA12 (3) USB0_VSSA AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] G4 USB1 1.1 OHCI (USB1) USB1_DM - B3 A USB1 PHY data minus USB1_DP - A3 A USB1 PHY data plus USB1_VDDA33 VDDA33 - C1 PWR USB1_VDDA18 VDDA18 - C2 PWR 125 B5 I AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] (1) (2) (3) USB1 PHY 3.3-V supply USB1 PHY 1.8-V supply IPD USB_REFCLKIN. Optional clock input. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 -µF capacitor to VSS. When the USB peripheral is not used, the USB_VDDA12 VDDA12 signal should still be connected via a 1-µF capacitor to VSS. 3.6.17 Ethernet Media Access Controller (EMAC) Table 3-20. Ethernet Media Access Controller (EMAC) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION RMII AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] (1) (2) 34 129 A4 I/O IPD McASP0, GPIO, BOOT EMAC 50-MHz clock input or output. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 Table 3-20. Ethernet Media Access Controller (EMAC) Terminal Functions (continued) PIN NO TYPE (1) PULL (2) PTP ZKB AXR0[6]/RMII_RXER/ACLKR2/GP3[6] 118 D7 I 117 C7 I IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] 116 B7 I IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] 115 A7 I IPD AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] 113 D8 O IPD AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] 112 C8 O IPD AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] 111 B8 O DESCRIPTION IPD AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] MUXED IPD EMAC RMII receiver error. EMAC RMII receive data. McASP0, McASP2, GPIO EMAC RMII carrier sense data valid. EMAC RMII transmit enable. EMAC RMII trasmit data. MDIO AXR0[8]/MDIO_D/GP3[8] 121 B6 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] 120 A6 O IPD McASP0, GPIO MDIO data clock. 3.6.18 Multimedia Card/Secure Digital (MMC/SD) Table 3-21. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions PIN NO TYPE (1) PULL (2) R9 O IPU P9 I/O IPU 54 M15 I/O IPU EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] 52 N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] 51 N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] 49 P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] 48 P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] 46 R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] 45 R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU SIGNAL NAME PTP ZKB EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] 30 EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] 31 EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] (1) (2) MUXED DESCRIPTION EMIFA, UHPI, GPIO MMCSD_CLK. MMCSD_CMD. EMIFA, UHPI, GPIO, BOOT EMIFA, UHPI, GPIO MMC/SD data. EMIFA, UHPI, GPIO, BOOT I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 35 ADVANCE INFORMATION SIGNAL NAME TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 3.6.19 www.ti.com Liquid Crystal Display Controller(LCD) Table 3-22. Liquid Crystal Display Controller (LCD) Terminal Functions PIN NO TYPE (1) PULL (2) M16 I/O IPD - N14 I/O IPD - N16 I/O IPD EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] - P14 I/O IPD EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] - P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD EMA_A[0]/LCD_D[7]/GP1[0] - T9 I/O IPD EMA_A[3]/LCD_D[6]/GP1[3] - N9 I/O IPD EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] - P8 I/O IPU EMA_BA[0]/LCD_D[4]/GP1[14] - R8 I/O IPU EMA_A[4]/LCD_D[3]/GP1[4] - T10 I/O IPD EMA_A[5]/LCD_D[2]/GP1[5] - R10 I/O IPD EMA_A[6]/LCD_D[1]/GP1[6] - P10 I/O IPD EMA_A[7]/LCD_D[0]/GP1[7] - N10 I/O IPD EMA_A[8]/LCD_PCLK/GP1[8] - T11 O IPU EMA_A[9]/LCD_HSYNC/GP1[9] - R11 O IPU LCD horizontal sync. EMA_A[10]/LCD_VSYNC/GP1[10] - N8 O IPU LCD vertical sync. EMA_A[11]/LCD_AC_ENB_CS/GP1[11] - P11 O IPU LCD AC bias enable chip select. EMA_A[12]/LCD_MCLK/GP1[12] - N11 O IPU LCD memory clock. SIGNAL NAME PTP ZKB EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] - EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] ADVANCE INFORMATION (1) (2) MUXED DESCRIPTION EMIFA, UHPI, GPIO LCD data bus. EMIFA, GPIO EMIFA, UHPI, GPIO EMIFA, GPIO LCD pixel clock. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.20 Reserved Table 3-23. Reserved Terminal Functions SIGNAL NAME PIN NO TYPE (1) DESCRIPTION PTP ZKB RSV1 - F7 PWR Reserved. (Leave unconnected, do not connect to power or ground.) RSV2 133 B1 PWR Reserved. For proper device operation, this pin must be tied directly to CVDD. RSV3 149 - PWR Reserved. For proper device operation, this pin must be tied directly to CVDD. RSV4 148 - PWR Reserved. For proper operation, this pin must be tied low." (1) PWR = Supply voltage. 36 Device Overview Submit Documentation Feedback TMS320C6745/6747 TMS320C6745/6747 Floating-point Digital Signal Processor www.ti.com SPRS377B SPRS377B ­ SEPTEMBER 2008 ­ REVISED DECEMBER 2008 3.6.21 Supply and Ground Table 3-24. Supply and Ground Terminal Functions PIN NO PTP ZKB F6,G6, G7, G10, G11, H7, H10, H11, J6, J7, J10, J11, J12, K6, K7, K10, K11,L6 CVDD (Core supply) 10, 20, 28, 38, 50, 56, 61, 69, 77, 93, 104, 114, 147, 154, 161, 167, RVDD (Internal RAM supply)