TMS320C6743 SPRS565A TMS320C6000 C6000 TMS320 C6743 TMS320C6000TM 128KB 1024KB - Datasheet Archive

 

www.ti.com SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 1 TMS320C6743 Fixed/Floating-point Digital Signal Processor

 

TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 1 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor · · · · · · Applications ­ Industrial Control ­ Networking ­ High-Speed Encoding ­ Professional Audio Software Support ­ TI DSP/BIOSTM ­ Chip Support Library and DSP Library C674x Instruction Set Features ­ Superset of the C67x+TM and C64x+TM ISAs ­ 2400/1800 C674x MIPS/MFLOPS ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions C674x Two Level Cache Memory Architecture ­ 32K-Byte L1P Program RAM/Cache ­ 32K-Byte L1D Data RAM/Cache ­ 128K-Byte L2 Unified Mapped RAM/Cache ­ Flexible RAM/Cache Partition (L1 and L2) ­ 1024K-Byte L2 ROM Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Transfer Controllers ­ 32 Independent DMA Channels ­ 8 Quick DMA Channels ­ Programmable Transfer Burst Size TMS320C674x Floating Point VLIW DSP Core ­ Load-Store Architecture With Non-Aligned Support ­ 64 General-Purpose Registers (32 Bit) ­ Six ALU (32-/40-Bit) Functional Units · Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point · Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks · Supports up to Two Floating Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle ­ Two Multiply Functional Units · Mixed-Precision IEEE Floating Point · · · · · · · · Multiply Supported up to: ­ 2 SP x SP -> SP Per Clock ­ 2 SP x SP -> DP Every Two Clocks ­ 2 SP x DP -> DP Every Three Clocks ­ 2 DP x DP -> DP Every Four Clocks · Fixed Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Hardware Support for Modulo Loop Operation ­ Protected Mode Operation ­ Exceptions Support for Error Detection and Program Redirection 3.3V LVCMOS IOs Two External Memory Interfaces: ­ EMIFA · NOR (8-Bit-Wide Data) · NAND (8-Bit-Wide Data) · 16-bit SDRAM, up to 128 Mbit (ZKB package only) ­ EMIFB · 16/32-bit SDRAM, up to 512 Mbit (ZKB package only) · 16-bit SDRAM, up to 256 Mbit (PTP package only) Two Configurable 16550 type UART Modules: ­ UART0 With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option One Serial Peripheral Interface (SPI) With One Chip-Select Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Two Master/Slave Inter-Integrated Circuit (I2C BusTM) Two Multichannel Audio Serial Ports: ­ Transmit/Receive Clocks up to 50 MHz ­ Supports TDM, I2S, and Similar Formats ­ FIFO buffers for Transmit and Receive 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802.3 Compliant (3.3-V I/O Only) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. TMS320C6000 TMS320C6000, C6000 C6000 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2009­2009, Texas Instruments Incorporated ADVANCE INFORMATION 1.1 Features TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 · · · ADVANCE INFORMATION 2 ­ RMII Media Independent Interface ­ Management Data I/O (MDIO) Module One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers) One 64-Bit General-Purpose Timer (Watch Dog) Three Enhanced Pulse Width Modulators (eHRPWM): ­ Dedicated 16-Bit Time-Base Counter With Period And Frequency Control ­ 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs ­ Dead-Band Generation ­ PWM Chopping by High-Frequency Carrier ­ Trip Zone Input TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com · · · · · Three 32-Bit Enhanced Capture Modules (eCAP): ­ Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs ­ Single Shot Capture of up to Four Event Time-Stamps Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP) 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch Commercial or Extended Temperature Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 1.2 Trademarks DSP/BIOS, TMS320C6000 TMS320C6000, C6000 C6000, TMS320 TMS320, and TMS320C64x are trademarks of Texas Instruments. ADVANCE INFORMATION All trademarks are the property of their respective owners. Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor 3 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 1.3 Description The C6743 C6743 is a Low-power digital signal processor based on C674x DSP core. It provides significantly lower power than other members of the TMS320C6000TM TMS320C6000TM platform of DSPs. The C6743 C6743 enables OEMs and ODMs to quickly bring to market devices featuring high processing performance . The C6743 C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128KB 128KB memory space that is shared between program and data space. L2 also has a 1024KB 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. ADVANCE INFORMATION The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 2 multichannel audio serial port (McASP) with 14/9 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. 4 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 1.4 Functional Block Diagram JTAG Interface DSP Subsystem System Control C674x DSP CPU PLL/Clock Generator w/OSC GeneralPurpose Timer GeneralPurpose Timer (Watchdog) AET 32 KB L1 Pgm Power/Sleep Controller 32 KB L1 RAM 128 KB L2 RAM Pin Multiplexing 1024 KB L2 ROM ADVANCE INFORMATION Input Clock(s) Switched Central Resource (SCR) Peripherals DMA EDMA3 McASP w/FIFO (2) (1) eCAP (3) I2C (2) Connectivity Control Timers ePWM (3) Serial Interfaces Audio Ports eQEP (2) (10/100) EMAC (RMII) MDIO MMC/SD (8b) SPI (1) UART (2) External Memory Interfaces EMIFA(8b) NAND/Flash EMIFB SDRAM Only (16b) Not all peripherals are available at the same time due to multiplixing. Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor 5 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Contents 1 1.1 1.3 Description . 4 1.4 Functional Block Diagram . 5 ADVANCE INFORMATION External Memory Interface A (EMIFA) . 62 6.11 External Memory Interface B (EMIFB) . 69 6.12 MMC / SD / SDIO (MMCSD) . 74 6.13 Ethernet Media Access Controller (EMAC) . 77 6.14 6.15 Device Compatibility . 9 3.3 . EDMA 6.10 Device Characteristics . 8 3.2 General-Purpose Input/Output (GPIO) . 54 6.9 Revision History . 7 Device Overview . 8 3.1 Interrupts . 50 6.8 Trademarks . 3 Clock PLLs . 46 6.7 Features . 1 1.2 2 3 6.6 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor . 1 Management Data Input/Output (MDIO) . 82 Multichannel Audio Serial Ports (McASP0, McASP1) . 84 DSP Subsystem . 10 57 3.4 5 16 6.16 Serial Peripheral Interface Ports (SPI0) . 97 Pin Assignments 19 6.17 6.18 Enhanced Capture (eCAP) Peripheral . 110 Enhanced Quadrature Encoder (eQEP) Peripheral . 113 6.19 eHRPWM 37 6.20 Timers . 119 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted) . 37 4 Memory Map Summary 3.5 6.21 6.22 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) . 121 Universal Asynchronous Receiver/Transmitter (UART) . 125 Recommended Operating Conditions . 38 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted) . 39 6.23 Power and Sleep Controller (PSC) 6.24 Emulation Logic . 129 . . 3.6 Terminal Functions . Device Configuration . 4.1 SYSCFG Module . Device Operating Conditions . 21 34 34 5.1 5.2 5.3 6 Peripheral Information and Electrical Specifications . 40 6.1 6.2 6.3 Power Supplies . 42 6.4 Reset . 42 6.5 6 Parameter Information . 40 Recommended Clock and Control Signal Transition Behavior . 41 Crystal Oscillator or External Clock Input . 45 Contents 7 . . 115 126 Device and Documentation Support . 132 7.1 8 Device Support. 132 7.2 Documentation Support . 132 Mechanical Packaging and Orderable Information . 134 8.1 Device and Development-Support Tool Nomenclature . 134 8.2 Thermal Data for ZKB. 135 8.3 Thermal Data for PTP. 136 8.4 Mechanical Drawings . 136 Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the changes made to the SPRS565 SPRS565 device-specific data manual to make it an SPRS565A SPRS565A revision. Table 2-1. Revision History ADDITIONS/MODIFICATIONS/DELETIONS ADVANCE INFORMATION Section 1.4, Updated the Functional Block Diagram. Submit Documentation Feedback Revision History 7 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 3 Device Overview 3.1 Device Characteristics Table 3-1 provides an overview of the C6743 C6743 Low power digital signal processor. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Table 3-1. Characteristics of the C6743 C6743 Processor HARDWARE FEATURES C6743 C6743 ADVANCE INFORMATION EMIFB SDRAM only, 16-bit bus width, up to 256 Mbit (PTP) SDRAM only, 16-bit bus width, up to 512 Mbit (ZKB) EMIFA Asynchronous (8-bit bus width) RAM, Flash, NOR, NAND (PTP) Asynchronous (8-bit bus width) RAM, Flash, NOR, NAND, 16-bit SDRAM add "up to 128 Mbit (ZKB) Flash Card Interface MMC and SD cards supported. EDMA3 Timers Not all peripherals pins are available at the same time (for more detail, see the Device Configurations section). 2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as Watch Dog) UART Peripherals 32 independent channels, 8 QDMA channels, 2 Transfer controllers 2 (One with RTS and CTS flow control) SPI One with one hardware chip select I2C 2 (both Master/Slave) Multichannel Audio Serial Port [McASP] 10/100 Ethernet MAC with Management Data I/O eHRPWM 2 (each with transmit/receive, FIFO buffer, 14/9 serializers) 1 (RMII Interface) 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs eQEP 2 32-bit QEP channels with 4 inputs/channel General-Purpose Input/Output Port 8 banks of 16-bit Size (Bytes) On-Chip Memory 488KB 488KB RAM, 1088KB 1088KB ROM Organization DSP 32KB L1 Program (L1P)/Cache (up to 32KB) 32KB L1 Data (L1D)/Cache (up to 32KB) 128KB 128KB Unified Mapped RAM/Cache (L2) 1024KB 1024KB ROM (L2) DSP Memories can be made accessible to EDMA3, and other peripherals. C674x CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1400 C674x Megamodule Revision Revision ID Register (MM_REVID[15:0]) 0x0000 JTAG BSDL_ID JTAGID Register CPU Frequency MHz Cycle Time ns Core (V) Voltage I/O (V) (1) 8 674x DSP 300(/200) MHz 674x DSP 3.33(/5) ns 1.2 V 3.3 V 24 mm x 24 mm, 176-Pin, 0.5 mm pitch, TQFP (PTP) Package Product Status 0x0B7D_F02F (1) Product Preview (PP), Advance Information (AI), or Production Data (PD) 17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB) AI ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.2 Device Compatibility ADVANCE INFORMATION The C674x DSP core is code-compatible with the C6000TM C6000TM DSP platform and supports features of both the C64x+ and C67x+ DSP families. Submit Documentation Feedback Device Overview 9 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 3.3 DSP Subsystem The DSP Subsystem includes the following features: · C674x DSP CPU · 32KB L1 Program (L1P)/Cache (up to 32KB) · 32KB L1 Data (L1D)/Cache (up to 32KB) · 128KB 128KB Unified Mapped RAM/Cache (L2) · 1MB Mask-programmable ROM · Little endian ADVANCE INFORMATION 32K Bytes L1P RAM/ Cache 128K Bytes L2 RAM 256 256 256 Cache Control Memory Protect 1M Byte L2 ROM 256 Cache Control Memory Protect L1P Bandwidth Mgmt L2 Bandwidth Mgmt 256 256 256 Instruction Fetch 256 Power Down Interrupt Controller C64x Fixed/Floating-Point CPU IDMA Register File A Register File B 64 64 256 CFG Bandwidth Mgmt Memory Protect Cache Control 8 x 32 EMC L1D MDMA 64 32K Bytes L1D RAM/ Cache 32 Configuration Peripherals Bus SDMA 64 64 64 High Performance Switch Fabric Figure 3-1. C674x Megamodule Block Diagram 10 Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com 3.3.1 SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 C674x DSP CPU Description The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory. Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types. The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support. Other new features include: · SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. · Compact Instructions - The native instruction size for the C6000 C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools. · Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. · Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). · Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. · Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. Submit Documentation Feedback Device Overview 11 ADVANCE INFORMATION The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents: · TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 SPRU732) · TMS320C64x Technical Overview (literature number SPRU395 SPRU395) ADVANCE INFORMATION 12 Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á Á Á ÁÁ Á ÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁ www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 src1 Odd register file A (A1, A3, A5.A31) src2 .L1 odd dst Even register file A (A0, A2, A4.A30) (D) even dst long src ST1b ST1a 32 MSB 32 LSB long src Data path A .S1 8 8 even dst odd dst src1 (D) .M1 dst2 dst1 src1 32 32 src2 LD1a 32 MSB 32 LSB DA1 DA2 LD2a LD2b Á Á Á Á Á Á Á LD1b ADVANCE INFORMATION src2 (A) (B) (C) dst .D1 src1 src2 2x 1x Odd register file B (B1, B3, B5.B31) src2 .D2 32 LSB 32 MSB src1 dst src2 .M2 Even register file B (B0, B2, B4.B30) (C) src1 dst2 32 (B) dst1 32 (A) src2 src1 .S2 odd dst even dst long src Data path B ST2a ST2b 32 MSB 32 LSB long src even dst .L2 (D) 8 8 (D) odd dst src2 src1 Control Register A. B. C. D. On .M unit, dst2 is 32 MSB. On .M unit, dst1 is 32 LSB. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths Submit Documentation Feedback Device Overview 13 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.3.2 www.ti.com DSP Memory Mapping The DSP memory map is shown in Section 3.4. 3.3.2.1 External Memories The DSP has access to the following External memories: · Asynchronous EMIF / NAND / NOR Flash (EMIFA) · SDRAM (EMIFB) 3.3.2.2 DSP Internal Memories ADVANCE INFORMATION The DSP has access to the following DSP memories: · L2 RAM · L1P RAM · L1D RAM 3.3.2.3 C674x CPU The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 128 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 3-2 shows a memory map of the C674x CPU cache registers for the device. Table 3-2. C674x Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM 0x0184 0000 L2CFG 0x0184 0020 L1PCFG 0x0184 0024 L1PCC 0x0184 0040 L1DCFG 0x0184 0044 L1DCC 0x0184 0048 - 0x0184 0FFC - 0x0184 1000 EDMAWEIGHT DESCRIPTION L2 Cache configuration register L1P Size Cache configuration register L1P Freeze Mode Cache configuration register L1D Size Cache configuration register L1D Freeze Mode Cache configuration register Reserved L2 EDMA access control register 0x0184 1004 - 0x0184 1FFC - 0x0184 2000 L2ALLOC0 Reserved L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 0x0184 2010 - 0x0184 3FFF - 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register Reserved 0x0184 4018 L2 invalidate base address register L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 14 L2IBAR 0x0184 401C L1DIBAR L1D invalidate base address register Device Overview Reserved Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 Table 3-2. C674x Cache Registers (continued) REGISTER ACRONYM 0x0184 404C L1DIWC 0x0184 4050 - 0x0184 4FFF - 0x0184 5000 L2WB 0x0184 5004 L2WBINV 0x0184 5008 L2INV DESCRIPTION L1D invalidate word count register Reserved L2 writeback all register L2 writeback invalidate all register L2 Global Invalidate without writeback 0x0184 500C - 0x0184 5027 - 0x0184 5028 L1PINV Reserved 0x0184 502C - 0x0184 5039 - 0x0184 5040 L1DWB 0x0184 5044 L1DWBINV 0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 ­ 0x0184 80FF MAR0 - MAR63 MAR63 Reserved 0x0000 0000 ­ 0x3FFF FFFF 0x0184 8100 ­ 0x0184 817F MAR64 MAR64 ­ MAR95 MAR95 Reserved 0x4000 0000 ­ 0x5FFF FFFF 0x0184 8180 ­ 0x0184 8187 MAR96 MAR96 - MAR97 MAR97 Memory Attribute Registers for EMIFA Async Data (CS2) 0x6000 0000 ­ 0x61FF FFFF 0x0184 8188 ­ 0x0184 818F MAR98 MAR98 ­ MAR99 MAR99 Memory Attribute Registers for EMIFA Async Data (CS3) 0x6200 0000 ­ 0x63FF FFFF L1P Global Invalidate Reserved L1D Global Writeback L1D Global Writeback with Invalidate 0x0184 8190 ­ 0x0184 8197 MAR100 MAR100 ­ MAR101 MAR101 Reserved 0x6400 0000 ­ 0x65FF FFFF 0x0184 8198 ­ 0x0184 819F MAR102 MAR102 ­ MAR103 MAR103 Reserved 0x6600 0000 ­ 0x67FF FFFF 0x0184 81A0 ­ 0x0184 81FF MAR104 MAR104 ­ MAR127 MAR127 Reserved 0x6800 0000 ­ 0x7FFF FFFF 0x0184 8200 MAR128 MAR128 Reserved 0x8000 0000 ­ 0x81FF FFFF 0x0184 8204 ­ 0x0184 82FF MAR129 MAR129 ­ MAR191 MAR191 Reserved 0x8200 0000 ­ 0xBFFF FFFF 0x0184 8300 ­ 0x0184 837F MAR192 MAR192 ­ MAR223 MAR223 Memory Attribute Registers for EMIFB SDRAM Data (CS2) 0xC000 0000 ­ 0xDFFF FFFF 0x0184 8380 ­ 0x0184 83FF MAR224 MAR224 ­ MAR255 MAR255 Reserved 0xE000 0000 ­ 0xFFFF FFFF See Table 3-3 for a detailed top level C6743 C6743 memory map that includes the DSP memory space. Submit Documentation Feedback Device Overview 15 ADVANCE INFORMATION HEX ADDRESS RANGE TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 3.4 Memory Map Summary Table 3-3. C6743 C6743 Top Level Memory Map START ADDRESS END ADDRESS SIZE 0x0000 0000 0x006F FFFF 6M + 1024K 1024K 0x0070 0000 0x007F FFFF 1024K 1024K 0x0080 0000 0x0081 FFFF 128K 0x0083 FFFF 128K 0x0084 0000 0x00DF FFFF 0x00E0 7FFF 32K 0x00E0 8000 0x00EF FFFF 0x00F0 7FFF 32K 0x00F0 8000 0x017F FFFF 0x0180 FFFF 0x0181 0000 DSP L2 ROM - 8M + 992K 0x0180 0000 DSP L2 RAM - DSP L1P RAM - DSP L1D RAM - 64K DSP Interrupt Controller - 0x0181 0FFF 4K DSP Powerdown Controller - 0x0181 1000 0x0181 1FFF 4K DSP Security ID - 0x0181 2000 0x0181 2FFF 4K DSP Revision ID - 0x0181 3000 0x0181 FFFF 52K - - 0x0182 0000 0x0182 FFFF 64K DSP EMC - 0x0183 0000 0x0183 FFFF 64K DSP Internal Reserved - 0x0184 0000 0x0184 FFFF 64K DSP Memory System - 0x0185 0000 0x01BB FFFF 3M + 600K 0x01BC 0000 0x01BC 0FFF 4K - 0x01BC 1000 0x01BC 17FF 2K - 0x01BC 1900 0x01BC 18FF 256 - 0x01BC 0500 0x01BF FFFF 260K 0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC 0x01C0 8000 0x01C0 83FF 1024 EDMA3 TC0 0x01C0 8400 0x01C0 87FF 1024 EDMA3 TC1 0x01C0 8800 0x01C0 FFFF 30K 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0x01C1 2000 0x01C1 3FFF 8K 0x01C1 4000 0x01C1 4FFF 4K BootConfig 0x01C1 5000 0x01C1 5FFF 4K - 0x01C1 6000 0x01C1 6FFF 4K - 0x01C1 7000 0x01C1 7FFF 4K - 0x01C1 8000 0x01C1 FFFF 32K - 0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 0x01C2 2000 0x01C2 2FFF 4K I2C 0 0x01C2 3000 0x01C2 3FFF 4K - 0x01C2 4000 0x01C2 4FFF 4K - 0x01C2 5000 0x01C3 FFFF 110K - 0x01C4 0000 16 MASTER PERIPHERAL MEM MAP 992K 0x00F0 0000 EDMA MEM MAP - 5M + 768K 0x00E0 0000 ADVANCE INFORMATION 0x0082 0000 DSP MEM MAP 0x01C4 0FFF 4K MMC/SD 0 Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 Table 3-3. C6743 C6743 Top Level Memory Map (continued) END ADDRESS SIZE DSP MEM MAP EDMA MEM MAP 0x01C4 1000 0x01C4 1FFF 4K SPI 0 0x01C4 2000 0x01C4 2FFF 4K UART 0 0x01C4 3000 0x01CF FFFF 774K - 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data 0x01D0 3000 0x01D0 3FFF 4K - 0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control 0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Ctrl 0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data 0x01D0 7000 0x01D0 7FFF 4K - 0x01D0 8000 0x01D0 8FFF 4K - 0x01D0 9000 0x01D0 9FFF 4K - 0x01D0 A000 0x01D0 AFFF 4K - 0x01D0 B000 0x01D0 BFFF 4K 0x01D0 C000 0x01D0 CFFF 4K - 0x01D0 D000 0x01D0 DFFF 4K UART2 0x01D0 E000 0x01D0 EFFF 4K - 0x01D0 F000 0x01DF FFFF 964K - 0x01E0 0000 0x01E0 FFFF 64K - 0x01E1 0000 0x01E1 0FFF 4K - 0x01E1 1000 0x01E1 1FFF 4K - 0x01E1 2000 0x01E1 2FFF 4K - 0x01E1 3000 0x01E1 3FFF 4K - 0x01E1 4000 0x01E1 4FFF 4K - 0x01E1 5000 0x01E1 5FFF 4K - 0x01E1 6000 0x01E1 FFFF 40K - 0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM 0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers 0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers 0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port 0x01E2 5000 0x01E2 5FFF 4K - 0x01E2 6000 0x01E2 6FFF 4K GPIO 0x01E2 7000 0x01E2 7FFF 4K PSC 1 0x01E2 8000 0x01E2 8FFF 4K I2C 1 0x01E2 9000 0x01E2 9FFF 4K - 0x01E2 A000 0x01EF FFFF 856K - 0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 0x01F0 7000 0x01F0 7FFF 4K ECAP 1 0x01F0 8000 0x01F0 8FFF 4K MASTER PERIPHERAL MEM MAP ADVANCE INFORMATION START ADDRESS ECAP 2 Submit Documentation Feedback Device Overview 17 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Table 3-3. C6743 C6743 Top Level Memory Map (continued) START ADDRESS END ADDRESS SIZE DSP MEM MAP EDMA MEM MAP 0x01F0 9000 0x01F0 9FFF 4K EQEP 0 0x01F0 A000 0x01F0 AFFF 4K EQEP 1 0x01F0 B000 0x01F0 BFFF 4K - 0x01F0 C000 0x116F FFFF 247M + 976K - 0x1170 0000 0x117F FFFF 1024K 1024K DSP L2 ROM 0x1180 0000 0x1181 FFFF 128K DSP L2 RAM 0x1183 FFFF 128K 0x1184 0000 0x11DF FFFF 5M + 768K - 0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM 0x11E0 8000 0x11EF FFFF 992K - 0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM 0x11F0 8000 0x3FFF FFFF 736M + 992K - 0x4000 0000 0x5FFF FFFF 512M - 0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) 0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) 0x6400 0000 0x65FF FFFF 32M - 0x6600 0000 0x67FF FFFF 32M - 0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs 0x6800 8000 ADVANCE INFORMATION 0x1182 0000 0x7FFF FFFF 383M + 992K - 0x8000 0000 0x8001 FFFF 128K - 0x8002 0000 0xAFFF FFFF 767M + 896K - 0xB000 0000 0xB000 7FFF 32K EMIFB Control Regs 0xB000 8000 0xBFFF FFFF 255M + 992K - 0xC000 0000 0xDFFF FFFF 512M EMIFB SDRAM Data 0xE000 0000 0xFFFC FFFF 511M + 832K - 0xFFFD 0000 0xFFFD FFFF 64K - 0xFFFE 0000 0xFFFE DFFF 56K - 0xFFFE E000 0xFFFE FFFF 8K - 0xFFFF 0000 0xFFFF 1FFF 8K - 0xFFFF 2000 18 MASTER PERIPHERAL MEM MAP 0xFFFF FFFF 56K - Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.5 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 3.5.1 Pin Map (Bottom View) Figure 3-3 and Figure 3-4 show the pin assignments for ZKB package and PTP package respectively. Note that micro-vias are not required. Contact your TI representative for routing recommendations. 1 2 3 4 5 6 NC SPI0_CLK/ EQEP1I/ GP5[2]/ BOOT[2] EQEP1S/ GP5[7]/ BOOT[7] 7 8 9 10 11 12 13 14 15 16 GP0[9] VSS VSS T NC EMA_A[0]/ GP1[0] EMA_A[4]/ GP1[4] EMA_A[8]/ GP1[8] NC EMA_OE/ AXR0[13]/ GP2[7] EMA_BA[0]/ GP1[14] EMA_A[1]/ MMCSD_CLK/ GP1[1] EMA_A[5]/ GP1[5] EMA_A[9]/ GP1[9] NC EMA_D[2]/ MMCSD_DAT[2]/ GP0[2] GP0[10] EMA_D[1]/ MMCSD_DAT[1]/ GP0[1] DVDD R SPI0_SIMO[0]/ EMA_CS[2]/ EMA_BA[1]/ EQEP0S/ GP2[5]/ GP1[13] GP5[1]/ BOOT[15] BOOT[1] EMA_A[2]/ MMCSD_CMD/ GP1[2] EMA_A[6]/ GP1[6] EMA_A[11]/ GP1[11] NC EMA_D[4]/ MMCSD_DAT[4]/ GP0[4] GP0[12] EMA_D[3]/ MMCSD_DAT[3]/ GP0[3] GP0[11] P EMA_A[10]/ GP1[10] EMA_A[3]/ GP1[3] EMA_A[7]/ GP1[7] EMA_A[12]/ GP1[12] GP0[8] EMA_D[6]/ MMCSD_DAT[6]/ GP0[6] GP0[14] EMA_D[5]/ MMCSD_DAT[5]/ GP0[5] GP0[13] N VSS DVDD DVDD VSS VSS DVDD EMA_WE/ AXR0[12]/ GP2[3]/ BOOT[14]] NC EMA_D[7]/ MMCSD_DAT[7]/ GP0[7]/ BOOT[13] GP0[15] M CVDD VSS VSS VSS VSS DVDD DVDD EMB_CAS NC NC NC L DVDD CVDD CVDD VSS VSS CVDD CVDD DVDD NC EMB_WE_ DQM[0]/ GP5[15] EMB_WE NC K TRST NC CVDD CVDD VSS VSS CVDD CVDD CVDD EMB_D[5]/ GP6[5] NC EMB_D[6]/ GP6[6] EMB_D[7]/ GP6[7] J TCK VSS NC RVDD CVDD VSS VSS CVDD CVDD RVDD EMB_D[3]/ GP6[3] NC NC EMB_D[4]/ GP6[4] H VSS RESET VSS DVDD CVDD CVDD VSS VSS CVDD CVDD DVDD EMB_D[1]/ GP6[1] NC NC EMB_D[2]/ GP6[2] G OSCOUT OSCIN VSS VSS DVDD CVDD RSV1 VSS VSS VSS DVDD DVDD EMB_D[15]/ GP6[15] NC NC EMB_D[0]/ GP6[0] F E PLL0_VSSA OSCVSS NC NC DVDD VSS VSS DVDD DVDD VSS VSS DVDD EMB_D[13]/ GP6[13] NC NC EMB_D[14]/ GP6[14] E D PLL0_VDDA NC NC AMUTE1/ EHRPWMTZ/ GP4[14] AFSX0/ GP2[13]/ BOOT[10] AXR0[10]/ GP3[10] AXR0[6]/ RMII_RXER/ GP3[6] AXR0[2]/ RMII_TXEN/ GP3[2] EMB_CS[0] EMB_A[0]/ GP7[2] EMB_A[4]/ GP7[6] EMB_A[8]/ GP7[10] EMB_D[9]/ GP6[9] EMB_D[10]/ GP6[10] EMB_D[11]/ GP6[11] EMB_D[12]/ GP6[12] D C NC NC NC AFSR0/ GP3[12] ACLKX0/ ECAP0/ APWM0/ GP2[12] AXR0[9]/ GP3[9] AXR0[5]/ AXR0[1]/ RMII_RXD[1]/ RMII_TXD[1]/ GP3[5] GP3[1] EMB_BA[0]/ GP7[1] EMB_A[1]/ GP7[3] EMB_A[5]/ GP7[7] EMB_A[9]/ GP7[11] EMB_SDCKE EMB_CLK EMB_WE_ DQM[1]/ GP5[14] EMB_D[8]/ GP6[8] C B RSV2 VSS VSS ACLKR0/ ECAP1/ APWM1/ GP2[15] AHCLKX0/ GP2[11] AXR0[8]/ MDIO_D/ GP3[8] AXR0[4]/ AXR0[0]/ RMII_RXD[0]/ RMII_TXD[0]/ GP3[4] GP3[0] EMB_BA[1]/ GP7[0] EMB_A[2]/ GP7[4] EMB_A[6]/ GP7[8] EMB_A[11]/ GP7[13] NC NC EMB_A[12]/ GP3[13] DVDD B A VSS VSS VSS AHCLKR0/ RMII_MHZ_ 50_CLK/ GP2[14]/ BOOT[11] AXR0[11]/ GP3[11] AXR0[7]/ MDIO_CLK/ GP3[7] AXR0[3]/ RMII_CRS_DV/ GP3[3] EMB_RAS EMB_A[10]/ GP7[12] EMB_A[3]/ GP7[5] EMB_A[7]/ GP7[9] NC NC NC VSS VSS A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AXR1[0]/ GP4[0] T VSS VSS R DVDD AXR1[1]/ GP4[1] SPI0_ENA/ SPIO_SOMI[0]/ UART0_RXD/ UART0_CTS/ EQEPOI/ GP5[12]/ TM64P0 TM64P0_IN12/ IN12/ EQEP0A/ GP5[8]/BOOT[8]/ UART2_RXD GP5[0]/ GP5[3]/ I2C0_SDA BOOT[0] BOOT[3] P AXR1[3]/ EQEP1A/ GP4[3] AXR1[2]/ GP4[2] UART0_TXD/ GP5[13]/ TM64P0 TM64P0_OUT12/ OUT12/ GP5[9]/BOOT[9]/ UART2_TXD I2C0_SCL I2C1_SCL/ GP5[5]/ BOOT[5] N AXR1[5]/ EPWM2B/ GP4[5] AXR1[4]/ EQEP1B/ GP4[4] NC SPI0_SCS[0]/ UART0_RTS/ EQEP0B/ GP5[4]/ BOOT[4] I2C1_SDA/ GP5[6]/ BOOT[6] EMA_WAIT[0]/ GP2[10] NC M NC AXR1[8]/ EPWM1A/ GP4[8] AXR1[7]/ EPWM1B/ GP4[7] AXR1[6]/ EPWM2A/ GP4[6] DVDD VSS L AHCLKR1/ GP4[11] ACLKR1/ ECAP2/ APWM2/ GP4[12] AFSR1/ GP4[13] NC DVDD K GP7[14] AHCLKX1/ EPWM0B/ GP3[14] ACLKX1/ EPWM0A/ GP3[15] AFSX1/ EPWMSYNCI/ EPWMSYNCO/ GP4[10] J TMS TDI TDO H VSS NC G CVDD F ADVANCE INFORMATION EMA_CS[3]/ GP2[6] EMA_D[0]/ MMCSD_DAT[0]/ GP0[0]/ BOOT[12] Note: NC = No Connect Figure 3-3. Pin Map (ZKB) Submit Documentation Feedback Device Overview 19 RSV2 NC NC VSS VSS VSS VSS NC PLL0_VDDA PLL0_VSSA OSCIN OSCVSS OSCOUT RESET CVDD RSV4 RSV3 TRST DVDD TMS TDI CVDD TCK TDO GP7[14] DVDD RVDD AHCLKX1/EPWM0B/GP3[14] CVDD ACLKX1/EPWM0A/GP3[15] AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10] DVDD ACLKR1/ECAP2/APWM2/GP4[12] AFSR1/GP4[13] CVDD AXR1[8]/EPWM1A/GP4[8] AXR1[7]/EPWM1B/GP4[7] AXR1[6]/EPWM2A/GP4[6] AXR1[5]/EPWM2B/GP4[5] DVDD AXR1[4]/EQEP1B/GP4[4] AXR1[3]/EQEP1A/GP4[3] AXR1[2]/GP4[2] AXR1[1]/GP4[1] 20 Device Overview 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 CVDD SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] I2C1_SCL/GP5[5]/BOOT[5] I2C1_SDA/GP5[6]/BOOT[6] DVDD EQEP1S/GP5[7]/BOOT[7] SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] EMA_WAIT[0]/GP2[10] CVDD EMA_CS[3]/GP2[6] EMA_OE//AXR0[13]/GP2[7] EMA_CS[2]/GP2[5]/BOOT[15] DVDD EMA_BA[0]/GP1[14] EMA_BA[1]/GP1[13] EMA_A[10]/GP1[10] CVDD EMA_A[0]/GP1[0] EMA_A[1]/MMCSD_CLK/GP1[1] EMA_A[2]/MMCSD_CMD/GP1[2] EMA_A[3]/GP1[3] DVDD EMA_A[4]/GP1[4] EMA_A[5]/GP1[5] EMA_A[6]/GP1[6] EMA_A[7]/GP1[7] CVDD EMA_A[8]/GP1[8] EMA_A[9]/GP1[9] EMA_A[11]/GP1[11] EMA_A[12]/GP1[12] DVDD EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 ADVANCE INFORMATION AXR1[0]/GP4[0] UART0_RXD/M64P0 RXD/M64P0_IN12/GP5 IN12/GP5[8]/BOOT8/I2C0_SDA UART0_TXD/TM64P0 TXD/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9]/I2C0_SCL GP5[10] DVDD GP5[11] GP5[12]/UART2_RXD GP5[13]/UART2_TXD SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 AMUTE1/EHRPWMTZ/GP4[14] AFSR0/GP3[12] ACLKR0/ECAP1/APWM1/GP2[15] AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] DVDD AFSX0/GP2[13]/BOOT[10] ACLKX0/ECAP0/APWM0/GP2[12] AHCLKX0/GP2[11] AXR0[11]/GP3[11] AXR0[10]/GP3[10] AXR0[9]/GP3[9] AXR0[8]/MDIO_D/GP3[8] AXR0[7]/MDIO_CLK/GP3[7] DVDD AXR0[6]/RMII_RXER/GP3[6] AXR0[5]/RMII_RXD[1]/GP3[5] AXR0[4]/RMII_RXD[0]/GP3[4] AXR0[3]/RMII_CRS_DV/GP3[3] CVDD AXR0[2]/RMII_TXEN/GP3[2] AXR0[1]/RMII_TXD[1]/GP3[1] AXR0[0]/RMII_TXD[0]/GP3[0] EMB_RAS DVDD EMB_CS[0] EMB_BA[0]/GP7[1] EMB_BA[1]/GP7[0] EMB_A[10]/GP7[12] CVDD EMB_A[0]/GP7[2] EMB_A[1]/GP7[3] EMB_A[2]/GP7[4] EMB_A[3]/GP7[5] DVDD EMB_A[4]/GP7[6] EMB_A[5]/GP7[7] EMB_A[6]/GP7[8] EMB_A[7]/GP7[9] EMB_A[8]/GP7[10] CVDD EMB_A[9]/GP7[11] EMB_A[11]/GP7[13] DVDD EMB_A[12]/GP3[13] TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Thermal Pad (177) 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 EMB_SDCKE DVDD EMB_CLK EMB_WE_DQM[1]/GP5[14] EMB_D[8]/GP6[8] EMB_D[9]/GP6[9] EMB_D[10]/GP6[10] DVDD EMB_D[11]/GP6[11] EMB_D[12]/GP6[12] EMB_D[13]/GP6[13] CVDD EMB_D[14]/GP6[14] DVDD EMB_D[15]/GP6[15] EMB_D[0]/GP6[0] EMB_D[1]/GP6[1] DVDD EMB_D2/GP6[2] CVDD EMB_D[3]/GP6[3] RVDD EMB_D[4]/GP6[4] DVDD EMB_D[5]/GP6[5] EMB_D[6]/GP6[6] EMB_D[7]/GP6[7] CVDD EMB_WE_DQM[0]/GP5[15] EMB_WE DVDD EMB_CAS CVDD EMA_WE/AXR0[12]/GP2[3]/BOOT[14] EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] DVDD EMA_D[6]/MMCSD_DAT[6]/GP0[6] EMA_D[5]/MMCSD_DAT[5]/GP0[5] CVDD EMA_D[4]/MMCSD_DAT[4]/GP0[4] EMA_D[3]/MMCSD_DAT[3]/GP0[3] DVDD EMA_D[2]/MMCSD_DAT[2]/GP0[2] EMA_D[1]/MMCSD_DAT[1]/GP0[1] Figure 3-4. Pin Map (PTP) Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.6 Terminal Functions Table 3-4 to Section 3.6.18 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description. 3.6.1 Device Reset and JTAG Table 3-4. Reset and JTAG Terminal Functions PTP ZKB 146 G3 TYPE (1) PULL (2) DESCRIPTION RESET RESET I Device reset input JTAG TMS 152 J1 I IPU JTAG test mode select TDI 153 J2 I IPU JTAG test data input TDO 156 J3 O IPU JTAG test data output TCK 155 H3 I IPU JTAG test clock TRST 150 J4 I IPD JTAG test reset (1) (2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.2 High-Frequency Oscillator and PLL Table 3-5. High-Frequency Oscillator and PLL Terminal Functions SIGNAL NAME PIN NO TYPE (1) PULL (2) DESCRIPTION PTP ZKB OSCIN 143 F2 I Oscillator input OSCOUT 145 F1 O Oscillator output OSCVSS 144 E2 GND 1.2-V OSCILLATOR Oscillator ground (for filter only) 1.2-V PLL PLL0_VDDA 141 D1 PWR PLL analog VDD (1.2-V filtered supply) PLL0_VSSA 142 E1 GND PLL analog VSS (for filter) (1) (2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 21 ADVANCE INFORMATION PIN NO SIGNAL NAME TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.6.3 www.ti.com External Memory Interface A (ASYNC, SDRAM) Table 3-6. External Memory Interface A (EMIFA) Terminal Functions PIN NO TYPE (1) PULL (2) M15 I/O IPU 52 N13 I/O IPU 51 N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/GP0[4] 49 P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/GP0[3] 48 P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/GP0[2] 46 R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/GP0[1] 45 R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU EMA_A[12]/GP1[12] 42 N11 O IPU EMA_A[11]/GP1[11] 41 P11 O IPU EMA_A[10]/GP1[10] 27 N8 O IPU EMA_A[9]/GP1[9] 40 R11 O IPU EMA_A[8]/GP1[8] 39 T11 O IPU EMA_A[7]/GP1[7] 37 N10 O IPD EMA_A[6]/GP1[6] 36 P10 O IPD EMA_A[5]/GP1[5] 35 R10 O IPD EMA_A[4]/GP1[4] 34 T10 O IPD EMA_A[3]/GP1[3] 32 N9 O IPD EMA_A[2]/MMCSD_CMD/GP1[2] 31 P9 O IPU EMA_A[1]/MMCSD_CLK/GP1[1] 30 R9 O IPU EMA_A[0]/GP1[0] 29 T9 O IPD EMA_BA[1]/GP1[13] 26 P8 O IPU EMA_BA[0]/GP1[14] 25 R8 O IPU EMA_CS[3]/GP2[6] 21 T7 O IPU GPIO EMA_CS[2]/GP2[5]/BOOT[15] 25 P7 O IPU GPIO, BOOT EMIFA Async Chip Select EMA_WE/AXR0[12]/GP2[3]/BOOT[14] 55 M13 O IPU MCASP0, GPIO, BOOT EMIFA SDRAM write enable. EMA_OE/AXR0[13]/GP2[7] 22 R7 O IPU McASP0, GPIO EMIFA output enable. EMA_WAIT[0]/GP2[10] 19 N6 I IPU GPIO EMIFA wait input/interrupt. SIGNAL NAME PTP ZKB EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 54 EMA_D[6]/MMCSD_DAT[6]/GP0[6] EMA_D[5]/MMCSD_DAT[5]/GP0[5] ADVANCE INFORMATION (1) (2) 22 MUXED DESCRIPTION MMC/SD, GPIO, BOOT MMC/SD, GPIO EMIFA data bus MMC/SD, GPIO, BOOT GPIO EMIFA address bus MMCSD, GPIO EMIFA address bus. GPIO EMIFA bank address I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com 3.6.4 SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 External Memory Interface B (only SDRAM ) Table 3-7. External Memory Interface B (EMIFB) Terminal Functions PIN NO TYPE (1) PULL (2) F13 I/O IPD 76 E16 I/O IPD 78 E13 I/O IPD EMB_D[12]/GP6[12] 79 D16 I/O IPD EMB_D[11]/GP6[11] 80 D15 I/O IPD EMB_D[10]/GP6[10] 82 D14 I/O IPD EMB_D[9]/GP6[9] 83 D13 I/O IPD EMB_D[8]/GP6[8] 84 C16 I/O IPD EMB_D[7]/GP6[7] 62 J16 I/O IPD EMB_D[6]/GP6[6] 63 J15 I/O IPD EMB_D[5]/GP6[5] 64 J13 I/O IPD EMB_D[4]/GP6[4] 66 H16 I/O IPD EMB_D[3]/GP6[3] 68 H13 I/O IPD EMB_D[2]/GP6[2] 70 G16 I/O IPD EMB_D[1]/GP6[1] 72 G13 I/O IPD EMB_D[0]/GP6[0] 73 F16 I/O IPD EMB_A[12]/GP3[13] 89 B15 O IPD EMB_A[11]/GP7[13] 91 B12 O IPD EMB_A[10]/GP7[12] 105 A9 O IPD EMB_A[9]/GP7[11] 92 C12 O IPD EMB_A[8]/GP7[10] 94 D12 O IPD EMB_A[7]/GP7[9] 95 A11 O IPD EMB_A[6]/GP7[8] 96 B11 O IPD EMB_A[5]/GP7[7] 97 C11 O IPD EMB_A[4]/GP7[6] 98 D11 O IPD EMB_A[3]/GP7[5] 100 A10 O IPD EMB_A[2]/GP7[4] 101 B10 O IPD EMB_A[1]/GP7[3] 102 C10 O IPD EMB_A[0]/GP7[2] 103 D10 O IPD EMB_BA[1]/GP7[0] 106 B9 O IPU EMB_BA[0]/GP7[1] 107 C9 O IPU EMIFB SDRAM band address. EMB_CLK 86 C14 O IPU EMIF SDRAM clock. EMB_SDCKE 88 C13 I/O IPU EMIFB SDRAM clock enable. EMB_WE 59 K15 O IPU EMIFB write enable EMB_RAS 110 A8 O IPU EMB_CAS 57 L13 O IPU EMIFB column address strobe. EMB_CS[0] 108 D9 O IPU EMIFB SDRAM chip select 0. EMB_WE_DQM[1]/GP5[14] 85 C15 O IPU EMB_WE_DQM[0]/GP5[15] 60 K14 O IPU PTP ZKB EMB_D[15]/GP6[15] 74 EMB_D[14]/GP6[14] EMB_D[13]/GP6[13] (1) (2) MUXED DESCRIPTION GPIO EMIFB SDRAM data bus. GPIO ADVANCE INFORMATION SIGNAL NAME EMIFB SDRAM row/column address bus. EMIFB SDRAM row/column address. GPIO GPIO GPIO EMIFB SDRAM row address strobe. EMIFB write enable/data mask for EMB_D. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 23 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.6.5 www.ti.com Serial Peripheral Interface Modules (SPI0) Table 3-8. Serial Peripheral Interface (SPI) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION SPI0 9 N4 I/O IPU UART0, EQEP0B, GPIO, BOOT SPI0 chip select. SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I/O IPU UART0, EQEP0A, GPIO, BOOT SPI0 enable. SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] ADVANCE INFORMATION SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 11 T5 I/O IPD eQEP1, GPIO, BOOT SPI0 clock. SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I/O IPD eQEP0, GPIO, BOOT SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] (1) (2) 24 17 R6 I/O IPD SPI0 data slave-in-masterout. SPI0 data slave-out-masterin. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com 3.6.6 SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2) The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon how the eCAP module is programmed. Table 3-9. Enhanced Capture Module (eCAP) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) I/O IPD McASP0, GPIO enhanced capture 0 input or auxiliary PWM 0 output. I/O IPD McASP0, GPIO enhanced capture 1 input or auxiliary PWM 1 output. I/O IPD McASP1, GPIO enhanced capture 2 input or auxiliary PWM 2 output. MUXED DESCRIPTION ACLKX0/ECAP0/APWM0/GP2[12] 126 C5 eCAP1 ACLKR0/ECAP1/APWM1/GP2[15] 130 B4 eCAP2 ACLKR1/ECAP2/APWM2/GP4[12] (1) (2) 165 L2 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.7 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2) Table 3-10. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION eHRPWM0 ACLKX1/EPWM0A/GP3[15] 162 K3 I/O eHRPWM0 A output (with high-resolution). IPD McASP1, GPIO eHRPWM0 B output. AHCLKX1/EPWM0B/GP3[14] 160 K2 I/O IPD AMUTE1/EPWMTZ/GP4[14] 132 D4 I/O IPD McASP1, eHRPWM1, GPIO, eHRPWM2 eHRPWM0 trip zone input. AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 K4 I/O IPD McASP1, eHRPWM0, GPIO Sync input to eHRPWM0 module or sync output to external PWM. eHRPWM1 AXR1[8]/EPWM1A/GP4[8] 168 M2 I/O AXR1[7]/EPWM1B/GP4[7] 169 M3 I/O IPD AMUTE1/EPWMTZ/GP4[14] 132 D4 I/O IPD eHRPWM1 A (with high-resolution). IPD McASP1, GPIO (1) (2) eHRPWM1 B output. McASP1, eHRPWM0, GPIO, eHRPWM2 eHRPWM1 trip zone input. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 25 ADVANCE INFORMATION eCAP0 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Table 3-10. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions (continued) PIN NO SIGNAL NAME PTP TYPE (1) ZKB PULL (2) MUXED DESCRIPTION eHRPWM2 AXR1[6]/EPWM2A/GP4[6] 170 M4 I/O IPD AXR1[5]/EPWM2B/GP4[5] 171 N1 I/O IPD AMUTE1/EPWMTZ/GP4[14] 132 D4 I/O IPD McASP1, GPIO ADVANCE INFORMATION 3.6.8 McASP1, eHRPWM0, GPIO, eHRPWM2 eHRPWM2 A (with high-resolution). eHRPWM2 B output. eHRPWM2 trip zone input. Enhanced Quadrature Encoder Pulse Module (eQEP) Table 3-11. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions PIN NO SIGNAL NAME PTP TYPE (1) ZKB PULL (2) MUXED DESCRIPTION eQEP0 SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I IPU SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I IPD SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I IPD SPIO, UART0, GPIO, BOOT SPI0, GPIO, BOOT eQEP0A quadrature input. eQEP0B quadrature input. eQEP0 index. eQEP0 strobe. eQEP1 eQEP1A quadrature input. AXR1[3]/EQEP1A/GP4[3] 174 P1 I IPD AXR1[4]/EQEP1B/GP4[4] 173 N2 I IPD SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 174 T5 I IPD SPI0, GPIO, BOOT eQEP1 index. EQEP1S/GP5[7]/BOOT[7] 16 T6 I IPD GPIO, BOOT eQEP1 strobe. McASP1, GPIO (1) (2) eQEP1B quadrature input. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.9 Boot Table 3-12. Boot Terminal Functions (1) SIGNAL NAME EMA_CS[2]/GP2[5]/BOOT[15] PIN NO PTP ZKB 23 P7 TYPE (2) PULL (3) I IPU EMIFA, GPIO BOOT[15]. EMIFA, McASP0, GPIO BOOT[14]. MUXED DESCRIPTION EMA_WE/AXR0[12]/GP2[3]/BOOT[14] 55 M13 I IPU EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 54 M15 I IPU EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 T13 I IPU AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 A4 I IPD McASP0, EMAC, GPIO BOOT[11]. AFSX0/GP2[13]/BOOT[10] 127 D5 I IPD McASP0, GPIO BOOT[10]. (1) (2) (3) 26 EMIFA, MMC/SD, GPIO BOOT[13]. BOOT[12]. Boot decoding will be defined in the ROM datasheet. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 Table 3-12. Boot Terminal Functions (continued) PIN NO TYPE (2) PULL (3) P3 I IPU UART0, I2C0, Timer0, GPIO BOOT[9]. 2 R3 I IPU UART0, I2C0, Timer0, GPIO BOOT[8]. EQEP1S/GP5[7]/BOOT[7] 16 T6 I IPD eQEP1, GPIO BOOT[7]. I2C1_SDA/GP5[6]/BOOT[6] 14 N5 I IPU I2C1_SCL/GP5[5]/BOOT[5] 13 P5 I IPU SIGNAL NAME PTP ZKB UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] 3 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] MUXED DESCRIPTION BOOT[6]. I2C1, GPIO BOOT[5]. SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I IPU SPI0, UART0, eQEP0, GPIO SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU SPI0, UART0, eQEP0, GPIO SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 T5 I IPD SPIO, eQEP1, GPIO BOOT[2]. SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I IPD SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I IPD BOOT[3]. SPI0, eQEP0, GPIO ADVANCE INFORMATION BOOT[4]. BOOT[1]. BOOT[0]. 3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART2) Table 3-13. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION UART0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] 2 R3 I IPU I2C0, BOOT, Timer0, GPIO, UART0 receive data. UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] 3 P3 O IPU I2C0, Timer0, GPIO, BOOT UART0 transmit data. SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 O IPU SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU UART0 clear-to-send input UART2 receive data. UART0 ready-to-send output SPIO, eQEP0, GPIO, BOOT UART2 UART2_RXD/GP5[12] 7 R4 I IPU UART2_TXD/GP5[13] 8 P4 O IPU GPIO (1) (2) UART2 transmit data. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.11 Inter-Integrated Circuit Modules(I2C0, I2C1) Table 3-14. Inter-Integrated Circuit (I2C) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) I/O IPU MUXED DESCRIPTION I2C0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] (1) (2) 2 R3 UART0, Timer0, GPIO, BOOT I2C0 serial data. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 27 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Table 3-14. Inter-Integrated Circuit (I2C) Terminal Functions (continued) PIN NO SIGNAL NAME TYPE (1) PULL (2) I/O IPU N5 I/O IPU P5 I/O IPU PTP ZKB UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] 3 P3 I2C1_SDA/GP5[6]/BOOT[6] 14 I2C1_SCL/GP5[5]/BOOT[5] 13 MUXED UART0, Timer0, GPIO, BOOT DESCRIPTION I2C0 serial clock. I2C1 GPIO, BOOT I2C1 serial Data. I2C1 serial clock. 3.6.12 Timers ADVANCE INFORMATION Table 3-15. Timers Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION TIMER0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] 2 R3 I IPU UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] 3 P3 O IPU UART0, I2C0, GPIO, BOOT Timer0 lower input. Timer0 lower output TIMER1 (Watchdog ) No external pins. The Timer1 peripheral pins are not pinned out as external pins. (1) (2) 28 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1) Table 3-16. Multichannel Audio Serial Ports (McASPs) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION McASP0 24 R7 I/O IPU EMIFA, GPIO EMA_WE/AXR0[12]/GP2[3]/BOOT[14] 55 M13 I/O IPU EMIFA, GPIO, BOOT AXR0[11]/GP3[11] 124 A5 I/O IPD GPIO AXR0[10]/GP3[10] 123 D6 I/O IPD GPIO AXR0[9]/GP3[9] 122 C6 I/O IPD GPIO AXR0[8]/MDIO_D/GP3[8] 121 B6 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] 120 A6 I/O IPD AXR0[6]/RMII_RXER/GP3[6] 118 D7 I/O IPD AXR0[5]/RMII_RXD[1]/GP3[5] 117 C7 I/O IPD AXR0[4]/RMII_RXD[0]/GP3[4] 116 B7 I/O IPD AXR0[3]/RMII_CRS_DV/GP3[3] 115 A7 I/O IPD AXR0[2]/RMII_TXEN/GP3[2] 113 D8 I/O IPD AXR0[1]/RMII_TXD[1]/GP3[1] 112 C8 I/O IPD AXR0[0]/RMII_TXD[0]/GP3[0] 111 B8 I/O IPD AHCLKX0/GP2[11] 125 B5 I/O IPD GPIO McASP0 transmit master clock. ACLKX0/ECAP0/APWM0/GP2[12] 126 C5 I/O IPD eCAP0, GPIO McASP0 transmit bit clock. AFSX0/GP2[13]/BOOT[10] 127 D5 I/O IPD GPIO, BOOT McASP0 transmit frame sync. AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 A4 I/O IPD EMAC, GPIO, BOOT McASP0 receive master clock. ACLKR0/ECAP1/APWM1/GP2[15] 130 B4 I/O IPD eCAP1, GPIO McASP0 receive bit clock. AFSR0/GP3[12] 131 C4 I/O IPD GPIO McASP0 receive frame sync. (1) (2) MDIO, GPIO McASP0 serial data. EMAC, GPIO I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 29 ADVANCE INFORMATION EMA_OE/AXR0[13]/GP2[7] TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Table 3-16. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued) SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION McASP1 168 M2 I/O IPD eHRPWM1 A, GPIO AXR1[7]/EPWM1B/GP4[7] 169 M3 I/O IPD eHRPWM1 B, GPIO AXR1[6]/EPWM2A/GP4[6] 170 M4 I/O IPD eHRPWM2 A, GPIO AXR1[5]/EPWM2B/GP4[5] ADVANCE INFORMATION AXR1[8]/EPWM1A/GP4[8] 171 N1 I/O IPD eHRPWM2 B, GPIO AXR1[4]/EQEP1B/GP4[4] 173 N2 I/O IPD AXR1[3]/EQEP1A/GP4[3] 174 P1 I/O IPD AXR1[2]/GP4[2] 175 P2 I/O IPD AXR1[1]/GP4[1] 176 R2 I/O IPD AXR1[0]/GP4[0] 1 T3 I/O IPD AHCLKX1/EPWM0B/GP3[14] 160 K2 I/O IPD eHRPWM0, GPIO McASP1 transmit master clock. ACLKX1/EPWM0A/GP3[15] 162 K3 I/O IPD eHRPWM0, GPIO McASP1 transmit bit clock. AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 K4 I/O IPD eHRPWM0, GPIO McASP1 transmit frame sync. - L1 I/O IPD GPIO McASP1 receive master clock. ACLKR1/ECAP2/APWM2/GP4[12] 165 L2 I/O IPD eCAP2, GPIO McASP1 receive bit clock. AFSR1/GP4[13] 166 L3 I/O IPD GPIO McASP1 receive frame sync. IPD eHRPWM0, eHRPWM1, GPIO, eHRPWM2 McASP1 mute output. AHCLKR1/GP4[11] AMUTE1/EPWMTZ/GP4[14] 30 Device Overview 132 D4 O McASP1 serial data. eQEP, GPIO GPIO Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.6.14 Ethernet Media Access Controller (EMAC) Table 3-17. Ethernet Media Access Controller (EMAC) Terminal Functions SIGNAL NAME PIN NO PTP ZKB TYPE (1) PULL (2) MUXED DESCRIPTION RMII 129 A4 I/O IPD AXR0[6]/RMII_RXER/GP3[6] 118 D7 I IPD AXR0[5]/RMII_RXD[1]/GP3[5] 117 C7 I IPD AXR0[4]/RMII_RXD[0]/GP3[4] 116 B7 I IPD AXR0[3]/RMII_CRS_DV/GP3[3] 115 A7 I IPD AXR0[2]/RMII_TXEN/GP3[2] 113 D8 O IPD AXR0[1]/RMII_TXD[1]/GP3[1] 112 C8 O IPD AXR0[0]/RMII_TXD[0]/GP3[0] 111 B8 O EMAC 50-MHz clock input or output. McASP0, GPIO, BOOT IPD EMAC RMII receiver error. EMAC RMII receive data. EMAC RMII carrier sense data valid. McASP0, GPIO EMAC RMII transmit enable. EMAC RMII trasmit data. MDIO AXR0[8]/MDIO_D/GP3[8] 121 B6 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] 120 A6 O IPD (1) (2) McASP0, GPIO MDIO data clock. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.15 Multimedia Card/Secure Digital (MMC/SD) Table 3-18. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions PIN NO TYPE (1) PULL (2) R9 O IPU P9 I/O IPU 54 M15 I/O IPU EMA_D[6]/MMCSD_DAT[6]/GP0[6] 52 N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/GP0[5] 51 N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/GP0[4] 49 P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/GP0[3] 48 P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/GP0[2] 46 R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/GP0[1] 45 R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU SIGNAL NAME PTP ZKB EMA_A[1]/MMCSD_CLK/GP1[1] 30 EMA_A[2]/MMCSD_CMD/GP1[2] 31 EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] (1) (2) MUXED DESCRIPTION MMCSD_CLK. EMIFA, GPIO MMCSD_CMD. EMIFA, GPIO, BOOT EMIFA, GPIO MMC/SD data. EMIFA, GPIO, BOOT I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Submit Documentation Feedback Device Overview 31 ADVANCE INFORMATION AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 3.6.16 General-Purpose IO Only Terminal Functions Table 3-19. General-Purpose IO Only Terminal Functions PIN NO TYPE (1) PULL (2) M16 I/O/Z IPD - N14 I/O/Z IPD - N16 I/O/Z IPD GP0[12] - P14 I/O/Z IPD GP0[11] - P16 I/O/Z IPD GP0[10] - R14 I/O/Z IPD GP0[9] - T14 I/O/Z IPD GP0[8] - N12 I/O/Z IPD GP5[11] 6 - I/O/Z IPD GP5[10] 4 - I/O/Z IPD GP7[14] 157 K1 I/O IPU SIGNAL NAME PTP ZKB GP0[15] - GP0[14] GP0[13] ADVANCE INFORMATION (1) (2) MUXED DESCRIPTION General-Purpose IO None I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.17 Reserved Table 3-20. Reserved Terminal Functions SIGNAL NAME PIN NO TYPE (1) DESCRIPTION PTP ZKB RSV1 - F7 PWR Reserved. (Leave unconnected, do not connect to power or ground.) RSV2 133 B1 PWR Reserved. For proper device operation, this pin must be tied directly to CVDD. RSV3 149 - PWR Reserved. For proper device operation, this pin must be tied directly to CVDD. RSV4 148 - PWR Reserved. For proper operation, this pin must be tied low. H1 I Reserved. For proper operation, this pin must be tied low. RSV5 (1) PWR = Supply voltage. 32 Device Overview Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 3.6.18 Supply and Ground Table 3-21. Supply and Ground Terminal Functions PIN NO SIGNAL NAME PTP CVDD (Core supply) 10, 20, 28, 38, 50, 56, 61, 69, 77, 93, 104, 114, 147, 154, 161, 167, RVDD (Internal RAM supply) 67, 159 DVDD (I/O supply) (1) F6,G6, G7, G10, G11, H7, H10, H11, J6, J7, J10, J11, J12, K6, K7, K10, K11,L6,G1 TYPE (1) DESCRIPTION PWR 1.2-V core supply voltage pins H6, H12 PWR 1.2V internal ram supply voltage pins 5, 15, 24, 33, 43, 47, 53, 58, 65, 71, 75, 81, 87, 90, 99, 109, 119, 128, 151, 158, 164, 172, B16, E5, E8, E9, E12, F5, F11, F12, G5, G12, K5, K12, L5, L11, L12, M5, M8, M9, M12, R1, R16 PWR 3.3-V I/O supply voltage pins. 177 A1, A2, A15, A16, B2, E6, E7, E10, E11, F8, F9, F10, G8, G9, H8, H9, J8, J9, K8, K9, L7, L8, L9, L10, M6, M7, M10, M11, T1, T2, T15, T16,G2 GND Ground pins. ADVANCE INFORMATION VSS (Ground) ZKB PWR = Supply voltage, GND - Ground. Submit Documentation Feedback Device Overview 33 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 4 Device Configuration 4.1 SYSCFG Module ADVANCE INFORMATION The following system level features of the chip are controlled by the SYSCFG peripheral: · Readable Device, Die, and Chip Revision ID · Control of Pin Multiplexing · Priority of bus accesses different bus masters in the system · Capture at power on reset the chip BOOT[15:0] pin values and make them available to software · Special case settings for peripherals: ­ Locking of PLL controller settings ­ Default burst sizes for EDMA3 TC0 and TC1 ­ Selection of the source for the eCAP module input capture (including on chip sources) ­ McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals ­ Clock source selection for EMIFA and EMIFB · Selects the source of emulation suspend signal (from DSP) of peripherals supporting this function. Since the SYSCFG peripheral controls global operation of the device, its registers are protected against erroneous accesses by several mechanisms: · A special key sequence must be written to KICK0, KICK1 registers before any other registers are writeable. · Additionally, many registers are accessible only by a host (DSP) when it is operating in its privileged mode. (ex. from the kernel, but not from user space code). 34 Device Configuration Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 Table 4-1. System Configuration (SYSCFG) Module Register Access BYTE ADDRESS ACRONYM REGISTER DESCRIPTION ACCESS 0x01C1 4000 REVID Revision Identification Register - 0x01C1 4008 DIEIDR0 Device Identification Register 0 - 0x01C1 400C DIEIDR1 Device Identification Register 1 - 0x01C1 4010 DIEIDR2 Device Identification Register 2 - 0x01C1 4014 DIEIDR3 Device Identification Register 3 - 0x01C1 4018 DEVIDR0 Device Identification Register 0 - 0x01C1 4020 BOOTCFG Boot Configuration Register Privileged mode 0x01C1 4038 KICK0R Kick 0 Register Privileged mode KICK1R Kick 1 Register Privileged mode 0x01C1 4040 HOST0CFG Host 0 Configuration Register - 0x01C1 4044 HOST1CFG Host 1 Configuration Register - 0x01C1 40E0 IRAWSTAT Interrupt Raw Status/Set Register Privileged mode 0x01C1 40E4 IENSTAT Interrupt Enable Status/Clear Register Privileged mode 0x01C1 40E8 IENSET Interrupt Enable Register Privileged mode 0x01C1 40EC IENCLR Interrupt Enable Clear Register Privileged mode 0x01C1 40F0 EOI End of Interrupt Register Privileged mode 0x01C1 40F4 FLTADDRR Fault Address Register Privileged mode 0x01C1 40F8 FLTSTAT Fault Status Register - 0x01C1 4110 MSTPRI0 Master Priority 0 Register Privileged mode 0x01C1 4114 MSTPRI1 Master Priority 1 Register Privileged mode 0x01C1 4118 MSTPRI2 Master Priority 2 Register Privileged mode 0x01C1 4120 PINMUX0 Pin Multiplexing Control 0 Register Privileged mode 0x01C1 4124 PINMUX1 Pin Multiplexing Control 1 Register Privileged mode 0x01C1 4128 PINMUX2 Pin Multiplexing Control 2 Register Privileged mode 0x01C1 412C PINMUX3 Pin Multiplexing Control 3 Register Privileged mode 0x01C1 4130 PINMUX4 Pin Multiplexing Control 4 Register Privileged mode 0x01C1 4134 PINMUX5 Pin Multiplexing Control 5 Register Privileged mode 0x01C1 4138 PINMUX6 Pin Multiplexing Control 6 Register Privileged mode 0x01C1 413C PINMUX7 Pin Multiplexing Control 7 Register Privileged mode 0x01C1 4140 PINMUX8 Pin Multiplexing Control 8 Register Privileged mode 0x01C1 4144 PINMUX9 Pin Multiplexing Control 9 Register Privileged mode 0x01C1 4148 PINMUX10 PINMUX10 Pin Multiplexing Control 10 Register Privileged mode 0x01C1 414C PINMUX11 PINMUX11 Pin Multiplexing Control 11 Register Privileged mode 0x01C1 4150 PINMUX12 PINMUX12 Pin Multiplexing Control 12 Register Privileged mode 0x01C1 4154 PINMUX13 PINMUX13 Pin Multiplexing Control 13 Register Privileged mode 0x01C1 4158 PINMUX14 PINMUX14 Pin Multiplexing Control 14 Register Privileged mode 0x01C1 415C PINMUX15 PINMUX15 Pin Multiplexing Control 15 Register Privileged mode 0x01C1 4160 PINMUX16 PINMUX16 Pin Multiplexing Control 16 Register Privileged mode 0x01C1 4164 PINMUX17 PINMUX17 Pin Multiplexing Control 17 Register Privileged mode 0x01C1 4168 PINMUX18 PINMUX18 Pin Multiplexing Control 18 Register Privileged mode 0x01C1 416C PINMUX19 PINMUX19 Pin Multiplexing Control 19 Register Privileged mode 0x01C1 4170 SUSPSRC Suspend Source Register Privileged mode 0x01C1 4174 CHIPSIG Chip Signal Register - 0x01C1 4178 CHIPSIG_CLR Chip Signal Clear Register - 0x01C1 417C CFGCHIP0 Chip Configuration 0 Register Privileged mode 0x01C1 4180 CFGCHIP1 Chip Configuration 1 Register Privileged mode 0x01C1 4184 CFGCHIP2 Chip Configuration 2 Register ADVANCE INFORMATION 0x01C1 403C Privileged mode Submit Documentation Feedback Device Configuration 35 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Table 4-1. System Configuration (SYSCFG) Module Register Access (continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION ACCESS 0x01C1 4188 CFGCHIP3 Chip Configuration 3 Register Privileged mode 0x01C1 418C CFGCHIP4 Chip Configuration 4 Register Privileged mode ADVANCE INFORMATION 36 Device Configuration Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 5 Device Operating Conditions 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted) (1) -0.5 V to 1.4 V (2) I/O, 3.3V (DVDD) (2) -0.5 V to 3.8V VI I/O, 1.2V (OSCIN) Input voltage ranges -0.3 V to CVDD + 0.3V VI I/O, 3.3V (Steady State) -0.3V to DVDD + 0.3V VI I/O, 3.3V (Transient Overshoot/Undershoot) Output voltage ranges Clamp Current 20% of DVDD for up to 20% of the signal period VO I/O, 3.3V (Steady State) -0.5 V to DVDD + 0.3V VO I/O, 3.3V (Transient Overshoot/Undershoot ) 20% of DVDD for up to 20% of the signal period ±20mA Input or Output Voltages 0.3V above or below their respective power rails. Limit clamp current that flows through the I/O's internal diode protection cells. Operating Junction Temperature ranges, TJ (default) (T version) -40°C to 125°C Storage temperature range, Tstg (default) -55°C to 150°C (1) (2) 0°C to 90°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS Submit Documentation Feedback Device Operating Conditions 37 ADVANCE INFORMATION Supply voltage ranges Core (CVDD, RVDD, PLL0_VDDA ) TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 5.2 Recommended Operating Conditions MIN NOM MAX UNIT 1.14 1.2 or 1.26 1.32 V CVDD Supply voltage, Core (CVDD, PLL0_VDDA ) RVDD Supply Voltage, Internal RAM 1.14 1.2 or 1.26 1.32 V DVDD Supply voltage, I/O, 3.3V (DVDD) 3.15 3.3 3.45 V VSS Supply ground (VSS, PLL0_VSSA, OSCVSS (2) 0 0 0 V (1) High-level input voltage, I/O, 3.3V VIH 2 High-level input voltage, OSCIN Low-level input voltage, I/O, 3.3V VIL V TBD V 0.8 ADVANCE INFORMATION Low-level input voltage, OSCIN V Operating junction temperature range FSYSCLK1,6 DSP Operating Frequency (SYSCLK1,6) ns 0 70 °C -40 105 °C 0 300 or 200 MHz Automotive (T suffix) 0 300 or 200 MHz Transition time, 10%-90%, All Inputs TJ V 10 Default tt TBD Default (1) (2) 38 Automotive (T suffix) Future variants of TI devices may operate at CVDD voltages ranging from 1.0 V to 1.32 V to provide a range of system power/ performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.1 V, 1.2, 1.26 V with ±5% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI devices. RVDD and PLL0_VDDA must always be maintained at the voltages shown. (1.14 V - 1.32 V). When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground. Device Operating Conditions Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted) VOH VOL High-level output voltage (3.3V I/O) TEST CONDITIONS DVDD = 3.15V, IOH = -4 mA DVDD = 3.15V, IOH = -100 µA MIN TYP MAX UNIT 2.4 V 2.95 V 0.4 V DVDD = 3.15V, IOL = -100 µA 0.2 V VI = VSS to DVDD without opposing internal resistor Low-level output voltage (3.3V I/O) DVDD = 3.15V, IOL = 4mA ±35 µA (1) Input current VI = VSS to DVDD with opposing internal pullup resistor (2) 30 200 µA VI = VSS to DVDD with opposing internal pulldown resistor (2) II -50 -250 µA IOH High-level output current All peripherals -4 mA IOL Low-level output current All peripherals 4 mA (1) (2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current. Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. Submit Documentation Feedback Device Operating Conditions 39 ADVANCE INFORMATION PARAMETER TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 6 Peripheral Information and Electrical Specifications 6.1 Parameter Information 6.1.1 Parameter Information Device-Specific Information Tester Pin Electronics 42 3.5 nH Transmission Line ADVANCE INFORMATION Z0 = 50 (see note) 4.0 pF A. 1.85 pF Data Sheet Timing Reference Point Output Under Test Device Pin (see note) The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 6-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 6.1.1.1 Signal Transition Levels All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O, Vref = 1.65 V. Vref Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels 40 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 6.2 Recommended Clock and Control Signal Transition Behavior ADVANCE INFORMATION All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. Submit Documentation Feedback Peripheral Information and Electrical Specifications 41 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com 6.3 Power Supplies 6.3.1 Power-on Sequence 647x devices include on chip logic that ensures I/O pins are tri-stated during the power on ramp, as long as the RESET pin is asserted. This is true even if the core voltage (CVDD) has not yet ramped. Normally, the only requirement during the power on ramp is that both the RESET and TRST pins remain asserted (low) until after the power supply rails have fully ramped. 6.4 Reset 6.4.1 Power-On Reset (POR) ADVANCE INFORMATION A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset. A summary of the effects of Power-On Reset is given below: · All internal logic (including emulation logic and the PLL logic) is reset to its default state · Internal memory is not maintained through a POR · RESETOUT goes active · All device pins go to a high-impedance state A watchdog reset triggers a POR. 6.4.2 Warm Reset A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low (TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset. During emulation, the emulator will maintain TRST high so only warm reset (not POR) is available during emulation debug and development. A summary of the effects of Warm Reset is given below: · All internal logic (except for the emulation logic and the PLL logic) is reset to its default state · Internal memory is maintained through a warm reset · RESETOUT goes active · All device pins go to a high-impedance state 42 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com 6.4.3 SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 Reset Electrical Data Timings Table 6-1 assumes testing over the recommended operating conditions. Table 6-1. Reset Timing Requirements ( (1), (2) ) NO MIN MAX UNIT 1 tw(RSTL) Pulse width, RESET/TRST low 100 ns 2 tsu(BPV-RSTH) Setup time, boot pins valid before RESET/TRST high 20 ns 3 th(RSTH-BPV) Hold time, boot pins valid after RESET/TRST high 20 4 td(RSTH-RESETOUTH) RESET high to RESETOUT high; Warm reset 4096 RESET high to RESETOUT high; Power-on Reset 6192 5 td(RSTL-RESETOUTL) (3) TBD ns ADVANCE INFORMATION (1) (2) Delay time, RESET/TRST low to RESETOUT low ns cycles (3) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-4 for details. For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this table refer to RESET only (TRST is held high). OSCIN cycles. Power Supplies Ramping Power Supplies Stable Clock Source Stable OSCIN 1 RESET TRST 4 RESETOUT 3 2 Boot Pins Config Figure 6-4. Power-On Reset (RESET and TRST active) Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 43 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Power Supplies Stable OSCIN TRST 1 RESET 5 4 ADVANCE INFORMATION RESETOUT 3 2 Boot Pins Driven or Hi-Z Config Figure 6-5. Warm Reset (RESET active, TRST high) Timing 44 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 6.5 Crystal Oscillator or External Clock Input The device includes two choices to provide an external clock input, which is fed to the on-chip PLL to generate high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended. Typical C1, C2 values are 10-20 pF. · Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit. · Figure 6-7 illustrates the option that uses an external 1.2V clock input. OSCIN Clock Input to PLL ADVANCE INFORMATION C2 X1 OSCOUT C1 OSCVSS Figure 6-6. On-Chip 1.2V Oscillator Table 6-2. Oscillator Timing Requirements NO fosc PARAMETER MIN OSCIN NC MAX UNIT 12 30 MHz MIN MAX UNIT 12 Oscillator frequency range (OSCIN/OSCOUT) 50 MHz Clock Input to PLL OSCOUT OSCVSS Figure 6-7. External 1.2V Clock Source Table 6-3. CLKIN Timing Requirements NO PARAMETER fCLKIN CLKIN frequency range (OSCIN) tc(CLKIN) Cycle time, external clock driven on OSCIN 20 ns tw(CLKINH) Pulse width high, external clock on OSCIN 0.4 ns tc(CLKIN) Submit Documentation Feedback Peripheral Information and Electrical Specifications 45 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 www.ti.com Table 6-3. CLKIN Timing Requirements (continued) NO PARAMETER tw(CLKINL) MIN Pulse width low, external clock on OSCIN MAX 0.4 UNIT ns tc(CLKIN) tt(CLKIN) Transition time, CLKIN 5 ns 6.6 Clock PLLs The device has one PLL controller that provides clock to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device. ADVANCE INFORMATION The PLL controller provides the following: · Glitch-Free Transitions (on changing clock settings) · Domain Clocks Alignment · Clock Gating · PLL power down The various clock outputs given by the controller are as follows: · Domain Clocks: SYSCLK [1:n] · Auxiliary Clock from reference clock source: AUXCLK Various dividers that can be used are as follows: · Post-PLL Divider: POSTDIV · SYSCLK Divider: D1, , Dn Various other controls supported are as follows: · PLL Multiplier Control: PLLM · Software programmable PLL Bypass: PLLEN 6.6.1 PLL Device-Specific Information The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL. The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8. 1.14V - 1.32V 50R PLL0_VDDA 0.1 µF VSS 50R 0.01 µF PLL0_VSSA Ferrite Bead: Murata BLM31PG500SN1L BLM31PG500SN1L or Equivalent Figure 6-8. PLL External Filtering Components The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the CLKIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 6-9 illustrates the PLL Topology. The PLL is disabled by default after a device reset. It must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the DSP to run from the PLL by setting PLLEN = 1. 46 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor www.ti.com SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 DIV4p5 (/4.5) PLLREF PREDIV (/1 to /32) PLLOUT PLLM (x4 to x32) POSTDIV (/2 to /32) 1 SYSCLK2 PLLDIV3 (/1, /2, . /32) SYSCLK3 PLLDIV4 (/1, /2, . /32) SYSCLK4 PLLDIV7 (/1, /2, . /32) PLLEN (PLL_CSR[0]) SYSCLK1 PLLDIV2 (/1, /2, . /32) 0 PLLDIV1 (/1, /2, . /32) SYSCLK7 ADVANCE INFORMATION Clock Input from CLKIN or OSCIN AUXCLK Figure 6-9. PLL Topology Table 6-4. Allowed PLL Operating Conditions NO PARAMETER Default Value MIN MAX UNIT 1 PLLRST: Assertion time during initialization N/A 125 N/A ns 2 Lock time: The time that the application has to wait for the PLL to acquire locks before setting PLLEN, after changing PREDIV, PLLM, or OSCIN N/A N/A 3 PREDIV /1 /1 /32 ns 4 PLL input frequency ( PLLREF) 12 50 MHz 2000 N m where N = Pre-Divider Ratio M = PLL Multiplier Max PLL Lock Time = ns 5 PLL multiplier values (PLLM) x20 x4 x32 6 PLL output frequency. ( PLLOUT ) N/A 400 600 (1) MHz /32 ns 7 (1) POSTDIV /1 /2 (1) PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL output clock. Submit Documentation Feedback Peripheral Information and Electrical Specifications 47 TMS320C6743 TMS320C6743 Fixed/Floating-point Digital Signal Processor SPRS565A SPRS565A ­ APRIL 2009 ­ REVISED APRIL 2009 6.6.2 www.ti.com Device Clock Generation PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock alignment, and test points. PLLC0 generates several clocks from the PLL0 output clock for use by the various modules. These are summarized in Table 6-5. The clock ratios between SYSCLK1, SYSCLK2, SYSCLK4 and SYSCLK6 must always be maintained as shown in the table. Table 6-5. System PLLC0 Output Clocks ADVANCE INFORMATION OUTPUT CLOCK USED BY DEFAULT RATIO (RELATIVE TO SYSCLK1) NOTES SYSCLK1 DSP /1 No Required Ratio SYSCLK2 EDMA, DSP ports, EMIFB (ports to switch fabric), ECAP 0/1/2, EPWM 0/1/2, EQEP 0/1, McASP/FIFO 0/1, UART 2, HRPWM 0/1/2 /2 SYSCLK1 / 2 SYSCLK3 EMIFA /3 No Required Ratio SYSCLK4 SYSCFG, Interrupt Controller, PLLC0, PSC 0, EMAC/MDIO, GPIO, I2C 1, PSC 1 /4 SYSCLK1 / 4 SYSCLK5 EMIFB /3 No Required Ratio SYSCLK7 RMII clock to EMAC /6 No Required Ratio ; Should be set to 50 MHz AUXCLK McASP AuxClk, Timer64P0,Timer64P1 N/A No Required Ratio DIV4p5 133MHz clock source for EMIFB PLL output/4.5 No Required Ratio · · · 6.6.3 The divide values in the PLL Controller 0 for SYSCLK1/SYSCLK6, SYSCLK2 and SYSCLK4 are not fixed so that user can change the divide values for power saving reasons. But users are responsible to guarantee that the divide ratios between these clock domains must be fixed to 1:2:4. Although the PLL is capable of running at 600 MHz, the SYSCLK dividers in the PLLC0 are not (maximum 400 MHz). For this reason, the post-divider