TMS320C6713 SPRS186 MIPS/1350 IEC60958-1 IEEE-1149 208-PIN 256-PIN C6713 - Datasheet Archive

 

FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 ­ DECEMBER 2001 D D D D D D Signal Processor (DSP): TMS320C6713 ­ Eight

 

TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 D D D D D D Signal Processor (DSP): TMS320C6713 TMS320C6713 ­ Eight 32-Bit Instructions/Cycle ­ 32/64-Bit Data Word ­ 225-, 150-MHz Clock Rate ­ 4.4-, 6.7-ns Instruction Cycle Time ­ 1800 MIPS/1350 MIPS/1350 MFLOPS, 1200 MIPS /900 MFLOPS ­ Rich Peripheral Set, Optimized for Audio VelociTI Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core ­ Eight Independent Functional Units: ­ Two ALUs (Fixed-Point) ­ Four ALUs (Floating- and Fixed-Point) ­ Two Multipliers (Floating- and Fixed-Point) ­ Load-Store Architecture With 32 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional Instruction Set Features ­ Native Instructions for IEEE 754 ­ Single- and Double-Precision ­ Byte-Addressable (8-, 16-, 32-Bit Data) ­ 8-Bit Overflow Protection ­ Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture ­ 4K-Byte L1P Program Cache (Direct-Mapped) ­ 4K-Byte L1D Data Cache (2-Way) ­ 256K-Byte L2 Memory, With 64K-Byte L2 Unified Cache/Mapped RAM ­ 192K-Byte Additional L2 Mapped RAM Device Configuration ­ Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot ­ Endianness: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) ­ Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM ­ 512M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) D 16-Bit Host-Port Interface (HPI) D Two Multichannel Audio Serial Ports D D D D D D D D D (McASPs) ­ Two Independent Clock Zones Each (1 TX and 1 RX) ­ Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones ­ Each Clock Zone Includes: ­ Programmable Clock Generator ­ Programmable Frame Sync Generator ­ TDM Streams From 2-32 Time Slots ­ Support for Slot Size: 8, 12, 16, 20, 24, 28, 32 Bits ­ Data Formatter for Bit Manipulation ­ Wide Variety of I2S and Similar Bit Stream Formats ­ Integrated Digital Audio Interface Transmitter (DIT) Supports: ­ S/PDIF, IEC60958-1 IEC60958-1, AES-3 Formats ­ Up to 16 transmit pins ­ Enhanced Channel Status/User Data RAM ­ Extensive Error Checking and Recovery Two Inter-Integrated Circuit (I2C) Buses Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports (McBSPs): ­ Serial-Peripheral-Interface (SPI) ­ High-Speed TDM Interface ­ AC97 Interface Two 32-Bit General-Purpose Timers One Dedicated General-Purpose Input/Output Module With 16 pins Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149 IEEE-1149.1 (JTAG) Boundary-Scan-Compatible Package Options: ­ 208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP) ­ 256-Pin Ball Grid Array Package (GFN) 0.13-µm/6-Level Metal Process ­ CMOS Technology 3.3-V I/Os, 1.2-V Internal PRODUCT PREVIEW D Highest-Performance Floating-Point Digital Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x, VelociTI, and PowerPAD are trademarks of Texas Instruments. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 2001, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 1 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 Table of Contents PRODUCT PREVIEW PYP PowerPAD QFP package (top view) . . . . . . . . . . . . . . 3 GFN BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional block and CPU (DSP core) diagram . . . . . . . . . . . 6 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 7 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 11 PWRD bits in CPU CSR register description . . . . . . . . . . . 19 interrupts and interrupt selector . . . . . . . . . . . . . . . . . . . . . . . 20 EDMA module and EDMA selector . . . . . . . . . . . . . . . . . . . . 21 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 clock generator, oscillator, and PLL . . . . . . . . . . . . . . . . . . . 61 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 recommended operating conditions . . . . . . . . . . . . . . . . . . . 67 2 POST OFFICE BOX 1443 electrical characteristics over recommended ranges of supply voltage and operating case temperature . 68 parameter measurement information . . . . . . . . . . . . . . . 69 signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timing parameters and board routing analysis . . . . . . . 70 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 75 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 78 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 80 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 90 multichannel audio serial port (McASP) timing . . . . . . . 91 inter-integrated circuits (I2C) timing . . . . . . . . . . . . . . . . 94 host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 95 multichannel buffered serial port timing . . . . . . . . . . . . . 98 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 general-purpose input/output (GPIO) port timing . . . . 110 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 PYP PowerPAD QFP package (top view) PYP 208-PIN 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP) ( TOP VIEW ) 156 105 104 208 53 1 PRODUCT PREVIEW 157 52 GFN BGA package (bottom view) GFN 256-PIN 256-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) Y W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 POST OFFICE BOX 1443 11 10 13 12 15 14 17 16 19 18 20 · HOUSTON, TEXAS 77251­1443 3 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 description The TMS320C67xt DSPs (including the TMS320C6713 TMS320C6713 device) compose the floating­point DSP generation in the TMS320C6000t DSP platform. The TMS320C6713 TMS320C6713 (C6713 C6713) device is based on the high-performance, advanced VelociTIt very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Operating at 225 MHz, the C6713 C6713 delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). The C6713 C6713 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-Byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-Byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-Byte memory space that is shared between program and data space. 64K Bytes of the 256K Bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K Bytes in L2 serves as mapped SRAM. PRODUCT PREVIEW The C6713 C6713 has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713 C6713 has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958 IEC60958, AES-3 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The two I2C ports on the TMS320C6713 TMS320C6713 allow the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. The TMS320C67x DSP generation is supported by the TI eXpressDSPt set of industry benchmark development tools, including a highly optimizing C/C+ Compiler, the Code Composer Studiot Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOSt kernel. TMS320C6000 TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments. 4 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 device characteristics Table 1 provides an overview of the C6713 C6713 DSP. The table shows significant features of the C6713 C6713 device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C67x DSP device part numbers and part numbering, see Table 32 and Figure 11. Table 1. Characteristics of the C6713 C6713 Processor C6713 C6713 (FLOATING-POINT DSP) HARDWARE FEATURES GFN EMIF PYP 1 (32 bit) 1 (16 bit) HPI (16 bit) 1 McASPs 2 I2Cs 2 McBSPs 2 32-Bit Timers 2 GPIO Modules Peripherals 1 1 Size (Bytes) On-Chip Memory Organization CPU ID+CPU Rev ID MHz 264K 4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified L2 Cache/Mapped RAM 192KB 192KB L2 Mapped RAM Control Status Register (CSR.[31:16]) Frequency Cycle Time 0x0203 225, 150 150 4.4 ns (C6713GFN-225 C6713GFN-225), 6.7 ns (C6713GFN-150 C6713GFN-150) ns 6.7 ns (C6713PYP-150 C6713PYP-150) Core (V) Voltage Clock Generator Options Process Technology 1.2 I/O (V) 3.3 Prescaler Multiplier Postscaler 27 x 27 mm Packages PRODUCT PREVIEW EDMA (16 Channels) 28 x 28 mm /1, /2, /3, ., /32 x1, x2, x3, ., x16 /1, /2, /3, ., /32 256-Pin BGA (GFN) ­ ­ 208-Pin PowerPAD PQFP (PYP) µm 0.13 Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) PP PP C67x is a trademark of Texas Instruments. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 5 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 functional block and CPU (DSP core) diagram C6713 C6713 Digital Signal Processor 32 EMIF L1P Cache Direct Mapped 4K Bytes Total L2 Cache/ Memory 4 Banks 64K Bytes Total McASP1 (up to 4-Way) McASP0 C67x CPU Instruction Fetch Control Registers Instruction Dispatch McBSP1 Data Path A PRODUCT PREVIEW Pin Multiplexing McBSP0 I2C1 I2C0 Timer 1 Data Path B A Register File Enhanced DMA Controller (16 channel) In-Circuit Emulation .D2 .M2 .S2 .L2 Interrupt Control L1D Cache 2-Way Set Associative 4K Bytes L2 Memory 192K Bytes Clock Generator, Oscillator, and PLL x1 through x16 Multipliers GPIO HPI In addition to fixed-point instructions, these functional units execute floating-point instructions. EMIF interfaces to: ­SDRAM ­SBSRAM ­SRAM, ­ROM/Flash, and ­I/O devices 6 McBSPs interface to: ­SPI Control Port ­High-Speed TDM Codecs ­AC97 Codecs ­Serial EEPROM POST OFFICE BOX 1443 Test B Register File .L1 .S1 .M1 .D1 Timer 0 16 Control Logic Instruction Decode McASPs interface to: ­I2S Multichannel ADC, DAC, Codec, DIR ­DIT: Multiple Outputs · HOUSTON, TEXAS 77251­1443 Power-Down Logic TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 CPU (DSP core) description The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 7 PRODUCT PREVIEW The TMS320C6713 TMS320C6713 floating-point digital signal processor is based on the C67x CPU. The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 CPU (DSP core) description (continued) ÁÁ Á Á ÁÁ Á ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁ ÁÁ Á ÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁ Á ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á Á Á ÁÁÁÁ Á ÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁ Á ÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁ Á ÁÁÁÁ Á .L1 src2 dst long dst long src LD1 32 MSB ST1 8 8 long src long dst dst .S1 src1 Data Path A 32 32 8 8 src2 dst src1 .M1 PRODUCT PREVIEW src2 LD1 32 LSB ÁÁ ÁÁ ÁÁ ÁÁ DA1 DA2 LD2 32 LSB .D1 .D2 dst src1 src2 1X src2 .M2 src1 dst src2 Data Path B LD2 32 MSB ST2 long src long dst dst .L2 src2 Register File B (B0­B15) 8 8 32 32 8 8 ÁÁ ÁÁ src1 In addition to fixed-point instructions, these functional units execute floating-point instructions. Figure 1. TMS320C67x CPU (DSP Core) Data Paths 8 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 Register File A (A0­A15) 2X src2 src1 dst src1 .S2 dst long dst long src Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ src1 Control Register File TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 memory map summary Table 2 shows the memory map address ranges of the C6713 C6713 device. Table 2. TMS320C6713 TMS320C6713 Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE Internal RAM (L2) 192K 0000 0000 ­ 0002 FFFF Internal RAM/Cache 64K 0003 0000 ­ 0003 FFFF Reserved 24M ­ 256K 0004 0000 ­ 017F FFFF External Memory Interface (EMIF) Registers 256K 0180 0000 ­ 0183 FFFF L2 Registers 128K 0184 0000 ­ 0185 FFFF Reserved 128K 0186 0000 ­ 0187 FFFF HPI Registers 256K 0188 0000 ­ 018B FFFF McBSP 0 Registers 256K 018C 0000 ­ 018F FFFF McBSP 1 Registers 256K 0190 0000 ­ 0193 FFFF Timer 0 Registers 256K 0194 0000 ­ 0197 FFFF Timer 1 Registers 256K 0198 0000 ­ 019B FFFF 019C 0000 ­ 019C 01FF 512 4 019C 0200 ­ 019C 0203 Reserved 256K ­ 516 019C 0204 ­ 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 ­ 01A3 FFFF Reserved 768K 01A4 0000 ­ 01AF FFFF GPIO Registers 16K 01B0 0000 ­ 01B0 3FFF Reserved 240K 01B0 4000 ­ 01B3 FFFF I2C0 Registers 16K 01B4 0000 ­ 01B4 3FFF I2C1 Registers 16K 01B4 4000 ­ 01B4 7FFF Reserved 16K 01B4 8000 ­ 01B4 BFFF McASP0 Registers 16K 01B4 C000 ­ 01B4 FFFF McASP1 Registers 16K 01B5 0000 ­ 01B5 3FFF Reserved 160K 01B5 4000 ­ 01B7 BFFF PLL Registers 8K 01B7 C000 ­ 01B7 DFFF Reserved 4M + 520K 01B7 E000 ­ 01FF FFFF QDMA Registers 52 0200 0000 ­ 0200 0033 Reserved 16M ­ 52 PRODUCT PREVIEW Interrupt Selector Registers Device Configuration Registers 0200 0034 ­ 02FF FFFF Reserved 720M 0300 0000 ­ 2FFF FFFF McBSP0 Data 64M 3000 0000 ­ 33FF FFFF McBSP1 Data 64M 3400 0000 ­ 37FF FFFF Reserved 64M 3800 0000 ­ 3BFF FFFF McASP0 Data 1M 3C00 0000 ­ 3C0F FFFF McASP1 Data 1M 3C10 0000 ­ 3C1F FFFF Reserved EMIF CE0 1G + 62M 3C20 0000 ­ 7FFF FFFF 256M 8000 0000 ­ 8FFF FFFF EMIF CE1 EMIF CE2 256M 9000 0000 ­ 9FFF FFFF 256M A000 0000 ­ AFFF FFFF EMIF CE3 256M B000 0000 ­ BFFF FFFF Reserved 1G C000 0000 ­ FFFF FFFF The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB 128MB per CE space. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 9 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 L2 memory structure expanded Figure 2 shows the detail of the L2 memory structure. L2 Mode 000 001 010 L2 Memory 011 Block Base Address 111 192K SRAM 208K SRAM 224K SRAM 240KSRAM 240KSRAM 256K SRAM (All) PRODUCT PREVIEW 0x0000 0000 192 K Bytes 0x0003 0000 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ 64K 4-Way Cache 48K 3-Way Cache 32K 2-Way Cache 16K 1-Way Cache 16 K Bytes 0x0003 4000 16 K Bytes 0x0003 8000 16 K Bytes 0x0003 C000 16 K Bytes 0x0003 FFFF Figure 2. L2 Memory Configuration 10 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions Table 3 through Table 13 identify the peripheral registers for the C6713 C6713 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the TMS320C6000 TMS320C6000 Peripherals Reference Guide (literature number SPRU190 SPRU190). Table 3. EMIF Registers HEX ADDRESS RANGE ACRONYM 0180 0000 GBLCTL EMIF global control REGISTER NAME 0180 0004 CECTL1 EMIF CE1 space control 0180 0008 CECTL0 EMIF CE0 space control 0180 000C ­ 0180 0010 CECTL2 EMIF CE2 space control 0180 0014 CECTL3 EMIF CE3 space control 0180 0018 SDCTL EMIF SDRAM control 0180 001C SDTIM EMIF SDRAM refresh control 0180 0020 SDEXT EMIF SDRAM extension 0180 0024 ­ 0183 FFFF ­ Reserved PRODUCT PREVIEW Reserved Table 4. L2 Cache Registers HEX ADDRESS RANGE ACRONYM 0184 0000 CCFG REGISTER NAME 0184 4000 L2FBAR L2 flush base address register 0184 4004 L2FWC L2 flush word count register 0184 4010 L2CBAR L2 clean base address register 0184 4014 L2CWC L2 clean word count register 0184 4020 L1PFBAR L1P flush base address register 0184 4024 L1PFWC L1P flush word count register 0184 4030 L1DFBAR L1D flush base address register 0184 4034 L1DFWC L1D flush word count register 0184 5000 L2FLUSH L2 flush register 0184 5004 L2CLEAN L2 clean register 0184 8200 MAR0 Controls CE0 range 8000 0000 ­ 80FF FFFF 0184 8204 MAR1 Controls CE0 range 8100 0000 ­ 81FF FFFF Cache configuration register 0184 8208 MAR2 Controls CE0 range 8200 0000 ­ 82FF FFFF 0184 820C MAR3 Controls CE0 range 8300 0000 ­ 83FF FFFF 0184 8240 MAR4 Controls CE1 range 9000 0000 ­ 90FF FFFF 0184 8244 MAR5 Controls CE1 range 9100 0000 ­ 91FF FFFF 0184 8248 MAR6 Controls CE1 range 9200 0000 ­ 92FF FFFF 0184 824C MAR7 Controls CE1 range 9300 0000 ­ 93FF FFFF 0184 8280 MAR8 Controls CE2 range A000 0000 ­ A0FF FFFF 0184 8284 MAR9 Controls CE2 range A100 0000 ­ A1FF FFFF 0184 8288 MAR10 MAR10 Controls CE2 range A200 0000 ­ A2FF FFFF 0184 828C MAR11 MAR11 Controls CE2 range A300 0000 ­ A3FF FFFF 0184 82C0 MAR12 MAR12 Controls CE3 range B000 0000 ­ B0FF FFFF 0184 82C4 MAR13 MAR13 Controls CE3 range B100 0000 ­ B1FF FFFF 0184 82C8 MAR14 MAR14 Controls CE3 range B200 0000 ­ B2FF FFFF 0184 82CC MAR15 MAR15 Controls CE3 range B300 0000 ­ B3FF FFFF 0184 82D0 ­ 0185 FFFF ­ Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 11 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions (continued) Table 5. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10­15 (INT10 INT10­INT15 INT15) 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4­9 (INT04 INT04­INT09 INT09) 019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts (EXT_INT4­EXT_INT7) 019C 000C ­ 019F FFFF ­ Reserved Table 6. EDMA Parameter RAM ACRONYM 01A0 0000 ­ 01A0 0017 ­ Parameters for Event 0 (6 words) 01A0 0018 ­ 01A0 002F ­ Parameters for Event 1 (6 words) 01A0 0030 ­ 01A0 0047 PRODUCT PREVIEW HEX ADDRESS RANGE REGISTER NAME ­ Parameters for Event 2 (6 words) 01A0 0048 ­ 01A0 005F ­ Parameters for Event 3 (6 words) 01A0 0060 ­ 01A0 0077 ­ Parameters for Event 4 (6 words) 01A0 0078 ­ 01A0 008F ­ Parameters for Event 5 (6 words) 01A0 0090 ­ 01A0 00A7 ­ Parameters for Event 6 (6 words) 01A0 00A8 ­ 01A0 00BF ­ Parameters for Event 7 (6 words) 01A0 00C0 ­ 01A0 00D7 ­ Parameters for Event 8 (6 words) 01A0 00D8 ­ 01A0 00EF ­ Parameters for Event 9 (6 words) 01A0 00F0 ­ 01A0 00107 ­ Parameters for Event 10 (6 words) 01A0 0108 ­ 01A0 011F ­ Parameters for Event 11 (6 words) 01A0 0120 ­ 01A0 0137 ­ Parameters for Event 12 (6 words) 01A0 0138 ­ 01A0 014F ­ Parameters for Event 13 (6 words) 01A0 0150 ­ 01A0 0167 ­ Parameters for Event 14 (6 words) 01A0 0168 ­ 01A0 017F ­ Parameters for Event 15 (6 words) 01A0 0180 ­ 01A0 0197 ­ Reload/link parameters for Event M (6 words) 01A0 0198 ­ 01A0 01AF ­ Reload/link parameters for Event N (6 words) . . 01A0 07E0 ­ 01A0 07F7 ­ 01A0 07F8 ­ 01A0 07FF ­ Reload/link parameters for Event Z (6 words) Scratch pad area (2 words) The C6211/C6211B C6211/C6211B device has sixty-nine parameter sets [six (6) words each] that can be used to reload/link EDMA transfers. 12 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions (continued) Table 7. EDMA Registers HEX ADDRESS RANGE ACRONYM 01A0 0800 ­ 01A0 FEFC ­ REGISTER NAME 01A0 FF00 ESEL0 EDMA event selector 0 01A0 FF04 ESEL1 EDMA event selector 1 01A0 FF08 ­ 01A0 FF0C ESEL3 01A0 FF1F ­ 01A0 FFDC ­ 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPR Channel interrupt pending register 01A0 FFE8 CIER Channel interrupt enable register 01A0 FFEC CCER Channel chain enable register Reserved Reserved EDMA event selector 3 Reserved ER 01A0 FFF4 EER Event register Event enable register 01A0 FFF8 ECR Event clear register 01A0 FFFC ESR Event set register 01A1 0000 ­ 01A3 FFFF ­ PRODUCT PREVIEW 01A0 FFF0 Reserved Table 8. Quick DMA (QDMA) and Pseudo Registers HEX ADDRESS RANGE ACRONYM 0200 0000 QOPT QDMA options parameter register REGISTER NAME 0200 0004 QSRC QDMA source address register 0200 0008 QCNT QDMA frame count register 0200 000C QDST QDMA destination address register 0200 0010 QIDX QDMA index register 0200 0014 ­ 0200 001C ­ 0200 0020 QSOPT QDMA pseudo options register 0200 0024 QSSRC QDMA pseudo source address register 0200 0028 QSCNT QDMA pseudo frame count register 0200 002C QSDST QDMA pseudo destination address register 0200 0030 QSIDX Reserved QDMA pseudo index register All the QDMA and Pseudo registers are write-accessible only Table 9. PLL Wrapper Registers HEX ADDRESS RANGE ACRONYM 01B7 C000 ­ 01B7 C0FF ­ 01B7 C100 PLLCSR REGISTER NAME Reserved PLL control/status register 01B7 C104 ­ 01B7 C10F ­ 01B7 C110 PLLM Reserved PLL multiplier control register 01B7 C114 PLLDIV0 PLL wrapper divider 0 register 01B7 C118 PLLDIV1 PLL wrapper divider 1 register 01B7 C11C PLLDIV2 PLL wrapper divider 2 register 01B7 C120 PLLDIV3 PLL wrapper divider 3 register 01B7 C124 OSCDIV1 Oscillator divider 1 register 01B7 C128 ­ 01B7 DFFF ­ Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 13 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions (continued) Table 10. McASP0 and McASP1 Registers HEX ADDRESS RANGE ACRONYM McASP0 McASP1 01B4 C000 01B5 0000 ­ 01B4 C004 01B5 0004 PWRDEMU REGISTER NAME Reserved Power down and emulation management register 01B5 0008 ­ Reserved 01B5 000C ­ Reserved 01B4 C010 01B5 0010 PFUNC Pin function register 01B4 C014 01B5 0014 PDIR Pin direction register 01B4 C018 01B5 0018 PDOUT Pin data out register 01B4 C01C PRODUCT PREVIEW 01B4 C008 01B4 C00C 01B5 001C PDIN/PDSET Pin data in / data set register Read returns: PDIN Writes affect: PDSET 01B4 C020 01B5 0020 PDCLR 01B4 C024 ­ 01B4 C040 01B5 0024 ­ 01B5 0040 ­ Pin data clear register 01B4 C044 01B5 0044 GBLCTL Global control register Reserved 01B4 C048 01B5 0048 AMUTE Mute control register 01B4 C04C 01B5 004C DLBCTL Digital Loop-back control register DIT mode control register 01B4 C050 01B5 0050 DITCTL 01B4 C054 ­ 01B4 C05C 01B5 0054 ­ 01B5 005C ­ 01B4 C060 01B5 0060 RGBLCTL 01B4 C064 01B5 0064 RMASK 01B4 C068 01B5 0068 RFMT 01B4 C06C 01B5 006C AFSRCTL 01B4 C070 01B5 0070 ACLKRCTL 01B4 C074 01B5 0074 AHCLKRCTL Reserved Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive. Receiver format unit bit mask register Receive bit stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register 01B4 C078 01B5 0078 RTDM 01B4 C07C 01B5 007C RINTCTL Receive TDM slot 0­31 register 01B4 C080 01B5 0080 RSTAT Status register ­ Receiver 01B4 C084 01B5 0084 RSLOT Current receive TDM slot register 01B4 C088 01B5 0088 RCLKCHK 01B4 C08C ­ 01B4 C09C 01B5 008C ­ 01B5 009C ­ 01B4 C0A0 01B5 00A0 XGBLCT Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. 01B4 C0A4 01B5 00A4 XMASK Transmit format unit bit mask register 01B4 C0A8 01B5 00A8 XFMT 01B4 C0AC 01B5 00AC AFSXCTL 01B4 C0B0 01B5 00B0 ACLKXCTL 01B4 C0B4 01B5 00B4 AHCLKXCTL Receiver interrupt control register Receiver clock check control register Reserved Transmit bit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register 01B4 C0B8 XTDM Transmit TDM slot 0­31 register 01B5 00BC XINTCTL Transmit interrupt control register 01B4 C0C0 01B5 00C0 XSTAT Status register ­ Transmitter 01B4 C0C4 14 01B5 00B8 01B4 C0BC 01B5 00C4 XSLOT Current transmit TDM slot POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions (continued) Table 10. McASP0 and McASP1 Registers (Continued) HEX ADDRESS RANGE McASP0 McASP1 ACRONYM REGISTER NAME 01B4 C0C8 01B5 00C8 XCLKCHK 01B4 C0CC ­ 01B4 C0FC 01B5 00CC ­ 01B5 00FC ­ Transmit clock check control register 01B4 C100 01B5 0100 DITCSRA0 Left (even TDM slot) channel status register file 01B4 C104 01B5 0104 DITCSRA1 Left (even TDM slot) channel status register file 01B4 C108 01B5 0108 DITCSRA2 Left (even TDM slot) channel status register file 01B4 C10C 01B5 010C DITCSRA3 Left (even TDM slot) channel status register file 01B4 C110 01B5 0110 DITCSRA4 Left (even TDM slot) channel status register file 01B4 C114 01B5 0114 DITCSRA5 Left (even TDM slot) channel status register file Reserved 01B5 0118 DITCSRB0 Right (odd TDM slot) channel status register file 01B5 011C DITCSRB1 Right (odd TDM slot) channel status register file 01B4 C120 01B5 0120 DITCSRB2 Right (odd TDM slot) channel status register file 01B4 C124 01B5 0124 DITCSRB3 Right (odd TDM slot) channel status register file 01B4 C128 01B5 0128 DITCSRB4 Right (odd TDM slot) channel status register file 01B4 C12C 01B5 012C DITCSRB5 Right (odd TDM slot) channel status register file 01B4 C130 01B5 0130 DITUDRA0 Left (even TDM slot) user data register file 01B4 C134 01B5 0134 DITUDRA1 Left (even TDM slot) user data register file 01B4 C138 01B5 0138 DITUDRA2 Left (even TDM slot) user data register file 01B4 C13C 01B5 013C DITUDRA3 Left (even TDM slot) user data register file 01B4 C140 01B5 0140 DITUDRA4 Left (even TDM slot) user data register file 01B4 C144 01B5 0144 DITUDRA5 Left (even TDM slot) user data register file 01B4 C148 01B5 0148 DITUDRB0 Right (odd TDM slot) user data register file 01B4 C14C 01B5 014C DITUDRB1 Right (odd TDM slot) user data register file 01B4 C150 01B5 0150 DITUDRB2 Right (odd TDM slot) user data register file 01B4 C154 01B5 0154 DITUDRB3 Right (odd TDM slot) user data register file 01B4 C158 01B5 0158 DITUDRB4 Right (odd TDM slot) user data register file 01B4 C15C 01B5 015C DITUDRB5 Right (odd TDM slot) user data register file 01B4 C160 ­ 01B4 C17C 01B5 0160 ­ 01B5 017C ­ 01B4 C180 01B5 0180 SRCTL0 Serializer 0 control register 01B4 C184 01B5 0184 SRCTL1 Serializer 1 control register 01B4 C188 01B5 0188 SRCTL2 Serializer 2 control register 01B4 C18C 01B5 018C SRCTL3 Serializer 3 control register 01B4 C190 01B5 0190 SRCTL4 Serializer 4 control register 01B4 C194 01B5 0194 SRCTL5 Serializer 5 control register 01B4 C198 01B5 0198 SRCTL6 PRODUCT PREVIEW 01B4 C118 01B4 C11C Serializer 6 control register Serializer 7 control register Reserved 01B4 C19C 01B5 019C SRCTL7 01B4 C1A0 ­ 01B4 C1FC 01B5 C1A0 ­ 01B5 01FC ­ 01B4 C200 01B5 0200 XBUF0 Transmit Buffer for Serializer 0 01B4 C204 01B5 0204 XBUF1 Transmit Buffer for Serializer 1 01B4 C208 01B5 0208 XBUF2 Transmit Buffer for Serializer 2 01B4 C20C 01B5 020C XBUF3 Transmit Buffer for Serializer 3 01B4 C210 01B50C210 01B50C210 XBUF4 Transmit Buffer for Serializer 4 POST OFFICE BOX 1443 Reserved · HOUSTON, TEXAS 77251­1443 15 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions (continued) Table 10. McASP0 and McASP1 Registers (Continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME McASP0 McASP1 01B4 C214 01B5 0214 XBUF5 Transmit Buffer for Serializer 5 01B4 C218 01B5 0218 XBUF6 Transmit Buffer for Serializer 6 01B4 C21C 01B5 021C XBUF7 Transmit Buffer for Serializer 7 01B4 C220 ­ 01B4 C27C 01B5 C220 ­ 01B5 027C ­ 01B4 C280 01B5 0280 RBUF0 Receive Buffer for Serializer 0 01B4 C284 01B5 0284 RBUF1 Receive Buffer for Serializer 1 01B4 C288 01B5 0288 RBUF2 Receive Buffer for Serializer 2 01B4 C28C 01B5 028C RBUF3 Receive Buffer for Serializer 3 01B4 C290 01B5 0290 RBUF4 Receive Buffer for Serializer 4 01B4 C294 01B5 0294 RBUF5 Receive Buffer for Serializer 5 Reserved PRODUCT PREVIEW 01B4 C298 01B5 0298 RBUF6 Receive Buffer for Serializer 6 01B4 C29C 01B5 029C RBUF7 Receive Buffer for Serializer 7 01B4 C2A0 ­ 01B4 FFFF 01B5 02A0 ­ 01B5 3FFF ­ Reserved Table 11. I2C0 Registers HEX ADDRESS RANGE I2COAR0 I2C0 own address register 01B4 0004 I2CIER0 I2C0 interrupt enable register 01B4 0008 I2CSTR0 I2C0 interrupt status register 01B4 000C I2CCLKL0 I2C0 clock low-time divider register 01B4 0010 I2CCLKH0 I2C0 clock high-time divider register 01B4 0014 I2CCNT0 I2C0 data count register 01B4 0018 I2CDRR0 I2C0 data receive register 01B4 001C I2CSAR0 I2C0 slave address register 01B4 0020 I2CDXR0 I2C0 data transmit register 01B4 0024 I2CMDR0 I2C0 mode register 01B4 0028 I2CISRC0 I2C0 interrupt source register 01B4 002C ­ 01B4 0030 I2CPSC0 01B4 0034 ­ 01B4 3FFF 16 ACRONYM 01B4 0000 REGISTER NAME ­ Reserved I2C0 prescaler register Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions (continued) Table 12. I2C1 Registers HEX ADDRESS RANGE ACRONYM 01B4 4000 I2COAR1 I2C1 own address register 01B4 4004 I2CIER1 I2C1 interrupt enable register 01B4 4008 I2CSTR1 I2C1 interrupt status register 01B4 400C I2CCLKL1 I2C1 clock low-time divider register 01B4 4010 I2CCLKH1 I2C1 clock high-time divider register 01B4 4014 I2CCNT1 I2C1 data count register 01B4 4018 I2CDRR1 I2C1 data receive register 01B4 401C I2CSAR1 I2C1 slave address register 01B4 4020 I2CDXR1 I2C1 data transmit register 01B4 4024 I2CMDR1 I2C1 mode register I2C1 interrupt source register I2CISRC1 ­ 01B4 4030 I2CPSC1 01B4 4034 ­ 01B4 7FFF ­ Reserved I2C1 prescaler register PRODUCT PREVIEW 01B4 4028 01B4 402C REGISTER NAME Reserved Table 13. HPI Registers HEX ADDRESS RANGE ACRONYM ­ HPID HPI data register REGISTER NAME Host read/write access only COMMENTS ­ HPIA HPI address register Host read/write access only 0188 0000 HPIC HPI control register Both Host/CPU read/write access 0188 0001 ­ 018B FFFF ­ Reserved Table 14. McBSP 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 018C 0000 DRR0 McBSP0 data receive register via Peripheral Bus 0x3000 0000 ­ 0x33FF FFFF DRR0 McBSP0 data receive register via EDMA Bus 018C 0004 DXR0 McBSP0 data transmit register via Peripheral Bus 0x3000 0000 ­ 0x33FF FFFF DXR0 McBSP0 data transmit register via EDMA Bus 018C 0008 SPCR0 018C 000C RCR0 McBSP0 receive control register 018C 0010 XCR0 McBSP0 transmit control register 018C 0014 SRGR0 018C 0018 MCR0 McBSP0 multichannel control register 018C 001C RCER0 McBSP0 receive channel enable register 018C 0020 XCER0 McBSP0 transmit channel enable register 018C 0024 PCR0 018C 0028 ­ 018F FFFF ­ COMMENTS The CPU and DMA/EDMA controller can only read this register; they cannot write to it. McBSP0 serial port control register McBSP0 sample rate generator register McBSP0 pin control register Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 17 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions (continued) Table 15. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0190 0000 DRR1 Data receive register via Peripheral Bus 0x3400 0000 ­ 0x37FF FFFF DRR1 McBSP1 data receive register via EDMA Bus 0190 0004 DXR1 McBSP1 data transmit register via Peripheral Bus 0x3400 0000 ­ 0x37FF FFFF DXR1 The CPU and DMA/EDMA controller can only read this register; they cannot write to it. McBSP1 data transmit register via EDMA Bus SPCR1 RCR1 McBSP1 receive control register 0190 0010 XCR1 McBSP1 transmit control register 0190 0014 SRGR1 0190 0018 MCR1 McBSP1 multichannel control register 0190 001C RCER1 McBSP1 receive channel enable register 0190 0020 XCER1 McBSP1 transmit channel enable register 0190 0024 PCR1 0190 0028 ­ 0193 FFFF PRODUCT PREVIEW 0190 0008 0190 000C McBSP1 serial port control register ­ McBSP1 sample rate generator register McBSP1 pin control register Reserved Table 16. Timer 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0194 0000 CTL0 Timer 0 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0194 0004 PRD0 Timer 0 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter. 0194 000C ­ 0197 FFFF ­ Reserved Table 17. Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0198 0000 Timer 1 control register 0198 0004 PRD1 Timer 1 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter. 0198 000C ­ 019B FFFF 18 CTL1 Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. ­ Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 peripheral register descriptions (continued) Table 18. GPIO Registers HEX ADDRESS RANGE ACRONYM 01B0 0000 GPEN GPIO enable register REGISTER NAME 01B0 0004 GPDIR GPIO direction register 01B0 0008 GPVAL GPIO value register 01B0 000C ­ 01B0 0010 GPDH GPIO delta high register 01B0 0014 GPHM GPIO high mask register 01B0 0018 GPDL GPIO delta low register 01B0 001C GPLM GPIO low mask register 01B0 0020 GPGC GPIO global control register 01B0 0024 GPPOL GPIO interrupt polarity register 01B0 0028 ­ 01B0 3FFF ­ Reserved Reserved Table 19 identifies the PWRD field (bits 15­10) in the CPU CSR register. These bits control the device power-down modes. For more detailed information on the PWRD bit field of the CPU CSR register, see the TMS320C6000 TMS320C6000 Peripherals Reference Guide (literature number SPRU190 SPRU190). Table 19. PWRD field bits in the CPU CSR Register HEX ADDRESS RANGE ­ ACRONYM CSR REGISTER NAME Control status register COMMENTS The PWRD field (bits 15­10 in the CPU CSR) controls the device power-down modes. Accessible by writing a value to the CSR register. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 19 PRODUCT PREVIEW PWRD bits in CPU CSR register description TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 interrupts and interrupt selector The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 20. The highest priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable and fixed. The remaining interrupts (4­15) are maskable and default to the interrupt source listed in Table 20. However, their interrupt source may be reprogrammed to any one of the sources listed in Table 21 (Interrupt Selector). Table 21 lists the selector value corresponding to each of the alternate interrupt sources. The selector choice for interrupts 4­15 is made by programming the corresponding fields (listed in Table 20) in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers. Table 20. DSP Interrupts Table 21. Interrupt Selector DSP INTERRUPT NUMBER INTERRUPT SELECTOR CONTROL REGISTER DEFAULT SELECTOR VALUE (BINARY) DEFAULT INTERRUPT EVENT INTERRUPT SELECTOR VALUE (BINARY) INTERRUPT EVENT INT_00 ­ ­ RESET 00000 DSPINT HPI INT_01 ­ ­ NMI 00001 TINT0 Timer 0 INT_02 ­ ­ Reserved 00010 TINT1 Timer 1 MODULE ­ ­ Reserved 00011 SDINT EMIF INT_04 MUXL[4:0] 00100 EXTINT4 00100 EXTINT4 GPIO INT_05 MUXL[9:5] 00101 EXTINT5 00101 EXTINT5 GPIO INT_06 MUXL[14:10] 00110 EXTINT6 00110 EXTINT6 GPIO INT_07 MUXL[20:16] 00111 EXTINT7 00111 EXTINT7 GPIO INT_08 MUXL[25:21] 01000 EDMAINT 01000 EDMAINT EDMA INT_09 MUXL[30:26] 01001 EMUDTDMA 01001 EMUDTDMA Emulation INT_10 MUXH[4:0] 00011 SDINT 01010 EMURTDXRX Emulation INT_11 MUXH[9:5] 01010 EMURTDXRX 01011 EMURTDXTX Emulation INT_12 MUXH[14:10] 01011 EMURTDXTX 01100 XINT0 McBSP0 INT_13 MUXH[20:16] 00000 DSPINT 01101 RINT0 McBSP0 INT_14 MUXH[25:21] 00001 TINT0 01110 XINT1 McBSP1 INT_15 PRODUCT PREVIEW INT_03 MUXH[30:26] 00010 TINT1 01111 RINT1 McBSP1 10000 GPINT0 GPIO 10001 Reserved ­ 10010 Reserved ­ 10011 Reserved ­ 10100 Reserved ­ 10101 Reserved ­ 10110 I2CINT0 I2C0 10111 ­ Reserved ­ 11010 Reserved ­ 11011 Reserved ­ 11100 AXINT0 McASP0 11101 ARINT0 McASP0 11110 AXINT1 McASP1 11111 POST OFFICE BOX 1443 I2C1 Reserved 11001 20 I2CINT1 11000 ARINT1 McASP1 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 EDMA module and EDMA selector The C67x EDMA supports up to 16 EDMA channels. Four of the sixteen channels (channels 8­11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned EDMA selector code (see Table 23). By loading each EVTSELx register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA channel. Table 22 lists the default EDMA selector value for each EDMA channel. PRODUCT PREVIEW See Table 24 and Table 25 for the EDMA Event Selector registers and their assoicated bit descriptions. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 21 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 EDMA module and EDMA selector (continued) Table 22. EDMA Channels Table 23. EDMA Selector DEFAULT SELECTOR VALUE (BINARY) DEFAULT EDMA EVENT EDMA SELECTOR CODE (BINARY) EDMA EVENT MODULE 0 ESEL0[5:0] 000000 DSPINT 000000 DSPINT HPI 1 ESEL0[13:8] 000001 TINT0 000001 TINT0 TIMER0 2 ESEL0[21:16] 000010 TINT1 000010 TINT1 TIMER1 3 ESEL0[29:24] 000011 SDINT 000011 SDINT EMIF 4 ESEL1[5:0] 000100 EXTINT4 000100 EXTINT4 GPIO 5 ESEL1[13:8] 000101 EXTINT5 000101 EXTINT5 GPIO 6 ESEL1[21:16] 000110 EXTINT6 000110 EXTINT6 GPIO 7 ESEL1[29:24] 000111 EXTINT7 000111 EXTINT7 GPIO 8 n/a n/a TCC8 (Chaining) 001000 GPINT0 GPIO 9 n/a n/a TCC9 (Chaining) 001001 GPINT1 GPIO 10 n/a n/a TCC10 TCC10 (Chaining) 001010 GPINT2 GPIO 11 n/a n/a TCC11 TCC11 (Chaining) 001011 GPINT3 GPIO 12 ESEL3[5:0] 001000 XEVT0 001100 XEVT0 McBSP0 13 ESEL3[13:8] 001001 REVT0 001101 REVT0 McBSP0 14 ESEL3[21:16] 001010 XEVT1 001110 XEVT1 McBSP1 15 PRODUCT PREVIEW EDMA CHANNEL EDMA SELECTOR CONTROL REGISTER ESEL3[29:24] 001011 REVT1 001111 REVT1 010000­011111 McBSP1 Reserved 100000 AXEVTE0 McASP0 100001 AXEVTO0 McASP0 100010 AXEVT0 McASP0 100011 AREVTE0 McASP0 100100 AREVTO0 McASP0 100101 AREVT0 McASP0 100110 AXEVTE1 McASP1 100111 AXEVTO1 McASP1 101000 AXEVT1 McASP1 101001 AREVTE1 McASP1 101010 AREVTO1 McASP1 101011 AREVT1 McASP1 101100 I2CREVT0 I2C0 101101 I2CXEVT0 I2C0 101110 I2CREVT1 I2C1 101111 I2CXEVT1 I2C1 110000 GPINT8 GPIO 110001 GPINT9 GPIO 110010 GPINT10 GPINT10 GPIO 110011 GPINT11 GPINT11 GPIO 110100 GPINT12 GPINT12 GPIO 110101 GPINT13 GPINT13 GPIO 110110 GPINT14 GPINT14 GPIO 110111 GPINT15 GPINT15 111000­111111 22 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 GPIO Reserved TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 EDMA module and EDMA selector (continued) Table 24. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3) ESEL0 Register (0x01A0 FF00) 30 31 29 28 27 24 23 22 21 20 19 Reserved EVTSEL3 Reserved EVTSEL2 R­0 R/W­00 0011b R­0 16 R/W­00 0010b 14 15 13 12 11 8 7 6 5 4 0 3 Reserved EVTSEL1 Reserved EVTSEL0 R­0 R/W­00 0001b R­0 R/W­00 0000b Legend: R = Read only, R/W = Read/Write; -n = value after reset ESEL1 Register (0x01A0 FF04) 29 28 27 24 23 22 21 20 19 Reserved EVTSEL7 Reserved EVTSEL6 R­0 R/W­00 0111b R­0 16 R/W­00 0110b 14 15 13 12 11 8 6 5 7 4 0 3 Reserved EVTSEL5 Reserved EVTSEL4 R­0 R/W­00 0101b R­0 R/W­00 0100b Legend: R = Read only, R/W = Read/Write; -n = value after reset ESEL3 Register (0x01A0 FF0C) 30 31 29 28 27 24 23 22 21 20 19 Reserved EVTSEL15 EVTSEL15 Reserved EVTSEL14 EVTSEL14 R­0 R/W­00 1011b R­0 16 R/W­00 1010b 14 15 13 12 11 8 7 6 5 4 3 0 Reserved EVTSEL13 EVTSEL13 Reserved EVTSEL12 EVTSEL12 R­0 R/W­00 1001b R­0 R/W­00 1000b Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 25. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description BIT # NAME 31:30 23:22 15:14 7:6 Reserved DESCRIPTION Reserved. Read-only, writes have no effect. EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels. 29:24 21:16 13:8 5:0 EVTSELx The EVTSEL0 through EVTSEL15 EVTSEL15 bits correspond to the channels 0 to 15, respectively. These EVTSELx fileds are user­selectable. By configuring the EVTSELx fields to the EDMA selector value of the desired EDMA sync event number (see Table 23), users can map any EDMA event to the EDMA channel. For example, if EVTSEL15 EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then channel 15 is triggered by Timer0 TINT0 events. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 23 PRODUCT PREVIEW 30 31 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 signal groups description CLKIN CLKOUT2/GP[2] CLKOUT3 CLKMODE0 PLLV PLLG OSCIN OSCOUT PRODUCT PREVIEW TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 Clock/PLL Oscillator Reset and Interrupts RESET NMI GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 IEEE Standard 1149.1 (JTAG) Emulation Control/Status HD15/GP HD15/GP[15] HD14/GP HD14/GP[14] HD13/GP HD13/GP[13] HD12/GP HD12/GP[12] HD11/GP HD11/GP[11] HD10/GP HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4] HPI (Host-Port Interface) Control Data Register Select Half-Word Select HAS/ACLKX1 HR/W/AXR1[0] HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HINT/GP[1] HCNTL0/AXR1[3] HCNTL1/AXR1[1] HHWIL/AFSR1 These external pins are applicable to the GFN package only. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 3. CPU (DSP Core) and Peripheral Signals 24 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 signal groups description (continued) HD15/GP HD15/GP[15] HD14/GP HD14/GP[14] HD13/GP HD13/GP[13] HD12/GP HD12/GP[12] HD11/GP HD11/GP[11] HD10/GP HD10/GP[10] HD9/GP[9] HD8/GP[8] GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0] GPIO General-Purpose Input/Output (GPIO) Port Timer 1 Timer 0 TOUT0/AXR0[2] TINP0/AXR0[3] PRODUCT PREVIEW TOUT1/AXR0[4] TINP1/AHCLKX0 Timers CLKS1/SCL1 DR1/SDA1 I2C1 I2C0 SCL0 SDA0 I2Cs NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 4. Peripheral Signals POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 25 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 signal groups description (continued) ED[31:16] 16 16 Data Memory Control ED[15:0] CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 PRODUCT PREVIEW BE1 BE0 ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY Memory Map Space Select 20 Bus Arbitration Address HOLD HOLDA BUSREQ Byte Enables EMIF (External Memory Interface) McBSP1 McBSP0 CLKX1/AMUTE0 FSX1 DX1/AXR0[5] Transmit Transmit CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1] CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1 Receive Receive CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0] Clock Clock CLKS1/SCL1 CLKS0/AHCLKR0 McBSPs (Multichannel Buffered Serial Ports) These external pins are applicable to the GFN package only. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 4. Peripheral Signals (Continued) 26 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 signal groups description (continued) (Transmit/Receive Data Pins) FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF (Receive Bit Clock) Receive Clock Generator (Receive Master Clock) CLKS0/AHCLKR0 (Transmit Master Clock) Receive Clock Check Circuit FSR0/AFSR0 (Receive Frame Sync or Left/Right Clock) CLKX0/ACLKX0 Transmit Clock Check Circuit Receive Frame Sync Transmit Frame Sync PRODUCT PREVIEW CLKR0/ACLKR0 TINP1/AHCLKX0 (Transmit Bit Clock) Transmit Clock Generator Error Detect (see Note A) Auto Mute Logic FSX0/AFSX0 (Transmit Frame Sync or Left/Right Clock) CLKX1/AMUTE0 GP[5](EXT_INT5)/AMUTEIN0 McASP0 (Multichannel Audio Serial Port 0) NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 4. Peripheral Signals (Continued) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 27 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 signal groups description (continued) (Transmit/Receive Data Pins) HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF (Receive Bit Clock) HRDY/ACLKR1 HD6/AHCLKR1 (Transmit Bit Clock) Receive Clock Generator Transmit Clock Generator PRODUCT PREVIEW (Receive Master Clock) HD5/AHCLKX1 (Transmit Master Clock) Receive Clock Check Circuit HHWIL/AFSR1 (Receive Frame Sync or Left/Right Clock) HAS/ACLKX1 Transmit Clock Check Circuit Receive Frame Sync Transmit Frame Sync Error Detect (see Note A) Auto Mute Logic HD2/AFSX1 (Transmit Frame Sync or Left/Right Clock) HD3/AMUTE1 GP[4](EXT_INT4)/AMUTEIN1 McASP1 (Multichannel Audio Serial Port 1) NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 4. Peripheral Signals (Continued) 28 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS On the C6713 C6713 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset. device configurations at device reset Table 26 describes the C6713 C6713 device configuration pins, which are set up via external pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, and HD12) and CLKMODE0 pin. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section. Table 26. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) HD8 PYP GFN B17 FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 ­ System operates in Big Endian mode 1 ­ System operates in Little Endian mode (default) HD[4:3] (BOOTMODE) A15, C19, C20 Bootmode Configuration Pins (BOOTMODE) 00 ­ CE1 width 32-bit, HPI boot 01 ­ CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 ­ CE1 width 16-bit, Asynchronous external ROM boot 11 ­ CE1 width 32-bit, Asynchronous external ROM boot HD12 C15 Pulldown. For proper device operation, this pin must be externally pulled down with a 1-k resistor. CLKMODE0 C4 Clock generator input clock source select 0 ­ Oscillator pads (OSCIN, OSCOUT directly from the crystal oscillator) 1 ­ CLKIN square wave [default] This pin must be pulled to the correct level even after reset. Other HD pins (HD [15, 13, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). For proper device operation, do not oppose these pins with external IPUs/IPDs at reset. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 29 PRODUCT PREVIEW CONFIGURATION PIN TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) peripheral selection at device reset Some C6713 C6713 peripherals share the same pins but are mutually exclusive (i.e., HPI, general-purpose input/output 0 pins GP[15:8, 3, 1, 0], McASP0, and I2C0). D HPI versus McASP1, I2C0, and GP peripherals The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral or McASP1, I2C0 peripherals, and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 27). Table 27. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, I2C0, and Select GP Pins) PERIPHERAL SELECTION PRODUCT PREVIEW HPI_EN (HD14 Pin) PERIPHERALS SELECTED HPI McASP1, I2C0, and GP [15:8,3,1,0] 0 DESCRIPTION HPI_EN = 0 HPI is disabled; McASP1 and I2C0 peripherals and GP [15:8, 3, 1,0] pins are enabled. All multiplexed HPI/McASP1 and HPI/GP pins function as McASP1 and GP pins, respectively. To use the GP pins, the appropriate bits in the GPEN and GPDIR registers need to be configured. The IPUs on the I2C0 pins are disabled, allowing for I2C0 use. When the I2C0 peripheral is not used, to avoid floating inputs, these I2C0 pins must be externally pulled up with 1-k resistor. 1 HPI_EN = 1 HPI is enabled; McASP1 and I2C0 peripherals and GP [15:8, 3, 1,0] pins are disabled [default]. All multiplexed HPI/McASP1 and HPI/GP pins function as HPI pins. In addition, since the I2C0 peripheral is disabled, the IPUs on the I2C0 pins are enabled to avoid floating inputs. 30 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) peripheral selection/device configurations via the DEVCFG control register The device configuration register (DEVCFG) allows the user to control the peripheral selection of the McBSP0, McBSP1, McASP0, and I2C1 peripherals. The DEVCFG register also offers the user control of the EMIF input clock source and the timer output functions of the TOUT1/AXR0[4] and TOUT0/AXR0[2] multiplexed pins. For more detailed information on the DEVCFG register control bits, see Table 28 and Table 29. Table 28. Device Configuration Register (DEVCFG) [Address location: 0x019C0200] 31 16 Reserved RW-0 5 4 3 2 1 0 Reserved EKSRC TOUT1SEL TOUT0SEL McASP0EN I2C1EN RW-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 PRODUCT PREVIEW Legend: R/W = Read/Write; -n = value after reset Do not write non-zero values to these bit locations. Table 29. Device Configuration (DEVCFG) Register Selection Bit Descriptions BIT # NAME 31:5 Reserved 4 3 2 1 0 EKSRC DESCRIPTION Reserved. Do not write non-zero values to these bit locations. EMIF input clock source bit. Determines which clock signal is used as the EMIF input clock. 0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default) 1 = ECLKIN external pin is the EMIF input clock source TOUT1SEL Timer 1 output (TOUT1) pin function select bit. Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 1 output (TOUT1) pin (default) 1 = The pin functions as the McASP0 AXR0[4] pin. TOUT0SEL Timer 0 output (TOUT0) pin function select bit. Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 0 output (TOUT0) pin (default) 1 = The pin functions as the McASP0 AXR0[2] pin. MCASP0EN Multichannel Audio Serial Port 0 (McASP0) enable bit. Selects whether McASP0 or the McBSP0 peripheral is enabled. 0 = McASP0 is disabled (functional for DIT mode only), McBSP0 is enabled (default). 1 = McASP0 is enabled, McBSP0 is disabled. I2C1EN Inter-integrated circuit 1 (I2C1) enable bit. Selects whether I2C1 or the McBSP1 peripheral is enabled. 0 = I2C1 is disabled, McBSP1 is enabled (default) The internal IPU/IPDs on the CLKS1/SCL1 and DR1/SDA1 pins are enabled for McBSP1's use. 1 = I2C1 is enabled, McBSP1 is disabled The internal IPU/IPDs on the CLKS1/SCL1 and DR1/SDA1 pins are disabled for I2C1's use POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 31 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins PRODUCT PREVIEW Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of these pins are configured by software via the device configuration register (DEVCFG), and the others (specifically, the HPI pins) are configured by an external pullup/pulldown resistor on the HD14 pin (HPI_EN) at reset. The muxed pins that are configured by software are intended to be programmed once during software initialization. The muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 30 summarizes the peripheral pins affected by the HPI_EN (HD14 pin) and DEVCFG register. Table 31 identifies the multiplexed pins on the C6713 C6713 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure the specific multiplexed functions. 32 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) Table 30. Peripheral Pin Selection Matrix SELECTION BITS N A M E M c A S P 0 V A L U E M c A S P 1 AHCLKX1 AHCLKR1 ACLKX1 ACLKR1 AFSX1 AFSR1 AMUTE1 AXR1[0] to AXR1[7] 0 HPI_EN (boot config pin) 1 None I 2 C 0 I 2 C 1 M c B S P 0 T I M E R T I M E R 0 M c B S P 1 1 All None None All None 1 0 None All 1 AMUTE0 AXR0[5] AXR0[6] AXR0[7] All None 0 NO AXR0[2] TOUT0 1 AXR0[2] NO TOUT0 0 TOUT1SEL (DEVCFG bit) NO AXR0[4] TOUT1 1 AXR0[4] NO GP[0:1], GP[3], GP[8:15] None NO AMUTE0 AXR0[5] AXR0[6] AXR0[7] Plus: GP2 ctrl'd by GP2EN All ACLKK0 ACLKR0 AFSX0 AFSR0 AHCLKR0 AXR0[0] AXR0[1] NO TOUT1 IIC1EN (DEVCFG bit) TOUT0SEL (DEVCFG bit) P I N S E M I F GP[0:1], GP[3], GP[8:15] 0 McASP0EN (DEVCFG bit) H P I G P I O PRODUCT PREVIEW B I T PERIPHERAL PINS AVAILABILITY B I T Gray blocks indicate that the peripheral is not affected by the selection bit. The McASP0 pins AXR0[3] and AHCLKX0 are shared with the timer input pins TINP0 and TINP1, respectively. See Table 31 for more detailed information. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 33 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) Table 31. C6713 C6713 Device Multiplexed/Shared Pins MULTIPLEXED PINS NAME PRODUCT PREVIEW CLKOUT2/GP[2] GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 PYP GFN Y12 C1 C2 CLKS0/AHCLKR0 H2 FSR0/AFSR0 J3 FSX0/AFSX0 H1 When the CLKOUT2 pin is enabled , the CLK2EN bit in the EMIF global control register (GBLCTL) controls the CLKOUT2 pin. CLK2EN = 0: CLKOUT2 held high CLK2EN = 1: CLKOUT2 enabled to clock No Function GP5EN = 0 (disabled) GP4EN = 0 (disabled) GPxDIR = 0 (input) To use these as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output To use AMUTEIN0/1 pin function, the GP[5]/GP[4] pins must be configured as an input, and set to 1 the INSTAT bit in the associated McASP AMUTE register. J1 DX0/AXR0[1] GP[5](EXT_INT5) GP[4](EXT_INT4) DESCRIPTION GP2EN = 0 (GPEN reigster bit) GP[2] function disabled, CLKOUT2 enabled CLKOUT2 DEFAULT SETTING K3 DR0/AXR0[0] DEFAULT FUNCTION To enable the I2C1 peripheral, the I2C1EN bit in the DEVCFG register must be set to 1, disabling the McBSP1 peripheral pins. I2C1EN = 0 (DEVCFG register bit) I2C1 disabled disabled, McBSP1 pins enabled To enable the McASP0 peripheral pins the I2C1EN bit in the DEVCFG register must be set to 1. E1 DR1/SDA1 I2C1EN = 0 (DEVCFG register bit) I2C1 disabled, McBSP0 pins enabled G3 CLKS1/SCL1 To enable the McASP0 peripheral, the McASP0EN bit in h M ASP0EN bi i the DEVCFG register must be set to 1 (disabling the McBSP0 peripheral pins). eri heral ins). H3 CLKX0/ACLKX0 MCASP0EN = 0 (DEVCFG register bit) i bi ) McASP0 pins disabled disabled, McBSP0 pins enabled ins McBSP1 pin function CLKR0/ACLKR0 McBSP0 pin function in M2 DX1/AXR0[5] L2 FSR1/AXR0[7] M3 CLKR1/AXR0[6] M1 CLKX1/AMUTE0 McBSP1 pin function L3 34 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) Table 31. C6713 C6713 Device Multiplexed/Shared Pins MULTIPLEXED PINS NAME PYP GFN HINT/GP[1] DESCRIPTION B14 HD14/GP HD14/GP[14] DEFAULT SETTING J20 HD15/GP HD15/GP[15] DEFAULT FUNCTION C14 HD13/GP HD13/GP[13] A15 HD12/GP HD12/GP[12] C15 HD11/GP HD11/GP[11] A16 B16 HD9/GP[9] C16 HD8/GP[8] B17 HD7/GP[3] A18 HD4/GP[0] C19 HD1/AXR1[7] D20 HD0/AXR1[4] E20 HCNTL1/AXR1[1] G19 HCNTL0/AXR1[3] HPI pin function McASP1, I2C0, and , , eleven GP pins are l i disabled disabled. G18 HR/W/AXR1[0] HPI_EN (HD14 pin) = 1 (HPI enabled) G20 HDS1/AXR1[6] E9 HDS2/AXR1[5] F18 HCS/AXR1[2] F20 HD6/AHCLKR1 B18 HD3/AMUTE1 C20 HD2/AFSX1 D18 HHWIL/AFSR1 H20 HRDY/ACLKR1 H19 HAS/ACLKX1 To use these as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an in ut input in GPxDIR = 1: GPx pin is an output H19 HD5/AHCLKX1 To enable the McASP1 and I2C0 peripherals and the eleven GP pins, eri herals ins, an external pulldown resistor (1 k) must be provided on the HD14 pin setting HPI_EN = 0 at reset. HPI EN E18 TINP0/AXR0[3] TINP1/AHCLKX0 G2 F2 Both TINP0 and AXR0[3] input function AXR3 bit in the McASP0 PDIR register = 0 (input) By default, this pin functions as TINP0 and AXR0[3] input. Setting the AXR3 bit in the McASP0 PDIR register to a 1 enables AXR0[3] as an output and disables the TINP0 pin function. Both TINP1 and AHCLKX0 input function AHCLKX bit in the McASP0 PDIR register = 0 (input) By default, this pin functions as TINP1 and AHCLKX0 input. Setting the AHCLKX bit in the McASP0 PDIR register to a 1 enables AHCLKX0 as an output and disables the TINP1 pin function. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 35 PRODUCT PREVIEW HD10/GP HD10/GP[10] TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) Table 31. C6713 C6713 Device Multiplexed/Shared Pins MULTIPLEXED PINS NAME PYP GFN DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION To enable the McASP0 AXR0[2] pin, the following must be properly configured: TOUT0/AXR0[2] G1 Timer 0 output function TOUT0SEL = 0 (DEVCFG register bit) TOUT0 pin enabled and McASP0 AXR0[2] disabled TOUT0SEL = 1 (TOUT0 disabled, AXR0[2] enabled. If the AXR2 bit in the McASP0 PDIR register = 0, then AXR0[2] is an input pin. PRODUCT PREVIEW If the AXR2 bit in the McASP0 PDIR register = 1, then AXR0[2] is an output pin. To enable the McASP0 AXR0[4] pin, the following must be properly configured: TOUT1/AXR0[4] F1 Timer 1 output function TOUT1SEL = 0 (DEVCFG register bit) TOUT1 pin enabled and McASP0 AXR0[4] disabled TOUT1SEL = 1 (TOUT1 disabled, AXR0[4] enabled. If the AXR4 bit in the McASP0 PDIR register = 0, then AXR0[4] is an input pin. If the AXR4 bit in the McASP0 PDIR register = 1, then AXR0[4] is an output pin. configuration examples Figure 5 through Figure 10 illustrate examples of peripheral selections that are configurable on this device. 36 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI SCL1, SDA1 I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 PRODUCT PREVIEW ED [31:16], ED[15:0] SCL0, SDA0 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 McASP1 8 AXR1[7:0] 8 McBSP1 McASP0 TIMER0 McBSP0 AXR0[7:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F McASP0EN = 1 I2C1EN = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (GPEN Register) Figure 5. Configuration Example A (2 I2C + 2 McASP) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 37 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF PRODUCT PREVIEW CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 McASP1 8 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] 5 DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McBSP1 McASP0 TIMER0 AXR0[4:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 McBSP0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000E McASP0EN = 1 I2C1EN = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (GPEN Register) Figure 6. Configuration Example B (1 I2C + 1 McBSP + 2 McASP) 38 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI SCL1, SDA1 I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 PRODUCT PREVIEW ED [31:16], ED[15:0] SCL0, SDA0 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 McASP1 8 AXR1[7:0] 6 McBSP1 McASP0 (DIT Mode) AXR0[7:2] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0 TIMER0 McBSP0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000D McASP0EN = 0 I2C1EN = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (GPEN Register) Figure 7. Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT)] POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 39 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF PRODUCT PREVIEW CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 McASP1 8 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] 3 McBSP1 DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McASP0 (DIT Mode) AXR0[4:2] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0 TIMER0 McBSP0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000C McASP0EN = 0 I2C1EN = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (GPEN Register) Figure 8. Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT)] 40 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI Clock, System, EMU, and Reset CLKOUT2 GPIO and EXT_INT GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) PRODUCT PREVIEW 16 HD[15:0] HPI I2C0 I2C1 McASP1 HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS SCL1, SDA1 8 McBSP1 McASP0 TIMER0 McBSP0 AXR0[7:0], TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F McASP0EN = 1 I2C1EN = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (GPEN Register) Figure 9. Configuration Example E (1 I2C + HPI + 1 McASP) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 41 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI Clock, System, EMU, and Reset CLKOUT2 GPIO and EXT_INT GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) PRODUCT PREVIEW 16 HD[15:0] HPI I2C0 I2C1 McASP1 HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS 5 DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McBSP1 McASP0 TIMER0 AXR0[4:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 McBSP0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000E McASP0EN = 1 I2C1EN = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (GPEN Register) Figure 10. Configuration Example F (1 McBSP + HPI + 1 McASP) 42 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 DEVICE CONFIGURATIONS (CONTINUED) debugging considerations It is recommended that external connections be provided to peripheral selection/device configuration pins, including HD[14:12, 8, 4, 3], and CLKMODE0. Although internal pullup resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the HPI data bus (HD[15, 13, 11:9, 7:5, 2:0]). For proper device operation, do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. PRODUCT PREVIEW For the internal pullup/pulldown resistors for all device pins, see the terminal functions table. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 43 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 TERMINAL FUNCTIONS PRODUCT PREVIEW The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet. 44 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 Terminal Functions SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION CLOCK/PLL CONFIGURATION CLKIN A3 I IPD Clock Input CLKOUT2/GP[2] Y12 O/Z IPD Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z) CLKOUT3 D10 I IPD Programmable clock output (OSC Divider internal signal from clock generator) CLKMODE0 C4 I IPU Clock generator input clock source select 0 ­ Oscillator pads (OSCIN, OSCOUT directly from the crystal oscillator) 1 ­ CLKIN square wave [default] PLLV A4 PLLG C6 A§ A§ OSCIN D12 I - Crystal oscillator Input (XI) OSCOUT C12 O - Crystal oscillator output (XO) TMS B7 I IPU JTAG test-port mode select TDO A8 O/Z IPU JTAG test-port data out TDI A7 I IPU JTAG test-port data in TCK A6 I IPU JTAG test-port clock Analog power (1.2 V) for PLL Analog ground for PLL TRST B6 I IPD JTAG test-port reset EMU5 - B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 - C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 - B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 - D3 I/O/Z IPU EMU1 B9 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. Emulation pin 1¶ EMU0 D9 I/O/Z IPU PRODUCT PREVIEW JTAG EMULATION Emulation pin 0¶ RESETS AND INTERRUPTS RESET A13 I IPU Device reset NMI C13 I IPD Nonmaskable interrupt · Edge-driven (rising edge) GP[7](EXT_INT7) E3 GP[6](EXT_INT6) D2 GP[5](EXT_INT5)/ AMUTEIN0 C1 GP[4](EXT_INT4)/ AMUTEIN1 C2 I/O/Z IPU General-purpose input/output pins (I/O/Z) which also function as external interrupts [default] · Edge-driven · Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[4] and GP[5] pins also f d i l function as AMUTEIN1 M ASP1 mute i ti McASP1 t input and t d AMUTEIN0 McASP0 mute input, respectively, if enabled by the INSTAT bit in the McASP AMUTE register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) § A = Analog signal (PLL Filter) ¶ The EMU0 and EMU1 pins are internally pulled up with 30-k resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k resistor. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 45 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION HOST-PORT INTERFACE (HPI) J20 O/Z IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). HCNTL1/AXR1[1] G19 I IPU Host control ­ selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z). HCNTL0/AXR1[3] G18 I IPU Host control ­ selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z). HHWIL/AFSR1 H20 I IPU Host half-word select ­ first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). HR/W/AXR1[0] G20 I IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z). HD15/GP HD15/GP[15] B14 IPU HD14/GP HD14/GP[14] PRODUCT PREVIEW HINT/GP[1] C14 IPU HD13/GP HD13/GP[13] A15 IPU HD12/GP HD12/GP[12] C15 IPU HD11/GP HD11/GP[11] A16 IPU HD10/GP HD10/GP[10] B16 IPU HD9/GP[9] C16 B17 ­ Boot mode (HD[4:3]) 00 ­ CE1 width 32-bit, HPI boot 01 ­ CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 ­ CE1 width 16-bit, Asynchronous external ROM boot 11 ­ CE1 width 32-bit, Asynchronous external ROM boot ­ HPI_EN (HD14) ­ HPI disabled, McASP1 and I2C0 enabled 0 1 ­ HPI enabled, McASP1 and I2C0 disabled (default) IPU I/O/Z HD8/GP[8] Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z) · Used for transfer of data, address, and control data address · Also controls initialization of DSP modes at reset via pullup/pulldown resistors ­ Device Endian mode (HD8) 0 ­ Big Endian 1 ­ Little Endian For proper device operation, the HD12 pin must be externally pulled down with a 1-k resistor. IPU , , ] ) Other HD pins ( (HD [ , 13, 11:9, 7:5, 2:0] have pullups/pulldowns ( [15, , (IPUs/IPDs). For proper device operation, do not oppose these pins with external IPUs/IPDs at reset. For more details, see the Device Configurations section of this data sheet. HD7/GP[3] A18 IPU HD6/AHCLKR1 C17 IPU Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). HD5/AHCLKX1 B18 IPU Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). HD4/GP[0] C19 IPD Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP 0 pin (I/O/Z). HD3/AMUTE1 C20 IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (I/O/Z). HD2/AFSX1 D18 IPU Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z). HD1/AXR1[7] D20 IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 data pin 7 (I/O/Z). HD0/AXR1[4] E20 IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 data pin 4 (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) 46 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) HAS/ACLKX1 E18 I IPU Host address strobe (I) [default] or McASP1 transmit bit clock (I/O/Z). HCS/AXR1[2] F20 I IPU Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z). HDS1/AXR1[6] E19 I IPU Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z). HDS2/AXR1[5] F18 I IPU Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z) . HRDY/ACLKR1 H19 O/Z IPD Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z). EMIF ­ COMMON SIGNALS TO ALL TYPES OF MEMORY CE3 V6 O/Z IPU CE2 W6 O/Z IPU CE1 W18 O/Z IPU V17 O/Z IPU BE3 - V5 O/Z IPU BE2 - Y4 O/Z IPU BE1 U19 O/Z IPU BE0 V20 O/Z IPU Byte-enable control · Decoded from the two lowest bits of the internal address y y y · Byte-write enables for most types of memory · C b di tl connected t SDRAM read and write mask signal (SDQM) Can be directly t d to d d it k i l EMIF ­ BUS ARBITRATION HOLDA J18 O/Z IPU Hold-request-acknowledge to the host HOLD J17 I IPU Hold request from the host BUSREQ J19 O/Z IPU Bus request output EMIF ­ ASYNCHRONOUS/SYNCHROUS MEMORY CONTROL ECLKIN Y11 I IPD External EMIF input clock source ECLKOUT Y10 O/Z IPD EMIF output clock depends on the EKSRC bit (DEVCFG.[16]). · EKSRC = 0 EMIF output clock source is the internal SYSCLK3 signal from the clock generator (default). · EKSRC = 1 ECLKOUT is based on the the external EMIF input clock source pin (ECLKIN). ARE/SDCAS/ SSADS V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe AOE/SDRAS/ SSOE W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable AWE/SDWE/ SSWE V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable ARDY Y5 I IPU Asynchronous memory ready input EA21 U18 EA20 Y18 EA19 W17 EA18 Y16 EA17 V16 EMIF ­ ADDRESS O/Z IPU External address (word address) EA16 Y15 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 47 PRODUCT PREVIEW CE0 Memory space enables · Enabled by bits 28 through 31 of the word address · Only one asserted during any external data access TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION EMIF ­ ADDRESS (CONTINUED) EA15 W15 EA14 Y14 EA13 W14 EA12 V14 EA11 W13 EA10 V10 EA9 Y9 EA8 V9 EA7 External address (word address) W8 EA5 V8 EA4 PRODUCT PREVIEW IPU Y8 EA6 O/Z W7 EA3 V7 EA2 Y6 EMIF ­ DATA ED31 N3 ED30 P3 ED29 P2 ED28 P1 ED27 R2 ED26 R3 ED25 T2 ED24 T1 ED23 U3 ED22 U1 ED21 U2 ED20 V1 ED19 V2 ED18 Y3 ED17 W4 ED16 External data pins (ED[31:16] pins applicable to GFN package only) T19 ED14 IPU V4 ED15 I/O/Z T20 ED13 T18 ED12 R20 ED11 R19 ED10 P20 ED9 P18 ED8 N20 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) 48 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION EMIF ­ DATA (CONTINUED) ED7 N19 ED6 N18 ED5 M20 ED4 M19 ED3 L19 ED2 External data pins (ED[31:16] pins applicable to GFN package only) K19 ED0 IPU L18 ED1 I/O/Z K18 MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1) C2 I/O/Z IPU General-purpose input/output pin 4 and external interrupt 4 (I/O/Z) [default] or McASP1 mute input (I/O/Z). HD3/AMUTE1 C20 I/O/Z IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (I/O/Z). HRDY/ACLKR1 H19 I/O/Z IPU Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z). HD6/AHCLKR1 C17 I/O/Z IPU Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). HAS/ACLKX1 E18 I/O/Z IPU Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z). HD5/AHCLKX1 B18 I/O/Z IPU Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). HHWIL/AFSR1 H20 I/O/Z IPU Host half-word select ­ first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). HD2/AFSX1 D18 I/O/Z IPU Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z). HD1/AXR1[7] D20 I/O/Z IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 data pin 7 (I/O/Z). HDS1/AXR1[6] E19 I/O/Z IPU Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z). HDS2/AXR1[5] F18 I/O/Z IPU Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z). HD0/AXR1[4] E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 data pin 4 (I/O/Z). HCNTL0/AXR1[3] G18 I/O/Z IPU Host control ­ selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z). HCS/AXR1[2] F20 I/O/Z IPU Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z). HCNTL1/AXR1[1] G19 I/O/Z IPU Host control ­ selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z). HR/W/AXR1[0] G20 I/O/Z IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 49 PRODUCT PREVIEW GP[4](EXT_INT4)/ AMUTEIN1 TMS320C6713 TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS186 SPRS186 ­ DECEMBER 2001 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) C1 I/O/Z IPU General-purpose input/output pin 5 and external interrupt 5 (I/O/Z) [default] or McASP0 mute input (I/O/Z). CLKX1/AMUTE0 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (I/O/Z). CLKR0/ACLKR0 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z). TINP1/AHCLKX0 F2 I/O/Z IPD Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock (I/O/Z). CLKX0/ACLKX0 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z). CLKS0/AHCLKR0 K3 I/O/Z IPD McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z). FSR0/AFSR0 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). FSX0/AFSX0 PRODUCT PREVIEW GP[5](EXT_INT5)/ AMUTEIN0 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). FSR1/AXR0[7] M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 data pin 7 (I/O/Z). CLKR1/AXR0[6] M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 data pin 6 (I/O/Z). DX1/AXR0[5] L2 I/O/Z IPU McBSP1 rransmit data (O/Z) [default] or McASP0 data pin 5 (I/O/Z)