TMS320C6414 TMS320C6415 TMS320C6416 SPRS146M C6414/15/16 C6416 C6415/C6416 - Datasheet Archive

 

FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 D Highest-Performance Fixed-Point Digital

 

TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors (DSPs) - 2-, 1.67-, 1.39-ns Instruction Cycle Time - 500-, 600-, 720-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - Twenty-Eight Operations/Cycle - 4000, 4800, 5760 MIPS - Fully Software-Compatible With C62xTM - C6414/15/16 C6414/15/16 Devices Pin-Compatible VelociTI.2TM Extensions to VelociTITM Advanced Very-Long-Instruction-Word (VLIW) TMS320C64xTM DSP Core - Eight Highly Independent Functional Units With VelociTI.2TM Extensions: - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle - Non-Aligned Load-Store Architecture - 64 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Byte-Addressable (8-/16-/32-/64-Bit Data) - 8-Bit Overflow Protection - Bit-Field Extract, Set, Clear - Normalization, Saturation, Bit-Counting - VelociTI.2TM Increased Orthogonality Viterbi Decoder Coprocessor (VCP) [C6416 C6416] - Supports Over 600 7.95-Kbps AMR - Programmable Code Parameters Turbo Decoder Coprocessor (TCP) [C6416 C6416] - Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations) - Programmable Turbo Code and Decoding Parameters L1/L2 Memory Architecture - 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) - 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) - 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation) D Two External Memory Interfaces (EMIFs) D D D D D D D D D D D D D - One 64-Bit (EMIFA), One 16-Bit (EMIFB) - Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) - 1280M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) Host-Port Interface (HPI) - User-Configurable Bus Width (32-/16-Bit) 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 C6415/C6416 ] - Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O - Four-Wire Serial EEPROM Interface - PCI Interrupt Request Under DSP Program Control - DSP Interrupt Via PCI I/O Cycle Three Multichannel Buffered Serial Ports - Direct Interface to T1/E1, MVIP, SCSA Framers - Up to 256 Channels Each - ST-Bus-Switching-, AC97-Compatible - Serial Peripheral Interface (SPI) Compatible (MotorolaTM) Three 32-Bit General-Purpose Timers Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416 C6415/C6416] - UTOPIA Level 2 Slave ATM Controller - 8-Bit Transmit and Receive Operations up to 50 MHz per Direction - User-Defined Cell Format up to 64 Bytes Sixteen General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator IEEE-1149 IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 532-Pin Ball Grid Array (BGA) Package (GLZ and ZLZ Suffixes), 0.8-mm Ball Pitch 0.13-µm/6-Level Cu Metal Process (CMOS) 3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz) 3.3-V I/Os, 1.4-V Internal (600 and 720 MHz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright © 2005 Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 1 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 Table of Contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 GLZ and ZLZ BGA packages (bottom view) . . . . . . . . . . . . . 4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional block and CPU (DSP core) diagram . . . . . . . . . . . 8 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 9 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 15 EDMA channel synchronization events . . . . . . . . . . . . . . . . 28 interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 30 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 70 power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 73 74 75 75 76 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature . 76 77 77 78 recommended clock and control signal transition behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 parameter measurement information . . . . . . . . . . . . . . . 79 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 85 programmable synchronous interface timing . . . . . . . . 89 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 94 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 108 host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . 109 peripheral component interconnect (PCI) timing [C6415 C6415 and C6416 C6416 only] . . . . . . . . . . . . . . . . . . . . 114 multichannel buffered serial port (McBSP) timing . . . . 117 UTOPIA slave timing [C6415 C6415 and C6416 C6416 only] . . . . . . 128 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 general-purpose input/output (GPIO) port timing . . . . 132 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS146L SPRS146L device-specific data sheet to make it an SPRS146M SPRS146M revision. Scope: Applicable updates to the C64x device family, specifically relating to the C6414 C6414, C6415 C6415, and C6416 C6416 devices, have been incorporated. Added C6414 C6414, C6415 C6415, and C6416 C6416 silicon revision 2.0 devices and associated device-specific information at the production data (PD) stage of development. Changed/removed all references to the advance information (AI) stage of development to production data (PD) state of development. All devices are now at the Production Data (PD) stage of development. PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS 6 53 2 Device Characteristics: Table 1, Characteristics of the C6414 C6414, C6515 C6515, and C6416 C6416 Processors: Removed AI Product Status from C6414 C6414, C6415 C6415, and C6416 C6416 Changed "The extended temperature devices." footnote to "All devices are now at the Production Data (PD) stage of development." Terminal Functions table: Added "Following RESET, TOUTx will be configured as a general-purpose output (GPO) due to the default value of the Timerx Control Register (CTLx); therefore, an external resistor may not be used to pull the signal to the opposite supply rail" footnote POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS 64 Device Support: Device and Development-Support Tool Nomenclature section: Updated the "To designate the stages ." paragraph 65 Device Support: Figure 5, TMS320C64xTM DSP Device Nomenclature (Including the C6414 C6414, C6415 C6415, and C6416 C6416 Devices): Added "The ZLZ mechanical package designator represents ." footnote 134-135 Mechanical Data for C6414 C6414, C6415 C6415, and C6416 C6416 section: Updated title of section to include the devices Added new "Packaging Information" title Added lead-in sentence for Packaging Information title POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 3 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 GLZ and ZLZ BGA packages (bottom view) GLZ and ZLZ 532-PIN 532-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AF AD AB Y V T P M K H F D B AE AC AA W U R N L J G E C A 1 3 2 4 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 The ZLZ mechanical package designator represents the version of the GLZ package with lead-free balls. For more detailed information see the Mechanical Data section of this document. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 description The TMS320C64xTM DSPs (including the TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, and TMS320C6416 TMS320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000TM TMS320C6000TM DSP platform. The TMS320C64xTM (C64xTM) device is based on the second-generation high-performance, advanced VelociTITM very-long-instruction-word (VLIW) architecture (VelociTI.2TM) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64xTM is a code-compatible member of the C6000TM C6000TM DSP platform. With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64xTM DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2TM extensions. The VelociTI.2TM extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTITM architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000TM C6000TM DSP platform devices. The C6416 C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 600 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to forty-three 384-Kbps or seven 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller. The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port (C6415/C6416 C6415/C6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32 HPI16/HPI32); a peripheral component interconnect (PCI) [C6415/C6416 C6415/C6416 only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution. TMS320C6000 TMS320C6000, C64x, and C6000 C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. All trademarks are the property of their respective owners. Throughout the remainder of this document, the TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, and TMS320C6416 TMS320C6416 shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414 C6414, C6415 C6415, or C6416 C6416. These C64xTM devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 5 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 device characteristics Table 1 provides an overview of the C6414 C6414, C6415 C6415, and C6416 C6416 DSPs. The table shows significant features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1. Characteristics of the C6414 C6414, C6415 C6415, and C6416 C6416 Processors HARDWARE FEATURES C6414 C6414, C6415 C6415, AND C6416 C6416 EMIFA (64-bit bus width) (default clock source = AECLKIN) 1 Peripherals EMIFB (16-bit bus width) (default clock source = BECLKIN) 1 Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.) EDMA (64 independent channels) 1 HPI (32- or 16-bit user selectable) 1 (HPI16 HPI16 or HPI32 HPI32) Peripheral performance is dependent on chip-level configuration. PCI (32-bit) [DeviceID Register value 0xA106] 1 [C6415/C6416 C6415/C6416 only] McBSPs (default internal clock source = CPU/4 clock frequency) 3 UTOPIA (8-bit mode) 1 [C6415/C6416 C6415/C6416 only] 3 General-Purpose Input/Output 0 (GP0) Decoder Coprocessors 32-Bit Timers (default internal clock source = CPU/8 clock frequency) 16 VCP 1 (C6416 C6416 only) TCP 1 (C6416 C6416 only) Size (Bytes) On-Chip Memory 1056K 1056K 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 1024KB 1024KB Unified Mapped RAM/Cache (L2) Organization CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) Device_ID Silicon Revision Identification Register (DEVICE_REV [19:16]) Address: 0x01B0 0200 Frequency MHz Cycle Time Voltage 0x0C01 DEVICE_REV[19:16] 1111 0001 0010 or 0000 0011 Silicon Revision 1.03 or earlier 1.03 1.1 2.0 500, 600, 720 2 ns (C6414-5E0 C6414-5E0, C6415-5E0 C6415-5E0, C6416-5E0 C6416-5E0) and (C6414A-5E0 C6414A-5E0, C6415A-5E0 C6415A-5E0, C6416A-5E0 C6416A-5E0) [500-MHz CPU, 100-MHz EMIF] 1.67 ns (C6414-6E3 C6414-6E3, C6415-6E3 C6415-6E3, C6416-6E3 C6416-6E3) and (C6414A-6E3 C6414A-6E3, C6415A-6E3 C6415A-6E3, C6416A-6E3 C6416A-6E3) [600-MHz CPU, 133-MHz EMIFA] 1.39 ns (C6414-7E3 C6414-7E3, C6415-7E3 C6415-7E3, C6416-7E3 C6416-7E3) [720-MHz CPU, 133-MHz EMIFA] ns 1.2 V (-5E0) 1.25 V (A-5E0) 1.4 V (-6E3, A-6E3, -7E3) Core (V) I/O (V) 3.3 V PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12 BGA Package 23 x 23 mm Process Technology µm Product Status Product Preview (PP), Advance Information (AI), Production Data (PD) 532-Pin BGA (GLZ and ZLZ) 0.13 µm PD On these C64xTM devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the EMIF Device Speed section of this data sheet. All devices are now at the Production Data (PD) stage of development. 6 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 device compatibility The C64xTM generation of devices has a diverse and powerful set of peripherals. The common peripheral set and pin-compatibility that the C6414 C6414, C6415 C6415, and C6416 C6416 devices offer lead to easier system designs and faster time to market. Table 2 identifies the peripherals and coprocessors that are available on the C6414 C6414, C6415 C6415, and C6416 C6416 devices. The C6414 C6414, C6415 C6415, and C6416 C6416 devices are pin-for-pin compatible, provided the following conditions are met: D All devices are using the same peripherals. The C6414 C6414 is pin-for-pin compatible with the C6415/C6416 C6415/C6416 when the PCI and UTOPIA peripherals on the C6415/C6416 C6415/C6416 are disabled. The C6415 C6415 is pin-for-pin compatible with the C6416 C6416 when they are in the same peripheral selection mode. [For more information on peripheral selection, see the Device Configurations section of this data sheet.] D The BEA[9:7] pins are properly pulled up/down. [For more details on the device-specific BEA[9:7] pin configurations, see the Terminal Functions table of this data sheet.] Table 2. Peripherals and Coprocessors Available on the C6414 C6414, C6415 C6415, and C6416 C6416 Devices PERIPHERALS/COPROCESSORS C6414 C6414 C6415 C6415 C6416 C6416 EMIFA (64-bit bus width) EMIFB (16-bit bus width) EDMA (64 independent channels) HPI (32- or 16-bit user selectable) PCI (32-bit) [Specification v2.2] - McBSPs (McBSP0, McBSP1, McBSP2) UTOPIA (8-bit mode) [Specification v1.0] - Timers (32-bit) [TIMER0, TIMER1, TIMER2] GPIOs (GP[15:0]) VCP/TCP Coprocessors - - - denotes peripheral/coprocessor is not available on this device. Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.) For more detailed information on the device compatibility and similarities/differences among the C6414 C6414, C6415 C6415, and C6416 C6416 devices, see the How To Begin Development Today With the TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, and TMS320C6416 TMS320C6416 DSPs application report (literature number SPRA718 SPRA718). POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 7 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 functional block and CPU (DSP core) diagram C64x Digital Signal Processor VCP L1P Cache Direct-Mapped 16K Bytes Total TCP SDRAM 64 SBSRAM 16 EMIF A EMIF B C64x DSP Core ZBT SRAM Instruction Fetch Timer 2 FIFO SRAM Control Registers Instruction Dispatch Advanced Instruction Packet Timer 1 ROM/FLASH Control Logic Instruction Decode Timer 0 I/O Devices Data Path A A Register File A31-A16 A31-A16 A15-A0 A15-A0 McBSP2 .L1 UTOPIA UTOPIA: Up to 400 Mbps Master ATMC or McBSPs: Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs Enhanced DMA Controller (64-channel) .S1 .M1 .D1 Data Path B B Register File B31-B16 B31-B16 B15-B0 B15-B0 .D2 .M2 .S2 Test Advanced In-Circuit Emulation .L2 L2 Memory 1024K 1024K Bytes Interrupt Control McBSP1 L1D Cache 2-Way Set-Associative 16K Bytes Total McBSP0 16 GPIO[8:0] GPIO[15:9] 32 HPI or PCI Boot Configuration PLL (x1, x6, x12) Power-Down Logic Interrupt Selector 8 VCP and TCP decoder coprocessors are applicable to the C6416 C6416 device only. For the C6415 C6415 and C6416 C6416 devices, the UTOPIA peripheral is muxed with McBSP1, and the PCI peripheral is muxed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 CPU (DSP core) description The CPU fetches VelociTITM advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTITM VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64xTM VelociTI.2TM extensions add enhancements to the TMS320C62xTM DSP VelociTITM architecture. These enhancements include: D D D D D D Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62xTM VelociTITM VLIW architecture, the C64xTM register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a "data cross path"-a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62xTM DSP fixed-point instructions, the C64xTM DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2TM extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically "true"). TMS320C62x is a trademark of Texas Instruments. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 9 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 CPU (DSP core) description (continued) The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64xTM DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62xTM/TMS320C67xTM DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64xTM DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: The TMS320C6000 TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189 SPRU189) TMS320C64x Technical Overview (literature number SPRU395 SPRU395) How To Begin Development Today With the TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, and TMS320C6416 TMS320C6416 DSPs application report (literature number SPRA718 SPRA718) TMS320C67x is a trademark of Texas Instruments. 10 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 CPU (DSP core) description (continued) src1 .L1 ST1b (Store Data) ST1a (Store Data) 32 MSBs 32 LSBs src2 dst long dst long src long src long dst dst .S1 src1 Data Path A 8 8 8 8 Register File A (A0-A31 A0-A31) src2 See Note A See Note A long dst dst .M1 src1 src2 LD1b (Load Data) LD1a (Load Data) 32 MSBs 32 LSBs DA1 (Address) .D1 dst src1 src2 2X 1X .D2 DA2 (Address) LD2a (Load Data) LD2b (Load Data) src2 src1 dst 32 LSBs 32 MSBs src2 .M2 src1 dst See Note A See Note A long dst Register File B (B0- B31) src2 Data Path B .S2 src1 dst long dst long src ST2a (Store Data) ST2b (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst 8 8 .L2 src2 src1 Control Register File NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs. Figure 1. TMS320C64xTM CPU (DSP Core) Data Paths POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 11 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 memory map summary Table 3 shows the memory map address ranges of the TMS320C64x device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the C64x device begin at the hex address locations 0x6000 0000 for EMIFB and 0x8000 0000 for EMIFA. 12 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 memory map summary (continued) Table 3. TMS320C64x Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) Internal RAM (L2) 1M Reserved 23M External Memory Interface A (EMIFA) Registers 256K L2 Registers 256K HPI Registers 256K McBSP 0 Registers 256K McBSP 1 Registers 256K Timer 0 Registers 256K Timer 1 Registers 256K Interrupt Selector Registers 256K EDMA RAM and EDMA Registers 256K McBSP 2 Registers 256K EMIFB Registers 256K Timer 2 Registers 256K GPIO Registers 256K UTOPIA Registers (C6415 C6415 and C6416 C6416 only) 256K TCP/VCP Registers (C6416 C6416 only) 256K Reserved 256K PCI Registers (C6415 C6415 and C6416 C6416 only) 256K Reserved 4M ­ 256K QDMA Registers 52 Reserved 736M ­ 52 McBSP 0 Data 64M McBSP 1 Data 64M McBSP 2 Data UTOPIA Queues (C6415 C6415 and C6416 C6416 64M only) 64M Reserved 256M TCP/VCP (C6416 C6416 only) 256M EMIFB CE0 64M EMIFB CE1 64M EMIFB CE2 64M EMIFB CE3 64M Reserved 256M EMIFA CE0 256M EMIFA CE1 256M EMIFA CE2 256M EMIFA CE3 256M Reserved 1G HEX ADDRESS RANGE 0000 0010 0180 0184 0188 018C 0190 0194 0198 019C 01A0 01A4 01A8 01AC 01B0 01B4 01B8 01BC 01C0 01C4 0200 0200 3000 3400 3800 3C00 4000 5000 6000 6400 6800 6C00 7000 8000 9000 A000 B000 C000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0034 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ 000F 017F 0183 0187 018B 018F 0193 0197 019B 019F 01A3 01A7 01AB 01AF 01B3 01B7 01BB 01BF 01C3 01FF 0200 2FFF 33FF 37FF 3BFF 3FFF 4FFF 5FFF 63FF 67FF 6BFF 6FFF 7FFF 8FFF 9FFF AFFF BFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0033 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF For the C6414 C6414 device, these memory address locations are reserved. The C6414 C6414 device does not support the UTOPIA and PCI peripherals. Only the C6416 C6416 device supports the VCP/TCP Coprocessors. For the C6414 C6414 and C6415 C6415 devices, these memory address locations are reserved. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 13 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 L2 architecture expanded Figure 2 shows the detail of the L2 architecture on the TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, and TMS320C6416 TMS320C6416 devices. For more information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610 SPRU610). L2MODE 000 001 010 L2 Memory 011 Block Base Address 111 768K SRAM 896K SRAM 960K SRAM 992K SRAM 768K-Byte SRAM ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ 1024K 1024K SRAM (All) 0x0000 0000 0x000C 0000 256K Cache (4 Way) 128K Cache (4 Way) 64K Cache (4 Way) 32K Cache (4 Way) 128K-Byte RAM 0x000E 0000 64K-Byte RAM 0x000F 0000 32K-Byte RAM 0x000F 8000 32K-Byte RAM 0x000F FFFF Figure 2. TMS320C6414/C6415/C6416 TMS320C6414/C6415/C6416 L2 Architecture Memory Configuration 14 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions Table 4 through Table 23 identify the peripheral registers for the C6414 C6414, C6415 C6415, and C6416 C6416 devices by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190 SPRU190). Table 4. EMIFA Registers HEX ADDRESS RANGE ACRONYM 0180 0000 GBLCTL EMIFA global control REGISTER NAME 0180 0004 CECTL1 EMIFA CE1 space control 0180 0008 CECTL0 EMIFA CE0 space control 0180 000C - 0180 0010 CECTL2 EMIFA CE2 space control 0180 0014 CECTL3 EMIFA CE3 space control 0180 0018 SDCTL EMIFA SDRAM control 0180 001C SDTIM EMIFA SDRAM refresh control 0180 0020 SDEXT EMIFA SDRAM extension 0180 0024 - 0180 003C - 0180 0040 PDTCTL Peripheral device transfer (PDT) control 0180 0044 CESEC1 EMIFA CE1 space secondary control 0180 0048 CESEC0 EMIFA CE0 space secondary control Reserved Reserved 0180 004C - 0180 0050 CESEC2 Reserved EMIFA CE2 space secondary control 0180 0054 CESEC3 EMIFA CE3 space secondary control 0180 0058 - 0183 FFFF ­ Reserved Table 5. EMIFB Registers HEX ADDRESS RANGE ACRONYM 01A8 0000 GBLCTL EMIFB global control REGISTER NAME 01A8 0004 CECTL1 EMIFB CE1 space control 01A8 0008 CECTL0 EMIFB CE0 space control 01A8 000C - 01A8 0010 CECTL2 EMIFB CE2 space control 01A8 0014 CECTL3 EMIFB CE3 space control 01A8 0018 SDCTL EMIFB SDRAM control 01A8 001C SDTIM EMIFB SDRAM refresh control 01A8 0020 SDEXT EMIFB SDRAM extension 01A8 0024 - 01A8 003C - 01A8 0040 PDTCTL Peripheral device transfer (PDT) control 01A8 0044 CESEC1 EMIFB CE1 space secondary control 01A8 0048 CESEC0 EMIFB CE0 space secondary control 01A8 004C - 01A8 0050 CESEC2 EMIFB CE2 space secondary control 01A8 0054 CESEC3 EMIFB CE3 space secondary control 01A8 0058 - 01AB FFFF ­ Reserved Reserved Reserved Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 15 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 6. L2 Cache Registers HEX ADDRESS RANGE ACRONYM 0184 0000 CCFG 0184 0004 - 0184 0FFC - REGISTER NAME Cache configuration register Reserved 0184 1000 EDMAWEIGHT 0184 1004 - 0184 1FFC - L2 EDMA access control register 0184 2000 L2ALLOC0 L2 allocation register 0 0184 2004 L2ALLOC1 L2 allocation register 1 0184 2008 L2ALLOC2 L2 allocation register 2 L2 allocation register 3 Reserved 0184 200C L2ALLOC3 0184 2010 - 0184 3FFC - 0184 4000 L2WBAR L2 writeback base address register 0184 4004 L2WWC L2 writeback word count register 0184 4010 L2WIBAR L2 writeback invalidate base address register 0184 4014 L2WIWC L2 writeback invalidate word count register 0184 4018 L2IBAR L2 invalidate base address register 0184 401C L2IWC L2 invalidate word count register 0184 4020 L1PIBAR L1P invalidate base address register 0184 4024 L1PIWC L1P invalidate word count register 0184 4030 L1DWIBAR L1D writeback invalidate base address register 0184 4034 L1DWIWC L1D writeback invalidate word count register 0184 4038 - 0184 4044 - Reserved Reserved 0184 4048 L1DIBAR L1D invalidate base address register 0184 404C L1DIWC L1D invalidate word count register 0184 4050 - 0184 4FFC - 0184 5000 L2WB 0184 5004 L2WBINV Reserved L2 writeback all register L2 writeback invalidate all register 0184 5008 - 0184 7FFC Reserved 0184 8000 - 0184 817C Reserved 0184 8180 MAR96 MAR96 Controls EMIFB CE0 range 6000 0000 - 60FF FFFF 0184 8184 MAR97 MAR97 Controls EMIFB CE0 range 6100 0000 - 61FF FFFF 0184 8188 MAR98 MAR98 Controls EMIFB CE0 range 6200 0000 - 62FF FFFF 0184 818C MAR99 MAR99 Controls EMIFB CE0 range 6300 0000 - 63FF FFFF 0184 8190 MAR100 MAR100 Controls EMIFB CE1 range 6400 0000 - 64FF FFFF 0184 8194 MAR101 MAR101 Controls EMIFB CE1 range 6500 0000 - 65FF FFFF 0184 8198 MAR102 MAR102 Controls EMIFB CE1 range 6600 0000 - 66FF FFFF 0184 819C MAR103 MAR103 Controls EMIFB CE1 range 6700 0000 - 67FF FFFF 0184 81A0 MAR104 MAR104 Controls EMIFB CE2 range 6800 0000 - 68FF FFFF 0184 81A4 MAR105 MAR105 Controls EMIFB CE2 range 6900 0000 - 69FF FFFF 0184 81A8 MAR106 MAR106 Controls EMIFB CE2 range 6A00 0000 - 6AFF FFFF 0184 81AC 16 - MAR0 to MAR95 MAR95 MAR107 MAR107 Controls EMIFB CE2 range 6B00 0000 - 6BFF FFFF POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 COMMENTS TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 6. L2 Cache Registers (Continued) HEX ADDRESS RANGE ACRONYM 0184 81B0 MAR108 MAR108 Controls EMIFB CE3 range 6C00 0000 - 6CFF FFFF REGISTER NAME 0184 81B4 MAR109 MAR109 Controls EMIFB CE3 range 6D00 0000 - 6DFF FFFF 0184 81B8 MAR110 MAR110 Controls EMIFB CE3 range 6E00 0000 - 6EFF FFFF 0184 81BC MAR111 MAR111 Controls EMIFB CE3 range 6F00 0000 - 6FFF FFFF 0184 81C0 - 0184 81FC MAR112 MAR112 to MAR127 MAR127 0184 8200 MAR128 MAR128 Controls EMIFA CE0 range 8000 0000 - 80FF FFFF 0184 8204 MAR129 MAR129 Controls EMIFA CE0 range 8100 0000 - 81FF FFFF 0184 8208 MAR130 MAR130 Controls EMIFA CE0 range 8200 0000 - 82FF FFFF 0184 820C MAR131 MAR131 Controls EMIFA CE0 range 8300 0000 - 83FF FFFF 0184 8210 MAR132 MAR132 Controls EMIFA CE0 range 8400 0000 - 84FF FFFF 0184 8214 MAR133 MAR133 COMMENTS Controls EMIFA CE0 range 8500 0000 - 85FF FFFF Reserved 0184 8218 MAR134 MAR134 Controls EMIFA CE0 range 8600 0000 - 86FF FFFF 0184 821C MAR135 MAR135 Controls EMIFA CE0 range 8700 0000 - 87FF FFFF 0184 8220 MAR136 MAR136 Controls EMIFA CE0 range 8800 0000 - 88FF FFFF 0184 8224 MAR137 MAR137 Controls EMIFA CE0 range 8900 0000 - 89FF FFFF 0184 8228 MAR138 MAR138 Controls EMIFA CE0 range 8A00 0000 - 8AFF FFFF 0184 822C MAR139 MAR139 Controls EMIFA CE0 range 8B00 0000 - 8BFF FFFF 0184 8230 MAR140 MAR140 Controls EMIFA CE0 range 8C00 0000 - 8CFF FFFF 0184 8234 MAR141 MAR141 Controls EMIFA CE0 range 8D00 0000 - 8DFF FFFF 0184 8238 MAR142 MAR142 Controls EMIFA CE0 range 8E00 0000 - 8EFF FFFF 0184 823C MAR143 MAR143 Controls EMIFA CE0 range 8F00 0000 - 8FFF FFFF 0184 8240 MAR144 MAR144 Controls EMIFA CE1 range 9000 0000 - 90FF FFFF 0184 8244 MAR145 MAR145 Controls EMIFA CE1 range 9100 0000 - 91FF FFFF 0184 8248 MAR146 MAR146 Controls EMIFA CE1 range 9200 0000 - 92FF FFFF 0184 824C MAR147 MAR147 Controls EMIFA CE1 range 9300 0000 - 93FF FFFF 0184 8250 MAR148 MAR148 Controls EMIFA CE1 range 9400 0000 - 94FF FFFF 0184 8254 MAR149 MAR149 Controls EMIFA CE1 range 9500 0000 - 95FF FFFF 0184 8258 MAR150 MAR150 Controls EMIFA CE1 range 9600 0000 - 96FF FFFF 0184 825C MAR151 MAR151 Controls EMIFA CE1 range 9700 0000 - 97FF FFFF 0184 8260 MAR152 MAR152 Controls EMIFA CE1 range 9800 0000 - 98FF FFFF 0184 8264 MAR153 MAR153 Controls EMIFA CE1 range 9900 0000 - 99FF FFFF 0184 8268 MAR154 MAR154 Controls EMIFA CE1 range 9A00 0000 - 9AFF FFFF 0184 826C MAR155 MAR155 Controls EMIFA CE1 range 9B00 0000 - 9BFF FFFF 0184 8270 MAR156 MAR156 Controls EMIFA CE1 range 9C00 0000 - 9CFF FFFF 0184 8274 MAR157 MAR157 Controls EMIFA CE1 range 9D00 0000 - 9DFF FFFF 0184 8278 MAR158 MAR158 Controls EMIFA CE1 range 9E00 0000 - 9EFF FFFF 0184 827C MAR159 MAR159 Controls EMIFA CE1 range 9F00 0000 - 9FFF FFFF 0184 8280 MAR160 MAR160 Controls EMIFA CE2 range A000 0000 - A0FF FFFF 0184 8284 MAR161 MAR161 Controls EMIFA CE2 range A100 0000 - A1FF FFFF 0184 8288 MAR162 MAR162 Controls EMIFA CE2 range A200 0000 - A2FF FFFF 0184 828C MAR163 MAR163 Controls EMIFA CE2 range A300 0000 - A3FF FFFF 0184 8290 MAR164 MAR164 Controls EMIFA CE2 range A400 0000 - A4FF FFFF POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 17 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 6. L2 Cache Registers (Continued) HEX ADDRESS RANGE ACRONYM 0184 8294 MAR165 MAR165 Controls EMIFA CE2 range A500 0000 - A5FF FFFF REGISTER NAME 0184 8298 MAR166 MAR166 Controls EMIFA CE2 range A600 0000 - A6FF FFFF 0184 829C MAR167 MAR167 Controls EMIFA CE2 range A700 0000 - A7FF FFFF 0184 82A0 MAR168 MAR168 Controls EMIFA CE2 range A800 0000 - A8FF FFFF 0184 82A4 MAR169 MAR169 Controls EMIFA CE2 range A900 0000 - A9FF FFFF 0184 82A8 MAR170 MAR170 Controls EMIFA CE2 range AA00 0000 - AAFF FFFF 0184 82AC MAR171 MAR171 Controls EMIFA CE2 range AB00 0000 - ABFF FFFF 0184 82B0 MAR172 MAR172 Controls EMIFA CE2 range AC00 0000 - ACFF FFFF 0184 82B4 MAR173 MAR173 Controls EMIFA CE2 range AD00 0000 - ADFF FFFF 0184 82B8 MAR174 MAR174 Controls EMIFA CE2 range AE00 0000 - AEFF FFFF 0184 82BC MAR175 MAR175 Controls EMIFA CE2 range AF00 0000 - AFFF FFFF 0184 82C0 MAR176 MAR176 Controls EMIFA CE3 range B000 0000 - B0FF FFFF 0184 82C4 MAR177 MAR177 Controls EMIFA CE3 range B100 0000 - B1FF FFFF 0184 82C8 MAR178 MAR178 Controls EMIFA CE3 range B200 0000 - B2FF FFFF 0184 82CC MAR179 MAR179 Controls EMIFA CE3 range B300 0000 - B3FF FFFF 0184 82D0 MAR180 MAR180 Controls EMIFA CE3 range B400 0000 - B4FF FFFF 0184 82D4 MAR181 MAR181 Controls EMIFA CE3 range B500 0000 - B5FF FFFF 0184 82D8 Controls EMIFA CE3 range B600 0000 - B6FF FFFF MAR183 MAR183 Controls EMIFA CE3 range B700 0000 - B7FF FFFF 0184 82E0 MAR184 MAR184 Controls EMIFA CE3 range B800 0000 - B8FF FFFF 0184 82E4 MAR185 MAR185 Controls EMIFA CE3 range B900 0000 - B9FF FFFF 0184 82E8 MAR186 MAR186 Controls EMIFA CE3 range BA00 0000 - BAFF FFFF 0184 82EC MAR187 MAR187 Controls EMIFA CE3 range BB00 0000 - BBFF FFFF 0184 82F0 MAR188 MAR188 Controls EMIFA CE3 range BC00 0000 - BCFF FFFF 0184 82F4 MAR189 MAR189 Controls EMIFA CE3 range BD00 0000 - BDFF FFFF 0184 82F8 MAR190 MAR190 Controls EMIFA CE3 range BE00 0000 - BEFF FFFF 0184 82FC MAR191 MAR191 Controls EMIFA CE3 range BF00 0000 - BFFF FFFF 0184 8300 - 0184 83FC MAR192 MAR192 to MAR255 MAR255 Reserved 0184 8400 - 0187 FFFF 18 MAR182 MAR182 0184 82DC - Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 COMMENTS TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 7. EDMA Registers HEX ADDRESS RANGE ACRONYM 01A0 FF9C EPRH Event polarity high register REGISTER NAME 01A0 FFA4 CIPRH Channel interrupt pending high register 01A0 FFA8 CIERH Channel interrupt enable high register 01A0 FFAC CCERH Channel chain enable high register 01A0 FFB0 ERH 01A0 FFB4 EERH Event enable high register Event high register 01A0 FFB8 ECRH Event clear high register 01A0 FFBC ESRH Event set high register 01A0 FFC0 PQAR0 Priority queue allocation register 0 01A0 FFC4 PQAR1 Priority queue allocation register 1 01A0 FFC8 PQAR2 Priority queue allocation register 2 01A0 FFCC PQAR3 Priority queue allocation register 3 01A0 FFDC EPRL Event polarity low register 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPRL Channel interrupt pending low register 01A0 FFE8 CIERL Channel interrupt enable low register 01A0 FFEC CCERL Channel chain enable low register 01A0 FFF0 ERL 01A0 FFF4 EERL Event enable low register Event low register 01A0 FFF8 ECRL Event clear low register 01A0 FFFC ESRL Event set low register 01A1 0000 - 01A3 FFFF ­ Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 19 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 8. EDMA Parameter RAM HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0000 - 01A0 0017 - Parameters for Event 0 (6 words) 01A0 0018 - 01A0 002F - Parameters for Event 1 (6 words) 01A0 0030 - 01A0 0047 - Parameters for Event 2 (6 words) 01A0 0048 - 01A0 005F - Parameters for Event 3 (6 words) 01A0 0060 - 01A0 0077 - Parameters for Event 4 (6 words) 01A0 0078 - 01A0 008F - Parameters for Event 5 (6 words) 01A0 0090 - 01A0 00A7 - Parameters for Event 6 (6 words) 01A0 00A8 - 01A0 00BF - Parameters for Event 7 (6 words) 01A0 00C0 - 01A0 00D7 - Parameters for Event 8 (6 words) 01A0 00D8 - 01A0 00EF - Parameters for Event 9 (6 words) 01A0 00F0 - 01A0 00107 - Parameters for Event 10 (6 words) 01A0 0108 - 01A0 011F - Parameters for Event 11 (6 words) 01A0 0120 - 01A0 0137 - Parameters for Event 12 (6 words) 01A0 0138 - 01A0 014F - Parameters for Event 13 (6 words) 01A0 0150 - 01A0 0167 - Parameters for Event 14 (6 words) 01A0 0168 - 01A0 017F - Parameters for Event 15 (6 words) 01A0 0150 - 01A0 0167 - Parameters for Event 16 (6 words) 01A0 0168 - 01A0 017F - Parameters for Event 17 (6 words) . . . . 01A0 05D0 - 01A0 05E7 - Parameters for Event 62 (6 words) 01A0 05E8 - 01A0 05FF - Parameters for Event 63 (6 words) 01A0 0600 - 01A0 0617 - Reload/link parameters for Event M (6 words) 01A0 0618 - 01A0 062F - Reload/link parameters for Event N (6 words) . . 01A0 07E0 - 01A0 07F7 - Reload/link parameters for Event Z (6 words) 01A0 07F8 - 01A0 07FF COMMENTS - Scratch pad area (2 words) The C6414/C6415/C6416 C6414/C6415/C6416 device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers. Table 9. Quick DMA (QDMA) and Pseudo Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0200 0000 QOPT QDMA options parameter register 0200 0004 QSRC QDMA source address register 0200 0008 QCNT QDMA frame count register 0200 000C QDST QDMA destination address register 0200 0010 QIDX QDMA index register 0200 0014 - 0200 001C Reserved 0200 0020 QSOPT QDMA pseudo options register 0200 0024 QSSRC QDMA pseudo source address register 0200 0028 QDMA pseudo frame count register QSDST QDMA pseudo destination address register 0200 0030 20 QSCNT 0200 002C QSIDX QDMA pseudo index register POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 10. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10-15 (INT10-INT15 INT10-INT15) 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4-9 (INT04-INT09 INT04-INT09) 019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts (EXT_INT4-EXT_INT7) 019C 000C - 019C 01FF - Reserved Table 11. McBSP 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 018C 0000 DRR0 McBSP0 data receive register via Configuration Bus 0x3000 0000 - 0x33FF FFFF DRR0 McBSP0 data receive register via Peripheral Bus 018C 0004 DXR0 McBSP0 data transmit register via Configuration Bus 0x3000 0000 - 0x33FF FFFF DXR0 McBSP0 data transmit register via Peripheral Bus 018C 0008 SPCR0 018C 000C RCR0 McBSP0 receive control register 018C 0010 XCR0 McBSP0 transmit control register 018C 0014 SRGR0 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. McBSP0 serial port control register McBSP0 sample rate generator register 018C 0018 MCR0 018C 001C RCERE00 RCERE00 McBSP0 multichannel control register McBSP0 enhanced receive channel enable register 0 018C 0020 XCERE00 XCERE00 McBSP0 enhanced transmit channel enable register 0 018C 0024 PCR0 018C 0028 RCERE10 RCERE10 McBSP0 enhanced receive channel enable register 1 018C 002C XCERE10 XCERE10 McBSP0 enhanced transmit channel enable register 1 018C 0030 RCERE20 RCERE20 McBSP0 enhanced receive channel enable register 2 018C 0034 XCERE20 XCERE20 McBSP0 enhanced transmit channel enable register 2 McBSP0 pin control register 018C 0038 RCERE30 RCERE30 McBSP0 enhanced receive channel enable register 3 018C 003C XCERE30 XCERE30 McBSP0 enhanced transmit channel enable register 3 018C 0040 - 018F FFFF ­ Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 21 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 12. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0190 0000 DRR1 McBSP1 data receive register via Configuration Bus 0x3400 0000 - 0x37FF FFFF DRR1 McBSP1 data receive register via Peripheral Bus 0190 0004 DXR1 McBSP1 data transmit register via Configuration Bus 0x3400 0000 - 0x37FF FFFF DXR1 McBSP1 data transmit register via Peripheral Bus 0190 0008 SPCR1 0190 000C RCR1 McBSP1 receive control register 0190 0010 XCR1 McBSP1 transmit control register 0190 0014 SRGR1 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. McBSP1 serial port control register McBSP1 sample rate generator register 0190 0018 MCR1 0190 001C RCERE01 RCERE01 McBSP1 multichannel control register McBSP1 enhanced receive channel enable register 0 0190 0020 XCERE01 XCERE01 McBSP1 enhanced transmit channel enable register 0 0190 0024 PCR1 0190 0028 RCERE11 RCERE11 McBSP1 enhanced receive channel enable register 1 0190 002C XCERE11 XCERE11 McBSP1 enhanced transmit channel enable register 1 0190 0030 RCERE21 RCERE21 McBSP1 enhanced receive channel enable register 2 0190 0034 XCERE21 XCERE21 McBSP1 enhanced transmit channel enable register 2 McBSP1 pin control register 0190 0038 RCERE31 RCERE31 McBSP1 enhanced receive channel enable register 3 0190 003C XCERE31 XCERE31 McBSP1 enhanced transmit channel enable register 3 0190 0040 - 0193 FFFF ­ Reserved Table 13. McBSP 2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A4 0000 DRR2 McBSP2 data receive register via Configuration Bus 0x3800 0000 - 0x3BFF FFFF DRR2 McBSP2 data receive register via Peripheral Bus 01A4 0004 DXR2 McBSP2 data transmit register via Configuration Bus 0x3800 0000 - 0x3BFF FFFF DXR2 McBSP2 data transmit register via Peripheral Bus 01A4 0008 SPCR2 01A4 000C RCR2 McBSP2 receive control register 01A4 0010 XCR2 McBSP2 transmit control register 01A4 0014 SRGR2 McBSP2 serial port control register McBSP2 sample rate generator register 01A4 0018 MCR2 01A4 001C RCERE02 RCERE02 McBSP2 multichannel control register McBSP2 enhanced receive channel enable register 0 01A4 0020 XCERE02 XCERE02 McBSP2 enhanced transmit channel enable register 0 01A4 0024 PCR2 01A4 0028 RCERE12 RCERE12 McBSP2 enhanced receive channel enable register 1 01A4 002C XCERE12 XCERE12 McBSP2 enhanced transmit channel enable register 1 01A4 0030 RCERE22 RCERE22 McBSP2 enhanced receive channel enable register 2 01A4 0034 XCERE22 XCERE22 McBSP2 enhanced transmit channel enable register 2 McBSP2 pin control register 01A4 0038 McBSP2 enhanced receive channel enable register 3 XCERE32 XCERE32 McBSP2 enhanced transmit channel enable register 3 01A4 0040 - 01A7 FFFF 22 RCERE32 RCERE32 01A4 003C ­ Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 14. Timer 0 Registers HEX ADDRESS RANGE ACRONYM 0194 0000 CTL0 REGISTER NAME COMMENTS Timer 0 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0194 0004 PRD0 Timer 0 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter. 0194 000C - 0197 FFFF - Reserved Table 15. Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0198 0000 CTL1 Timer 1 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0198 0004 PRD1 Timer 1 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter. 0198 000C - 019B FFFF - Reserved Table 16. Timer 2 Registers HEX ADDRESS RANGE 01AC 0000 ACRONYM CTL2 REGISTER NAME COMMENTS Timer 2 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 01AC 0004 PRD2 Timer 2 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 01AC 0008 CNT2 Timer 2 counter register Contains the current value of the incrementing counter. 01AC 000C - 01AF FFFF - Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 23 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 17. HPI Registers HEX ADDRESS RANGE - HPID HPI data register Host read/write access only 0188 0000 HPIC HPI control register HPIC has both Host/CPU read/write access 0188 0004 HPIA (HPIAW) HPI address register (Write) 0188 0008 HPIA (HPIAR) HPI address register (Read) 0188 000C - 0189 FFFF - 018A 0000 TRCTL 018A 0004 - 018B FFFF ACRONYM REGISTER NAME COMMENTS - HPIA has both Host/CPU read/write access Reserved HPI transfer request control register Reserved Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently. Table 18. GPIO Registers HEX ADDRESS RANGE GPEN GPIO enable register 01B0 0004 GPDIR GPIO direction register 01B0 0008 GPVAL GPIO value register 01B0 000C - 01B0 0010 GPDH GPIO delta high register 01B0 0014 GPHM GPIO high mask register 01B0 0018 GPDL GPIO delta low register 01B0 001C GPLM GPIO low mask register 01B0 0020 GPGC GPIO global control register 01B0 0024 GPPOL GPIO interrupt polarity register 01B0 0028 - 01B0 01FF - 01B0 0200 DEVICE_REV 01B0 0204 - 01B3 FFFF 24 ACRONYM 01B0 0000 REGISTER NAME - Reserved Reserved Silicon Revision Identification Register (For more details, see the device characteristics listed in Table 1.) Reserved POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 19. PCI Peripheral Registers (C6415 C6415 and C6416 C6416 Only) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C0 0000 RSTSRC 01C0 0004 - 01C0 0008 PCIIS PCI interrupt source register 01C0 000C PCIIEN PCI interrupt enable register 01C0 0010 DSPMA DSP master address register 01C0 0014 PCIMA PCI master address register 01C0 0018 PCIMC PCI master control register 01C0 001C CDSPA Current DSP address register 01C0 0020 CPCIA Current PCI address register 01C0 0024 CCNT Current byte count register 01C0 0028 - Reserved 01C0 002C - 01C1 FFEF ­ Reserved 0x01C1 FFF0 HSR 0x01C1 FFF4 HDCR Host-to-DSP control register DSP page register DSP Reset source/status register Reserved Host status register 0x01C1 FFF8 - 01C2 0000 EEADD EEPROM address register 01C2 0004 EEDAT EEPROM data register 01C2 0008 EECTL EEPROM control register 01C2 000C - 01C2 FFFF ­ 01C3 0000 TRCTL 01C3 0004 - 01C3 FFFF DSPP 0x01C1 FFFC ­ Reserved Reserved PCI transfer request control register Reserved These PCI registers are not supported on the C6414 C6414 device. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 25 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 20. UTOPIA (C6415 C6415 and C6416 C6416 Only) HEX ADDRESS RANGE 01B4 0000 UCR 01B4 0004 - Reserved 01B4 0008 - Reserved 01B4 000C UIER UTOPIA interrupt enable register 01B4 0010 UIPR UTOPIA interrupt pending register 01B4 0014 CDR Clock detect register 01B4 0018 EIER Error interrupt enable register 01B4 001C EIPR Error interrupt pending register 01B4 0020 - 01B7 FFFF ACRONYM REGISTER NAME - UTOPIA control register Reserved These UTOPIA registers are not supported on the C6414 C6414 device. Table 21. UTOPIA QUEUES (C6415 C6415 and C6416 C6416 Only) HEX ADDRESS RANGE URQ UTOPIA receive queue 3D00 0000 UXQ UTOPIA transmit queue 3D00 0004 - 3FFF FFFF ACRONYM 3C00 0000 REGISTER NAME - Reserved These UTOPIA registers are not supported on the C6414 C6414 device. 26 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 peripheral register descriptions (continued) Table 22. VCP Registers (C6416 C6416 Only) EDMA BUS HEX ADDRESS RANGE ACRONYM 5000 0000 01B8 0000 VCPIC0 VCP input configuration register 0 5000 0004 01B8 0004 VCPIC1 VCP input configuration register 1 5000 0008 01B8 0008 VCPIC2 VCP input configuration register 2 5000 000C 01B8 000C VCPIC3 VCP input configuration register 3 5000 0010 01B8 0010 VCPIC4 VCP input configuration register 4 5000 0014 01B8 0014 VCPIC5 VCP input configuration register 5 5000 0040 01B8 0024 VCPOUT0 VCP output register 0 5000 0044 01B8 0028 VCPOUT1 VCP output register 1 5000 0080 - VCPWBM VCP branch metrics write register 5000 0088 - VCPRDECS - 01B8 0018 VCPEXE VCP execution register - 01B8 0020 VCPEND VCP endian register - 01B8 0040 VCPSTAT0 VCP status register 0 - 01B8 0044 VCPSTAT1 VCP status register 1 - PERIPHERAL BUS HEX ADDRESS RANGE 01B8 0050 VCPERR REGISTER NAME VCP decisions read register VCP error register These VCP registers are supported on the C6416 C6416 device only. Table 23. TCP Registers (C6416 C6416 Only) EDMA BUS HEX ADDRESS RANGE PERIPHERAL BUS HEX ADDRESS RANGE ACRONYM 5800 0000 01BA 0000 TCPIC0 TCP input configuration register 0 5800 0004 01BA 0004 TCPIC1 TCP input configuration register 1 5800 0008 01BA 0008 TCPIC2 TCP input configuration register 2 5800 000C 01BA 000C TCPIC3 TCP input configuration register 3 5800 0010 01BA 0010 TCPIC4 TCP input configuration register 4 5800 0014 01BA 0014 TCPIC5 TCP input configuration register 5 5800 0018 01BA 0018 TCPIC6 TCP input configuration register 6 5800 001C 01BA 001C TCPIC7 TCP input configuration register 7 5800 0020 01BA 0020 TCPIC8 TCP input configuration register 8 5800 0024 01BA 0024 TCPIC9 TCP input configuration register 9 5800 0028 01BA 0028 TCPIC10 TCPIC10 TCP input configuration register 10 5800 002C 01BA 002C TCPIC11 TCPIC11 TCP input configuration register 11 5800 0030 01BA 0030 TCPOUT TCP output parameters register 5802 0000 - TCPSP 5804 0000 - TCPEXT 5806 0000 - TCPAP 5808 0000 - TCPINTER REGISTER NAME TCP systematics and parities memory TCP extrinsics memory TCP apriori memory TCP interleaver memory 580A 0000 TCPHD TCP hard decisions memory 01BA 0038 TCPEXE TCP execution register - 01BA 0040 TCPEND TCP endian register - 01BA 0050 TCPERR TCP error register - - - 01BA 0058 TCPSTAT TCP status register These TCP registers are supported on the C6416 C6416 device only. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 27 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 EDMA channel synchronization events The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 24 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the C64x device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234 SPRU234). 28 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 EDMA channel synchronization events (continued) Table 24. TMS320C64x EDMA Channel Synchronization Events EDMA CHANNEL EVENT NAME 0 DSP_INT 1 TINT0 Timer 0 interrupt 2 TINT1 Timer 1 interrupt 3 SD_INTA 4 GPINT4/EXT_INT4 GPIO event 4/External interrupt pin 4 5 GPINT5/EXT_INT5 GPIO event 5/External interrupt pin 5 6 GPINT6/EXT_INT6 GPIO event 6/External interrupt pin 6 7 GPINT7/EXT_INT7 GPIO event 7/External interrupt pin 7 8 GPINT0 GPIO event 0 9 GPINT1 GPIO event 1 10 GPINT2 GPIO event 2 11 GPINT3 GPIO event 3 12 XEVT0 McBSP0 transmit event 13 REVT0 McBSP0 receive event 14 XEVT1 McBSP1 transmit event 15 REVT1 McBSP1 receive event 16 ­ 17 XEVT2 McBSP2 transmit event 18 REVT2 McBSP2 receive event 19 TINT2 Timer 2 interrupt 20 SD_INTB EMIFB SDRAM timer interrupt 21 ­ Reserved, for future expansion 22-27 ­ None 28 VCPREVT VCP receive event (C6416 C6416 only)§ 29 VCPXEVT VCP transmit event (C6416 C6416 only)§ 30 TCPREVT TCP receive event (C6416 C6416 only)§ 31 TCPXEVT TCP transmit event (C6416 C6416 only)§ 32 UREVT EVENT DESCRIPTION HPI/PCI-to-DSP interrupt (PCI peripheral supported on C6415 C6415 and C6416 C6416 only) EMIFA SDRAM timer interrupt None UTOPIA receive event (C6415 C6415 and C6416 C6416 only) 33-39 ­ 40 UXEVT None 41-47 ­ 48 GPINT8 GPIO event 8 49 GPINT9 GPIO event 9 50 GPINT10 GPINT10 GPIO event 10 51 GPINT11 GPINT11 GPIO event 11 52 GPINT12 GPINT12 GPIO event 12 53 GPINT13 GPINT13 GPIO event 13 54 GPINT14 GPINT14 GPIO event 14 55 GPINT15 GPINT15 GPIO event 15 56-63 ­ UTOPIA transmit event (C6415 C6415 and C6416 C6416 only) None None In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234 SPRU234). The PCI and UTOPIA peripherals are not supported on the C6414 C6414 device; therefore, these EDMA synchronization events are reserved. § The VCP/TCP EDMA synchronization events are supported on the C6416 C6416 only. For the C6414 C6414 and C6415 C6415 devices, these events are reserved. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 29 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 interrupt sources and interrupt selector The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 25. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00-INT 00-INT_03) are non-maskable and fixed. The remaining interrupts (INT_04-INT 04-INT_15) are maskable and default to the interrupt source specified in Table 25. The interrupt source for interrupts 4-15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004). 30 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 interrupt sources and interrupt selector (continued) Table 25. C64x DSP Interrupts CPU INTERRUPT NUMBER INTERRUPT EVENT - - RESET INT_01 - - NMI INT_02 - - Reserved Reserved. Do not use. INT_03 - - Reserved Reserved. Do not use. INT_04 MUXL[4:0] 00100 GPINT4/EXT_INT4 GPIO interrupt 4/External interrupt pin 4 INT_05 MUXL[9:5] 00101 GPINT5/EXT_INT5 GPIO interrupt 5/External interrupt pin 5 INT_06 MUXL[14:10] 00110 GPINT6/EXT_INT6 GPIO interrupt 6/External interrupt pin 6 INT_07 MUXL[20:16] 00111 GPINT7/EXT_INT7 GPIO interrupt 7/External interrupt pin 7 INT_08 MUXL[25:21] 01000 EDMA_INT EDMA channel (0 through 63) interrupt INT_09 MUXL[30:26] 01001 EMU_DTDMA INT_10 MUXH[4:0] 00011 SD_INTA INT_11 MUXH[9:5] 01010 EMU_RTDXRX EMU real-time data exchange (RTDX) receive INT_12 MUXH[14:10] 01011 EMU_RTDXTX EMU RTDX transmit INT_13 MUXH[20:16] 00000 DSP_INT INT_14 MUXH[25:21] 00001 TINT0 Timer 0 interrupt INT_15 MUXH[30:26] 00010 TINT1 Timer 1 interrupt - - 01100 XINT0 McBSP0 transmit interrupt - - 01101 RINT0 McBSP0 receive interrupt - - 01110 XINT1 McBSP1 transmit interrupt - - 01111 RINT1 McBSP1 receive interrupt - - 10000 GPINT0 - - 10001 XINT2 McBSP2 transmit interrupt - - 10010 RINT2 McBSP2 receive interrupt - - 10011 TINT2 Timer 2 interrupt - - 10100 SD_INTB EMIFB SDRAM timer interrupt - - 10101 Reserved Reserved. Do not use. - - 10110 Reserved Reserved. Do not use. - - 10111 UINT - - 11000 - 11101 Reserved - - 11110 VCPINT VCP interrupt (C6416 C6416 only) - SELECTOR VALUE (BINARY) INT_00 INTERRUPT SELECTOR CONTROL REGISTER - 11111 TCPINT TCP interrupt (C6416 C6416 only) INTERRUPT SOURCE EMU DTDMA EMIFA SDRAM timer interrupt HPI/PCI-to-DSP interrupt (PCI supported on C6415 C6415 and C6416 C6416 only) GPIO interrupt 0 UTOPIA interrupt (C6415/C6416 C6415/C6416 only) Reserved. Do not use. Interrupts INT_00 through INT_03 are non-maskable and fixed. Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 25 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the TMS320C6000 TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646 SPRU646). POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 31 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 signal groups description CLKIN CLKOUT4/GP1 CLKOUT6/GP2 CLKMODE1 CLKMODE0 PLLV TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMU10 EMU10 EMU11 EMU11 Reset and Interrupts Clock/PLL Reserved IEEE Standard 1149.1 (JTAG) Emulation RESET NMI GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 RSV RSV RSV RSV RSV RSV · · · RSV RSV RSV Peripheral Control/Status PCI_EN MCBSP2_EN Control/Status GP15/PRST GP15/PRST§ GP14/PCLK GP14/PCLK§ GP13/PINTA GP13/PINTA§ GP12/PGNT GP12/PGNT§ GP11/PREQ GP11/PREQ§ GP10/PCBE3 GP10/PCBE3§ GP9/PIDSEL§ CLKS2/GP8 GPIO GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 GP3 CLKOUT6/GP2 CLKOUT4/GP1 GP0 General-Purpose Input/Output (GPIO) Port These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2 clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO as input-only. § For the C6415 C6415 and C6416 C6416 devices, these GPIO pins are muxed with the PCI peripheral pins. By default, these signals are set up to no function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, the GPIO peripheral pins are not muxed; the C6414 C6414 device does not support the PCI peripheral. Figure 3. CPU and Peripheral Signals 32 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 signal groups description (continued) AED[63:0] 64 Data AECLKIN ACE3 ACE2 Memory Map Space Select ACE1 ACE0 AEA[22:3] 20 External Memory I/F Control Address ABE7 ABE6 ABE5 ABE4 Byte Enables ABE3 ABE2 ABE1 ABE0 BED[15:0] BBE1 BBE0 16 Data AHOLD AHOLDA ABUSREQ BECLKIN BECLKOUT1 BECLKOUT2 Memory Map Space Select 20 External Memory I/F Control BARE/BSDCAS/BSADS/BSRE BAOE/BSDRAS/BSOE BAWE/BSDWE/BSWE BARDY BSOE3 BPDT Address Byte Enables Bus Arbitration EMIFB (16-bit) AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE AARDY ASOE3 APDT EMIFA (64-bit) BCE3 BCE2 BCE1 BCE0 BEA[20:1] Bus Arbitration AECLKOUT1 AECLKOUT2 ASDCKE AARE/ASDCAS/ASADS/ASRE BHOLD BHOLDA BBUSREQ These C64xTM devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. Figure 4. Peripheral Signals POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 33 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 signal groups description (continued) HD[31:0]/AD[31:0] 32 Data HCNTL0/PSTOP HCNTL1/PDEVSEL Register Select Control Half-Word Select HHWIL/PTRDY (HPI16 HPI16 ONLY) HD[31:0]/AD[31:0] GP10/PCBE3 GP10/PCBE3 HR/W/PCBE2 HDS2/PCBE1 PCBE0§ GP12/PGNT GP12/PGNT GP11/PREQ GP11/PREQ HPI (Host-Port Interface) 32 Data/Address Clock Command Byte Enable Control Arbitration Error Serial EEPROM PCI Interface (C6415 C6415 and C6416 C6416 Only) HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME GP14/PCLK GP14/PCLK GP9/PIDSEL HCNTL1/PDEVSEL HINT/PFRAME GP13/PINTA GP13/PINTA HAS/PPAR GP15/PRST GP15/PRST HRDY/PIRDY HCNTL0/PSTOP HHWIL/PTRDY HDS1/PSERR HCS/PPERR DX2/XSP_DO XSP_CS§ CLKX2/XSP_CLK DR2/XSP_DI For the C6415 C6415 and C6416 C6416 devices, these HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, these HPI pins are not muxed; the C6414 C6414 device does not support the PCI peripheral. For the C6415 C6415 and C6416 C6416 devices, these PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI, McBSP2, or GPIO peripherals. By default, these signals function as HPI, McBSP2, and no function, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, the HPI, McBSP2, and GPIO peripheral pins are not muxed; the C6414 C6414 device does not support the PCI peripheral. § For the C6414 C6414 device, these pins are "Reserved (leave unconnected, do not connect to power or ground)." Figure 4. Peripheral Signals (Continued) 34 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 signal groups description (continued) McBSP1 McBSP0 CLKX1/URADDR4 FSX1/UXADDR3 DX1/UXADDR4 Transmit Transmit CLKR1/URADDR2 FSR1/UXADDR2 DR1/UXADDR1 Receive Receive CLKS1/URADDR3 Clock CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 Clock CLKS0 McBSP2 CLKX2/XSP_CLK FSX2 DX2/XSP_DO Transmit CLKR2 FSR2 DR2/XSP_DI Receive CLKS2/GP8 Clock McBSPs (Multichannel Buffered Serial Ports) For the C6415 C6415 and C6416 C6416 devices, these McBSP2 and McBSP1 pins are muxed with the PCI and UTOPIA peripherals, respectively. By default, these signals function as McBSP2 and McBSP1, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, these McBSP2 and McBSP1 peripheral pins are not muxed; the C6414 C6414 device does not support PCI and UTOPIA peripherals. The McBSP2 clock source pin (CLKS2, default) is muxed with the GP8 pin. To use this muxed pin as the GP8 signal, the appropriate GPIO register bits (GP8EN and GP8DIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. Figure 4. Peripheral Signals (Continued) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 35 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 signal groups description (continued) UTOPIA (SLAVE) [C6415 C6415 and C6416 C6416 Only] URDATA7 URDATA6 URDATA5 URDATA4 URDATA3 URDATA2 Receive Transmit URDATA1 URDATA0 URENB CLKX1/URADDR4 CLKS1/URADDR3 CLKR1/URADDR2 URADDR1 URADDR0 URCLAV URSOC UXDATA1 UXDATA0 Control/Status Control/Status URCLK Clock Clock TOUT1 TINP1 Timer 1 TOUT2 TINP2 UXENB DX1/UXADDR4 FSX1/UXADDR3 FSR1/UXADDR2 DR1/UXADDR1 UXADDR0 UXCLAV UXSOC Timer 2 Timer 0 UXCLK TOUT0 TINP0 Timers For the C6415 C6415 and C6416 C6416 devices, these UTOPIA pins are muxed with the McBSP1 peripheral. By default, these signals function as McBSP1. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, these McBSP1 peripheral pins are not muxed; the C6414 C6414 does not support the UTOPIA peripheral. Figure 4. Peripheral Signals (Continued) 36 UXDATA7 UXDATA6 UXDATA5 UXDATA4 UXDATA3 UXDATA2 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 DEVICE CONFIGURATIONS The C6414 C6414, C6415 C6415, and C6416 C6416 peripheral selections and other device configurations are determined by external pullup/pulldown resistors on the following pins (all of which are latched during device reset): D peripherals selection (C6415 C6415 and C6416 C6416 devices) - BEA11 BEA11 (UTOPIA_EN) - PCI_EN (for C6415 C6415 or C6416 C6416, see Table 27 footnotes) - MCBSP2_EN (for C6415 C6415 or C6416 C6416, see Table 27 footnotes) The C6414 C6414 device does not support the PCI and UTOPIA peripherals; for proper operation of the C6414 C6414 device, do not oppose the internal pulldowns (IPDs) on the BEA11 BEA11, PCI_EN, and MCBSP2_EN pins. (For IPUs/IPDs on pins, see the Terminal Functions table of this data sheet.) D other device configurations (C64x) - BEA[20:13, 7] - HD5 peripherals selection Some C6415/C6416 C6415/C6416 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:9], PCI and its internal EEPROM, McBSP1, McBSP2, and UTOPIA). The VCP/TCP coprocessors (C6416 C6416 only) and other C64x peripherals (i.e., the Timers, McBSP0, and the GP[8:0] pins), are always available. D UTOPIA and McBSP1 peripherals The UTOPIA_EN pin (BEA11 BEA11) is latched at reset. For C6415 C6415 and C6416 C6416 devices, this pin selects whether the UTOPIA peripheral or McBSP1 peripheral is functionally enabled (see Table 26). The C6414 C6414 device does not support the UTOPIA peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 BEA11 pin. Table 26. UTOPIA_EN Peripheral Selection (McBSP1 and UTOPIA) (C6415/C6416 C6415/C6416 Only) PERIPHERAL SELECTION UTOPIA_EN (BEA11 BEA11) Pin [D16] PERIPHERALS SELECTED UTOPIA 0 1 DESCRIPTION McBSP1 McBSP1 is enabled and UTOPIA is disabled [default]. This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other standalone UTOPIA pins are tied-off (Hi-Z). UTOPIA is enabled and McBSP1 is disabled. This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other standalone McBSP1 pins are tied-off (Hi-Z). D HPI, GP[15:9], PCI, EEPROM (internal to PCI), and McBSP2 peripherals The PCI_EN and MCBSP2_EN pins are latched at reset. They determine specific peripheral selection for the C6415 C6415 and C6416 C6416 devices, summarized in Table 27. The C6414 C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldowns (IPDs) on the PCI_EN and MCBSP2_EN pins. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 37 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 27. PCI_EN and MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, and McBSP2) PERIPHERAL SELECTION PERIPHERALS SELECTED PCI_EN Pin [AA4] MCBSP2_EN Pin [AF3] HPI GP[15:9] 0 0 0 1 1 0 1 1 PCI EEPROM (Internal to PCI) McBSP2 The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation. The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation. The only time McBSP2 is disabled is when both PCI_EN = 1 and MCBSP2_EN = 0. This configuration enables, at reset, the auto-initialization of the PCI peripheral through the PCI internal EEPROM [provided the PCI EEPROM Auto-Initialization pin (BEA13 BEA13) is pulled up (EEAI = 1)]. The user can then enable the McBSP2 peripheral (disabling EEPROM) by dynamically changing MCBSP2_EN to a "1" after the device is initialized (out of reset). - If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and GP[15:9] pins can be programmed as GPIO, provided the GPxEN and GPxDIR bits are properly configured. This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0 and XSP_CS) are tied-off (Hi-Z). Also, the multiplexed GPIO/PCI pins can be used as GPIO with the proper software configuration of the GPIO enable and direction registers (for more details, see Table 29). - If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled. This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GPIO/PCI pins function as PCI pins (for more details, see Table 29). - The MCBSP2_EN pin, in combination with the PCI_EN pin, controls the selection of the McBSP2 peripheral and the PCI internal EEPROM (for more details, see Table 27 and its footnotes). other device configurations Table 28 describes the C6414 C6414, C6415 C6415, and C6416 C6416 devices configuration pins, which are set up via external pullup/pulldown resistors through the specified EMIFB address bus pins (BEA[20:13, 11, 9:7]) and the HD5 pin. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section. 38 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11 BEA11) CONFIGURATION PIN NO. BEA20 BEA20 E16 BEA[19:18] BEA[17:16] BEA[15:14] BEA13 BEA13 FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 ­ System operates in Big Endian mode 1 - System operates in Little Endian mode (default) [D18, C18] Bootmode [1:0] 00 ­ No boot 01 - HPI boot 10 - EMIFB 8-bit ROM boot with default timings (default mode) 11 - Reserved [B18, A18] EMIFA input clock select Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 ­ AECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved [D17, C17] EMIFB input clock select Clock mode select for EMIFB (BECLKIN_SEL[1:0]) 00 ­ BECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved B17 PCI EEPROM Auto-Initialization (EEAI) [C6415 C6415 and C6416 C6416 devices only] [The C6414 C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA13 BEA13 pin.] PCI auto-initialization via external EEPROM 0 - PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default values (default). 1 - PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1) and the McBSP2 peripheral pin is disabled (MCBSP2_EN = 0). Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. For more information on the PCI EEPROM default values, see the TMS320C6000 TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (literature number SPRU581 SPRU581). UTOPIA Enable (UTOPIA_EN) [C6415 C6415 and C6416 C6416 devices only] [The C6414 C6414 device does not support the UTOPIA peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 BEA11 pin.] UTOPIA peripheral enable (functional) BEA11 BEA11 D16 0 - UTOPIA peripheral disabled (McBSP1 functions are enabled). [default] This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other standalone UTOPIA pins are tied-off (Hi-Z). 1 - UTOPIA peripheral enabled (McBSP1 functions are disabled). This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other standalone McBSP1 pins are tied-off (Hi-Z). POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 39 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11 BEA11) (Continued) CONFIGURATION PIN NO. FUNCTIONAL DESCRIPTION C6414 C6414 Devices BEA7 BEA8 BEA9 D15 A16 B16 Do not oppose internal pulldown (IPD) Pullup Do not oppose IPD Do not oppose IPD Do not oppose IPD Do not oppose IPD For HD5 40 Y1 C6415 C6415 Devices C6416 C6416 Devices Do not oppose IPD Pullup Pullup proper device operation, this pin must be externally pulled up with a 1-k resistor. HPI peripheral bus width (HPI_WIDTH) 0 - HPI operates as an HPI16 HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.) 1 - HPI operates as an HPI32 HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. Those muxed pins that are configured by software can be programmed to switch functionalities at any time. Those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 29 identifies the multiplexed pins on the C6414 C6414, C6415 C6415, and C6416 C6416 devices; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions. debugging considerations It is recommended that external connections be provided to device configuration pins, including CLKMODE[1:0], BEA[20:13, 11, 9:7], HD5/AD5, PCI_EN, and MCBSP2_EN. Although internal pullup/pulldown resistors exist on these pins (except for HD5/AD5), providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the BEA bus (BEA[12, 10, 6:1]). Do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors on the C6414 C6414, C6415 C6415, and C6416 C6416 device pins, see the terminal functions table. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 41 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 29. C6414 C6414, C6415 C6415, and C6416 C6416 Device Multiplexed Pins MULTIPLEXED PINS NAME NO. DEFAULT FUNCTION DEFAULT SETTING CLKOUT4/GP1 AE6 CLKOUT4 GP1EN = 0 (disabled) CLKOUT6/GP2 AD6 CLKOUT6 GP2EN = 0 (disabled) CLKS2/GP8 AE4 CLKS2 GP8EN = 0 (disabled) GP9/PIDSEL M3 GP10/PCBE3 GP10/PCBE3 L2 GP11/PREQ GP11/PREQ F1 GP12/PGNT GP12/PGNT J3 GP13/PINTA GP13/PINTA G4 GP14/PCLK GP14/PCLK F2 GP15/PRST GP15/PRST To use GP[15:9] as GPIO pins, the PCI needs to be disabled (PCI_EN = 0), the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output UTOPIA_EN UTOPIA EN (BEA11 BEA11) = 0 (disabled) By default, McBSP1 is enabled upon reset (UTOPIA is disabled). ( ) To T enable the UTOPIA peripheral, an bl h i h l external pullup resistor (1 k) must be provided on the BEA11 BEA11 pin (setting UTOPIA_EN = 1 at reset). _ ) PCI_EN PCI EN = 0 (disabled) By default, HPI is enabled upon reset disabled). (PCI is disabled) To enable the PCI peripheral an external p pullup resistor (1 k) must be p p ( ) provided on the PCI_EN pin (setting PCI_EN = 1 h PCI EN i ( i PCI EN at reset). reset) G3 AB11 DX1 FSX1/UXADDR3 AB13 FSX1 FSR1/UXADDR2 AC9 FSR1 DR1/UXADDR1 AF11 DR1 CLKX1/URADDR4 AB12 CLKX1 CLKS1/URADDR3 AC8 CLKS1 CLKR1/URADDR2 AC10 CLKR1 CLKX2/XSP_CLK AC2 CLKX2 DR2/XSP_DI AB3 DR2 DX2/XSP_DO AA2 These pins are software-configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output GPxEN GP EN = 0 (disabled) (di bl d) PCI_EN PCI EN = 0 (disabled) None DX1/UXADDR4 DESCRIPTION DX2 HD[31:0]/AD[31:0] § HD[31:0] HAS/PPAR T3 HAS HCNTL1/PDEVSEL R1 HCNTL1 HCNTL0/PSTOP T4 HCNTL0 HDS1/PSERR T1 HDS1 HDS2/PCBE1 T2 HDS2 HR/W/PCBE2 P1 HR/W HHWIL/PTRDY R3 HHWIL (HPI16 HPI16 only) HINT/PFRAME R4 HINT HCS/PPERR R2 HCS HRDY/PIRDY P4 HRDY For the C6415 C6415 and C6416 C6416 devices, all other standalone UTOPIA and PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [UTOPIA_EN (BEA11 BEA11) = 0 or PCI_EN = 0]. The C6414 C6414 device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414 C6414 device, all other pins are standalone peripheral functions and are not muxed. § For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table. 42 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 Terminal Functions SIGNAL NAME TYPE IPD/ IPU H4 I IPD Clock Input. This clock is the input to the on-chip PLL. CLKOUT4/GP1§ AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). CLKOUT6/GP2§ AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKMODE1 G1 I IPD CLKMODE0 H2 I IPD PLLV¶ J6 A# NO. DESCRIPTION CLOCK/PLL CONFIGURATION CLKIN Clock mode select · Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12. For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLL voltage supply JTAG EMULATION TMS AB16 I IPU JTAG test-port mode select TDO AE19 O/Z IPU JTAG test-port data out TDI AF18 I IPU JTAG test-port data in TCK AF16 I IPU JTAG test-port clock TRST AB15 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet. EMU11 EMU11 AC18 I/O/Z IPU Emulation pin 11. Reserved for future use, leave unconnected. EMU10 EMU10 AD18 I/O/Z IPU Emulation pin 10. Reserved for future use, leave unconnected. EMU9 AE18 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected. EMU8 AC17 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected. EMU7 AF17 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected. EMU6 AD17 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected. EMU5 AE17 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 AC16 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 AD16 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 AE16 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 EMU0 AC15 AF15 I/O/Z IPU Emulation [1:0] pins · Select the device functional mode of operation EMU[1:0] Operation 00 Boundary Scan/Normal Mode (see Note) 01 Reserved 10 Reserved 11 Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet) Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Normal mode. For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-k resister. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. ¶ PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. # A = Analog signal (PLL Filter) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251-1443 43 TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, TMS320C6416 TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146M SPRS146M - FEBRUARY 2001 - REVISED FEBRUARY 2005 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET AC7 I B4 NMI I Device reset IPD Nonmaskable interrupt, edge-driven (rising edge) IPU GP7/EXT_INT7 AF4 GP6/EXT_INT6 AD5 GP5/EXT_INT5 AE5 GP4/EXT_INT4 AF5 General purpose General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input-only. · When these pins function as External Interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge-driv