TMS320C6413 TMS320C6410 SPRS247E SPRS247D TMS320C6413/C6410 HPI16 HPI32 C6413 - Datasheet Archive

 

Fixed-Point Digital Signal Processors Data Manual Literature Number: SPRS247E April 2004 - Revised May 2005 PRODUCTION DATA

 

TMS320C6413 TMS320C6413, TMS320C6410 TMS320C6410 Fixed-Point Digital Signal Processors Data Manual Literature Number: SPRS247E SPRS247E April 2004 - Revised May 2005 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. This page intentionally left blank Revision History Revision History This data manual revision history highlights the technical changes made to the SPRS247D SPRS247D device-specific data manual to make it an SPRS247E SPRS247E revision. Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6413 TMS320C6413 and TMS320C6410 TMS320C6410 devices, have been incorporated. PAGE(s) NO. ADDS/CHANGES/DELETES 63 Terminal Functions table: Host-port data [7:0] pins (I/O/Z) description: Changed sentence from "Host-Port bus width user-configurable at device reset via a 10-kW resistor pullup/pulldown resistor on the HD5 pin (I):" to "Host-Port bus width user-configurable at device reset via a 1-kW pullup/pulldown resistor on the HD5 pin (I):" 78 I2C section: Updated/added "For more detailed information." paragraph 90 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature: IOH, Low-level output current, TEST CONDITIONS: Moved/added HPI to "Timer, TDO, GPIO, McBSP" April 2004 - Revised May 2005 SPRS247E SPRS247E 3 Contents Contents Section Page 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 GTS and ZTS BGA Packages (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 CPU (DSP Core) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 L2 Architecture Expanded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Peripheral Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Interrupt Sources and Interrupt Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Signal Groups Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 14 15 16 19 21 23 36 37 39 3 Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Peripheral Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Peripheral Selection After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Peripheral Configuration Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 JTAG ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Debugging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . 3.12.2 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 44 45 46 48 50 51 52 53 53 55 67 68 68 70 4 Peripherals Detailed Description (Device-Specific) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Clock PLL and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Host-Port Interface (HPI) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Multichannel Audio Serial Port (McASP) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 McASP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Power-Down Modes Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Triggering, Wake-up, and Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 C64x Power-Down Mode with an Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 Power-Supply Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Peripheral Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 75 76 76 78 79 82 82 84 84 84 85 86 4 SPRS247E SPRS247E April 2004 - Revised May 2005 Contents Section 4.10 4.11 4.12 4.13 Page IEEE 1149.1 JTAG Compatibility Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Device Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 87 88 88 5 Device Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range . . . . . . . . . . . . . . . . . . 89 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.4 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Signal Transition Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Peripheral Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.1 Input and Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3 Programmable Synchronous Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.4 Synchronous DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.5 HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.6 BUSREQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.7 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.8 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.9 Multichannel Audio Serial Port (McASP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.10 Inter-Integrated Circuits (I2C) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.11 Host-Port Interface (HPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.12 Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.13 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.14 General-Purpose Input/Output (GPIO) Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.15 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.1 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 April 2004 - Revised May 2005 SPRS247E SPRS247E 91 91 91 92 5 Figures List of Figures Figure Page 2-1 2-2 2-3 2-4 2-5 2-6 2-7 GTS and ZTS BGA Packages (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C64xE CPU (DSP Core) Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C6413 TMS320C6413 L2 Architecture Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C6410 TMS320C6410 L2 Architecture Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU and Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 15 18 21 22 39 40 3-1 3-2 3-3 3-4 3-5 3-6 46 48 49 50 51 3-7 Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000] . . . . . . . . . . . . . . . . . . Peripheral Enable/Disable Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] - Read/Write Accesses . . . . . . . . Device Status Register (DEVSTAT) Description - 0x01B3 F004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG ID Register Description - TMS320C6413/C6410 TMS320C6413/C6410 Register Value - 0x0007 902F . . . . . . . . . . . . Configuration Example A (HPI16 HPI16 + 2 McASPs + 2 McBSPs +2 I2Cs + EMIF + 3 Timers + GPIO) . . . . . . . . . . . . . . . . . . . . . . . . TMS320C6413/C6410 TMS320C6413/C6410 DSP Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode . . . . . . . . . . . . . . . . . . . . . . McASP0 and McASP1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2Cx Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Mode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWRD Field of the CSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schottky Diode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 77 79 80 81 82 83 85 6-1 6-2 6-3 6-4 Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input and Output Voltage Reference Levels for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . Rise and Fall Transition Time Voltage Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 91 91 92 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 CLKIN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AECLKIN Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AECLKOUT1 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AECLKOUT2 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Read Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Write Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 94 94 95 95 96 98 99 6 SPRS247E SPRS247E 54 69 April 2004 - Revised May 2005 Figures 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SDRAM Read Command (CAS Latency 3) for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SDRAM Write Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SDRAM ACTV Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SDRAM DCAB Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SDRAM DEAC Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SDRAM REFR Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SDRAM MRS Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SDRAM Self-Refresh Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 HOLD/HOLDA Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 BUSREQ Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 External/NMI Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 McASP Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 McASP Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 HPI16 HPI16 Read Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 HPI16 HPI16 Read Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 HPI16 HPI16 Write Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 HPI16 HPI16 Write Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 HPI32 HPI32 Read Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 HPI32 HPI32 Read Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 HPI32 HPI32 Write Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 HPI32 HPI32 Write Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 McBSP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 128 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 129 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 130 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 GPIO Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 April 2004 - Revised May 2005 SPRS247E SPRS247E 7 Tables List of Tables Table Page 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 Characteristics of the C6413 C6413 and C6410 C6410 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C6413/C6410 TMS320C6413/C6410 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L2 Cache Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick DMA (QDMA) and Pseudo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Parameter RAM (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Selector Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GP0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP0 and McASP1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP0 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP1 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C0 and I2C1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C6413/C6410 TMS320C6413/C6410 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C6413/C6410 C6413/C6410 DSP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 19 23 23 26 26 27 28 28 29 29 30 30 30 31 31 32 34 34 35 36 38 3-1 C6413/C6410 C6413/C6410 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN, HD5, CLKINSEL, and OSC_DIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TOUT0/HPI_EN and HD5 Peripheral Selection (HPI or McASP1 and Select GP0 Pins) . . . . . . . . . . . Peripheral Configuration (PERCFG) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . PCFGLOCK Register Selection Bit Descriptions - Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCFGLOCK Register Selection Bit Descriptions - Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Status (DEVSTAT) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG ID Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C6413/C6410 C6413/C6410 Device Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 45 47 49 49 50 51 52 56 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 4-1 4-3 4-4 TMS320C6413 TMS320C6413 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time for -500 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C6410 TMS320C6410 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time for -400 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal and Tank Circuit Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics of the Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Board-Level Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7-1 Timing Requirements for External Crystal Oscillator Input (OSCIN and OSCOUT) . . . . . . . . . . . . . . . 93 4-2 8 SPRS247E SPRS247E 73 74 74 84 April 2004 - Revised May 2005 Tables Table 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 Page Timing Requirements for CLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 . . . . . . . . . . . . . . 94 Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 . . . . . . . . . . . . . . 94 Timing Requirements for AECLKIN for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . 97 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . 100 Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . 104 Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . 110 Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Timing Requirements for Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Switching Characteristics Over Recommended Operating Conditions During Reset . . . . . . . . . . . . . 112 Timing Requirements for External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Timing Requirements for McASP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Switching Characteristics Over Recommended Operating Conditions for McASP . . . . . . . . . . . . . . . 115 Timing Requirements for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Switching Characteristics for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Timing Requirements for Host-Port Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Timing Requirements for McBSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Switching Characteristics Over Recommended Operating Conditions for McBSP . . . . . . . . . . . . . . . 126 Timing Requirements for FSR When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 April 2004 - Revised May 2005 SPRS247E SPRS247E 9 Tables 7-36 7-37 7-38 7-39 7-40 7-41 7-42 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Timing Requirements for Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs . . . . . . . . . 132 Timing Requirements for GPIO Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs . . . . . . . . . 133 Timing Requirements for JTAG Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port . . . . . . . . 134 8-1 8-2 Thermal Resistance Characteristics (S-PBGA Package) [GTS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Thermal Resistance Characteristics (S-PBGA Package) [ZTS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10 SPRS247E SPRS247E April 2004 - Revised May 2005 Features 1 Features D High-Performance Fixed-Point Digital D D D Signal Processor (TMS320C6413/C6410 TMS320C6413/C6410) - TMS320C6413 TMS320C6413 - 2-ns Instruction Cycle Time - 500-MHz Clock Rate - 4000 MIPS - TMS320C6410 TMS320C6410 - 2.5-ns Instruction Cycle Time - 400-MHz Clock Rate - 3200 MIPS - Eight 32-Bit Instructions/Cycle - Fully Software-Compatible With C64xTM - Extended Temperature Devices Available VelociTI.2TM Extensions to VelociTITM Advanced Very-Long-Instruction-Word (VLIW) TMS320C64xTM DSP Core - Eight Highly Independent Functional Units With VelociTI.2TM Extensions: - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle - Load-Store Architecture With Non-Aligned Support - 64 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Byte-Addressable (8-/16-/32-/64-Bit Data) - 8-Bit Overflow Protection - Bit-Field Extract, Set, Clear - Normalization, Saturation, Bit-Counting - VelociTI.2TM Increased Orthogonality VelociTI.2TM Extensions to VelociTITM Advanced Very-Long-Instruction-Word (VLIW) TMS320C64xTM DSP Core D L1/L2 Memory Architecture D D D D D D D D D D D D D D D - 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) - 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) - 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache [C6413 C6413] (Flexible RAM/Cache Allocation) - 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [C6410 C6410] (Flexible RAM/Cache Allocation) Endianess: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) - Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) - 1024M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) Host-Port Interface (HPI) [32-/16-Bit] Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each Two Inter-Integrated Circuit (I2C) Buses - Additional GPIO Capability Two Multichannel Buffered Serial Ports Three 32-Bit General-Purpose Timers Sixteen General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator On-Chip Fundamental Oscillator IEEE-1149 IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 288-Pin Ball Grid Array (BGA) Packages (GTS and ZTS Suffixes), 1.0-mm Ball Pitch 0.13-µm/6-Level Cu Metal Process (CMOS) 3.3-V I/Os, 1.2-V Internal VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. April 2004 - Revised May 2005 SPRS247E SPRS247E 11 Functional Overview 2 Functional Overview 2.1 GTS and ZTS BGA Packages (Bottom View) GTS and ZTS 288-PIN 288-PIN BALL GRID ARRAY (BGA) PACKAGES ( BOTTOM VIEW ) AB AA Y V T P M K H F W U R N L J G E D B C A 1 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 12 14 16 18 20 22 Figure 2-1. GTS and ZTS BGA Packages (Bottom View) 12 SPRS247E SPRS247E April 2004 - Revised May 2005 Description 2.2 Description The TMS320C64xTM DSPs (including the TMS320C6413 TMS320C6413, TMS320C6410 TMS320C6410 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000TM TMS320C6000TM DSP platform. The TMS320C6413 TMS320C6413 and TMS320C6410 TMS320C6410 (C6413 C6413 and C6410 C6410) devices are based on the second-generation high-performance, advanced VelociTITM very-long-instruction-word (VLIW) architecture (VelociTI.2TM) developed by Texas Instruments (TI). The high-performance, lower-cost C6413/C6410 C6413/C6410 DSPs enable customers to reduce system costs for telecom, medical, industrial, office, and photo lab equipment. The C64xTM is a code-compatible member of the C6000TM C6000TM DSP platform. With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C6413 C6413 device offers cost-effective solutions to high-performance DSP programming challenges. With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the C6410 C6410 device offers cost-effective solutions to high-performance DSP programming challenges. The C6410 C6410 device also provides excellent value for packet telephony and for other cost-sensitive applications demanding high performance. The C6413/C6410 C6413/C6410 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64xTM DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2TM extensions. The VelociTI.2TM extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTITM architecture. The C6413 C6413 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4000 MMACS. The C6410 C6410 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The C6413/C6410 C6413/C6410 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000TM C6000TM DSP platform devices. The C6413/C6410 C6413/C6410 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space [for C6413 C6413 device] and the Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space [for C6410 C6410 device]. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32 HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals. Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6413/C6410 C6413/C6410 has sufficient bandwidth to support all six serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958 IEC60958, AES-3, CP-430 CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. TMS320C6000 TMS320C6000, and C6000 C6000 are trademarks of Texas Instruments. April 2004 - Revised May 2005 SPRS247E SPRS247E 13 Device Characteristics The I2C ports on the TMS320C6413/C6410 TMS320C6413/C6410 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The C6413/C6410 C6413/C6410 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution. 2.3 Device Characteristics Table 2-1, provides an overview of the C6413 C6413 and C6410 C6410 DSPs. The tables show significant features of the C6413 C6413 and C6410 C6410 devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1. Characteristics of the C6413 C6413 and C6410 C6410 Processors HARDWARE FEATURES C6413 C6413 AND C6410 C6410 EMIFA (32-bit bus width) (clock source = AECLKIN, CLKOUT4, or CLKOUT6) Peripherals Not all peripherals pins are available at the i (F same time (For more detail, see the Device Configuration section). section) 1 EDMA (64 independent channels) 1 McASPs (use Peripheral Clock and AUXCLK) 2 I2Cs (use Peripheral Clock) HPI (32- or 16-bit user selectable) 2 1 (HPI16 HPI16 or HPI32 HPI32) McBSPs (internal clock source = CPU/4 clock frequency) 2 32-Bit Timers (internal clock source = CPU/8 clock frequency) 3 General-Purpose Input/Output Port (GP0) Size (Bytes) On-Chip Memory Organization 16 288K (C6413 C6413) 160K (C6410 C6410) 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 256KB 256KB Unified Mapped RAM/Cache (L2) [C6413 C6413] 128KB 128KB Unified Mapped RAM/Cache (L2) [C6410 C6410] CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) 0x0007902F Frequency MHz 500 (C6413 C6413) 400 (C6410 C6410) Cycle Time ns Voltage Core (V) I/O (V) PLL Options CLKIN frequency multiplier BGA Package 23 x 23 mm Process Technology µm Product Status Product Preview (PP), Advance Information (AI), or Production Data (PD) 0x0C01 2 ns (C6413-500 C6413-500, C6413 C6413 A-500) [500 MHz CPU, 100 MHz EMIF] 2.5 ns (C6410-400 C6410-400, C6410 C6410 A-400) [400 MHz CPU, 100 MHz EMIF] 1.2 V 3.3 V Bypass (x1), x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, and x24 288-Pin Flip-Chip Plastic BGA (GTS and ZTS) 0.13 µm PD On this C64xTM device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device speed portion of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 14 SPRS247E SPRS247E April 2004 - Revised May 2005 Functional Block Diagram 2.3.1 Functional Block Diagram Figure 2-2 shows the functional block diagram of the C6413/C6410 C6413/C6410 device. SDRAM 32 TMS320C6413/C6410 TMS320C6413/C6410 EMIF A SBSRAM L1P Cache Direct-Mapped 16K Bytes Total ZBT SRAM FIFO Timer 2 SRAM Timer 1 ROM/FLASH C64x DSP Core Timer 0 I/O Devices Instruction Fetch Control Registers Instruction Dispatch Advanced Instruction Packet Control Logic McBSP0 Instruction Decode Data Path A McBSP1 Data Path B A Register File A31-A16 A31-A16 A15-A0 A15-A0 Test B Register File B31-B16 B31-B16 B15-B0 B15-B0 Advanced In-Circuit Emulation McASP0 .L1 McASP1 and Enhanced DMA Controller (edma) .S1 .M1 .D1 .D2 .M2 .S2 Interrupt Control .L2 L2 Cache Memory 256KBytes§ L1D Cache 2-Way Set-Associative 16K Bytes Total HPI16 HPI16 or HPI32 HPI32 I2C0 OSCILLATOR and PLL (x1, x5 - x12, x16, x18, x19 - x22, x24) Power-Down Logic I2C1 16 Boot Configuration GP0 GP0 McBSPs: Framing Chips - H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs GP0[15:8] pins are muxed with the HPI HD[15:8] pins and GP0[2:1] pins are muxed with CLKOUT6 and CLKOUT4, respectively. § Note: the C6413 C6413 device has 256K-Bytes L2 Cache Memory; the C6410 C6410 device has only 128K-Bytes L2 Cache Memory. Figure 2-2. Functional Block Diagram April 2004 - Revised May 2005 SPRS247E SPRS247E 15 CPU (DSP Core) Description 2.4 CPU (DSP Core) Description The CPU fetches VelociTITM advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTITM VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64xTM VelociTI.2TM extensions add enhancements to the TMS320C62xTM DSP VelociTITM architecture. These enhancements include: · · · · · · Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62xTM VelociTITM VLIW architecture, the C64xTM register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 2-3]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a "data cross path"-a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62xTM DSP fixed-point instructions, the C64xTM DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2TM extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically "true"). TMS320C62x and C62x are trademarks of Texas Instruments. 16 SPRS247E SPRS247E April 2004 - Revised May 2005 CPU (DSP Core) Description The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64xTM DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62xTM/TMS320C67xTM DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64xTM DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: · · TMS320C6000 TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189 SPRU189) TMS320C64x Technical Overview (literature number SPRU395 SPRU395) TMS320C67x is a trademark of Texas Instruments. April 2004 - Revised May 2005 SPRS247E SPRS247E 17 CPU (DSP Core) Description src1 .L1 ST1b (Store Data) ST1a (Store Data) 32 MSBs 32 LSBs src2 dst long dst long src long src long dst dst .S1 src1 Data Path A 8 8 8 8 Register File A (A0-A31 A0-A31) src2 See Note A See Note A long dst dst .M1 src1 src2 LD1b (Load Data) LD1a (Load Data) 32 MSBs 32 LSBs DA1 (Address) .D1 dst src1 src2 2X 1X .D2 DA2 (Address) LD2a (Load Data) LD2b (Load Data) src2 src1 dst 32 LSBs 32 MSBs src2 .M2 src1 dst See Note A See Note A long dst Register File B (B0- B31) src2 Data Path B .S2 src1 dst long dst long src ST2a (Store Data) ST2b (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst 8 8 .L2 src2 src1 Control Register File NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs. Figure 2-3. TMS320C64xTM CPU (DSP Core) Data Paths 18 SPRS247E SPRS247E April 2004 - Revised May 2005 Memory Map Summary 2.5 Memory Map Summary Table 2-2 shows the memory map address ranges of the C6413 C6413 and C6410 C6410 devices. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the C6413/C6410 C6413/C6410 device begin at the hex address location 0x8000 0000 for EMIFA. Table 2-2. TMS320C6413/C6410 TMS320C6413/C6410 Memory Map Summary MEMORY BLOCK DESCRIPTION Internal RAM (L2) [C6413 C6413] Reserved [C6413 C6413] Internal RAM (L2) [C6410 C6410] Reserved [C6410 C6410] BLOCK SIZE (BYTES) HEX ADDRESS RANGE 256K 0000 0000 ­ 0003 FFFF 1024K 1024K minus 256K 0004 0000 ­ 000F FFFF 128K 0000 0000 ­ 0001 FFFF 1024K 1024K minus 128K 0002 0000 ­ 000F FFFF Reserved 15M 0010 0000 ­ 00FF FFFF Reserved 8M 0100 0000 ­ 017F FFFF External Memory Interface A (EMIFA) Registers 256K 0180 0000 ­ 0183 FFFF L2 Registers 256K 0184 0000 ­ 0187 FFFF HPI Registers 256K 0188 0000 ­ 018B FFFF McBSP 0 Registers 256K 018C 0000 ­ 018F FFFF McBSP 1 Registers 256K 0190 0000 ­ 0193 FFFF Timer 0 Registers 256K 0194 0000 ­ 0197 FFFF Timer 1 Registers 256K 0198 0000 ­ 019B FFFF Interrupt Selector Registers 256K 019C 0000 ­ 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 ­ 01A3 FFFF Reserved 512K 01A4 0000 ­ 01AB FFFF Timer 2 Registers 256K 01AC 0000 ­ 01AF FFFF 256K minus 4K 01B0 0000 ­ 01B3 EFFF Device Configuration Registers 4K 01B3 F000 ­ 01B3 FFFF I2C0 Data and Control Registers 16K 01B4 0000 ­ 01B4 3FFF I2C1 Data and Control Registers 16K 01B4 4000 ­ 01B4 7FFF Reserved 16K 01B4 8000 ­ 01B4 BFFF McASP0 Control Registers 16K 01B4 C000 ­ 01B4 FFFF McASP1 Control Registers 16K 01B5 0000 ­ 01B5 3FFF Reserved 176K 01B5 4000 ­ 01B7 FFFF Reserved 128K 01B8 0000 ­ 01B9 FFFF Reserved 128K 01BA 0000 ­ 01BB FFFF Emulation 256K 01BC 0000 ­ 01BF FFFF Reserved 528K 01C0 0000 ­ 01C8 3FFF Reserved 3.5M 01C8 4000 ­ 01FF FFFF GP0 Registers QDMA Registers 52 0200 0000 ­ 0200 0033 928M minus 52 0200 0034 ­ 2FFF FFFF McBSP 0 Data 64M 3000 0000 ­ 33FF FFFF McBSP 1 Data 64M 3400 0000 ­ 37FF FFFF Reserved 64M 3800 0000 ­ 3BFF FFFF McASP0 Data 1M 3C00 0000 ­ 3C0F FFFF Reserved April 2004 - Revised May 2005 SPRS247E SPRS247E 19 Memory Map Summary Table 2-2. TMS320C6413/C6410 TMS320C6413/C6410 Memory Map Summary (Continued) BLOCK SIZE (BYTES) HEX ADDRESS RANGE McASP1 Data 1M 3C10 0000 ­ 3C1F FFFF Reserved 62M 3C20 0000 ­ 3FFF FFFF MEMORY BLOCK DESCRIPTION Reserved 1G 4000 0000 ­ 7FFF FFFF EMIFA CE0 256M 8000 0000 ­ 8FFF FFFF EMIFA CE1 256M 9000 0000 ­ 9FFF FFFF EMIFA CE2 256M A000 0000 ­ AFFF FFFF EMIFA CE3 256M B000 0000 ­ BFFF FFFF 1G C000 0000 ­ FFFF FFFF Reserved 20 SPRS247E SPRS247E April 2004 - Revised May 2005 Memory Map Summary 2.5.1 L2 Architecture Expanded Figure 2-4 and Figure 2-5 show the detail of the L2 architecture on the TMS320C6413 TMS320C6413 and TMS320C6410 TMS320C6410 devices, respectively . For more information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610 SPRU610). L2MODE 000 001 010 L2 Memory 011 Block Base Address 111 128K SRAM 0x0000 0000 256K Cache (4 Way) [All] 256K SRAM (All) ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ 224K SRAM 192K SRAM 128K-Byte SRAM 0x0002 0000 128K Cache (4 Way) 64K Cache (4 Way) 32K Cache (4 Way) 64K-Byte RAM 0x0003 0000 32K-Byte RAM 0x0003 8000 32K-Byte RAM 0x0003 FFFF 0x0004 0000 Figure 2-4. TMS320C6413 TMS320C6413 L2 Architecture Memory Configuration April 2004 - Revised May 2005 SPRS247E SPRS247E 21 Memory Map Summary L2MODE 011 64K SRAM 010 0x0000 0000 64K-Byte RAM 128K Cache (4 Way) 64K Cache (4 Way) 96K SRAM 32K Cache (4 Way) 128K SRAM (All) 001 Block Base Address ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ 000 L2 Memory 0x0001 0000 32K-Byte RAM 0x0001 8000 32K-Byte RAM 0x0001 FFFF 0x0002 0000 The L2MODE = 111b is not supported on the C6410 C6410 device. Figure 2-5. TMS320C6410 TMS320C6410 L2 Architecture Memory Configuration 22 SPRS247E SPRS247E April 2004 - Revised May 2005 Peripheral Register Descriptions 2.6 Peripheral Register Descriptions Table 2-3 through Table 2-20 identify the peripheral registers for the C6413/C6410 C6413/C6410 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190 SPRU190). Table 2-3. EMIFA Registers HEX ADDRESS RANGE ACRONYM 0180 0000 GBLCTL EMIFA global control REGISTER NAME 0180 0004 CECTL1 EMIFA CE1 space control EMIFA CE0 space control 0180 0008 CECTL0 0180 000C - 0180 0010 CECTL2 EMIFA CE2 space control 0180 0014 CECTL3 EMIFA CE3 space control 0180 0018 SDCTL EMIFA SDRAM control 0180 001C SDTIM EMIFA SDRAM refresh control 0180 0020 SDEXT EMIFA SDRAM extension 0180 0024 - 0180 003C - 0180 0040 PDTCTL Peripheral device transfer (PDT) control 0180 0044 CESEC1 EMIFA CE1 space secondary control 0180 0048 CESEC0 COMMENTS EMIFA CE0 space secondary control Reserved Reserved 0180 004C - 0180 0050 CESEC2 Reserved EMIFA CE2 space secondary control 0180 0054 CESEC3 EMIFA CE3 space secondary control 0180 0058 - 0183 FFFF ­ Reserved Table 2-4. L2 Cache Registers (C64x) HEX ADDRESS RANGE ACRONYM 0184 0000 CCFG REGISTER NAME COMMENTS Cache configuration register 0184 0004 - 0184 0FFC - 0184 1000 EDMAWEIGHT Reserved 0184 1004 - 0184 1FFC - 0184 2000 L2ALLOC0 L2 allocation register 0 0184 2004 L2ALLOC1 L2 allocation register 1 L2 EDMA access control register Reserved 0184 2008 L2ALLOC2 L2 allocation register 2 0184 200C L2ALLOC3 L2 allocation register 3 0184 2010 - 0184 3FFC - 0184 4000 L2WBAR L2 writeback base address register 0184 4004 L2WWC L2 writeback word count register 0184 4010 L2WIBAR L2 writeback invalidate base address register 0184 4014 L2WIWC L2 writeback invalidate word count register 0184 4018 L2IBAR L2 invalidate base address register 0184 401C L2IWC L2 invalidate word count register 0184 4020 L1PIBAR L1P invalidate base address register 0184 4024 L1PIWC L1P invalidate word count register 0184 4030 L1DWIBAR April 2004 - Revised May 2005 Reserved L1D writeback invalidate base address register SPRS247E SPRS247E 23 Peripheral Register Descriptions Table 2-4. L2 Cache Registers (C64x) (Continued) HEX ADDRESS RANGE ACRONYM 0184 4034 L1DWIWC 0184 4038 - 0184 4044 - REGISTER NAME L1D writeback invalidate word count register Reserved 0184 4048 L1DIBAR L1D invalidate base address register 0184 404C L1DIWC L1D invalidate word count register 0184 4050 - 0184 4FFC - 0184 5000 L2WB 0184 5004 L2WBINV Reserved L2 writeback all register L2 writeback invalidate all register 0184 5008 - 0184 7FFC - Reserved 0184 8000 - 0184 81FC MAR0 to MAR127 MAR127 Reserved 0184 8200 MAR128 MAR128 Controls EMIFA CE0 range 8000 0000 - 80FF FFFF 0184 8204 MAR129 MAR129 Controls EMIFA CE0 range 8100 0000 - 81FF FFFF 0184 8208 MAR130 MAR130 Controls EMIFA CE0 range 8200 0000 - 82FF FFFF 0184 820C MAR131 MAR131 Controls EMIFA CE0 range 8300 0000 - 83FF FFFF 0184 8210 MAR132 MAR132 Controls EMIFA CE0 range 8400 0000 - 84FF FFFF 0184 8214 MAR133 MAR133 Controls EMIFA CE0 range 8500 0000 - 85FF FFFF 0184 8218 MAR134 MAR134 Controls EMIFA CE0 range 8600 0000 - 86FF FFFF 0184 821C MAR135 MAR135 Controls EMIFA CE0 range 8700 0000 - 87FF FFFF 0184 8220 MAR136 MAR136 Controls EMIFA CE0 range 8800 0000 - 88FF FFFF 0184 8224 MAR137 MAR137 Controls EMIFA CE0 range 8900 0000 - 89FF FFFF 0184 8228 MAR138 MAR138 Controls EMIFA CE0 range 8A00 0000 - 8AFF FFFF 0184 822C MAR139 MAR139 Controls EMIFA CE0 range 8B00 0000 - 8BFF FFFF 0184 8230 MAR140 MAR140 Controls EMIFA CE0 range 8C00 0000 - 8CFF FFFF 0184 8234 MAR141 MAR141 Controls EMIFA CE0 range 8D00 0000 - 8DFF FFFF 0184 8238 MAR142 MAR142 Controls EMIFA CE0 range 8E00 0000 - 8EFF FFFF 0184 823C MAR143 MAR143 Controls EMIFA CE0 range 8F00 0000 - 8FFF FFFF 0184 8240 MAR144 MAR144 Controls EMIFA CE1 range 9000 0000 - 90FF FFFF 0184 8244 MAR145 MAR145 Controls EMIFA CE1 range 9100 0000 - 91FF FFFF 0184 8248 MAR146 MAR146 Controls EMIFA CE1 range 9200 0000 - 92FF FFFF 0184 824C MAR147 MAR147 Controls EMIFA CE1 range 9300 0000 - 93FF FFFF 0184 8250 MAR148 MAR148 Controls EMIFA CE1 range 9400 0000 - 94FF FFFF 0184 8254 MAR149 MAR149 Controls EMIFA CE1 range 9500 0000 - 95FF FFFF 0184 8258 MAR150 MAR150 Controls EMIFA CE1 range 9600 0000 - 96FF FFFF 0184 825C MAR151 MAR151 Controls EMIFA CE1 range 9700 0000 - 97FF FFFF 0184 8260 MAR152 MAR152 Controls EMIFA CE1 range 9800 0000 - 98FF FFFF 0184 8264 MAR153 MAR153 Controls EMIFA CE1 range 9900 0000 - 99FF FFFF 0184 8268 MAR154 MAR154 Controls EMIFA CE1 range 9A00 0000 - 9AFF FFFF 0184 826C MAR155 MAR155 Controls EMIFA CE1 range 9B00 0000 - 9BFF FFFF 0184 8270 MAR156 MAR156 Controls EMIFA CE1 range 9C00 0000 - 9CFF FFFF 0184 8274 MAR157 MAR157 Controls EMIFA CE1 range 9D00 0000 - 9DFF FFFF 0184 8278 MAR158 MAR158 Controls EMIFA CE1 range 9E00 0000 - 9EFF FFFF 0184 827C MAR159 MAR159 Controls EMIFA CE1 range 9F00 0000 - 9FFF FFFF 0184 8280 24 COMMENTS MAR160 MAR160 Controls EMIFA CE2 range A000 0000 - A0FF FFFF SPRS247E SPRS247E April 2004 - Revised May 2005 Peripheral Register Descriptions Table 2-4. L2 Cache Registers (C64x) (Continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8284 MAR161 MAR161 Controls EMIFA CE2 range A100 0000 - A1FF FFFF 0184 8288 MAR162 MAR162 Controls EMIFA CE2 range A200 0000 - A2FF FFFF 0184 828C MAR163 MAR163 Controls EMIFA CE2 range A300 0000 - A3FF FFFF 0184 8290 MAR164 MAR164 Controls EMIFA CE2 range A400 0000 - A4FF FFFF 0184 8294 MAR165 MAR165 Controls EMIFA CE2 range A500 0000 - A5FF FFFF 0184 8298 MAR166 MAR166 Controls EMIFA CE2 range A600 0000 - A6FF FFFF 0184 829C MAR167 MAR167 Controls EMIFA CE2 range A700 0000 - A7FF FFFF 0184 82A0 MAR168 MAR168 Controls EMIFA CE2 range A800 0000 - A8FF FFFF 0184 82A4 MAR169 MAR169 Controls EMIFA CE2 range A900 0000 - A9FF FFFF 0184 82A8 MAR170 MAR170 Controls EMIFA CE2 range AA00 0000 - AAFF FFFF 0184 82AC MAR171 MAR171 Controls EMIFA CE2 range AB00 0000 - ABFF FFFF 0184 82B0 MAR172 MAR172 Controls EMIFA CE2 range AC00 0000 - ACFF FFFF 0184 82B4 MAR173 MAR173 COMMENTS Controls EMIFA CE2 range AD00 0000 - ADFF FFFF 0184 82B8 MAR174 MAR174 Controls EMIFA CE2 range AE00 0000 - AEFF FFFF 0184 82BC MAR175 MAR175 Controls EMIFA CE2 range AF00 0000 - AFFF FFFF 0184 82C0 MAR176 MAR176 Controls EMIFA CE3 range B000 0000 - B0FF FFFF 0184 82C4 MAR177 MAR177 Controls EMIFA CE3 range B100 0000 - B1FF FFFF 0184 82C8 MAR178 MAR178 Controls EMIFA CE3 range B200 0000 - B2FF FFFF 0184 82CC MAR179 MAR179 Controls EMIFA CE3 range B300 0000 - B3FF FFFF 0184 82D0 MAR180 MAR180 Controls EMIFA CE3 range B400 0000 - B4FF FFFF 0184 82D4 MAR181 MAR181 Controls EMIFA CE3 range B500 0000 - B5FF FFFF 0184 82D8 MAR182 MAR182 Controls EMIFA CE3 range B600 0000 - B6FF FFFF 0184 82DC MAR183 MAR183 Controls EMIFA CE3 range B700 0000 - B7FF FFFF 0184 82E0 MAR184 MAR184 Controls EMIFA CE3 range B800 0000 - B8FF FFFF 0184 82E4 MAR185 MAR185 Controls EMIFA CE3 range B900 0000 - B9FF FFFF 0184 82E8 MAR186 MAR186 Controls EMIFA CE3 range BA00 0000 - BAFF FFFF 0184 82EC MAR187 MAR187 Controls EMIFA CE3 range BB00 0000 - BBFF FFFF 0184 82F0 MAR188 MAR188 Controls EMIFA CE3 range BC00 0000 - BCFF FFFF 0184 82F4 MAR189 MAR189 Controls EMIFA CE3 range BD00 0000 - BDFF FFFF 0184 82F8 MAR190 MAR190 Controls EMIFA CE3 range BE00 0000 - BEFF FFFF 0184 82FC MAR191 MAR191 Controls EMIFA CE3 range BF00 0000 - BFFF FFFF 0184 8300 -0184 83FC MAR192 MAR192 to MAR255 MAR255 Reserved 0184 8400 -0187 FFFF - Reserved April 2004 - Revised May 2005 SPRS247E SPRS247E 25 Peripheral Register Descriptions Table 2-5. Quick DMA (QDMA) and Pseudo Registers HEX ADDRESS RANGE ACRONYM 0200 0000 QOPT QDMA options parameter register 0200 0004 QSRC QDMA source address register 0200 0008 QCNT QDMA frame count register 0200 000C QDST QDMA destination address register 0200 0010 QIDX QDMA index register 0200 0014 - 0200 001C REGISTER NAME Reserved 0200 0020 QSOPT QDMA pseudo options register 0200 0024 QSSRC QDMA psuedo source address register 0200 0028 QSCNT QDMA psuedo frame count register 0200 002C QSDST QDMA destination address register 0200 0030 QSIDX QDMA psuedo index register Table 2-6. EDMA Registers (C64x) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0800 - 01A0 FF98 - 01A0 FF9C EPRH Reserved Event polarity high register 01A0 FFA4 CIPRH Channel interrupt pending high register 01A0 FFA8 CIERH Channel interrupt enable high register 01A0 FFAC CCERH Channel chain enable high register 01A0 FFB0 ERH 01A0 FFB4 EERH Event high register Event enable high register 01A0 FFB8 ECRH Event clear high register 01A0 FFBC ESRH Event set high register 01A0 FFC0 PQAR0 Priority queue allocation register 0 01A0 FFC4 PQAR1 Priority queue allocation register 1 01A0 FFC8 PQAR2 Priority queue allocation register 2 01A0 FFCC PQAR3 Priority queue allocation register 3 01A0 FFDC EPRL Event polarity low register 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPRL Channel interrupt pending low register 01A0 FFE8 CIERL Channel interrupt enable low register 01A0 FFEC CCERL Channel chain enable low register 01A0 FFF0 EERL Event enable low register 01A0 FFF8 ECRL Event clear low register 01A0 FFFC ESRL Event set low register 01A1 0000 - 01A3 FFFF 26 ERL 01A0 FFF4 ­ SPRS247E SPRS247E Event low register Reserved April 2004 - Revised May 2005 Peripheral Register Descriptions Table 2-7. EDMA Parameter RAM (C64x) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0000 - 01A0 0017 - Parameters for Event 0 (6 words) 01A0 0018 - 01A0 002F - Parameters for Event 1 (6 words) 01A0 0030 - 01A0 0047 - Parameters for Event 2 (6 words) 01A0 0048 - 01A0 005F - Parameters for Event 3 (6 words) 01A0 0060 - 01A0 0077 - Parameters for Event 4 (6 words) 01A0 0078 - 01A0 008F - Parameters for Event 5 (6 words) 01A0 0090 - 01A0 00A7 - Parameters for Event 6 (6 words) 01A0 00A8 - 01A0 00BF - Parameters for Event 7 (6 words) 01A0 00C0 - 01A0 00D7 - Parameters for Event 8 (6 words) 01A0 00D8 - 01A0 00EF - Parameters for Event 9 (6 words) 01A0 00F0 - 01A0 00107 - Parameters for Event 10 (6 words) 01A0 0108 - 01A0 011F - Parameters for Event 11 (6 words) 01A0 0120 - 01A0 0137 - Parameters for Event 12 (6 words) 01A0 0138 - 01A0 014F - Parameters for Event 13 (6 words) 01A0 0150 - 01A0 0167 - Parameters for Event 14 (6 words) 01A0 0168 - 01A0 017F - Parameters for Event 15 (6 words) 01A0 0150 - 01A0 0197 - Parameters for Event 16 (6 words) 01A0 0168 - 01A0 01AF - Parameters for Event 17 (6 words) . . 01A0 05D0 - 01A0 05E7 - Parameters for Event 62 (6 words) 01A0 05E8 - 01A0 05FF - Parameters for Event 63 (6 words) 01A0 0600 - 01A0 0617 - Reload/link parameters for Event 0 (6 words) 01A0 0618 - 01A0 062F - Reload/link parameters for Event 1 (6 words) Reload/Link Parameters for other Event 0-15 . . 01A0 07E0 - 01A0 07F7 - Reload/link parameters for Event 20 (6 words) 01A0 07F8 - 01A0 080F - Reload/link parameters for Event 21 (6 words) 01A0 0810 - 01A0 0827 - Reload/link parameters for Event 22 (6 words) . . 01A0 13C8 - 01A0 13DF - Reload/link parameters for Event 147 (6 words) 01A0 13E0 - 01A0 13F7 - Reload/link parameters for Event 148 (6 words) 01A0 13F8 - 01A0 13FF - Scratch pad area (2 words) 01A0 1400 - 01A3 FFFF COMMENTS Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event - Reserved The C6413/C6410 C6413/C6410 device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each] that can be used to reload/link EDMA transfers. April 2004 - Revised May 2005 SPRS247E SPRS247E 27 Peripheral Register Descriptions Table 2-8. Interrupt Selector Registers (C64x) HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10-15 (INT10-INT15 INT10-INT15) 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4-9 (INT04-INT09 INT04-INT09) 019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts (EXT_INT4-EXT_INT7) 019C 000C - 019F FFFF - Reserved Table 2-9. Device Configuration Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01B3 F000 PERCFG Peripheral Configuration Register Enables or disables specific peripherals. This register is also used for power-down of disabled peripherals. 01B3 F004 DEVSTAT Device Status Register Read-only. Provides status of the User's device configuration on reset. 01B3 F008 JTAGID JTAG Identification Register Read-only. Provides JTAG ID of the device. 01B3 F00C - 01B3 F014 PCFGLOCK 01B3 F01C - 01B3 FFFF 28 - 01B3 F018 - SPRS247E SPRS247E 32-bit Reserved Peripheral Configuration Lock Register Reserved April 2004 - Revised May 2005 Peripheral Register Descriptions Table 2-10. McBSP 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 018C 0000 DRR0 McBSP0 data receive register via Configuration Bus 0x3000 0000 - 0x33FF FFFF DRR0 McBSP0 data receive register via Peripheral Bus 018C 0004 DXR0 McBSP0 data transmit register via Configuration Bus 0x3000 0000 - 0x33FF FFFF DXR0 McBSP0 data transmit register via Peripheral Bus 018C 0008 SPCR0 018C 000C RCR0 McBSP0 receive control register 018C 0010 XCR0 McBSP0 transmit control register 018C 0014 SRGR0 018C 0018 MCR0 018C 001C RCERE00 RCERE00 McBSP0 enhanced receive channel enable register 0 018C 0020 XCERE00 XCERE00 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. McBSP0 enhanced transmit channel enable register 0 McBSP0 serial port control register McBSP0 sample rate generator register McBSP0 multichannel control register 018C 0024 PCR0 018C 0028 RCERE10 RCERE10 McBSP0 pin control register McBSP0 enhanced receive channel enable register 1 018C 002C XCERE10 XCERE10 McBSP0 enhanced transmit channel enable register 1 018C 0030 RCERE20 RCERE20 McBSP0 enhanced receive channel enable register 2 018C 0034 XCERE20 XCERE20 McBSP0 enhanced transmit channel enable register 2 018C 0038 RCERE30 RCERE30 McBSP0 enhanced receive channel enable register 3 018C 003C XCERE30 XCERE30 McBSP0 enhanced transmit channel enable register 3 018C 0040 - 018F FFFF ­ Reserved Table 2-11. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0190 0000 DRR1 McBSP1 data receive register via Configuration Bus 0x3400 0000 - 0x37FF FFFF DRR1 McBSP1 data receive register via peripheral bus 0190 0004 DXR1 McBSP1 data transmit register via configuration bus 0x3400 0000 - 0x37FF FFFF DXR1 McBSP1 data transmit register via peripheral bus 0190 0008 SPCR1 0190 000C RCR1 McBSP1 receive control register 0190 0010 XCR1 McBSP1 transmit control register 0190 0014 SRGR1 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. McBSP1 serial port control register McBSP1 sample rate generator register 0190 0018 MCR1 0190 001C RCERE01 RCERE01 McBSP1 multichannel control register McBSP1 enhanced receive channel enable register 0 0190 0020 XCERE01 XCERE01 McBSP1 enhanced transmit channel enable register 0 0190 0024 PCR1 0190 0028 RCERE11 RCERE11 McBSP1 enhanced receive channel enable register 1 0190 002C XCERE11 XCERE11 McBSP1 enhanced transmit channel enable register 1 0190 0030 RCERE21 RCERE21 McBSP1 enhanced receive channel enable register 2 0190 0034 XCERE21 XCERE21 McBSP1 enhanced transmit channel enable register 2 McBSP1 pin control register 0190 0038 RCERE31 RCERE31 McBSP1 enhanced receive channel enable register 3 0190 003C XCERE31 XCERE31 McBSP1 enhanced transmit channel enable register 3 0190 0040 - 0193 FFFF ­ April 2004 - Revised May 2005 Reserved SPRS247E SPRS247E 29 Peripheral Register Descriptions Table 2-12. Timer 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0194 0000 CTL0 Timer 0 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0194 0004 PRD0 Timer 0 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter. 0194 000C - 0197 FFFF - Reserved Table 2-13. Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0198 0000 CTL1 Timer 1 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0198 0004 PRD1 Timer 1 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter. 0198 000C - 019B FFFF - Reserved Table 2-14. Timer 2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01AC 0000 CTL2 Timer 2 control register Determines the operating mode of the timer, monitors the timer status. 01AC 0004 PRD2 Timer 2 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 01AC 0008 CNT2 Timer 2 counter register Contains the current value of the incrementing counter. 01AC 000C - 01AF FFFF - 30 SPRS247E SPRS247E Reserved April 2004 - Revised May 2005 Peripheral Register Descriptions Table 2-15. HPI Registers HEX ADDRESS RANGE HPID HPI data register Host read/write access only 0188 0000 HPIC HPI control register HPIC has both Host/CPU read/write access 0188 0004 HPIA (HPIAW) HPI address register (Write) 0188 0008 HPIA (HPIAR) HPI address register (Read) 0188 000C - 0189 FFFF - 018A 0000 HPI_TRCTL 018A 0004 - 018B FFFF ACRONYM - REGISTER NAME COMMENTS - HPIA has both Host/CPU read/write access Reserved HPI transfer request control register Reserved Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently. Table 2-16. GP0 Registers HEX ADDRESS RANGE ACRONYM 01B0 0000 GPEN GP0 enable register REGISTER NAME 01B0 0004 GPDIR GP0 direction register 01B0 0008 GPVAL GP0 value register 01B0 000C - Reserved 01B0 0010 GPDH GP0 delta high register 01B0 0014 GPHM GP0 high mask register 01B0 0018 GPDL GP0 delta low register 01B0 001C GPLM GP0 low mask register 01B0 0020 GPGC GP0 global control register 01B0 0024 GPPOL GP0 interrupt polarity register 01B0 0028 - 01B3 EFFF - April 2004 - Revised May 2005 Reserved SPRS247E SPRS247E 31 Peripheral Register Descriptions Table 2-17. McASP0 and McASP1 Control Registers HEX ADDRESS RANGE ACRONYM McASP0 McASP1 01B4 C000 01B5 0000 PID 01B4 C004 01B5 0004 PWRDEMU REGISTER NAME Peripheral Identification register [Register value: 0x0010 0101] Power down and emulation management register 01B4 C008 01B5 0008 - Reserved 01B4 C00C 01B5 000C - Reserved 01B4 C010 01B5 0010 PFUNC Pin function register 01B4 C014 01B5 0014 PDIR Pin direction register 01B4 C018 01B5 0018 PDOUT Pin data out register 01B4 C01C 01B5 001C PDIN/PDSET Pin data in / data set register Read returns: PDIN Writes affect: PDSET 01B4 C020 01B5 0020 PDCLR 01B4 C024 - 01B4 C040 01B5 0024 - 01B5 0040 - 01B4 C044 01B5 0044 GBLCTL Global control register 01B4 C048 01B5 0048 AMUTE Mute control register 01B4 C04C 01B5 004C DLBCTL Digital Loop-back control register DIT mode control register 01B4 C050 01B5 0050 DITCTL 01B4 C054 - 01B4 C05C 01B5 0054 - 01B5 005C - 01B4 C060 01B5 0060 RGBLCTL 01B4 C064 01B5 0064 RMASK Pin data clear register Reserved Reserved Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive. Receiver format unit bit mask register 01B4 C068 01B5 0068 RFMT 01B4 C06C 01B5 006C AFSRCTL 01B4 C070 01B5 0070 ACLKRCTL 01B4 C074 01B5 0074 AHCLKRCTL 01B4 C078 01B5 0078 RTDM 01B4 C07C 01B5 007C RINTCTL 01B4 C080 01B5 0080 RSTAT Status register - Receiver 01B4 C084 01B5 0084 RSLOT Current receive TDM slot register 01B4 C088 01B5 0088 RCLKCHK 01B4 C08C - 01B4 C09C 01B5 008C - 01B5 009C - 01B4 C0A0 01B5 00A0 XGBLCTL 01B4 C0A4 01B5 00A4 XMASK Receive bit stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive TDM slot 0-31 register Receiver interrupt control register Receiver clock check control register Reserved Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. Transmit format unit bit mask register 01B4 C0A8 XFMT 01B5 00AC AFSXCTL 01B4 C0B0 01B5 00B0 ACLKXCTL 01B4 C0B4 01B5 00B4 AHCLKXCTL 01B4 C0B8 01B5 00B8 XTDM Transmit TDM slot 0-31 register 01B4 C0BC 01B5 00BC XINTCTL Transmit interrupt control register 01B4 C0C0 01B5 00C0 XSTAT Status register - Transmitter 01B4 C0C4 01B5 00C4 XSLOT Current transmit TDM slot 01B4 C0C8 32 01B5 00A8 01B4 C0AC 01B5 00C8 XCLKCHK SPRS247E SPRS247E Transmit bit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register Transmit clock check control register April 2004 - Revised May 2005 Peripheral Register Descriptions Table 2-17. McASP0 and McASP1 Control Registers (Continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME McASP0 McASP1 01B4 C0CC - 01B4 C0FC 01B5 00CC - 01B5 00FC - 01B4 C100 01B5 0100 DITCSRA0 Left (even TDM slot) channel status register file 01B4 C104 01B5 0104 DITCSRA1 Left (even TDM slot) channel status register file 01B4 C108 01B5 0108 DITCSRA2 Left (even TDM slot) channel status register file 01B4 C10C 01B5 010C DITCSRA3 Left (even TDM slot) channel status register file 01B4 C110 01B5 0110 DITCSRA4 Left (even TDM slot) channel status register file 01B4 C114 01B5 0114 DITCSRA5 Left (even TDM slot) channel status register file Reserved 01B4 C118 01B5 0118 DITCSRB0 Right (odd TDM slot) channel status register file 01B4 C11C 01B5 011C DITCSRB1 Right (odd TDM slot) channel status register file 01B4 C120 01B5 0120 DITCSRB2 Right (odd TDM slot) channel status register file 01B4 C124 01B5 0124 DITCSRB3 Right (odd TDM slot) channel status register file 01B4 C128 01B5 0128 DITCSRB4 Right (odd TDM slot) channel status register file 01B4 C12C 01B5 012C DITCSRB5 Right (odd TDM slot) channel status register file 01B4 C130 01B5 0130 DITUDRA0 Left (even TDM slot) user data register file 01B4 C134 01B5 0134 DITUDRA1 Left (even TDM slot) user data register file 01B4 C138 01B5 0138 DITUDRA2 Left (even TDM slot) user data register file 01B4 C13C 01B5 013C DITUDRA3 Left (even TDM slot) user data register file 01B4 C140 01B5 0140 DITUDRA4 Left (even TDM slot) user data register file 01B4 C144 01B5 0144 DITUDRA5 Left (even TDM slot) user data register file 01B4 C148 01B5 0148 DITUDRB0 Right (odd TDM slot) user data register file 01B4 C14C 01B5 014C DITUDRB1 Right (odd TDM slot) user data register file 01B4 C150 01B5 0150 DITUDRB2 Right (odd TDM slot) user data register file 01B4 C154 01B5 0154 DITUDRB3 Right (odd TDM slot) user data register file 01B4 C158 01B5 0158 DITUDRB4 Right (odd TDM slot) user data register file 01B4 C15C 01B5 015C DITUDRB5 Right (odd TDM slot) user data register file 01B4 C160 - 01B4 C17C 01B5 0160 - 01B5 017C - 01B4 C180 01B5 0180 SRCTL0 Serializer 0 control register 01B4 C184 01B5 0184 SRCTL1 Serializer 1 control register Reserved 01B4 C188 01B5 0188 SRCTL2 Serializer 2 control register 01B4 C18C 01B5 018C SRCTL3 Serializer 3 control register 01B4 C190 01B5 0190 SRCTL4 Serializer 4 control register 01B4 C194 01B5 0194 SRCTL5 Serializer 5 control register 01B4 C198 01B5 0198 - Reserved 01B4 C19C 01B5 019C - Reserved 01B4 C1A0 - 01B4 C1FC 01B5 01A0 - 01B5 01FC - Reserved 01B4 C200 01B5 0200 XBUF0 Transmit Buffer for Serializer 0 01B4 C204 01B5 0204 XBUF1 Transmit Buffer for Serializer 1 01B4 C208 01B5 0208 XBUF2 Transmit Buffer for Serializer 2 01B4 C20C 01B5 020C XBUF3 Transmit Buffer for Serializer 3 01B4 C210 01B5 0210 XBUF4 Transmit Buffer for Serializer 4 01B4 C214 01B5 0214 XBUF5 Transmit Buffer for Serializer 5 April 2004 - Revised May 2005 SPRS247E SPRS247E 33 Peripheral Register Descriptions Table 2-17. McASP0 and McASP1 Control Registers (Continued) HEX ADDRESS RANGE McASP0 McASP1 ACRONYM REGISTER NAME 01B4 C218 01B5 0218 - Reserved 01B4 C21C 01B5 021C - Reserved 01B4 C220 - 01B4 C27C 01B5 0220 - 01B5 027C - Reserved 01B4 C280 01B5 0280 RBUF0 Receive Buffer for Serializer 0 01B4 C284 01B5 0284 RBUF1 Receive Buffer for Serializer 1 01B4 C288 01B5 0288 RBUF2 Receive Buffer for Serializer 2 01B4 C28C 01B5 028C RBUF3 Receive Buffer for Serializer 3 01B4 C290 01B5 0290 RBUF4 Receive Buffer for Serializer 4 01B4 C294 01B5 0294 RBUF5 Receive Buffer for Serializer 5 01B4 C298 01B5 0298 - Reserved 01B4 C29C 01B5 029C - Reserved 01B4 C2A0 - 01B4 FFFF 01B5 02A0 - 01B5 3FFF - Reserved Table 2-18. McASP0 Data Registers HEX ADDRESS RANGE ACRONYM 3C00 0000 - 3C0F FFFF RBUF/XBUFx REGISTER NAME McASPx receive buffers or McASPx transmit buffers via the Peripheral Data Bus. COMMENTS (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].) Table 2-19. McASP1 Data Registers HEX ADDRESS RANGE 3C10 0000 - 3C1F FFFF 34 SPRS247E SPRS247E ACRONYM RBUF/XBUFx REGISTER NAME McASPx receive buffers or McASPx transmit buffers via the Peripheral Data Bus. COMMENTS (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].) April 2004 - Revised May 2005 Peripheral Register Descriptions Table 2-20. I2C0 and I2C1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME I2C0 I2C1 01B4 0000 01B4 4000 I2COARx I2Cx own address register 01B4 0004 01B4 4004 I2CIMRx I2Cx interrupt mask/status register 01B4 0008 01B4 4008 I2CSTRx I2Cx interrupt status register 01B4 000C 01B4 400C I2CCLKLx I2Cx clock low-time divider register 01B4 0010 01B4 4010 I2CCLKHx I2Cx clock high-time divider register 01B4 0014 01B4 4014 I2CCNTx I2Cx data count register 01B4 0018 01B4 4018 I2CDRRx I2Cx data receive register 01B4 001C 01B4 401C I2CSARx I2Cx slave address register 01B4 0020 01B4 4020 I2CDXRx I2Cx data transmit register 01B4 0024 01B4 4024 I2CMDRx I2Cx mode register 01B4 0028 01B4 4028 I2CIVRx I2Cx interrupt vector register 01B4 002C 01B4 402C I2CEMDRx I2Cx Extended mode register 01B4 0030 01B4 4030 I2CPSCx I2Cx prescaler register 01B4 0034 01B4 4034 I2CPID1x I2Cx Peripheral Identification register 1 [Value: 0x0000 0105] 01B4 0038 01B4 4038 I2CPID2x I2Cx Peripheral Identification register 2 [Value: 0x0000 0005] 01B4 003C - 01B4 0044 01B4 403C - 01B4 4044 - 01B4 0048 01B4 4048 I2CPFUNCx I2Cx pin function register 01B4 004C 01B4 404C I2CPDIRx I2Cx pin direction register 01B4 0050 01B4 4050 I2CPDINx I2Cx pin data in register 01B4 0054 01B4 4054 I2CPDOUTx I2Cx pin data out register Reserved 01B4 0058 01B4 4058 I2CPDSETx I2Cx pin data set register 01B4 005C 01B4 405C I2CPDCLRx I2Cx pin data clear register 01B4 0060 - 01B4 3FFF 01B4 4060 - 01B4 7FFF - April 2004 - Revised May 2005 Reserved SPRS247E SPRS247E 35 EDMA Channel Synchronization Events 2.7 EDMA Channel Synchronization Events The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 2-21 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the C6413/C6410 C6413/C6410 device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234 SPRU234). Table 2-21. TMS320C6413/C6410 TMS320C6413/C6410 EDMA Channel Synchronization Events EDMA CHANNEL EVENT NAME 0 DSP_INT 1 TINT0 Timer 0 interrupt 2 TINT1 Timer 1 interrupt 3 SD_INTA 4 GPINT4/EXT_INT4 GP0 event 4/External interrupt pin 4 5 GPINT5/EXT_INT5 GP0 event 5/External interrupt pin 5 6 GPINT6/EXT_INT6 GP0 event 6/External interrupt pin 6 7 GPINT7/EXT_INT7 GP0 event 7/External interrupt pin 7 8 GPINT0 GP0 event 0 9 GPINT1 GP0 event 1 10 GPINT2 GP0 event 2 11 GPINT3 GP0 event 3 12 XEVT0 McBSP0 transmit event 13 REVT0 McBSP0 receive event 14 XEVT1 McBSP1 transmit event McBSP1 receive event EVENT DESCRIPTION HPI-to-DSP interrupt EMIFA SDRAM timer interrupt 15 REVT1 16-18 ­ 19 TINT2 20-27 ­ None 28 ­ None None Timer 2 interrupt 29 ­ None 30-31 ­ None 32 AXEVTE0 McASP0 transmit even event 33 AXEVTO0 McASP0 transmit odd event 34 AXEVT0 McASP0 transmit event 35 AREVTE0 McASP0 receive even event 36 AREVTO0 McASP0 receive odd event 37 AREVT0 McASP0 receive event 38 36 McASP1 transmit even event AXEVTO1 McASP1 transmit odd event 40 AXEVTE1 39 AXEVT1 McASP1 transmit event In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234 SPRU234). SPRS247E SPRS247E April 2004 - Revised May 2005 Interrupt Sources and Interrupt Selector Table 2-21. TMS320C6413/C6410 TMS320C6413/C6410 EDMA Channel Synchronization Events (Continued) EDMA CHANNEL EVENT NAME EVENT DESCRIPTION 41 McASP1 receive even event AREVTO1 McASP1 receive odd event 43 AREVT1 McASP1 receive event 44 ICREVT0 I2C0 receive event 45 ICXEVT0 I2C0 transmit event 46 ICREVT1 I2C1 receive event 47 ICXEVT1 I2C1 transmit event 48 GPINT8 GP0 event 8 49 GPINT9 GP0 event 9 50 GPINT10 GPINT10 GP0 event 10 51 GPINT11 GPINT11 GP0 event 11 52 GPINT12 GPINT12 GP0 event 12 53 GPINT13 GPINT13 GP0 event 13 54 GPINT14 GPINT14 GP0 event 14 55 GPINT15 GPINT15 GP0 event 15 56-63 AREVTE1 42 ­ None In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234 SPRU234). 2.8 Interrupt Sources and Interrupt Selector The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 2-22. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00-INT 00-INT_03) are non-maskable and fixed. The remaining interrupts (INT_04-INT 04-INT_15) are maskable and default to the interrupt source specified in Table 2-22. The interrupt source for interrupts 4-15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004). April 2004 - Revised May 2005 SPRS247E SPRS247E 37 Interrupt Sources and Interrupt Selector Table 2-22. C6413/C6410 C6413/C6410 DSP Interrupts CPU INTERRUPT NUMBER INTERRUPT SELECTOR CONTROL REGISTER SELECTOR VALUE (BINARY) INTERRUPT EVENT INT_00 - - RESET INT_01 - - NMI INT_02 - - Reserved Reserved. Do not use. INT_03 - - Reserved Reserved. Do not use. INT_04 MUXL[4:0] 00100 GPINT4/EXT_INT4 GP0 interrupt 4/External interrupt pin 4 INT_05 MUXL[9:5] 00101 GPINT5/EXT_INT5 GP0 interrupt 5/External interrupt pin 5 INT_06 MUXL[14:10] 00110 GPINT6/EXT_INT6 GP0 interrupt 6/External interrupt pin 6 INT_07 MUXL[20:16] 00111 GPINT7/EXT_INT7 GP0 interrupt 7/External interrupt pin 7 INT_08 MUXL[25:21] 01000 EDMA_INT EDMA channel (0 through 63) interrupt INT_09 MUXL[30:26] 01001 EMU_DTDMA INT_10 MUXH[4:0] 00011 SD_INTA INT_11 MUXH[9:5] 01010 EMU_RTDXRX EMU real-time data exchange (RTDX) receive INT_12 MUXH[14:10] 01011 EMU_RTDXTX EMU RTDX transmit INT_13 MUXH[20:16] 00000 DSP_INT HPI-to-DSP interrupt INT_14 MUXH[25:21] 00001 TINT0 Timer 0 interrupt INT_15 MUXH[30:26] 00010 TINT1 Timer 1 interrupt - - 01100 XINT0 McBSP0 transmit interrupt - - 01101 RINT0 McBSP0 receive interrupt - - 01110 XINT1 McBSP1 transmit interrupt - - 01111 RINT1 McBSP1 receive interrupt - - 10000 GPINT0 - - 10001 Reserved Reserved. Do not use. - - 10010 Reserved Reserved. Do not use. - - 10011 TINT2 - - 10100 Reserved Reserved. Do not use. - - 10101 Reserved Reserved. Do not use. - - 10110 ICINT0 I2C0 interrupt - - 10111 ICINT1 I2C1 interrupt - - 11000 AXINT1 McASP1 transmit interrupt - - 11001 ARINT1 McASP1 receive interrupt - - 11010 Reserved Reserved. Do not use. - - 11011 Reserved Reserved. Do not use. - - 11100 AXINT0 McASP0 transmit interrupt - - 11101 ARINT0 McASP0 receive interrupt - - 11110 Reserved Reserved. Do not use. - - 11111 Reserved Reserved. Do not use. INTERRUPT SOURCE EMU DTDMA EMIFA SDRAM timer interrupt GP0 interrupt 0 Timer 2 interrupt Interrupts INT_00 through INT_03 are non-maskable and fixed. Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 2-22 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the TMS320C6000 TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646 SPRU646). 38 SPRS247E SPRS247E April 2004 - Revised May 2005 Signal Groups Description 2.9 Signal Groups Description CLKINSEL CLKIN CLKOUT4/GP0[1] CLKOUT6/GP0[2] CLKMODE3 CLKMODE2 CLKMODE1 CLKMODE0 PLLV OSCIN OSCOUT OSCVDD OSCVSS OSC_DIS