SPRA511B TMS320C6000 TMS320C6201 C6000 MSAN-126 SPRU190 E32B0 SPRA488 INT15 - Datasheet Archive

 

SPRA511B - June 2002 TMS320C6000 McBSP Interface to an ST-BUS Device Jamon Bowen Shaku Anjanaiah Digital Signal Processing

 

Application Report SPRA511B SPRA511B - June 2002 TMS320C6000 TMS320C6000 McBSP Interface to an ST-BUS Device Jamon Bowen Shaku Anjanaiah Digital Signal Processing Solutions ABSTRACT This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000 TMS320C6000 digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device. The McBSP receives the framing signal, clock, and data from the ST-BUS device and processes them to generate internal frame syncs and clocks for correct data reception. The highly programmable features of the McBSP make it easy to interface to ST-BUS signals. This application report focuses on the single rate ST-BUS, wherein the ST-BUS system clock and the data rate (number of bits per second) are equal. Hence, the name "single rate", which applies only to a 2.048 MHz system clock. The usage of McBSP registers and sample code to perform the above function are described in this document. 1 2 3 4 5 6 7 Contents Design Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST-BUS Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Operation for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Code Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 2 4 6 6 7 List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. McBSP Connection for 2.048-MHz Single-Rate ST Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Rate ST-BUS Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Rate ST-BUS Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Rate Generator Register (SRGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST-BUS Emulator and the McBSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram for Example Single Rate ST-BUS Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 5 5 5 5 7 7 List of Tables Table 1. Bit Field Values for McBSP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TMS320C6000 TMS320C6000 is a trademark of Texas Instruments Incorporated. ST-BUS is a trademark of Mitel. All trademarks are the property of their respective owners. 1 SPRA511B SPRA511B 1 Design Problem How do I use the multichannel buffered serial port in the TMS320C6201 TMS320C6201 to communicate to a single-rate ST-BUS-compliant device? 2 ST-BUS Requirements The ST-BUS1 is a synchronous serial bus with data transfer rates of 2.048, 4.096, or 8.192 Mbps. The interface to an ST-BUS device comprises the clock, frame, and data signals. These signals are available on the McBSP and are programmable, thereby making it a glueless interface. The ST-BUS data stream comprises of frames with a period of 125 ms, or a frame rate of 8000 frames per sec. This 8 kHz sampling rate (twice the highest signal frequency in order to retain all the information in the stream) corresponds to the 3.5 to 4 kHz voice band frequency. The frame signal indicates the start of a frame and each frame carries blocks of 8-bit data. The clocks for ST-BUS data can be 2.048, 4.096, 8.192, or 16.384 MHz. Note that these clocks are always twice the data rate, except for 2.048 MHz. Since the 2.048 MHz ST-BUS clock rate can also be the data rate, it is referred to as a single-rate ST-BUS. An example of a double-rate ST-BUS would be a 2.048 Mbps data stream, clocked by a 4.096MHz clock. The following sections describe the hardware and software interface of the C6000 C6000 McBSP to a single rate ST-BUS device.2 3 McBSP Operation for ST-BUS The ST-BUS-compliant device that the McBSP is interfacing to, is the master of frames and clock. This means that the ST-BUS device should provide a 2.048 MHz clock, C2, which becomes the external clock source to the McBSP via the CLKS pin. Also, the framing signal, FO, generated by the ST-BUS device, is used as the receive frame sync (FSR) input to the McBSP. The data transmitted on STo by the ST-BUS device, is received on the DR pin of the McBSP. These connections are shown in Figure 1. ST-BUSCompliant Device C6000 C6000 McBSP F0 FSR STo DR C2 CLKS Figure 1. McBSP Connection for 2.048-MHz Single-Rate ST Bus 1 See Mitel application note MSAN-126 MSAN-126, ST-BUS Generic Device Specification (Rev. B). 2 It is recommended that you be familiar with the features of the C6000 C6000 McBSP by reading the TMS320C6000 TMS320C6000 Peripheral Reference Guide (SPRU190 SPRU190), especially section 12.5.5. 2 TMS320C6000 TMS320C6000 McBSP Interface to an ST-BUS Device SPRA511B SPRA511B In order for the McBSP to recognize an ST-BUS data stream, the GSYNC bit in the sample rate Generator register must be set. The ST-BUS-provided frame sync, FO,is an active-low signal that is low for one-half of the CLKS period. The GSYNC bit causes the external frame sync that arrives on FSR to be sampled on the rising edge of CLKS and, in turn, generates an internal frame sync in the McBSP that is active-high for one CLKS clock period. This internal frame sync, FSR_int, is used as the reference for data reception. This is shown in Figure 2. C4 = 4.096 MHz FSR Sampled C2 = CLKS = 2.048 MHz FSR External FS(R/X)_INT, FSG CLK(R/X)_INT (First FSR) D(R/X) (First FSR) E1B7 E1B6 E1B5 E1B0 E2B7 E1B7 E1B6 E1B5 E1B0 E2B7 CLK(R/X)_INT (Subsequent FSR) D(R/X) (Subsequent FSR) E32B0 E32B0 ExBy = Element x Bit y Figure 2. Single-Rate ST-BUS Example In the 2.048 MHz single-rate ST-BUS example shown in Figure 2, the data stream comprises 32 elements of 8 bits each, in each frame. Each new frame starts with a new frame sync signal, FO. Since the McBSP receiver does not know when the first frame will arrive on FSR, and therefore does not know when to get out of reset and receive data, special interrupts should be used. This is made easy with the new frame sync interrupt that is available on the McBSP, and which works even when the receiver is in reset. The receive CPU interrupt (RINT) can be programmed to detect a new frame sync pulse, after which the CPU can safely take the receiver out of reset. Further initialization details are discussed in section 5 of this document. For the case of a double-rate ST-BUS clock, 4.096, 8.192, and 16.38-MHz clocks are supported with data rates equal to half of the ST-BUS clock rate. The ST-BUS clock drives the CLKS pin of the McBSP. The frame sync provided by the ST-BUS (FO) is active-low for one ST-BUS clock period, and drives the FSR pin of the McBSP. This external frame sync is sampled by the McBSP on the falling edge of CLKS to generate the required internal frame sync. The timing diagram for a double rate ST-BUS clock is shown in Figure 3. TMS320C6000 TMS320C6000 McBSP Interface to an ST-BUS Device 3 SPRA511B SPRA511B FSR Sampled CLKS=4.096/8.192 /16.384 MHz FSR External FS(R/X)_INT, FSG CLK(R/X)_INT (First FSR) D(R/X) (First FSR) E1B7 E1B6 E1B5 E1B0 E2B7 E1B7 E1B6 E1B5 E1B0 E2B7 CLK(R/X)_INT (Subsequent FSR) D(R/X) (Subsequent FSR) E32B0 E32B0 ExBy = Element x Bit y Figure 3. Double-Rate ST-BUS Timing Diagram The McBSP register setup for a double-rate operation is the same as the single rate, with the following exceptions: · · 4 CLKGDV = 1, so that the data rate is half the clock rate (CLKS). CLKSP = 1 ensures that the internal clocks CLKG, CLKR_int, CLKX_int are generated on the falling edge of CLKS; the same edge that generates the FSG, FSR_int, and FSX_int. McBSP Register Configuration As shown in Figure 1, FSR, CLKS, and DR are inputs. · Framing Signal: The polarity of the incoming frame sync signal (FO) must be inverted to provide the necessary active-high input signal to the McBSP. The external frame sync pulse dictates the arrival of a new frame; therefore, the frame period (FPER) and frame width (FWID) is not used/programmed. Although FSR is treated as input, the FSRM bit in PCR and FRST bit in SPCR must be set to 1. The FRST bit must be set to enable the frame sync signal generation. FSRM = 1 indicates that the internally generated FSR_int will be used to detect the arrival of data, but will not be output on FSR pin because GSYNC = 1 disables the output buffer. Since it is a single-phase frame, with each frame comprising of 32 elements with 8 bits each, FRLEN1 = 31 and WDLEN1 = 0. · · 4 Data Delay: Since there is no delay between the arrival of the first bit of data and the generation of internal frame sync FSR_int, the receiver should be set up for a data delay of zero. Clocks: Although CLKR pin of the McBSP is not used in this set up, it is necessary to configure it as an output. Another important parameter is the polarity of CLKS signal. The CLKS polarity determines the edge that samples the incoming frame sync signal and also the edge that generates internal clocks CLKG, CLKR_int, CLKX_int, and internal frame-sync signals FSG, FSR_int, and FSX_int. For the single-rate ST-BUS case, the rising edge of CLKS does the above function. TMS320C6000 TMS320C6000 McBSP Interface to an ST-BUS Device SPRA511B SPRA511B The various bit settings for the above requirements are shown in Figure 4 through Figure 7 and Table 1. 31 30 24 23 21 20 19 18 17 16 0 0 0 0 0 00 RPHASE RFRLEN2 RWDLEN2 RCOMPAND RFIG RDATDLY 15 8 7 14 5 4 0 0 31 0 0 R-0 RFRLEN1 RWDLEN1 R-0 Legend: R = Read Figure 4. Receive Control Register (RCR) 31 30 29 28 27 16 1 0 0 0 0 GSYNC CLKSP CLKSM FSGM FPER 8 7 15 0 0 0x00 FWID CLKGDV Figure 5. Sample Rate Generator Register (SRGR) 31 16 0x0000 R/W-0 15 14 13 12 9 10 11 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 R-0 XIOEN RIOEN FSXM FSRM CLKXM CLKRM R-0 CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP Legend: R = Read; R/W = Read/write Figure 6. Pin Control Register (PCR) 31 22 1 1 R+0 14 23 0x00 15 24 FRST GRST 13 12 11 10 8 21 20 19 18 17 16 0 0 0 0 0 XINTM XSYNCERR XEMPTY XRDY XRST 7 6 3 2 1 0 0 0 0 0 0 0 5 10 4 0 0 0 0 DLB RJUST CLKSTP R/W-0 R/W-0 R/W-0 RINTM RSYNCERR RFULL RRDY RRST Legend: R/W = Read/write Figure 7. Serial Port Control Register (SPCR) TMS320C6000 TMS320C6000 McBSP Interface to an ST-BUS Device 5 SPRA511B SPRA511B Table 1. Bit Field Values for McBSP Registers Register (Bit Field No.) Value (in Binary) Slave (Receiver) RCR[17:16] RDATDLY 0 (default) SPCR[5:4] RINTM 10b SPCR[23] FRST 1 SPCR[22] GRST 1 SRGR[31] GSYNC 1 SRGR[29] CLKSM 0 (default) SRGR[7:0] CLKGDV 0 (default) PCR[10] FSRM 1 PCR[8] CLKRM 1 PCR[2] 5 Bit Field Name FSRP 1 McBSP Initialization Typical applications use the (E)DMA to service the McBSP. Please refer to TMS320C6000 TMS320C6000 McBSP Initialization (SPRA488 SPRA488) to program the McBSP control registers and (E)DMA registers for proper serial port operation. In addition to this, the following step is required since the new frame sync interrupt is used to wake up the McBSP. 1. After the (E)DMA has been started, the first frame sync that arrives on FSR will wake up the receiver. This is done in the ISR corresponding to CPU_INT15 INT15. The interrupt service routine (ISR) should also disable this interrupt, so that subsequent frame syncs do not cause unnecessary enabling of the receiver that has already been taken out of reset. When the next frame sync arrives, the receiver provides the read sync event to the (E)DMA, which causes transfer of data from DRR to the specified destination address. The receiver continues to receive data until the required number of frames has been received. 6 Sample Code Setup The example code included with this document was tested on two McBSPs (McBSP0 and McBSP1) on a TMS320C6211 TMS320C6211 device. The block diagram of this test setup is shown in Figure 8. 6 TMS320C6000 TMS320C6000 McBSP Interface to an ST-BUS Device SPRA511B SPRA511B McBSP0 ST-BUS Emulator McBSP1 ST-BUSCompliant DR1 FSR1 CLKS1 DX0 FSX0 CLKS0 PAL fsx_in fsx_out CLKS 2.048 MHz Figure 8. ST-BUS Emulator and McBSP McBSP0 is configured as the ST-BUS transmitter (master), which provides the frame sync and data. The ST-BUS clock in this example is 2.048 MHz. The PAL uses FSX0 (fsx_in) to generate the active-low frame sync signal, fsx_out, at the appropriate rising edge of CLKS 0/1. Signal fsx_out is equivalent to FSR_ext signal, shown in Figure 2. The PAL equations in VHDL are included with this document. The resulting signals, due to the above set up, are shown in Figure 9. CLKS FSX0/fsx_in FSR1/fsx_out FSR1_int /FSG1_int RDATDLY1=0 XDATDLY0=1 DX0/DR1 E1B7 E1B6 E1B5 Figure 9. Timing Diagram for Example Single-Rate ST-BUS Setup 7 References 1. Mitel application note, MSAN-126 MSAN-126, ST-BUS Generic Device Specification (Rev. B). 2. TMS320C6000 TMS320C6000 Peripherals Reference Guide (SPRU190 SPRU190). 3. TMS320C6000 TMS320C6000 McBSP Initialization (SPRA488 SPRA488). TMS320C6000 TMS320C6000 McBSP Interface to an ST-BUS Device 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third­party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated