D415015-9761 SPRU164 XDS510 SPRU056 SPRS030 SPRA030 SPRA033 TMS320 SPRA052 - Datasheet Archive

 

GeneralPurpose Applications User's Guide 1997 Digital Signal Processing Solutions Printed in U.S.A., July 1997 D415015-9761

 

TMS320C5x GeneralPurpose Applications User's Guide 1997 Digital Signal Processing Solutions Printed in U.S.A., July 1997 D415015-9761 D415015-9761 revision * SPRU164 SPRU164 TMS320C5x General-Purpose Applications User's Guide Literature Number: SPRU164 SPRU164 Manufacturing Part Number: D415015-9761 D415015-9761 revision * July 1997 Printed on Recycled Paper Running Title-Attribute Reference IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright © 1997, Texas Instruments Incorporated ii Running Title-Attribute Reference Preface Read This First About This Manual This user's guide serves as a reference book for developing hardware and/or software applications for the TMS320C5x digital signal processors (DSPs). How to Use This Manual The following table summarizes the 'C5x information contained in this user's guide: If you are looking for information about: Turn to: Application reports Appendix C, Application Reports and Designer's Notebook Pages Designer's notebook pages Appendix C, Application Reports and Designer's Notebook Pages DSP features Chapter 1, Introduction External memory interfacing Chapter 3, External Memory interface Extended-precision arithmetic subroutines Chapter 2, Software Applications Fast Fourier transform subroutine Chapter 2, Software Applications Floating-point arithmetic subroutines Chapter 2, Software Applications Hardware applications Chapter 3, Analog Interface Peripherals and Applications Infinite impulse response (IIR) filter subroutines Chapter 2, Software Applications Memory-to-memory block move subroutines Chapter 2, Software Applications Modem applications Chapter 2, Software Applications Chapter 4, Analog Interface Peripherals and Applications iii How to Use This Manual / Notational Conventions If you are looking for information about: Turn to: Multimedia applications Chapter 4, Analog Interface Peripherals and Applications PACK and UNPACK subroutines Chapter 2, Software Applications Part order information Appendix B, Development Support and Part Order Information Processor initialization subroutine Chapter 2, Software Applications Servo control/disk drive applications Chapter 4, Analog Interface Peripherals and Applications Software applications Chapter 2, Software Applications Speech synthesis applications Chapter 4, Analog Interface Peripherals and Applications Telecommunications applications Chapter 4, Analog Interface Peripherals and Applications XDS510 XDS510 emulator Appendix A, Design Considerations for Using XDS510 XDS510 Emulator Notational Conventions This document uses the following conventions: - Program listings and program examples are shown in a special typeface. Here is a segment of a program listing: OUTPUT: LDP BLDD RET - #6 #300, 20h ;data page 6 ;move data at address 300h to 320h In syntax descriptions, the instruction is in a bold typeface and parameters are in an italic typeface. Portions of a syntax in bold must be entered as shown; portions of a syntax in italics describe the type of information that you specify. Here is an example of an instruction syntax: [label] BLDD src, dst BLDD is the instruction and has two parameters, src and dst. When you use BLDD, the first parameter must be an actual data memory source address and dst a destination address. A comma and a space (optional) must separate the two addresses. iv Notational Conventions / Related Documentation from Texas Instruments - The term OR is used in the assembly language instructions to denote a Boolean operation. The term or is used to indicate selection. Here is an example of an instruction with OR and or: lk OR (src) ³ src or [, dst] This instruction ORs the value of lk with the contents of src. Then, it stores the result in src or dst, depending on the syntax of the instruction. - - Square brackets, [ and ], identify an optional parameter. If you use an optional parameter, specify the information within the brackets; do not type the brackets themselves. In the example above, instead of typing [label], you specify a name for the label. When you specify more than one optional parameter from a list, you separate them with a comma and a space. Braces, { and }, indicate a list. Unless the list is enclosed in square brackets, you must choose one item from the list; do not type the braces themselves. Here's an example of a list that provides seven choices: ind: { * *+ - *­ *0+ *0­ *BRO+ *BRO­} The term 'C5x refers to the TMS320C5x. Related Documentation from Texas Instruments The following books describe the 'C5x and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477­8924. When ordering, please identify the book by its title and literature number. TMS320C5x User's Guide (literature number SPRU056 SPRU056) describes the 'C5x 16-bit, fixed-point, general-purpose digital signal processors. Covered are its architecture, internal register structure, instruction set, pipeline, specifications, DMA, I/O ports, and on-chip peripherals. TMS320C5x, TMS320LC5x Digital Signal Processors (literature number SPRS030 SPRS030) data sheet contains the electrical and timing specifications for these devices, as well as signal descriptions and pinouts for all of the available packages. Calculation of TMS320C5x Power Dissipation (literature number SPRA030 SPRA030). This application report describes techniques for analyzing system and device conditions to determine operating current levels. From this analysis, power dissipation for the device can be determined. Knowledge of power dissipation can, in turn, be used to determine thermal management requirements for the device. Read This First v Related Documentation from Texas Instruments Telecommunications Applications With the TMS320C5x DSPs (literature number SPRA033 SPRA033). This application book is a collection of DSP applications related to the field of telecommunications and implemented on the TMS320C5x. Topics covered are digital cellular systems, speech synthesis, error-correction coding, baseband modulation and demodulation, equalization and channel estimation, speech and character recognition algorithms, and system design considerations. PCMCIA TMS320 TMS320 DSP MediaCard (literature number SPRA052 SPRA052). This application report describes the DSP MediaCard, version 1.0, how it operates, and how to use it. The DSP MediaCard is a card for sound and fax/ modem applications, and it uses a TMS320 TMS320 DSP and on-board stereo codec. Use of the TMS320C5x Internal Oscillator With External Crystals or Ceramic Resonators (literature number SPRA054 SPRA054). This application report provides information about crystal and ceramic resonators, their frequency characteristics, a general background on oscillators, and the type of oscillator circuit used on the TMS320C5x. Covered are design aspects of the 'C5x oscillator including appropriate configuration of the external components, measured parameters for the on-board portion of the circuitry, use of the oscillator with overtone crystals, and general design considerations for choosing the external components for the oscillator. This report presents some design solutions for common frequencies. Enhanced Control of an Alternating Current Motor Using Fuzzy Logic and a TMS320 TMS320 Digital Signal Processor (literature number SPRA057 SPRA057). This application report describes how the use of a digital signal processor with a specialized fuzzy logic software kernel provides the required computing performance for a control system design while maintaining a low cost. This report presents a fuzzy logic design that enhances the system's ability to handle the abrupt momentum changes of an ac motor controller and the software technology used to implement the fuzzy logic design. Improving 32-Channel DTMF Decoders Using the TMS320C5x (literature number SPRA085 SPRA085). This application report discusses improvements that you can make to a multichannel dual-tone multifrequency (DTMF) decoder by using a TMS320C5x. PBX systems use multiple DTMF chips to encode or decode tones. PBX systems also perform other functions, such as voice compression or expansion and voice mail. By using a 'C5x, you can increase the performance and flexibility of the PBX systems, while decreasing the cost of the systems. vi Related Documentation from Texas Instruments Digital Signal Processing Applications with the TMS320 TMS320 Family, Volumes 1, 2, and 3 (literature numbers SPRA012 SPRA012, SPRA016 SPRA016, SPRA017 SPRA017) Volumes 1 and 2 cover applications using the 'C10 and 'C20 families of fixed-point processors. Volume 3 documents applications using both fixed-point processors, as well as the 'C30 floating-point processor. TMS320C1x/C2x/C2xx/C5x Code Generation Tools Getting Started Guide (literature number SPRU121 SPRU121) describes how to install the TMS320C1x, TMS320C2x, TMS320C2xx, and TMS320C5x assembly language tools and the C compiler for the 'C1x, 'C2x, 'C2xx, and 'C5x devices. The installation for MS-DOSTM, OS/2TM, SunOSTM, and SolarisTM systems is covered. TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User's Guide (literature number SPRU018 SPRU018) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the 'C1x, 'C2x, 'C2xx, and 'C5x generations of devices. TMS320C2x/C2xx/C5x Optimizing C Compiler User's Guide (literature number SPRU024 SPRU024) describes the 'C2x/C2xx/C5x C compiler. This C compiler accepts ANSI standard C source code and produces TMS320 TMS320 assembly language source code for the 'C2x, 'C2xx, and 'C5x generations of devices. TMS320C5x C Source Debugger User's Guide (literature number SPRU055 SPRU055) tells you how to invoke the 'C5x emulator, evaluation module, and simulator versions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, command entry, code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionality. TMS320C5x Evaluation Module Technical Reference (literature number SPRU087 SPRU087) describes the 'C5x evaluation module, its features, design details and external interfaces. TMS320C5x Evaluation Module Getting Started Guide (literature number SPRU126 SPRU126) tells you how to install the MS-DOSTM, PC-DOSTM, and WindowsTM versions of the 'C5x evaluation module. XDS51x Emulator Installation Guide (literature number SPNU070 SPNU070) describes the installation of the XDS510TM XDS510TM, XDS510PPTM XDS510PPTM, and XDS510WSTM XDS510WSTM emulator controllers. The installation of the XDS511TM XDS511TM emulator is also described. Read This First vii Related Documentation from Texas Instruments / Related Documents and Technical Articles JTAG/MPSD Emulation Technical Reference (literature number SPDU079 SPDU079) provides the design requirements of the XDS510TM XDS510TM emulator controller, discusses JTAG designs (based on the IEEE 1149.1 standard), and modular port scan device (MPSD) designs. TMS320 TMS320 DSP Development Support Reference Guide (literature number SPRU011 SPRU011) describes the TMS320 TMS320 family of digital signal processors and the tools that support these devices. Included are code-generation tools (compilers, assemblers, linkers, etc.) and system integration and debug tools (simulators, emulators, evaluation modules, etc.). Also covered are available documentation, seminars, the university program, and factory repair and exchange. TMS320 TMS320 Third-Party Support Reference Guide (literature number SPRU052 SPRU052) alphabetically lists over 100 third parties that provide various products that serve the family of TMS320 TMS320 digital signal processors. A myriad of products and applications are offered-software and hardware development tools, speech recognition, image processing, noise cancellation, modems, etc. Related Documents and Technical Articles If you are an assembly language programmer and would like more information about C or C expressions, you may find this book useful: The C Programming Language (second edition, 1988), by Brian W. Kernighan and Dennis M. Ritchie, published by Prentice-Hall, Englewood Cliffs, New Jersey. A wide variety of related documentation is available on DSPs. These references fall into one of the following application categories: viii General-purpose DSP Graphics/imagery Speech/voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development support Related Documents and Technical Articles In the following list, references appear in alphabetical order according to author. The documents contain beneficial information regarding designs, operations, and applications for signal-processing systems; all of the documents provide additional references. General-Purpose DSP: 1) Antoniou, A., Digital Filters: Analysis and Design, New York, NY: McGrawHill Company, Inc., 1979. 2) Brigham, E.O., The Fast Fourier Transform, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1974. 3) Burrus, C.S., and T.W. Parks, DFT/FFT and Convolution Algorithms, New York, NY: John Wiley and Sons, Inc., 1984. 4) Chassaing, R., Horning, D.W., "Digital Signal Processing with Fixed and Floating-Point Processors." CoED, USA, Volume 1, Number 1, pages 1­4, March 1991. 5) Defatta, David J., Joseph G. Lucas, and William S. Hodgkiss, Digital Signal Processing: A System Design Approach, New York: John Wiley, 1988. 6) Erskine, C., and S. Magar, "Architecture and Applications of a SecondGeneration Digital Signal Processor." Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, USA, 1985. 7) Essig, D., C. Erskine, E. Caudel, and S. Magar, "A Second-Generation Digital Signal Processor." IEEE Journal of Solid-State Circuits, USA, Volume SC­21, Number 1, pages 86­91, February 1986. 8) Frantz, G., K. Lin, J. Reimer, and J. Bradley, "The Texas Instruments TMS320C25 TMS320C25 Digital Signal Microcomputer." IEEE Microelectronics, USA, Volume 6, Number 6, pages 10­28, December 1986. 9) Gass, W., R. Tarrant, T. Richard, B. Pawate, M. Gammel, P. Rajasekaran, R. Wiggins, and C. Covington, "Multiple Digital Signal Processor Environment for Intelligent Signal Processing." Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1246­1259, September 1987. 10) Gold, Bernard, and C.M. Rader, Digital Processing of Signals, New York, NY: McGraw-Hill Company, Inc., 1969. 11) Hamming, R.W., Digital Filters, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977. 12) IEEE ASSP DSP Committee (Editor), Programs for Digital Signal Processing, New York, NY: IEEE Press, 1979. Read This First ix Related Documents and Technical Articles 13) Jackson, Leland B., Digital Filters and Signal Processing, Hingham, MA: Kluwer Academic Publishers, 1986. 14) Jones, D.L., and T.W. Parks, A Digital Signal Processing Laboratory Using the TMS32010 TMS32010, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 15) Lim, Jae, and Alan V. Oppenheim, Advanced Topics in Signal Processing, Englewood Cliffs, NJ: Prentice- Hall, Inc., 1988. 16) Lin, K., G. Frantz, and R. Simar, Jr., "The TMS320 TMS320 Family of Digital Signal Processors." Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1143­1159, September 1987. 17) Lovrich, A., Reimer, J., "An Advanced Audio Signal Processor." Digest of Technical Papers for 1991 International Conference on Consumer Electronics, June 1991. 18) Magar, S., D. Essig, E. Caudel, S. Marshall and R. Peters, "An NMOS Digital Signal Processor with Multiprocessing Capability." Digest of IEEE International Solid-State Circuits Conference, USA, February 1985. 19) Morris, Robert L., Digital Signal Processing Software, Ottawa, Canada: Carleton University, 1983. 20) Oppenheim, Alan V. (Editor), Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. 21) Oppenheim, Alan V., and R.W. Schafer, Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975 and 1988. 22) Oppenheim, A.V., A.N. Willsky, and I.T. Young, Signals and Systems, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983. 23) Papamichalis, P.E., and C.S. Burrus, "Conversion of Digit-Reversed to Bit-Reversed Order in FFT Algorithms." Proceedings of ICASSP 89, USA, pages 984­987, May 1989. 24) Papamichalis, P., and R. Simar, Jr., "The TMS320C30 TMS320C30 Floating-Point Digital Signal Processor." IEEE Micro Magazine, USA, pages 13­29, December 1988. 25) Parks, T.W., and C.S. Burrus, Digital Filter Design, New York, NY: John Wiley and Sons, Inc., 1987. 26) Peterson, C., Zervakis, M., Shehadeh, N., "Adaptive Filter Design and Implementation Using the TMS320C25 TMS320C25 Microprocessor." Computers in Education Journal, USA, Volume 3, Number 3, pages 12­16, July­ September 1993. x Related Documents and Technical Articles 27) Prado, J., and R. Alcantara, "A Fast Square-Rooting Algorithm Using a Digital Signal Processor." Proceedings of IEEE, USA, Volume 75, Number 2, pages 262­264, February 1987. 28) Rabiner, L.R. and B. Gold, Theory and Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975. 29) Simar, Jr., R., and A. Davis, "The Application of High-Level Languages to Single-Chip Digital Signal Processors." Proceedings of ICASSP 88, USA, Volume D, page 1678, April 1988. 30) Simar, Jr., R., T. Leigh, P. Koeppen, J. Leach, J. Potts, and D. Blalock, "A 40 MFLOPS Digital Signal Processor: the First Supercomputer on a Chip." Proceedings of ICASSP 87, USA, Catalog Number 87CH2396 87CH2396 ­0, Volume 1, pages 535­538, April 1987. 31) Simar, Jr., R., and J. Reimer, "The TMS320C25 TMS320C25: a 100 ns CMOS VLSI Digital Signal Processor." 1986 Workshop on Applications of Signal Processing to Audio and Acoustics, September 1986. 32) Texas Instruments, Digital Signal Processing Applications with the TMS320 TMS320 Family, 1986; Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 33) Treichler, J.R., C.R. Johnson, Jr., and M.G. Larimore, A Practical Guide to Adaptive Filter Design, New York, NY: John Wiley and Sons, Inc., 1987. Graphics/Imagery: 1) Andrews, H.C., and B.R. Hunt, Digital Image Restoration, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977. 2) Gonzales, Rafael C., and Paul Wintz, Digital Image Processing, Reading, MA: Addison-Wesley Publishing Company, Inc., 1977. 3) Papamichalis, P.E., "FFT Implementation on the TMS320C30 TMS320C30." Proceedings of ICASSP 88, USA, Volume D, page 1399, April 1988. 4) Pratt, William K., Digital Image Processing, New York, NY: John Wiley and Sons, 1978. 5) Reimer, J., and A. Lovrich, "Graphics with the TMS32020 TMS32020." WESCON/85 WESCON/85 Conference Record, USA, 1985. Speech/Voice: 1) DellaMorte, J., and P. Papamichalis, "Full-Duplex Real-Time Implementation of the FED-STD-1015 FED-STD-1015 LPC-10e Standard V.52 on the TMS320C25 TMS320C25." Proceedings of SPEECH TECH 89, pages 218­221, May 1989. 2) Frantz, G.A., and K.S. Lin, "A Low-Cost Speech System Using the TMS320C17 TMS320C17." Proceedings of SPEECH TECH '87, pages 25­29, April 1987. Read This First xi Related Documents and Technical Articles 3) Gray, A.H., and J.D. Markel, Linear Prediction of Speech, New York, NY: Springer-Verlag, 1976. 4) Jayant, N.S., and Peter Noll, Digital Coding of Waveforms, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984. 5) Papamichalis, Panos, Practical Approaches to Speech Coding, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 6) Papamichalis, P., and D. Lively, "Implementation of the DOD Standard LPC­10/52E 10/52E on the TMS320C25 TMS320C25." Proceedings of SPEECH TECH '87, pages 201­204, April 1987. 7) Pawate, B.I., and G.R. Doddington, "Implementation of a Hidden Markov Model-Based Layered Grammar Recognizer." Proceedings of ICASSP 89, USA, pages 801­ 804, May 1989. 8) Rabiner, L.R., and R.W. Schafer, Digital Processing of Speech Signals, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. 9) Reimer, J.B. and K.S. Lin, "TMS320 TMS320 Digital Signal Processors in Speech Applications." Proceedings of SPEECH TECH '88, April 1988. 10) Reimer, J.B., M.L. McMahan, and W.W. Anderson, "Speech Recognition for a Low-Cost System Using a DSP." Digest of Technical Papers for 1987 International Conference on Consumer Electronics, June 1987. Control: 1) Ahmed, I., "16-Bit DSP Microcontroller Fits Motion Control System Application." PCIM, October 1988. 2) Ahmed, I., "Implementation of Self Tuning Regulators with TMS320 TMS320 Family of Digital Signal Processors." MOTORCON '88, pages 248­262, September 1988. 3) Ahmed, I., and S. Lindquist, "Digital Signal Processors: Simplifying HighPerformance Control." Machine Design, September 1987. 4) Ahmed, I., and S. Meshkat, "Using DSPs in Control." Control Engineering, February 1988. 5) Allen, C. and P. Pillay, "TMS320 TMS320 Design for Vector and Current Control of AC Motor Drives." Electronics Letters, UK, Volume 28, Number 23, pages 2188­2190, November 1992. 6) Bose, B.K., and P.M. Szczesny, "A Microcomputer-Based Control and Simulation of an Advanced IPM Synchronous Machine Drive System for Electric Vehicle Propulsion." Proceedings of IECON '87, Volume 1, pages 454­463, November 1987. xii Related Documents and Technical Articles 7) Hanselman, H., "LQG-Control of a Highly Resonant Disc Drive Head Positioning Actuator." IEEE Transactions on Industrial Electronics, USA, Volume 35, Number 1, pages 100­104, February 1988. 8) Jacquot, R., Modern Digital Control Systems, New York, NY: Marcel Dekker, Inc., 1981. 9) Katz, P., Digital Control Using Microprocessors, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1981. 10) Kuo, B.C., Digital Control Systems, New York, NY: Holt, Reinholt, and Winston, Inc., 1980. 11) Lovrich, A., G. Troullinos, and R. Chirayil, "An All-Digital Automatic Gain Control." Proceedings of ICASSP 88, USA, Volume D, page 1734, April 1988. 12) Matsui, N. and M. Shigyo, "Brushless DC Motor Control Without Position and Speed Sensors." IEEE Transactions on Industry Applications, USA, Volume 28, Number 1, Part 1, pages 120­127, January­February 1992. 13) Meshkat, S., and I. Ahmed, "Using DSPs in AC Induction Motor Drives." Control Engineering, February 1988. 14) Panahi, I. and R. Restle, "DSPs Redefine Motion Control." Motion Control Magazine, December 1993. 15) Phillips, C., and H. Nagle, Digital Control System Analysis and Design, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984. Multimedia: 1) Reimer, J., "DSP-Based Multimedia Solutions Lead Way Enhancing Audio Compression Performance." Dr. Dobbs Journal, December 1993. 2) Reimer, J., G. Benbassat, and W. Bonneau Jr., "Application Processors: Making PC Multimedia Happen." Silicon Valley PC Design Conference, July 1991. Military: 1) Papamichalis, P., and J. Reimer, "Implementation of the Data Encryption Standard Using the TMS32010 TMS32010." Digital Signal Processing Applications, 1986. Read This First xiii Related Documents and Technical Articles Telecommunications: 1) Ahmed, I., and A. Lovrich, "Adaptive Line Enhancer Using the TMS320C25 TMS320C25." Conference Records of Northcon/86, USA, 14/3/1­10, September/October 1986. 2) Casale, S., R. Russo, and G. Bellina, "Optimal Architectural Solution Using DSP Processors for the Implementation of an ADPCM Transcoder." Proceedings of GLOBECOM '89, pages 1267­1273, November 1989. 3) Cole, C., A. Haoui, and P. Winship, "A High-Performance Digital Voice Echo Canceller on a SINGLE TMS32020 TMS32020." Proceedings of ICASSP 86, USA, Catalog Number 86CH2243 86CH2243­4, Volume 1, pages 429­432, April 1986. 4) Cole, C., A. Haoui, and P. Winship, "A High-Performance Digital Voice Echo Canceller on a Single TMS32020 TMS32020." Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, USA, 1986. 5) Lovrich, A., and J. Reimer, "A Multi-Rate Transcoder." Transactions on Consumer Electronics, USA, November 1989. 6) Lovrich, A. and J. Reimer, "A Multi-Rate Transcoder." Digest of Technical Papers for 1989 International Conference on Consumer Electronics, June 7­9, 1989. 7) Lu, H., D. Hedberg, and B. Fraenkel, "Implementation of High-Speed Voiceband Data Modems Using the TMS320C25 TMS320C25." Proceedings of ICASSP 87, USA, Catalog Number 87CH2396 87CH2396­0, Volume 4, pages 1915­1918, April 1987. 8) Mock, P., "Add DTMF Generation and Decoding to DSP­ µP Designs." Electronic Design, USA, Volume 30, Number 6, pages 205­213, March 1985. 9) Reimer, J., M. McMahan, and M. Arjmand, "ADPCM on a TMS320 TMS320 DSP Chip." Proceedings of SPEECH TECH 85, pages 246­249, April 1985. 10) Troullinos, G., and J. Bradley, "Split-Band Modem Implementation Using the TMS32010 TMS32010 Digital Signal Processor." Conference Records of Electro/86 and Mini/Micro Northeast, USA, 14/1/1­21, May 1986. xiv Related Documents and Technical Articles Automotive: 1) Lin, K., "Trends of Digital Signal Processing in Automotive." International Congress on Transportation Electronic (CONVERGENCE '88), October 1988. Consumer: 1) Frantz, G.A., J.B. Reimer, and R.A. Wotiz, "Julie, The Application of DSP to a Product." Speech Tech Magazine, USA, September 1988. 2) Reimer, J.B., and G.A. Frantz, "Customization of a DSP Integrated Circuit for a Customer Product." Transactions on Consumer Electronics, USA, August 1988. 3) Reimer, J.B., P.E. Nixon, E.B. Boles, and G.A. Frantz, "Audio Customization of a DSP IC." Digest of Technical Papers for 1988 International Conference on Consumer Electronics, June 8­10 1988. Medical: 1) Knapp and Townshend, "A Real-Time Digital Signal Processing System for an Auditory Prosthesis." Proceedings of ICASSP 88, USA, Volume A, page 2493, April 1988. 2) Morris, L.R., and P.B. Barszczewski, "Design and Evolution of a PocketSized DSP Speech Processing System for a Cochlear Implant and Other Hearing Prosthesis Applications." Proceedings of ICASSP 88, USA, Volume A, page 2516, April 1988. Development Support: 1) Mersereau, R., R. Schafer, T. Barnwell, and D. Smith, "A Digital Filter Design Package for PCs and TMS320 TMS320." MIDCON/84 MIDCON/84 Electronic Show and Convention, USA, 1984. 2) Simar, Jr., R., and A. Davis, "The Application of High-Level Languages to Single-Chip Digital Signal Processors." Proceedings of ICASSP 88, USA, Volume 3, pages 1678­1681, April 1988. Read This First xv Trademarks Trademarks DuPont Electronics is a registered trademark of E.I. DuPont Corporation. HP-UX is a trademark of Hewlett-Packard Company. IBM, OS/2, and PC-DOS are trademarks of International Business Machines Corporation. MS and Windows are registered trademarks of Microsoft Corporation. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SPARC is a trademark of SPARC International, Inc., but licensed exclusively to Sun Microsystems, Inc. 320 Hotline On-line, TI, XDS510 XDS510, XDS510PP XDS510PP, XDS510WS XDS510WS, and XDS511 XDS511 are trademarks of Texas Instruments Incorporated. VAX and VMS are trademarks of Digital Equipment Corp. xvi If You Need Assistance If You Need Assistance . . . - World-Wide Web Sites TI Online Semiconductor Product Information Center (PIC) DSP Solutions 320 Hotline On-line - t http://www.ti.com http://www.ti.com/sc/docs/pic/home.htm http://www.ti.com/dsps http://www.ti.com/sc/docs/dsps/support.htm North America, South America, Central America Product Information Center (PIC) (972) 644-5580 TI Literature Response Center U.S.A. (800) 477-8924 Software Registration/Upgrades (214) 638-0333 Fax: (214) 638-7742 U.S.A. Factory Repair/Hardware Upgrades (281) 274-2285 U.S. Technical Training Organization (972) 644-5580 DSP Hotline (281) 274-2320 Fax: (281) 274-2324 DSP Modem BBS (281) 274-2323 DSP Internet BBS via anonymous ftp to ftp://ftp.ti.com/pub/tms320bbs - Europe, Middle East, Africa European Product Information Center (EPIC) Hotlines: Multi-Language Support +33 1 30 70 11 69 Deutsch +49 8161 80 33 11 or +33 1 30 70 11 68 English +33 1 30 70 11 65 Francais +33 1 30 70 11 64 Italiano +33 1 30 70 11 67 EPIC Modem BBS +33 1 30 70 11 99 European Factory Repair +33 4 93 22 25 40 Europe Customer Training Helpline - Email: dsph@ti.com Fax: +33 1 30 70 10 32 Email: epic@ti.com Fax: +49 81 61 80 40 10 Asia-Pacific Literature Response Center +852 2 956 7288 Fax: +852 2 956 2200 Hong Kong DSP Hotline +852 2 956 7268 Fax: +852 2 956 1002 Korea DSP Hotline +82 2 551 2804 Fax: +82 2 551 2828 Korea DSP Modem BBS +82 2 551 2914 Singapore DSP Hotline Fax: +65 390 7179 Taiwan DSP Hotline +886 2 377 1450 Fax: +886 2 377 2718 Taiwan DSP Modem BBS +886 2 376 2592 Taiwan DSP Internet BBS via anonymous ftp to ftp://dsp.ee.tit.edu.tw/pub/TI/ - Japan Product Information Center +0120-81-0026 (in Japan) +03-3457-0972 or (INTL) 813-3457-0972 DSP Hotline +03-3769-8735 or (INTL) 813-3769-8735 DSP BBS via Nifty-Serve Type "Go TIASP" - Fax: +0120-81-0036 (in Japan) Fax: +03-3457-1259 or (INTL) 813-3457-1259 Fax: +03-3457-7071 or (INTL) 813-3457-7071 Documentation When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments Incorporated Email: comments@books.sc.ti.com Technical Documentation Services, MS 702 P.O. Box 1443 Houston, Texas 77251-1443 Note: When calling a Literature Response Center to order documentation, please specify the literature number of the book. Read This First xvii xviii Running Title-Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Summarizes the features of the TMS320 TMS320 family of products and presents typical applications. Describes the TMS320C5x DSP and lists its key features. 1.1 1.2 1.3 2 TMS320 TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 History, Development, and Advantages of TMS320 TMS320 DSPs . . . . . . . . . . . . . . . . . 1.1.2 TMS320 TMS320 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C5x Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C5x Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2 1-4 1-5 1-7 Software Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the use of the TMS320C5x instruction set with particular emphasis on its new features and special applications. 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Software Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Logical and Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.4.1 Parallel Logic Unit (PLU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.4.2 Multiconditional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.4.3 Search Algorithm Using CRGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.4.4 Matrix Multiplication Using Nested Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Circular Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Single-Instruction Repeat (RPT) Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Extended-Precision Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.8.1 Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.8.2 Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.8.3 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.8.4 Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 Floating-Point Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Application-Oriented Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 2.10.1 Modem Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 2.10.2 Adaptive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.10.3 Infinite Impulse Response (IIR) Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 2.10.4 Dynamic Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55 Fast Fourier Transforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 xix Contents 3 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the external interface to program memory, local data memory, and I/O space. Also described is the direct memory access (DMA) in a portable computer configuration. 3.1 3.2 3.3 3.4 3.5 4 4.2 4.3 4.4 4.5 4.6 Multimedia Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 System Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 Multimedia-Related Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Telecommunications Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.1 System Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.2.2 Telecommunications-Related Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Dedicated Speech Synthesis Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.3.1 System Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.3.2 Speech Synthesis-Related Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Servo Control/Disk Drive Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.1 System Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.2 Servo Control/Disk Drive-Related Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Modem Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Advanced Digital Electronics Applications for Consumers . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.6.1 Advanced Television System Design Considerations . . . . . . . . . . . . . . . . . . . . 4-18 4.6.2 Advanced Digital Electronics-Related Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Design Considerations for Using XDS510 XDS510 Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Describes the JTAG emulator cable and how to construct a 14-pin connector on your target system and how to connect the target system to the emulator. A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 xx 3-2 3-4 3-6 3-6 3-7 Analog Interface Peripherals and Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Describes the use of the TMS320 TMS320 DSP in a variety of applications. 4.1 A External Interface to Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interface to Local Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interface to Global Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interface to I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Memory Access (DMA) in a Personal Computer Configuration . . . . . . . . . . . . . . Cable Header and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Emulator Cable Pod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Emulator Cable Pod Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Target System Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Configuring Multiple Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 Connections Between the Emulator and the Target System . . . . . . . . . . . . . . . . . . . . . . A-9 A.7.1 Emulation Signals Not Buffered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 A.7.2 Emulation Signals Buffered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 Emulation Timing Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 Contents B Development Support and Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Provides device part numbers and support tool ordering information for the TMS320C5x and development support information available from TI and third-party vendors. B.1 B.2 B.3 C Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.1 Software and Hardware Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.2 Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.3 TMS320C5x DSP Design Workshop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.4 Assistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.1 Device and Development Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . B.2.2 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.3 Development Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hewlett-Packard E2442A E2442A Preprocessor 'C5x Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.1 Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.2 Logic Analyzers Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.3 Pods Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.4 Termination Adapters (TAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.5 Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 B-2 B-2 B-3 B-3 B-4 B-4 B-5 B-6 B-8 B-8 B-8 B-9 B-9 B-9 Application Reports and Designer's Notebook Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Lists the TMS320C5x application reports and the TMS320C5x designer's notebook pages (DNP) available to you. Contents xxi Running Title-Attribute Reference Figures 1­1 1­2 2­1 2­2 2­3 2­4 2­5 2­6 2­7 2­8 2­9 3­1 3­2 3­3 3­4 4­1 4­2 4­3 4­4 4­5 4­6 4­7 4­8 4­9 4­10 4­11 4­12 4­13 4­14 A­1 A­2 A­3 A­4 A­5 A­6 A­7 B­1 B­2 xxii Evolution of the TMS320 TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Typical Applications for the TMS320 TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 32-Bit Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 32-Bit Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 16-Bit Integer Multiplication Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 32-Bit Multiplication Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 16-Bit Integer Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 Nth-Order, Direct-Form, Type II, IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 Backtracking With Path History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56 An In-Place DIT FFT With In-Order Outputs and Bit-Reversed Inputs . . . . . . . . . . . . . . . 2-57 An In-Place DIT FFT With In-Order Inputs but Bit-Reversed Outputs . . . . . . . . . . . . . . . . 2-58 'C5x Interfacing to External EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 'C5x Interfacing to External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Global Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Direct Memory Access in a PC Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Multimedia Speech Encoding and Modem Communication . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 TMS320C25 TMS320C25 to TLC32047 TLC32047 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Generic Telecom Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 General Telecom Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Typical DSP/Combo Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 DSP/Combo Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Generic Servo Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Disk Drive Control System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 TMS320C14 TMS320C14 to TLC32071 TLC32071 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 High-Speed V.32bis and Multistandard Modem With the TLC320AC01 TLC320AC01 AIC . . . . . . . . . . 4-17 Applications Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Video Signal Processing Basic System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Typical Digital Audio Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Header Signals and Header Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Emulator Cable Pod Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 Emulator Cable Pod Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Target-System Generated Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Multiprocessor Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 Emulator Connections Without Signal Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 Buffered Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 TMS320C5x Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 TMS320 TMS320 Development Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 Running Title-Attribute Reference Tables 1­1 2­1 2­2 2­3 4­1 4­2 4­3 4­4 4­5 4­6 4­7 4­8 4­9 A­1 A­2 B­1 C­1 C­2 Characteristics of the 'C5x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Conditions for Branch, Call, and Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Groups for Multiconditional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Bit-Reversal Algorithm for an 8-Point Radix-2 DIT FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58 Data Converter ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Switched-Capacitor Filter ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Telecom Devices-Codec/Filter ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Telecom Devices-Transient Suppressor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Voice Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Speech Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Control Related Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Modem AFE Data Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Audio/Video Analog/Digital Interface Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 XDS510 XDS510 Header Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Emulator Cable Pod Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 TMS320C5x Development Support Tools Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 TMS320C5x Application Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 TMS320C5x Designer's Notebook Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Contents xxiii Running Title-Attribute Reference Examples 2­1 2­2 2­3 2­4 2­5 2­6 2­7 2­8 2­9 2­10 2­11 2­12 2­13 2­14 2­15 2­16 2­17 2­18 2­19 2­20 2­21 2­22 2­23 2­24 2­25 2­26 2­27 2­28 2­29 2­30 2­31 2­32 2­33 2­34 2­35 xxiv Initialization of TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Use of INTR Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Software Stack Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Using PLU to Do Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Using PLU to Do Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Using Multiple Conditions With BCND Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Using CRGT and CRLT Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Using Nested Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Use of Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Modulo-256 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Memory-to-Memory Block Moves Using RPT with BLDD . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Memory-to-Memory Block Moves Using RPT with BLDP . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Memory-to-Memory Block Moves Using RPT with BLPD . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Memory-to-Memory Block Moves Using RPT with TBLR . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Memory-to-Memory Block Moves Using RPT with TBLW . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Memory-to-Memory Block Moves Using RPT with SMMR . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Memory-to-Memory Block Moves Using RPT with LMMR . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Square Root Computation Using XC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 64-Bit Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 64-Bit Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 32-Bit Integer Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 32-Bit Fractional Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 16-Bit Integer Division Using SUBC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 16-Bit Fractional Division Using SUBC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 Floating-Point Addition Using SATL and SATH Instructions . . . . . . . . . . . . . . . . . . . . . . . . 2-40 Floating-Point Multiplication Using BSAR Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 V.32 Encoder Using Accumulator Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 Adaptive FIR Filter Using RPT and RPTB Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 Nth-Order IIR Filter Using RPT and MACD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 N Cascaded BiQuad IIR Filter Using LTD and MPYA Instructions . . . . . . . . . . . . . . . . . . . 2-54 Backtracking Algorithm Using Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56 16-Point Radix-2 Complex FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 Bit-Reversed Addressing for an FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 Macros for 16-Point DIT FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69 Chapter 1 Introduction This user's guide provides applications for the TMS320C5x generation of fixed-point digital signal processors (DSPs) in the TMS320 TMS320 family. The 'C5x DSP provides improved performance over earlier 'C1x and 'C2x generations while maintaining upward compatibility of source code between the devices. The 'C5x central processing unit (CPU) is based on the 'C25 CPU and incorporates additional architectural enhancements that allow the device to run twice as fast as 'C2x devices. Future expansion and enhancements are expected to heighten the performance and range of applications of the 'C5x DSPs. The 'C5x generation of static CMOS DSPs consists of the following devices: Device On-Chip RAM On-Chip ROM TMS320C50/LC50 TMS320C50/LC50 10K words 2K words TMS320C51/LC51 TMS320C51/LC51 2K words 8K words TMS320C52/LC52 TMS320C52/LC52 1K words 4K words TMS320C53/LC53 TMS320C53/LC53 4K words 16K words TMS320C53S/LC53S TMS320C53S/LC53S 4K words 16K words TMS320LC56 TMS320LC56 7K words 32K words TMS320C57S TMS320C57S 7K words 2K words TMS320LC57 TMS320LC57 7K words 32K words Topic Page 1.1 TMS320 TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 TMS320C5x Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3 TMS320C5x Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Introduction 1-1 TMS320 TMS320 Family Overview 1.1 TMS320 TMS320 Family Overview The TMS320 TMS320 family consists of two types of single-chip DSPs: 16-bit fixedpoint and 32-bit floating-point. These DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. Combining these two qualities, the TMS320 TMS320 processors are inexpensive alternatives to custom-fabricated very large scale integration (VLSI) and multichip bit-slice processors. Refer to subsection 1.1.2, TMS320 TMS320 Typical Applications, for a detailed list of applications of the TMS320 TMS320 family. The following characteristics make this family the ideal choice for a wide range of processing applications: 1.1.1 Very flexible instruction set Inherent operational flexibility High-speed performance Innovative, parallel architectural design Cost-effectiveness History, Development, and Advantages of TMS320 TMS320 DSPs In 1982, Texas Instruments introduced the TMS32010 TMS32010 - the first fixed-point DSP in the TMS320 TMS320 family. Before the end of the year, Electronic Products magazine awarded the TMS32010 TMS32010 the title "Product of the Year". The TMS32010 TMS32010 became the model for future TMS320 TMS320 generations. Today, the TMS320 TMS320 family consists of these generations (Figure 1­1): 'C1x, 'C2x, 'C2xx, 'C5x, 'C54x, and 'C6x fixed-point DSPs; 'C3x and 'C4x floatingpoint DSPs; and 'C8x multiprocessor DSPs. Figure 1­1 illustrates the performance gains that the TMS320 TMS320 family has made over time with successive generations. Source code is upwardly compatible from one fixed-point generation to the next fixed-point generation (except for the 'C54x), and from one floating-point generation to the next floating-point generation. Upward compatibility preserves the software generation of your investment, thereby providing a convenient and cost-efficient means to a higher-performance, more versatile DSP system. Each generation of TMS320 TMS320 devices has a CPU and a variety of on-chip memory and peripheral configurations for developing spin-off devices. These spin-off devices satisfy a wide range of needs in the worldwide electronics market. When memory and peripherals are integrated into one processor, the overall system cost is greatly reduced, and circuit board space is saved. 1-2 TMS320 TMS320 Family Overview Figure 1­1. Evolution of the TMS320 TMS320 Family Introduction 1-3 TMS320 TMS320 Family Overview 1.1.2 TMS320 TMS320 Typical Applications The TMS320 TMS320 family of DSPs offers better, more adaptable approaches to traditional signal-processing problems, such as vocoding, filtering, and error coding. Furthermore, the TMS320 TMS320 family supports complex applications that often require multiple operations to be performed simultaneously. Figure 1­2 shows many of the typical applications of the TMS320 TMS320 family. Figure 1­2. Typical Applications for the TMS320 TMS320 Family Automotive Consumer Control Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis Voice commands Digital radios/TVs Educational toys Music synthesizers Power tools Radar detectors Solid-state answering machines Disk drive control Engine control Laser printer control Motor control Robotics control Servo control General-Purpose Graphics/Imaging Industrial Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing 3-D rotation Animation/digital map Homomorphic processing Pattern recognition Image enhancement Image compression/transmission Robot vision Workstations Numeric control Power-line monitoring Robotics Security access Instrumentation Medical Military Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Telecommunications 1200- to 19200-bps modems Adaptive equalizers ADPCM transcoders Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) Personal digital assistants (PDA) 1-4 DTMF encoding/decoding Echo cancellation Fax Line repeaters Speaker phones Spread spectrum communications Video conferencing X.25 Packet Switching Personal communications systems (PCS) Voice/Speech Speech enhancement Speech recognition Speech synthesis Speaker verification Speech vocoding Voice mail Text-to-speech TMS320C5x Overview 1.2 TMS320C5x Overview The 'C5x generation consists of the 'C50, 'C51, 'C52, 'C53, 'C53S, 'C56, 'C57, and 'C57S DSPs, which are fabricated by CMOS integrated-circuit technology. Their architectural design is based on the 'C25. The operational flexibility and speed of the 'C5x are the result of combining an advanced Harvard architecture (which has separate buses for program memory and data memory), a CPU with application-specific hardware logic, on-chip peripherals, on-chip memory, and a highly specialized instruction set. The 'C5x is designed to execute up to 50 million instructions per second (MIPS). Spin-off devices that combine the 'C5x CPU with customized on-chip memory and peripheral configurations may be developed for special applications in the worldwide electronics market. The 'C5x devices offer these advantages: - Enhanced TMS320 TMS320 architectural design for increased performance and versatility Modular architectural design for fast development of spin-off devices Advanced integrated-circuit processing technology for increased performance and low power consumption Source code compatibility with 'C1x, 'C2x, and 'C2xx DSPs for fast and easy performance upgrades Enhanced instruction set for faster algorithms and for optimized high-level language operation Reduced power consumption and increased radiation hardness because of new static design techniques Table 1­1 lists the major characteristics of the 'C5x DSPs. The table shows the capacity of on-chip RAM and ROM, number of serial and parallel input/output (I/O) ports, power supply requirements, execution time of one machine cycle, and package types available with total pin count. Use Table 1­1 for guidance in choosing the best 'C5x DSP for your application. Introduction 1-5 TMS320C5x Overview Table 1­1. Characteristics of the 'C5x DSPs TMS320 TMS320 Device ID On-Chip Memory (16-bit words) I/O Ports DARAM SARAM ROM Serial Parallel Power Supply (V) Cycle Time (ns) Package Type 'C50 PQ 1056 9K 2K§ 2¶ 64K 5 50/35/25 132 pin BQFPd 'LC50 PQ 1056 9K 2K§ 2¶ 64K 3.3 50/35/25 132 pin BQFPd 'C51 PQ 1056 1K 8K§ 2¶ 64K 5 50/35/25/20 132 pin BQFPd 'C51 PZ 1056 1K 8K§ 2¶ 64K 5 50/35/25/20 100 pin TQFPk 'LC51 PQ 1056 1K 8K§ 2¶ 64K 3.3 50/35/25 132 pin BQFPd 'LC51 PZ 1056 1K 8K§ 2¶ 64K 3.3 50/35/25 100 pin TQFPk 'C52 PJ 1056 - 4K§ 1 64K 5 50/35/25/20 100 pin QFPh 'C52 PZ 1056 - 4K§ 1 64K 5 50/35/25/20 100 pin TQFPk 'LC52 PJ 1056 - 4K§ 1 64K 3.3 50/35/25 100 pin QFPh 'LC52 PZ 1056 - 4K§ 1 64K 3.3 50/35/25 100 pin TQFPk 'C53 PQ 1056 3K 16K§ 2¶ 64K 5 50/35/25 132 pin BQFPd 'C53S PZ 1056 3K 16K§ 2 64K 5 50/35/25 100 pin TQFPk 'LC53 PQ 1056 3K 16K§ 2¶ 64K 3.3 50/35/25 132 pin BQFPd 'LC53S LC53S PZ 1056 3K 16K§ 2 64K 3.3 50/35/25 100 pin TQFPk 'LC56 PZ 1056 6K 32K 2# 64K 3.3 50/35/25 100 pin TQFPk 'C57S PGE 1056 6K 2K§ 2# 64Kk 5 50/35/25 144 pin TQFPD 'LC57 PBK 1056 6K 32K 2# 64Kk 3.3 50/35/25 128 pinTQFPk Dual-access RAM (DARAM) Single-access RAM (SARAM) § ROM bootloader available ¶ Includes time-division multiplexed (TDM) serial port # Includes buffered serial port (BSP) || Includes host port interface (HPI) d 20 × 20 × 3.8 mm bumpered quad flat-pack (BQFP) package k 14 × 14 × 1.4 mm thin quad flat-pack (TQFP) package h 14 × 20 × 2.7 mm quad flat-pack (QFP) package D 20 × 20 × 1.4 mm thin quad flat-pack (TQFP) package Sixteen of the 64K parallel I/O ports are memory mapped. 1-6 TMS320C5x Key Features 1.3 TMS320C5x Key Features Key features of the 'C5x DSPs are listed below. Where a feature is exclusive to a particular device, the device's name is enclosed within parentheses and noted after that feature. - - Compatibility: Source-code compatible with 'C1x, 'C2x, and 'C2xx devices Speed: 20-/25-/35-/50-ns single-cycle fixed-point instruction execution time (50/40/28.6/20 MIPS) Power J J 3.3-V and 5-V static CMOS technology with two power-down modes Power consumption control with IDLE1 and IDLE2 instructions for power-down modes Memory J J J J J J J J J J J 224K-word × 16-bit maximum addressable external memory space (64K-word program, 64K-word data, 64K-word I/O, and 32K-word global memory) 1056-word × 16-bit dual-access on-chip data RAM 9K-word × 16-bit single-access on-chip program/data RAM ('C50) 2K-word × 16-bit single-access on-chip boot ROM ('C50, 'C57S) 1K-word × 16-bit single-access on-chip program/data RAM ('C51) 8K-word × 16-bit single-access on-chip program ROM ('C51) 4K-word × 16-bit single-access on-chip program ROM ('C52) 3K-word × 16-bit single-access on-chip program/data RAM ('C53, 'C53S) 16K-word × 16-bit single-access on-chip program ROM ('C53, 'C53S) 6K-word × 16-bit single-access on-chip program/data RAM ('LC56, 'C57S, 'LC57) 32K-word × 16-bit single-access on-chip program ROM ('LC56, 'LC57) Introduction 1-7 TMS320C5x Key Features - Central processing unit (CPU) J Central arithmetic logic unit (CALU) consisting of the following: H H H J J - J J J J J 0- to 16-bit left and right data barrel-shifters and a 64-bit incremental data shifter 16-bit parallel logic unit (PLU) Dedicated auxiliary register arithmetic unit (ARAU) for indirect addressing Eight auxiliary registers 8-level hardware stack 4-deep pipelined operation for delayed branch, call, and return instructions Eleven shadow registers for storing strategic CPU-controlled registers during an interrupt service routine (ISR) Extended hold operation for concurrent external direct memory access (DMA) of external memory or on-chip RAM Two indirectly addressed circular buffers for circular addressing Instruction set J J J J J J J J J 1-8 16-bit × 16-bit parallel multiplier with a 32-bit product capability Program control J - 32-bit arithmetic logic unit (ALU), 32-bit accumulator (ACC), and 32-bit accumulator buffer (ACCB) Single-cycle multiply/accumulate instructions Single-instruction repeat and block repeat operations Block memory move instructions for better program and data management Memory-mapped register load and store instructions Conditional branch and call instructions Delayed execution of branch and call instructions Fast return from interrupt instructions Index-addressing mode Bit-reversed index-addressing mode for radix-2 fast Fourier transforms (FFTs) TMS320C5x Key Features - On-chip peripherals J J J J J J - - J J J 64K parallel I/O ports (16 I/O ports are memory mapped) Sixteen software-programmable wait-state generators for program, data, and I/O memory spaces Interval timer with period, control, and counter registers for software stop, start, and reset Phase-locked loop (PLL) clock generator with internal oscillator or external clock source Multiple PLL clocking option (x1, x2, x3, x4, x5, x9, depending on the device) Full-duplex synchronous serial port interface for direct communication between the 'C5x and another serial device Time-division multiplexed (TDM) serial port ('C50, 'C51, 'C53) Buffered serial port (BSP) ('LC56, 'C57S, 'LC57) 8-bit parallel host port interface (HPI) ('C57, 'C57S) Test/emulation J J On-chip scan-based emulation logic IEEE JTAG Standard 1149.1 boundary scan logic ('C50, 'C51, 'C53, 'C57S) Packages J J J J J 100-pin quad flat-pack (QFP) package ('C52) 100-pin thin quad flat-pack (TQFP) package ('C51, 'C52, 'C53S, 'LC56) 128-pin TQFP package ('LC57) 132-pin bumpered quad flat-pack (BQFP) package ('C50, 'C51, 'C53) 144-pin TQFP package ('C57S) Introduction 1-9 1-10 Chapter 2 Software Applications The 'C5x devices maintain source-code compatibility with 'C1x and 'C2x generations and have architectural enhancements that improve performance and versatility. An orthogonal instruction set is augmented by new instructions that support additional hardware and handle data movement and memorymapped registers. Other features include an independent parallel logic unit (PLU) for performing Boolean operations, a 32-bit accumulator buffer (ACCB), and a set of registers that provide zero-latency context-switching capabilities to interrupt service routines. The on-chip dual-access RAM and memorymapped register set are enhanced. This chapter explains the use of the 'C5x instruction set with particular emphasis on its new features and special applications. For a complete discussion of the assembler directives used in this chapter's examples, consult the TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User's Guide. Topic Page 2.1 Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3 Software Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4 Logical and Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.5 Circular Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.6 Single-Instruction Repeat (RPT) Loops . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.7 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.8 Extended-Precision Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.9 Floating-Point Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.10 Application-Oriented Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 2.11 Fast Fourier Transforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Software Applications 2-1 Processor Initialization 2.1 Processor Initialization Before executing a 'C5x algorithm, it is necessary to initialize the processor. Generally, initialization takes place anytime the processor is reset. The processor is reset by applying a low level to RS input; the interrupt vector pointer (IPTR) bits of the processor mode status register (PMST) are all cleared, thus mapping the vectors to page 0 in program memory space. This means that the reset vector always resides at program memory location 0. This location normally contains a branch instruction to direct program execution to the system initialization routine. A hardware reset clears all pending interrupt flags and sets the interrupt mode (INTM) bit in ST0, thereby disabling all interrupts. A hardware reset also initializes various status bits and peripheral registers. To configure the processor after the reset, the following internal functions must be initialized: - Memory-mapped core processor and peripheral control registers Interrupt structure (INTM bit) Mode control (OVM, SXM, PM, AVIS, NDX, TRM bits) Memory control (RAM, OVLY, CNF bits) Auxiliary registers and the auxiliary register pointer (ARP) Data memory page pointer (DP) The OVM (overflow mode), TC (test/control flag), IMR (interrupt mask register), auxiliary register pointer (ARP), auxiliary register buffer (ARB), and data memory page pointer (DP) are not initialized by reset. Example 2­1 shows coding for initializing the 'C5x to the following machine state and for the initialization performed after hardware reset: - 2-2 Internal single-access RAM configured as program memory Interrupt vector table loaded in internal program memory Interrupt vector table pointer (IPTR) Internal dual-access RAM blocks filled with 0s Interrupts enabled Processor Initialization Example 2­1. Initialization of TMS320C5x .title 'PROCESSOR INITIALIZATION' .mmregs .ref ISR0,ISR1,ISR2,ISR3,ISR4,TIME .ref RCV,XMT,TRX,TXMT,TRP,NMISR *; * Processor initialization for TMS320C50 TMS320C50. * * The memory mapping of S/A RAM in program space and data space is different for * the 'C5x devices. Therefore, the memory location pointed to by address 0800h * in data space is mapped to a different address in program space for different * 'C5x devices. Hence, the IPTR should be loaded with the corresponding value * to allocate the vector table to the correct program space. * * | C50 | C51 | C53 | C56 | C57 *­­­­­­­+­­­­­­­­­+­­­­­­­­­+­­­­­­­­­+­­­­­­­­­+­­­­­­­­ * PMST | 0081E 0081E | 0201E 0201E | 0401E 0401E | 0801E 0801E | 0801E 0801E * *; V_TBL .sect "vectors" RESET B INIT ;This section will be loaded in program ;memory address 0h. INT0 B ISR0 ;INT0 ­ begins processing here INT1 B ISR1 ;INT1 ­ begins processing here INT2 B ISR2 ;INT2 ­ begins processing here INT3 B ISR3 ;INT3 ­ begins processing here TINT B TIME ;Timer interrupt processing RINT B RCV ;Serial port receive interrupt XINT B XMT ;Serial port transmit interrupt TRNT B TRX ;TDM port receive interrupt TXNT B TXMT ;TDM port transmit interrupt INT4 B ISR4 ;INT4 ­ begins processing here .space 14*16 ;14 words TRAP B TRP NMI B NMISR .text INIT LDP #0 ;Initialize data pointer OPL #20h,PMST ;Configure S/A RAM in data memory LAR AR7,#0800h ;Data space address for vector table MAR *,AR7 RPT #39 BLPD #V_TBL,*+ ;Load vector table at 0800h SPLK #0081Eh,PMST ;Now configure S/A RAM in program space ;and initialize vector table pointer SPLK #01FFh,IMR ;Clear interrupt mask register CLRC OVM ;Disable overflow saturation mode LAR AR7,#60h ;Initialize B2 block RPTZ #31 SACL *+ Software Applications 2-3 Processor Initialization Example 2­1. Initialization of TMS320C5x (Continued) LAR RPTZ SACL LAR RPTZ SACL CLRC B 2-4 AR7,#100h #511 *+ AR7,#300h #511 *+ INTM MAIN_PRG ;Initialize B0 block ;Initialize B1 block ;Globally enable interrupts ;Return Interrupts 2.2 Interrupts The 'C5x devices have four external, maskable, user interrupts (INT1­INT4) and one nonmaskable interrupt (NMI) available for external devices. Internal interrupts are generated by the serial ports, the timer, and by the software interrupt instructions (INTR, TRAP, and NMI). The interrupt structure is described in the TMS320C5x User's Guide. The 'C5x devices are capable of generating software interrupts using the INTR instruction. This allows any of the 32 interrupt service routines (ISRs) to be executed from your software. The first 20 ISRs are reserved for external interrupts, peripheral interrupts, and future implementations. The remaining 12 locations in the interrupt vector table are user-definable. The INTR instruction can invoke any of the 32 interrupts available on the 'C5x devices. When an interrupt is executed, certain key CPU registers are saved automatically. The PC is saved on an 8-deep hardware stack, which is also used for subroutine calls. Therefore, the CPU supports subroutine calls within an ISR as long as the 8-level stack is not exceeded. Also, there is a 1-deep stack (or shadow register) for each of the following registers: - Accumulator (ACC) Accumulator buffer (ACCB) Auxiliary register compare register (ARCR) Index register (INDX) Processor mode status register (PMST) Product register (PREG) Status register 0 (ST0) Status register 1 (ST1) Temporary register 0 (TREG0) for multiplier Temporary register 1 (TREG1) for shift count Temporary register 2 (TREG2) for bit test When the interrupt trap is taken, the contents of all these registers are pushed onto a 1-level stack, with the exception of the the INTM bit in ST0 and the XF bit in ST1. On an interrupt, the INTM bit is always set to disable interrupts. The values in the registers at the time of the interrupt trap are still available to the ISR but are also protected in the shadow registers. The shadow registers are copied back to the CPU registers when the RETI or RETE instruction is executed. This function allows the CPU to be used for the ISR without requiring the overhead of context save and restore in the ISR. Software Applications 2-5 Interrupts Example 2­2 illustrates the use of the INTR instruction. The foreground program sets up auxiliary registers and invokes user-defined interrupt number 20. Since the context is saved automatically, the ISR is free to use any of the saved registers without destroying the calling program's variables. The routine shown here uses the CRGT instruction to find the maximum value of 16 executions of the equation Y = aX2 + bX + c. AR1 points to the X values, AR2 points to the coefficients, and AR3 points to the Y results. To return the result to the calling routine, all the registers are restored by executing an RETI instruction. The computed value is placed in the accumulator, and a standard return is executed because the stack is already popped. Example 2­2. Use of INTR Instruction * Foreground Program .mmregs TEMP .set 63h X .set 64h Y .set 65h COEFF .set 66h V_TBL .sect "vectors" RESET B INIT ;Temporary storage. ;This section will be loaded in program ;memory address 0h. ;Skip the next 38 locations to interrupt #20 :Interrupt #20 ­ begins processing here .space 38*16 B ISR20 ISR20 .text INIT LDP #0 ;Initialize data pointer LAR AR1,#X ;AR1 points to X values LAR AR2,#COEFF ;AR2 points to coefficients b,a,c in that order LAR AR3,#Y ;AR3 points to Y results INTR 20 ;Invoke software interrupt #20 B $ ;Finish the program *; * * This routine uses the block repeat feature of the 'C5x to find the maximum * value of 16 executions of the equation Y=aX^2+bX+c. The X values are pointed * at by AR1. The Y results are pointed at by AR3. The coefficients are pointed * at by AR2. At the completion of the routine, ACC contains the maximum value. * AR1, AR2, and AR3 are modified. All other registers are unaffected. * *; ISR20 ISR20 LDP #0 ;Use page 0 of data memory. LACC #08000h SACB ;Initialize AccB with min. possible value MAR *,AR1 ;ARP 0 Accumulator greater than 0 GEQ ACC 0 Accumulator greater than or equal to 0 NC C=0 Carry bit cleared C C=1 Carry bit set NOV OV = 0 No accumulator overflow detected OV OV = 1 Accumulator overflow detected BIO BIO is low BIO signal is low NTC TC = 0 Test/control flag cleared TC TC = 1 Test/control flag set UNC none Unconditional operation You can combine conditions from four groups (Table 2­2). Up to four conditions can be selected; however, each of these conditions must be from different groups. You cannot have two conditions from the same group. For example, you can test EQ and TC at the same time but not NEQ and GEQ. For example: BCND BRANCH,LT,NOV,TC t ; If ACC < 0, no overflow ; and TC bit set. In this example, LT (ACC 0), NOV (OV = 0), and TC (TC = 1) conditions must be met for the branch to be taken. 2-12 Logical and Arithmetic Operations Table 2­2. Groups for Multiconditional Instructions Group 1 Group 2 Group 3 Group 4 EQ OV C TC NEQ NOV NC NTC GT BIO LT GEQ LEQ Testing the status of the TC flag is mutually exclusive to testing the BIO pin. The code in Example 2­6 simultaneously tests the carry (C) flag and the sign bit of the accumulator to locate a zero bit (beginning from MSB) in a 64-bit word, consisting of ACC and ACCB with ACC having the higher part. This 64-bit word could be the serial port output where the first 0 indicates the start bit. Example 2­6. Using Multiple Conditions With BCND Instruction LDP SPLK . . . . LAR RPTB SFLB #0 #63,BRCR ;Code to get 64­bit input word and ;load it in ACC and ACCB AR0,#0 ENDLOOP­1 * MAR BCND ENDLOOP: APL ;No. of iterations ­ 1 *+ ENDLOOP,NC,LT #0FFFEh,PMST ;Initialize the bit counter ;For I=0,I previous largest value * Use CRLT to find minimum value SACL MAXVAL ;Save new largest which is in ACC & ACCB XC #1,C ;Save addr if current value > previous largest SAR AR0,MAXADR MAR *+ endb: RET * At the end of routine, following registers contain: * ACC = 32050 * ACCB = 32050 * (MAXVAL) = 32050 * (MAXADR) = 0307h .data ;Data is expected to be in data RAM .word 5000 ;Start address = 0300h .word 10000 .word 320 .word 3200 .word ­5600 .word ­2105 .word 2100 .word 32050 .word 1000 .word ­1 .end Software Applications 2-15 Logical and Arithmetic Operations Example 2­8. Using Nested Loops .title "NxN Matrix Multiply Routine" .mmregs *; * * This routine performs multiplication of two NxN matrices. * A x B = C where A,B, and C are NxN in size. * Entry Conditions: * AR1 ­> element (0,0) of A (in program space) * AR2 ­> element (0,0) of B (in data space) * AR3 ­> element (0,0) of C (in data space) * DP = 0, NDX = 1 * ARP = 2 * Storage of matrix elements in memory (beginning from low memory): * M(0,0),.,M(0,N­1),M(1,0),.,M(N­1,N­1) * *; LDP #0 SPLK #3Eh,PMST SPLK #2000h,AR1 SPLK #0810h,AR2 SPLK #0820h,AR3 MAR *,AR2 MTRX_MPY: LAR AR0,#(N­1) ;Set up loop count SPLK #N,INDX ;Row size SAR AR2,AR4 ;Save addr of B * ;For i=0,i A(i,0) SPLK #(N­1),BRCR ;Setup loop2 count SAR AR4,AR5 ;AR5 ­> B(0,0) LOOP2: RPTB ELOOP2 ;For j=0,j B(0,j) LOOP3: RPTZ #(N­1) ;For k=0,k B(0,j+1) ELOOP2: SACL *+,0,AR2 ;Save C(i,j) MAR *,AR0 ;Loop back if BANZD LOOP1,*­,AR1 ;Count != N ADRK N ;AR1 ­> A(i+1,0) ELOOP1: MAR *,AR2 ;ARp = AR2 2-16 Circular Buffers 2.5 Circular Buffers Circular addressing is an important feature of the 'C5x instruction set. Algorithms like convolution, correlation, and finite impulse response (FIR) filters can make use of circular buffers in memory. The 'C5x supports two concurrent buffers operating via the auxiliary registers. Five memory-mapped registers control the circular buffer operation: CBSR1, CBSR2, CBER1, CBER2, and CBCR. The start and end addresses must be loaded in the corresponding buffer registers (CBSRx and CBERx) before the circular buffer is enabled. Also, the auxiliary register that acts as a pointer to the buffer must be initialized with the proper value. Example 2­9 on page 2-18 shows the use of a circular buffer to generate a digital sine wave. A 256-word sine-wave table is loaded in the DARAM B1 block of internal data memory from external program memory. Accessing the internal DARAM requires only one machine cycle. The block move address register (BMAR) is loaded with the ROM address of the table. The block-move instruction moves 256 samples of the sine wave to internal data memory, which is then set up as a circular buffer. The start and end addresses of this circular buffer are loaded into the corresponding registers (CBSR1 and CBER1). The auxiliary register AR7 is also initialized to the beginning of the sine-wave table. Note the use of the SAMM instruction to update AR7 because all auxiliary registers are memory-mapped at data page 0. Finally, circular buffer #1 is enabled and AR7 is mapped to that buffer. The other circular buffer is disabled. Whenever the next sample is to be pulled off from the table, postincrement indirect addressing may be used with AR7 as the pointer. This ensures that the pointer wraps around to the beginning of the table if the previous sample was the last one on the table. Software Applications 2-17 Circular Buffers Example 2­9. Use of Circular Addressing .title 'Digital Sine­Wave Generator' .mmregs *; * * This routine illustrates the circular addressing capability of C5x devices. * A digital sine­wave generator is implemented as circular buffer #1 with AR7 * as its pointer. XSINTBL is the location in external program memory where this * table is stored. It is moved to internal data memory block B1 where it is * setup as a circular buffer. * *; XSINTBL .set 03000h ;Program space address of sine table .text SINTBL LDP #0 LAR AR0,#0300h ;Address of B1 block MAR *,AR0 LACC #XSINTBL ;Get sine table address in * ;external program memory SAMM BMAR ;Load source register * RPT #255 ;Move 256­word BLPD BMAR,*+ ;Load table from external program * ;memory to internal data memory SAMM CBSR1 ;Start address of buffer=300h SAMM AR7 ;AR7 points to start of buffer ADD #255 SAMM CBER1 ;End address of buffer=3FFh SPLK #0Fh,CBCR ;Enable CB#1, disable CB#2 . ;pointer for CB#1 is AR7 . . NXTSMP MAR *,AR7 LACC *+ ;Get next sample from table . ;AR7 is updated to next valid sample . . DISBLE APL #0FFF7h,CBCR ;Disable CB#1 . . . RET 2-18 Circular Buffers If the step size must be greater than 1, check to see if an update to the auxiliary register generates an address outside the range of the circular buffer. This may happen if the same sine table is used to generate sine waves of different frequencies by changing the step size. Modulo addressing can avoid such problems. A simple way to perform modulo addressing on 'C5x devices is to use the APL and OPL instructions. For example, to implement the modulo-256 counter, first load the dynamic bit manipulation register (DBMR) with 255 (the maximum value allowed); when the auxiliary register is updated (by any amount), it is ANDed with the DBMR and ORed with the start address of the buffer. The start address of the modulo-2k buffer must have 0s in the k LSBs. Hence, for modulo-256 addressing, the first eight LSBs of the start register must be 0 (see Example 2­10). Example 2­10. Modulo-256 Addressing START .set LDP LACL SAMM . . . MAR APL OPL . . . 04000h #0 #0FFh DBMR ;Start address of the buffer *0+ AR7 #START,AR7 ;Increment AR7 by some amount ;Extract lower 8 bits ;Add the start address ;Max value = 255 Software Applications 2-19 Single-Instruction Repeat (RPT) Loops 2.6 Single-Instruction Repeat (RPT) Loops The 'C5x provides two different types of repeat instructions. The repeat block (RPTB) instruction implements code loops that can be 3 to 65 536 words in size. These loops do not require any additional cycles to jump from the end-ofblock to the start-of-block address at the end of each iteration. In addition, these zero-overhead loops are interruptible so that they can be used in background processing without affecting the latency