TMS320 - Datasheet Archive

 

TMS320 DSP DESIGNER'S NOTEBOOK TMS320C5x Wait States Contributed by Joe George Design Problem Solution What is the difference

 

Number 48 TMS320 TMS320 DSP DESIGNER'S NOTEBOOK TMS320C5x Wait States Contributed by Joe George Design Problem Solution What is the difference between hardware and software wait states? The 1993 'C5x User's Guide describes how wait states are treated on the 'C5x. But some additional information is useful to tie it all together. Two types of wait states are often spoken of: l) Hardware wait states, 2) Software wait states. H/W wait states are generated by external logic and connected to the 'C5x READY pin. The 'C5x polls this pin on the falling edge of CLKOUT1 as shown in A-16 and A-17. The setup and hold times shown on these pages should be followed. Table A-13 gives these timings in relation to both RD/WE strobes and CLKOUT1. Following either set is sufficient depending on which set of memory interface signals are used (see Designer's Note #45). But as the note on the table describes, external ready is only sampled after S/W wait states are completed. The S/W wait states g enerator is described in Section 5.3 of the 1993 'C5x User's Guide. It is a very flexible on-chip peripheral that eliminates the need for external wait state logic. (Note that any internal access is always 0 wait state). In general, the 'C5x takes one cycle for a read and two cycles for a write. But in the case of READ-WRITE, WRITE-READ combinations, the write will take three cycles. Also, there is a subtle difference between S/W- (using on-chip S/W waitstate generator) and H/W- (using READY line) based wait states and their bus cycles. In the case of S/W wait states, ". the addition of a single wait state generated by the on-chip software wait-state generator only affects the read cycle ." Thus for S/W wait states, the memory R/W cycle for 0 wait state is 1/2, for l W/S is 2/2, for 2 W/S is 3/ 3, for 3 W/S is 4/4. Page 4-25 in the 'C5x User's Guide talks in detail about this. But since H/W wait states are done by ready line polling, the memory R/W cycle for 0 wait states is 1/2, for l W/S is 2/3, for 2 W/S is 3/ 4, and for 3 W/S is 4/5. In summary: Texas Instruments provides customer support in varied technical areas. Since TI does not possess full access to data concerning all of the uses and applications of customers' products, TI assumes no responsibility for customer product design or the use or application of customers' products or for any infringements of patents or rights of others which may result from TI assistance. 5/94 TMS320 TMS320 HOTLINE (713) 274-2320 TMS320 TMS320 FAX (713) 274-2324 TMS320 TMS320 BBS (713) 274-2323 email=4389750@mcimail.com No. of Wait States H/W Wait State Read H/W Wait State Write S/W Wait State Read S/W Wait State Write 0 1 2 1 2 1 2 3 2 2 2 3 4 3 3 3 4 5 4 4 . . . . . . . . . . 48-2