SPRA033 TMS320 IS-54 TMS320C51 IS54B TMS320C53 Q4/16 TEC320 TMS320C40 - Datasheet Archive

 

Applications With the TMS320C5x DSPs Application Book 1994 Digital Signal Processing Products Printed in U.S.A., October 1994

 

Telecommunications Applications With the TMS320C5x DSPs Application Book 1994 Digital Signal Processing Products Printed in U.S.A., October 1994 SPRA033 SPRA033 Telecommunications Applications With the TMS320C5x DSPs 1994 Application Book Telecommunications Applications With the TMS320C5x DSPs Edited by Mansoor A. Chishtie Digital Signal Processing Applications - Semiconductor Group Texas Instruments Incorporated SPRA033 SPRA033 October 1994 Printed on Recycled Paper Part I Introduction Part II Digital Cellular Systems Part III Speech Synthesis Part IV Error-Correction Coding Part V Baseband Modulation and Demodulation Part VI Equalization and Channel Estimation Part VII Speech and Character Recognition Algorithms Part VIII System Design Considerations Part IX Bibliography IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright © 1994, Texas Instruments Incorporated Preface This book belongs to a growing series of digital signal processing application books that Texas Instruments has published over the years. Some of these books are broad in content and cover a wide variety of DSP-related technologies and applications. Others are more focused and concentrate on one DSP application area. TI has also published many individual application reports. This particular collection of application reports focuses primarily on a variety of DSP applications that are related to the field of telecommunications and implemented on the 'C5x generation of the TMS320 TMS320 family. This book is divided into nine parts, including the introduction and the bibliography: Part I Introduction Part II Digital Cellular Systems Part III Speech Synthesis Part IV Error-Correction Coding Part V Baseband Modulation and Demodulation Part VI Equalization and Channel Estimation Part VII Speech and Character Recognition Algorithms Part VIII System Design Considerations Part IX Bibliography Part I introduces the TMS320 TMS320 family and the TMS320C5x generation; it also summarizes various telecommunications applications that use TMS320C5x DSPs. Parts II ­ VIII discuss major application topics. Most of the papers presented here are application reports written either by the engineering staff of the TI digital signal processing department (including factory and field personnel and summer students) or by third parties. Some of the papers were contributed by other departments within TI. It is generally assumed that reader is DSP literate and has some exposure to the TMS320 TMS320 DSP family. The application reports presented in this book represent practical implementations of DSP algorithms. Source code associated with these reports is not listed in this book because of space constraints. However, most of the papers have associated source code that is publicly available from the TMS320 TMS320 DSP Bulletin Board System (BBS) at 713­274­2323. The contents of this BBS are also mirrored at an Internet anonymous FTP site ti.com. Some technical papers included here present commercial implementations that are licensable from respective organizations. The technical data sheets of these implementations will also be included in a future update of the TMS320 TMS320 Software Cooperative Library. The editor would like to thank all the contributors and reviewers of this book. In particular, a special note of appreciation goes to Gene Frantz, Jay Reimer, Raj Chirayil, and Paul Buenaflor for their encouragement and helpful suggestions in improving the overall structure of this book. It is our hope that this book will help you in making the transition to DSP-based telecommunication applications. Lastly, the editor would like to acknowledge the untiring efforts of Ms. Katie Delbridge in planning and coordinating this project. Mansoor A. Chishtie Telecom Applications Digital Signal Processing Semiconductor Group Texas Instruments Incorporated iii iv Contents Title Page Part I: Introduction Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Programmable Versus Hard-Wired Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Fixed-Point Versus Floating-Point Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMS320 TMS320 Digital Signal Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TMS320C5x Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Summary of Telecom Applications Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bibliographies and Other References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Part II: Digital Cellular Systems Digital Cellular Phone: A Functional Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 14 24 29 29 IS-54 IS-54 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 33 35 39 40 40 Part III: Speech Synthesis Theory and Implementation of the Digital Cellular Standard Voice Coder: VSELP on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of VSELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speech Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features of VSELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C5x Real-Time Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Typical Digital Cellular Vocoder Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 43 43 57 59 59 60 61 61 v Contents Title Page Part IV: Error-Correction Coding U.S. Digital Cellular Error-Correction Coding Algorithm Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSELP Channel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FACCH Channel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 65 65 66 73 75 75 Viterbi Implementation on the TMS320C5x for V.32 Modems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Standard V.32 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Viterbi Decoder Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 A TMS320C53-Based Enhanced Forward Error-Correction Scheme for U.S. Digital Cellular Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Algorithm Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 105 105 105 107 108 109 109 Part V: Baseband Modulation and Demodulation IS-54 IS-54 Digital Cellular Modem Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of p/4-QPSK Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Theory of the p/4-DQPSK Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modem Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi 111 113 113 115 119 126 129 129 130 Contents Title Page A DSP GMSK Modem for Mobitex and Other Wireless Infrastructures . . . . . . . . . . . . . . . . . . . . . Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mobitex DSP Modem Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMSK Demodulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 133 133 135 137 140 144 144 145 Part VI: Equalization and Channel Estimation Equalization Concepts: A Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What Is Intersymbol Interference? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LMS Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 149 149 159 167 174 174 Channel Equalization for the IS-54 IS-54 Digital Cellular System With the TMS320C5x . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equalizer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Choosing an Update Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 179 179 183 186 187 187 Digital Voice Echo Canceler Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 'C5x Device Features Used in This Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix: Schematic of the Dual-Telephone Interface for the TMS320C51 TMS320C51 SWDS . . . . . . . . 189 191 191 201 201 201 201 202 vii Contents Title Page Part VII: Speech and Character Recognition Algorithms DSP-Based Handprinted Character Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System-Level Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 205 206 207 211 212 Implementation of an HMM-Based, Speaker-Independent Speech Recognition System on the TMS320C2x and TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The TMS320-Based HMM Recognizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 215 215 215 218 226 Automated Dialing of Cellular Telephones Using Speech Recognition . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Human Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 231 231 232 233 234 235 236 Part VIII: System Design Considerations The PCMCIA DSP Card: An All-in-One Communications System . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 239 240 242 245 Software Coding Guidelines for 'C5x Developers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Platform Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Source Code Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix: A Sample Linker Command File for the 'C5x Card . . . . . . . . . . . . . . . . . . . . . . . . 247 249 249 249 252 253 254 255 viii Contents Title Page TCM320AC3x/4x Voice-Band Audio Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed- and Variable-Data-Rate Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 261 262 262 264 265 266 267 Part IX: Bibliography Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320 TMS320 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mobile Radio Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation and Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equalization, Channel Estimation, and Adaptive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speech Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speech Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 273 273 274 274 275 276 280 ix List of Illustrations Figure Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. TMS320 TMS320 Family of Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Key Features of the TMS320C5x Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Digital Cellular Phone: A Functional Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1. Functional Components of a DualMode (IS54) Cellular Phone . . . . . . . . . . . . . . . . 13 2. Functional Blocks of the Digital Portion of a DualMode Phone . . . . . . . . . . . . . . . . 14 3. FrontEnd Analog Section Converts Audio to a 64kbps Data Stream . . . . . . . . . . . . 15 4. FullRate Speech Coder (VSELP) Reduces a 64kbps Data Stream to an 8kbps Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. A Channel Coder and Its Functional Components With Associated Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. Error Protection via Convolutional Coding and CRC Computation . . . . . . . . . . . . . . 18 7. Error Protection Adds 101 Extra Bits per Speech Frame . . . . . . . . . . . . . . . . . . . . . . . 18 8. Interleaving Adjacent Frames for Error Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9. ControlSignal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10. Burst Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11. A 4Level Modulator Groups Two Bits to Form a Symbol . . . . . . . . . . . . . . . . . . . . . . 22 13. p/4 Differential Quaternary PSK Modulator States . . . . . . . . . . . . . . . . . . . . . . . . . . . p/4 DQPSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14. Linear RF Amplifiers Are Needed for IS54 Cellular Phone . . . . . . . . . . . . . . . . . . . . 23 15. RF Portion of Receiver Section of DualMode Cellular Phone . . . . . . . . . . . . . . . . . . 24 12. 22 23 16. An MLSE Adaptive Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17. Channel Decoding and Speech Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IS54 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1. IS54B IS54B Simulation Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2. IS54 Error Encoding and Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3. IS54 Convolutional Encoding Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4. IS54 Slot Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Theory and Implementation of the Digital Cellular Standard Voice Coder: VSELP on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1. LPC Filter Coefficient Quantization and Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 47 2. Adaptive Code Book Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3. Code Book Search Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4. Possible Digital Cellular System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 U.S. Digital Cellular ErrorCorrection Coding Algorithm Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1. Voice and ControlChannel Multiplexing Over One Time Slot . . . . . . . . . . . . . . . . . . 65 2. Error Protection for VSELP Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3. Convolutional Encoder for VSELP Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4. Representative Trellis Section for VSELP Convolutional Encoder . . . . . . . . . . . . . . . 67 5. x Transition Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6. FACCH Rate1/4 Convolutional Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 List of Illustrations Figure Title Page Viterbi Implementation on the TMS320C5x for V.32 Modems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1. V .32 Modems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2. V .32 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3. Viterbi Encoder Convolutional Encoding Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4. V .32 Modem Trellis Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5. Viterbi Decoding Output Tracking and Cost Function . . . . . . . . . . . . . . . . . . . . . . 86 6. V .32 Modem Signal Element Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7. Viterbi Decoding Dynamic Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8. V .32 Encoder Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9. Decoder Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10. Delay State Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11. 128Word Circular Buffers Format of PAST_PATH and PAST_DL Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Y 12. DIST Table Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13. WhiteNoise Impairment Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 A TMS320C53-Based Enhanced Forward Error-Correction Scheme for U.S. Digital Cellular Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 1. IS54 VoiceChannel GVA Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2. Simulated Bit Error Rate of Serial GVA Versus VA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3. State Path History Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 IS-54 IS-54 Digital Cellular Modem Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . 111 1. p/4Shifted QPSK Signal Constellation 2. Modulator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 3. Demodulator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4. Interrupt Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5. Modem Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6. BER Versus SNR for a Static AWGN Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 A DSP GMSK Modem for Mobitex and Other Wireless Infrastructures . . . . . . . . . . . . . . . . . . . . . 131 1. Typical Mobitex Terminal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 2. Bit Error Rate Versus Eb/No Modem Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3. Idealized GMSK.3 Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4. Eye Pattern for 8kbps GMSK.3, 215-1 Length Pseudorandom Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5. GMSK Modulator DSP Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6. GMSK Demodulator DSP Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7. Mobitex Packet Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8. ComputerSimulated Eye Pattern for a 19.2kbps GMSK.5 (Amplitude Versus Time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 xi List of Illustrations Figure Title Page Equalization Concepts: A Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 1. A Pulse Train to Be Transmitted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 2. Component of r(t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 3. Contribution Due to x-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4. 5. Contribution Due to x1 at t = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Set of Shifted Pulse Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6. Odd Symmetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7. Spectral Response at 1/(2T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8. Time Response of the Raised Cosine Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9. Transmission Process With Example Pulse Responses . . . . . . . . . . . . . . . . . . . . . . . . 159 10. Case 1: Ideal Channel, No Multipath Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11. Case 2: System With a Single Unattenuated Multipath Channel . . . . . . . . . . . . . . . . 161 12. Equalization Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13. Simulated Pulse Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14. ZFE Filter Coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 15. Filter Output Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16. DecisionDirected Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 17. Received Signal Including Additive Noise Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 18. DFE Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Channel Equalization for the IS-54 IS-54 Digital Cellular System With the TMS320C5x . . . . . . . . . . . . 177 1. p/4 DQPSK 2. Multipath Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 3. Rayleigh Fading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 4. Intersymbol Interference: Interferer Level -3 dBc . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5. Block Diagram of a DecisionFeedback Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6. Equalizer Taps Responding to a Fade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 DSP-Based Handprinted Character Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 1. Prototype HHC Platform With Pen Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 2. DSP Card Memory Organization for HCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Implementation of an HMM-Based, Speaker-Independent Speech Recognition System on the TMS320C2x and TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 1. A Minimal TMS320C53 TMS320C53 HMM System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 3. Example of an HMM Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 4. Block Diagram of the HHM Recognizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 5. The Feature Extractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6. Example of Q4/16 Q4/16 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 7. xii Voice Dialer Sentence Hypothesizer Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 2. SISR System for Very Large Vocabulary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 List of Illustrations Figure Title Page Automated Dialing of Cellular Telephones Using Speech Recognition . . . . . . . . . . . . . . . . . . . . . . . 229 1. Flow Diagram of Human Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 The PCMCIA DSP Card: An All-in-One Communications System . . . . . . . . . . . . . . . . . . . . . . . . . 237 1. DSP Card Block Diagram 2. DSP Card Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 3. Loading and Executing a Single Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Software Coding Guidelines for 'C5x Developers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 1. Categories of Source Code Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 TCM320AC3x/4x Voice-Band Audio Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 1. VBAP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 2. VBAP Microphone Connection 3. VBAP Interfaced to a 'C5x DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 xiii List of Tables Table Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Benefits of TMS320C5x Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Digital Cellular Phone: A Functional Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1. Basic Parameters of a VSELP Speech Coder 2. Bit Allocations Within a Frame of Speech. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Detailed Bit Allocations of Parameters Within a Frame 4. Interleaving of T wo Adjacent Speech Frames, x and y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 . . . . . . . . . . . . . . . . . . . . . . . 16 . . . . . . . . . . . . . . . . . . . . . . . . . 19 Theory and Implementation of the Digital Cellular Standard Voice Coder: VSELP on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1. Primary VSELP Parameters 2. VSELP Frame Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3. VSELP V ocoder Processor Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4. VSELP V ocoder Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Viterbi Implementation on the TMS320C5x for V.32 Modems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1. Program Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2. V .32 Encoder Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3. V .32 Decoder Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 A TMS320C53-Based Enhanced Forward Error-Correction Scheme for U.S. Digital Cellular Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 1. Algorithm Execution Time on a 35ns TMS320C53 TMS320C53 2. Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 IS-54 IS-54 Digital Cellular Modem Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . 111 1. Phase Calculation 2. Reduced Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3. OddSymbol LookUp 4. EvenSymbol LookUp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5. Modulator LookUp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6. Program Memory and Speed Requirements 7. Modulator Code Size and Execution Time 8. Demodulator Code Size and Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 A DSP GMSK Modem for Mobitex and Other Wireless Infrastructures . . . . . . . . . . . . . . . . . . . 131 1. Receiver Code Processor Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Channel Equalization for the IS-54 IS-54 Digital Cellular System With the TMS320C5x . . . . . . . . . . . 177 1. Complexity Comparison of Update Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Digital Voice Echo Canceler Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . 189 1. Program Module Requirements 3. 512 ap Implementation Data V T ariables 4. xiv UserDefined System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 2. Code Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 List of Tables Table Title Page DSP-Based Handprinted Character Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 1. Application Command Table for HCR Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Implementation of an HMM-Based, Speaker-Independent Speech Recognition System on the TMS320C2x and TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 1. Current HMM Vocabulary (49 Words) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 2. HMM Processor Loading on a TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 3. Examples of Qn/m Notations (FixedPoint Representation) . . . . . . . . . . . . . . . . . . . 225 The PCMCIA DSP Card: An All-in-One Communications System . . . . . . . . . . . . . . . . . . . . . . . . 237 1. DSP Card Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 TCM320AC3x/4x Voice-Band Audio Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 1. ReceiveChannel VolumeControl Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 2. VBAP Master Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 3. PowerDown and Standby Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 xv List of Examples Example Title Page U.S. Digital Cellular Error-Correction Coding Algorithm Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1. Pseudocode for T rellis Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2. T rellis Expansion Macro in 'C5x Assembly Code 3. T raceBack Function PseudoC Code 4. T raceBack Implementation in 'C5x Assembly Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Digital Voice Echo Canceler Implementation on the TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . 189 1. Echo Estimation Routine FIR.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3. Coefficient Update Routine TAPINC.ASM 4. NearEnd Speech Detection Routine NESPDET .ASM 5. Echo Simulation Filter EFILT .ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 6. Use of Delayed Branches NESPDET .ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 7. Code Excerpt from MULAW .ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 8. T aps Update Routine UPDATE.ASM 9. xvi ZeroOverhead Loops UPDATE.ASM 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Serial Port ISR ECHOISR.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 . . . . . . . . . . . . . . . . . . . . . . . 193 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Introduction Mansoor A. Chishtie Digital Signal Processing Applications - Semiconductor Group Texas Instruments Incorporated 1 2 Overview The use of programmable digital signal processors (DSPs) is growing rapidly in telecommunication applications. Conventional wire-line telephony applications were among the earliest adopters of digital signal processing technologies. High-speed telephone-line modem products use more general-purpose DSPs than most other industries, and recent growth of personal and mobile communication services has spurred new interest in high-performance DSPs. With the ongoing integration of mobile communication services and portable computer applications, the role of programmable DSPs in emerging products is expanding. Today, digital signal processors are moving from high-end, low-volume applications to mainstream consumer applications. Telecommunication applications can be broadly categorized into two classes: 1. Core Applications. These applications are the essence of any telecommunication product and include baseband signal processing algorithms, voice and data compression, error correction techniques, and equalization and channel estimation. 2. Enabler Applications. These applications provide necessary human interface, improve overall quality of an end-product, and include speech and character recognition, echo cancellation, and noise cancellation. Programmable Versus Hard-Wired Solutions DSPs are following the path of microprocessors in terms of performance and on-chip integration. At the same time, users of DSPs are concerned about power consumption. As the communications industry improves portable applications, low power and high integration become key design care-abouts. Generally speaking, a product design is constrained by one or more of the following key design goals, not necessarily with equal importance: · · · · · · Power consumption Product form factor Upgradability Cost of product Cost of design System integration These design goals play key roles in selecting a programmable versus function-specific or hard-wired DSP solution. Newer generation DSPs are addressing these concerns. They support various low-power and power-down modes along with clock control options to help meet power goals. System integration and form-factor goals are often interrelated. With high on-chip integration of peripherals and memory, modern DSPs are well-suited for portable applications in which product form factor is extremely important. In Part VIII, "The PCMCIA DSP Card: An All-in-One Communications System", page 237, describes a DSP system based on Personal Computer Memory Card Interface Association (PCMCIA) type II card specifications. Many DSPs are now available in thin low-profile plastic packages, which are ideal for surface-mount applications. 3 In today's evolving communications world, flexibility and upgradability of design are key factors in longer product cycles. Many personal communication standards are in the early stages of development. Some of these standards must maintain compatibility with older standards. Programmable DSPs are especially suitable for designs that require multiple modes of operation and future upgradability. In a U.S. digital cellular subscriber unit, a programmable DSP engine can easily handle the two-mode operation. Finally, the traditional distinction between programmable and function-specific DSP designs is fading because of customizable DSP (cDSP) solutions. Now, designers can decide which section of a design is best suited for a hard-wired approach. Code that must maintain upgradability can be downloaded into on-chip RAM. The rest of the program can be masked on on-chip ROM. Algorithm accelerators or custom peripherals can be designed and placed on the same die. These techniques can be implemented through the TI standard cDSP cell design methodology or through the standard gate-array design flow of the TEC320 TEC320 product line. Fixed-Point Versus Floating-Point Solutions Typically, floating-point DSPs are used in high-end, high-performance telecom applications such as video conferencing, network packet switching, cellular base stations, etc. Floating-point DSPs offer large dynamic range, a fast floating-point computation engine, and large-memory addressability. Due to wider instruction word size, they support more addressing modes and higher execution unit parallelism as well. Floating-point support and large operand dynamic range result in an ease of transition from simulation environment to real-time implementation. A more orthogonal instruction set helps in providing efficient high-level language code generation tools. On the other hand, fixed-point 16-bit DSPs are very popular in high-volume, low-power applications. Generally, they consume less power and cost less because of a smaller die size. They can be operated at faster speeds because of their relatively simple architecture and fewer speed paths. Newer fixed-point DSPs provide application-specific instructions and on-chip power management for portable and mobile communication applications. Due to their prevalence in the mobile communications market, many upcoming industry standards are fine-tuned for 16-bit fixed-point implementations. One such example is the voice compression specification of U.S. Digital Cellular Standard, the IS-54 IS-54. This algorithm is optimized for 16-bit fixed-point DSP engines. With improved compiler support and a more orthogonal instruction set, the end-product development cycle has also become shorter. 4 TMS320 TMS320 Digital Signal Processors The TMS320 TMS320 family consists of five generations of fixed-point and floating-point devices (see Figure 1). Members of each generation are object-code and, in some cases, pin compatible. Each generation offers unique features and capabilities, which are optimized for certain types of applications. Figure 1. TMS320 TMS320 Family of Devices ÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ Ç TMS320C4x TMS320C40 TMS320C40 TMS320C40-40 TMS320C40-40 TMS320C30 TMS320C30 TMS320C30-27 TMS320C30-27 TMS320C30-40 TMS320C30-40 TMS320C30-50 TMS320C30-50 TMS320C31 TMS320C31 TMS320C31-27 TMS320C31-27 TMS320C31-40 TMS320C31-40 TMS320C31PQA TMS320C31PQA TMS320C31-50 TMS320C31-50 TMS320LC31 TMS320LC31 TMS320C2x TMS320C1x TMS320C10 TMS320C10 TMS320C10-14/-25 TMS320C10-14/-25 TMS320C14 TMS320C14 TMS320E14/P14 TMS320E14/P14 TMS320C15/LC15 TMS320C15/LC15 TMS320E15/P15 TMS320E15/P15 TMS320C15-25 TMS320C15-25 TMS320E15-25 TMS320E15-25 TMS320C16 TMS320C16 TMS320C17/LC17 TMS320C17/LC17 TMS320E17/P17 TMS320E17/P17 TMS320C25 TMS320C25 TMS320E25 TMS320E25 TMS320C25-33 TMS320C25-33 TMS320C25-50 TMS320C25-50 TMS320C26 TMS320C26 TMS320C5x TMS320C50/-50/-57/-80 TMS320C50/-50/-57/-80 TMS320LC50/-50/-80 TMS320LC50/-50/-80 TMS320C51/-57/-80 TMS320C51/-57/-80 TMS320BC51/-57/-80 TMS320BC51/-57/-80 TMS320C52/-57/-80 TMS320C52/-57/-80 TMS320C53/-57/-80 TMS320C53/-57/-80 TMS320BC53/-57/-80 TMS320BC53/-57/-80 TMS320C56 TMS320C56 TMS320C57 TMS320C57 Generation Fixed-Point Generations ÇÇ ÇÇ Performance (MIPS/MFLOPS) TMS320C3x Floating-Point Generations 5 TMS320 TMS320 Fixed-Point DSPs The three generations of TMS320 TMS320 fixed-point DSPs - TMS320C1x, TMS320C2x, and TMS320C5x - have a 16-bit architecture with a 32-bit ALU and accumulator. They are based on Harvard architecture with separate buses for program and data, allowing instructions and operands to be fetched in parallel. They also feature a 16 16-bit hardware multiplier for single-cycle multiply operations, and a hardware stack for fast interrupt response time. An overflow saturation mode prevents wraparound. Most of the instructions are executed in a single cycle. Performance currently ranges from 3.5 to 40 MIPS (million instructions per second). Even higher performance DSPs will become available in the near future. The TMS320C1x generation is based on the first DSP, the TMS32010 TMS32010, which was introduced in 1982. 'C1x devices include 144/256 words of on-chip RAM and 4K to 8K words of on-chip ROM. Instruction cycle time is 114 to 280 ns. Members of this generation include the TMS320C10 TMS320C10, TMS320C14 TMS320C14, TMS320E14 TMS320E14 (the EPROM version of the TMS320C14 TMS320C14), TMS320C15/E15 TMS320C15/E15, TMS320C16 TMS320C16, and TMS320C17/E17 TMS320C17/E17. The TMS320C14/E14 TMS320C14/E14 has been optimized for control applications. The TMS320C16 TMS320C16 has an expanded memory address space of 64K words. Low-power versions are also available for 3-volt designs. The TMS320C2x generation is based on the TMS320C25 TMS320C25, featuring 544 words of on-chip RAM and 4K words of on-chip ROM. Total address space is expanded to 64K words for both data and program. The instruction set has been considerably enhanced over the TMS320C1x instruction set, reducing the instruction cycle time to 120/80 ns. Other members of the 'C2x generation include the TMS320E25 TMS320E25 (an EPROM version of TMS320C25 TMS320C25), the TMS320C26 TMS320C26, and the TMS320C28 TMS320C28, which expands the on-chip RAM and ROM. The TMS320C5x generation includes the TMS320C50 TMS320C50 (10K words of on-chip RAM, 2K words of on-chip ROM), TMS320C51 TMS320C51 (2K words of on-chip RAM, 8K words of on-chip ROM), TMS320C52 TMS320C52 (1K words of on-chip RAM, 4K words of on-chip ROM), TMS320C53 TMS320C53 (4K words of on-chip RAM, 16K words of on-chip ROM), and TMS320C53SX TMS320C53SX (4K words of on-chip RAM, 16K words of on-chip ROM). All the devices except the 'C52 have two serial ports; the 'C52 has one. Most of the devices in this generation are available in thin plastic (132- and 100-pin) quad flatpack packages. With an enhanced instruction set, TMS320C5x devices can execute code at the rate of 25 ns per instruction. New architecture features include a bit-manipulation unit, called PLU (parallel logic unit), shadow registers for fast context switch, JTAG serial scan emulation, and zero-overhead loops. Low-power versions are also available. TMS320 TMS320 Floating-Point DSPs The two generations of TMS320 TMS320 floating-point DSPs - TMS320C3x and TMS320C4x (the first DSP designed for parallel processing) - have a 32-bit architecture with 40-bit extended-precision registers. They are based on Von Neuman architecture. Multiple buses have been added for faster throughput. Features include a hardware floating-point multiplier and a floating-point ALU. The TMS320C3x generation is based on the TMS320C30 TMS320C30 and features 2K 32 words of on-chip RAM, 4K 32 words of on-chip ROM, and a 64-word on-chip instruction cache. 'C3x devices include an on-chip DMA controller, two serial ports, two timers, two external 32-bit data buses, and a 16M-word linear address space. Instruction cycle rates are 60 and 50 ns, with peak performance of 40 MFLOPS (million floating-point operations per second). A low-power version of TMS320C31 TMS320C31 features special instructions for power management. The TMS320C4x generation includes the TMS320C40 TMS320C40, a parallel digital signal processor. It includes six communications ports, a self-programmable six-channel DMA coprocessor, a developing/debugging analysis module, two independent 32-bit memory interfaces, a 16G-byte address space, and two timers. Other features includes two 4K-byte RAM blocks, one 16K-byte ROM block, and a 512-byte instruction 6 cache. This generation is designed to execute each instruction in 40 ns, perform up to 275 MOPS (million operations per second), and provide 320M-byte/second throughput. TMS320C5x Architecture The TMS320C5x generation is designed to perform complex computation-intensive signal processing in real time. It has a high-performance pipelined architecture that enables it to execute each instruction at the maximum rate of 25 ns per instruction. It has a familiar 16/32-bit accumulator-based architecture with a 16-bit wide external address bus and a hardware multiplier similar to traditional DSP architectures. It includes a bit-manipulation or parallel logic unit, (PLU), which allows it to efficiently implement traditional microcontroller-type operations. Automatic interrupt context switch and reduced interrupt latency are made possible by on-chip shadow registers and an 8-word deep hardware stack. On-chip peripherals include two serial ports (one of which can be used in the time division multiplex mode), one timer, a wait-state generator, and a phase-locked loop for clock frequency multiplication. Figure 2 on page 8 shows the key features of the TMS320C5x architecture. The TMS320C5x architecture introduces several new features to make it suitable for telecommunication and related applications. Traditional communication designs (such as modems and cellular radios) use a microcontroller and one or more digital signal processors. Typical microcontroller tasks are system control, general housekeeping, and user interface. These tasks are generally run on a microcontroller because they do not require a high-performance processor. Additionally, these functions are often written in C and involve bit manipulation. The 'C5x bit manipulation unit (PLU), memory-mapped input-output ports, dynamic postscalers and prescalers, and C language support enable these traditional microcontroller tasks to be efficiently implemented. Salient features and benefits of TMS320C5x architecture are shown in Table 1. Table 1. Benefits of TMS320C5x Features ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Feature Benefit Harvard architecture Simultaneously accesses instructions and data operands Parallel logic unit Allows direct bit manipulation on memory operands Shadow registers Allow zero-overhead context switch for interrupts Hardware stack Supports fast interrupt processing Repeat-block loops Reduce overhead of looped code Memory-mapped I/O ports Efficiently handle peripheral data transfer Circular buffers Implement queues, delay lines, circular convolution, etc. Hardware multiplier Supports single-cycle signed and unsigned integer multiplication Power-down modes Reduce active and idle power consumption High-speed, single-cycle instruction execution unit Helps implement advanced signal-processing algorithms in real time 7 Figure 2. Key Features of the TMS320C5x Architecture Program/Data RAM ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ Program ROM Program/Data Buses Multiplexer Multiplexer JTAG Test/Emulator Control Serial Ports CPU 0 ­ 16-Bit Preshift 16-Bit T Register Timer 32-Bit ALU PLU 0 ­ 7-Bit Preshift 16 × 16-Bit Multiply 0 ­ 16-Bit Right-Shift Memory Mapped Registers ­ 8 Auxiliary ­ 3 TREGs 0-, 1-, 4-, 6-Bit Shift Context Switch Status Register ­ Block/Repeat ­ Circular Buffer Instruction Register Peripheral Bus 32-Bit ACC With Buffer Software Wait States I/O Ports Phase-Lock Loop 8 Summary of Telecom Applications Topics Digital Cellular Systems Digital cellular radio designs use general-purpose DSPs to perform speech synthesis, error-correction coding, baseband modem, and system control applications. Where other parts of this book concentrate on these individual applications, Part II focuses primarily on overall system design and highlights tasks suitable for DSP implementation. Speech Synthesis Speech compression and coding is one of the earliest and most widely used DSP applications. In both wireline or wireless communications vocoders are used to compress speech signals for limited bandwidth channels. An application paper on U.S. Digital Cellular vocoder implementation is presented in this section. Error-Correction Coding Forward error-correction (FEC) schemes are widely used in telecom applications to reduce bit error rate (BER) on noisy channels. The need for improved FEC techniques is becoming more prominent these days as more data is pumped through limited bandwidth channels. Cyclic redundancy check (CRC) and bit parity check are still used for simple error detection. However, more complex forward error-correction schemes such as convolutional encoding with Viterbi decoding and Reed-Solomon (RS) codes are often used to detect and correct multiple bit errors. Often, concatenated coding schemes are used to provide even more protection against bit errors than is possible with a single scheme. One such example is IS-54 IS-54 voice channel specification, in which Class I bits are protected by both the CRC and convolutional codes. This is described in a paper that is presented in this part. Another conference paper on FEC schemes is also included here, and a third describes an implementation of forward error-correction technique used for V.32 modems. Baseband Modulation and Demodulation Programmable digital signal processors can provide necessary performance and throughput to implement baseband modem functions. These functions include symbol timing recovery, automatic gain and frequency control, symbol detection, pulse-shaping, and matched filters. Many of these functions were formerly implemented in hardware. With the advent of high-performance DSPs and the growing need for multipurpose hardware designs, many of these functions are being implemented in DSP software. One such example is the U.S. Digital Cellular IS-54 IS-54 standard for mobile phones, in which every terminal is required to handle three modulation schemes: FM, FSK, and DQPSK. Two papers are presented in this book on this subject. Equalization and Channel Estimation Another computationally intensive DSP task is channel modeling for estimation of echo, noise, or intersymbol interference. Line echo cancellation is a common wireline telephony application suitable for DSP implementation. Acoustic echo and noise cancellation techniques are equally important for wireline and wireless communication links. Equalization is another channel estimation technique for removal of intersymbol interference caused by channel delay spread. The first paper in this section presents a tutorial on equalization techniques. The other two papers present implementation details of an equalizer and a line echo canceller. 9 Speech and Character Recognition Algorithms DSPs are often called upon to perform user-interface tasks in addition to core applications. This is a direct consequence of one very important feature of a DSP-based product: flexibility of design. This flexibility allows system designers to load additional tasks on their DSPs to better utilize spare MIPS. A pertinent example is that of a mobile phone; the voice dialing feature can be easily implemented on a DSP without additional DSP horsepower. This is because the phone will be on-hook (or off-air), and the DSP will have many spare MIPS available when the voice dialing feature is enabled. With the onset of personal digital assistant (PDA) technology in which computers and communication applications merge, human interface designs are gaining more importance. Three application papers are presented in this section. System Design Considerations Every DSP system engineer deals with several design care-abouts. This part highlights some of these general hardware and software design considerations. The paper "The PCMCIA DSP Card: An All-in-One Communications System" presents an embedded DSP hardware design example. The second paper, "Software Coding Guidelines for 'C5x Developers" outlines general programming guidelines for TMS320C5x assembly language programmers. Finally, the paper "TCM320AC3x/4x Voice-Band Audio Processors" describes DSP applications with voice-band audio processors. Bibliographies and Other References To keep TMS320 TMS320 designers aware of new applications and developments related to the TMS320 TMS320 DSPs, Texas Instruments has published extensive bibliographies of TMS320-related conference papers and technical articles. Part IX of this book serves as an extension to the previously published bibliographies. It lists only those papers and articles that are generally related to telecommunication applications. In addition to this collection of telecommunications-related papers on TMS320C5x digital signal processors, Texas Instruments has published related application papers on other TI digital signal processors. For more information, refer to Volumes 1, 2, and 3 of Digital Signal Processing Applications with the TMS320 TMS320 Family: Theory, Algorithms, and Implementations. 10 Digital Cellular Phone: A Functional Analysis B. I. (Raj) Pawate Mansoor A. Chishtie Digital Signal Processing Applications - Semiconductor Group Texas Instruments Incorporated 11 12 Introduction This document presents the functional components of a dual-mode cellular phone as specified by the CTIA IS-54 IS-54 standard. For each functional component, the relevant algorithm, its data structures, if any, and implementation details are given. A Functional View of a Dual-Mode Cellular Phone As shown in Figure 1, a dual-mode cellular phone consists of the following: · · · · · Transmitter Receiver Antenna assembly Control panel Coordinator A dual-mode phone is capable of operating in an analog-only cell or a dual-mode cell. Both the transmitter and the receiver support both analog FM and digital time division multiple access (TDMA) schemes. Digital transmission is preferred, so when a cellular system has digital capability, the mobile unit is assigned a digital channel first. If no digital channels are available, the cellular system will assign an analog channel. The transmitter converts the audio signal to a radio frequency (RF), and the receiver converts an RF signal to an audio signal. The antenna focuses and converts RF energy for reception and transmission into free space. The control panel serves as an input/output mechanism for the end user; it supports a keypad, a display, a microphone, and a speaker. The coordinator synchronizes the transmission and receive functions of the mobile unit. Figure 1. Functional Components of a Dual-Mode (IS-54 IS-54) Cellular Phone Transmitter Analog-to-Digital Converter Coder RF Amplifier Phase Modulator Transmit Audio Signal Processing FM Modulator RF Amplifier Display Coordinator Control Duplexer Keyboard Antenna Assembly Digital-to-Analog Converter RF Amplifier Demodulator Receive Audio Signal Processing Control Panel Decoder FM Demodulator RF Amplifier Receiver 13 Figure 2 shows the functional components of the digital portion of a dual-mode cellular phone. Figure 2. Functional Blocks of the Digital Portion of a Dual-Mode Phone Channel Coder A DQPSK Modulator FACCH CDVCC Speech Coder SACCH ADC A 90° Phase Shift Bandpass Filter Isolator Detector 824­849 MHz RF Control Coordinator Osc Detector CDVCC FACCH SACCH Osc Bandpass Filter X 864­904 MHz A Bandpass Filter 869 ­ 894 MHz 90° Phase Shift AGC 45 MHz DAC Speech Decoder Channel Decoder Equalizer DQPSK Demodulator X A CDVCC = coded digital verification color code DQPSK = differential quaternary phase-shift keying FACCH = fast associated control channel SACCH = slow associated control channel Transmitter The transmitter converts low-level audio signals from the microphone to digitally coded RF signals by audio processing, digital signal processing, modulation, and RF amplification. The transmitter converts 64-kbps pulse code modulation (PCM) data to a lower data rate, multiplexes control information, error-protects the data, and then passes the data stream to the RF section for modulation, amplification, and transmission. The coordinator inserts system control messages. Transmit Front-End Processing Speech signals from the microphone are first amplified, passed through an antiliasing filter, and sampled at a rate of 8 kHz to create a digitized µ-law 64-kbps bit stream. Typically, no pre-emphasis is applied. Figure 3 shows the functional blocks of the front-end analog section. The standard does not propose any specific echo canceler; however, it recommends implementing one. The front-end processing includes the following: · · · 14 An amplifier. The gain is specified to produce an average signal energy, during a frame, which is 18 dB down from full scale. A bandpass filter to avoid antialiasing. An analog-to-digital converter. The standard recommends that you either directly convert the analog signal to a uniform PCM format with a minimum resolution of 13 bits or convert the analog signal to an 8-bit µ-law codec sample. Figure 3. Front-End Analog Section Converts Audio to a 64-kbps Data Stream Amplifier BP Filter 64 kbps ADC Either a linear ADC with 13 bits of resolution or an 8-bit µ-law codec sampled at 8 kHz Speech Coder The speech coder further reduces the data rate by compressing the 64-kbps data stream input to create a 7.950-kbps data stream. The IS-54 IS-54 standard accepts a full-rate speech coder called vector sum excited linear prediction (VSELP). This algorithm belongs to a class of speech coders known as code excited linear predictive coders (CELP). This class uses code books to vector quantize the excitation (residual) signal. VSELP is a variation on CELP. The incoming 64 kbps of data are grouped into frames at a frame rate of 50 frames per second. Hence, each frame contains 160 samples and represents a duration of 20 ms. Each frame is coded into 159 bits. Hence, the rate of the conversions is 50 159 = 7950 bps, as shown in Figure 4. Figure 4. Full-Rate Speech Coder (VSELP) Reduces a 64-kbps Data Stream to an 8-kbps Data Stream 64-kbps Speech Coder ~15 MIPS 7.950-kbps The speech decoder utilizes two separate code books. Each code book has an independent gain. The two code-book excitations are each multiplied by their corresponding gains and summed to create a combined code-book excitation. The basic parameters are shown in Table 1. Table 1. Basic Parameters of a VSELP Speech Coder ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Parameter Notation Specification Sampling rate s 8 kHz Frame length Nf 160 samples (20 ms) Subframe length N 40 samples (5 ms) Short-term predictor order Np 10 Number of taps for long-term predictor NL 1 Number of bits in code word 1 (number of basis vectors) M1 7 bits Number of bits in code word 2 (number of basis vectors) M2 7 bits NOTE: Within a frame, the 159 bits are allocated as shown in Table 2; detailed bit allocations are shown in Table 3. 15 16 ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Parameter Parameter Name Bits Allocated Frame energy R0 5 1st reflection coefficient LPC1 6 2nd reflection coefficient LPC2 5 3rd reflection coefficient LPC3 5 4th reflection coefficient LPC4 4 5th reflection coefficient LPC5 4 6th reflection coefficient LPC6 3 7th reflection coefficient LPC7 3 8th reflection coefficient LPC8 3 9th reflection coefficient LPC9 3 10th reflection coefficient LPC10 LPC10 2 Lag for first subframe LAG_1 7 Lag for second subframe LAG_2 7 Lag for third subframe LAG_3 7 Lag for fourth subframe LAG_4 7 1st code book, I, for first subframe CODE1_1 7 1st code book, I, for second subframe CODE1_2 7 1st code book, I, for third subframe CODE1_3 7 2nd code book, H, for first subframe CODE2_1 7 2nd code book, H, for second subframe CODE2_2 7 2nd code book, H, for third subframe CODE2_3 7 2nd code book, H, for fourth subframe CODE2_4 7 {GS, P0, P1} code for first subframe GSP0_1 8 {GS, P0, P1} code for second subframe GSP0_2 8 {GS, P0, P1} code for third subframe GSP0_3 8 {GS, P0, P1} code for fourth subframe GSP0_4 8 Table 3. Detailed Bit Allocations of Parameters Within a Frame Parameter Bits Allocated Short-term filter coefficients 38 Frame energy, R0 5 Lag, L 28 Code words, I, H 56 Gains beta, gamma1, gamma2 32 Table 2. Bit Allocations Within a Frame of Speech Channel Coder The main function of the channel coder is to protect the data stream against the noise and fading that are inherent to a radio channel. The coder accomplishes this by adding extra or redundant bits. The greater the number of redundant bits, the higher the immunity to interference and the lower the bit-error rate. The tradeoff is an increased data rate. The channel coder protects the data stream in four stages: 1. Convolutional coding 2. Cyclic redundancy check (CRC) generation 3. Interleaving 4. Burst generation The first two are mathematical operations, whereas the last two are heuristic approaches. The receiver performs an inverse operation to determine whether errors have occurred during propagation. In radio propagation, it has been found that the fading occurs at localized instances of time and space. As a result, interleaving spreads the information of the data stream across two frames, because it is unlikely that a clustered bit error would occur in successive frames. Finally, data is propagated in bursts. Between interleaving and burst generation, the channel coder multiplexes control information. Figure 5 shows the functional components of a channel coder. Figure 5. A Channel Coder and Its Functional Components With Associated Data Rates Channel Coder 7.950-kbps Data Stream 7.950 kbps Error Protection Interleaving 13 kbps 13 kbps Control Signal Multiplexing 48.6-kbps Data Burst 16.2 kbps Burst Generator 48.6 kbps Convolutional Coding Convolutional coding provides error-correction capability by adding redundancy to the transmitted sequence. Convolutional encoding is implemented by linear feed-forward shift registers. A convolutional coder is described by the rate at which data enters the coder and the rate at which data leaves the coder. For example, a rate-1/2 convolutional coder implies that for every 1 bit of data entering the coder, 2 bits leave the coder. The smaller the ratio, the greater the redundancy. This improves the error-protection capability. To reduce the bit rate, not all of the 159 bits in a frame are error-protected. Only 77 of these bits, called class 1 bits, are error-protected. The remaining 82 bits, called class 2 bits, are not error-protected. This is shown in Figure 6. 17 Figure 6. Error Protection via Convolutional Coding and CRC Computation 12 Most Perceptually Significant Bits 5 Tail Bits 7-Bit CRC Calc. 7 Speech Coder Class 1 Bits 77 Rate 1/2 Convolutional Encoder Coded Class 1 Bits 260 Voice Cipher 2-Slot Interleaver 260 82 Class 2 Bits Speech Frames X and Y 178 Speech Frames Y and Z Cyclic Redundancy Check Of the 77 bits that are error-protected, it has been found that only 12 are perceptually significant. Hence these are protected by using a 7-bit cyclic redundancy computation before they are input to the convolutional coder. A 7-bit CRC is computed by dividing the data by a specified constant and transmitting the remainder with the data. The receiver detects errors by comparing the received remainder with what it has calculated. The following generator polynomial is used for the CRC: gCRC(X) = 1 + X + X2 + X4 + X5 + X7 (1) The parity polynomial, b(X), is the remainder of the division of the input polynomial by the generator polynomial as shown below: a(X)*X7 / gCRC(X) = q(X) + b(X)/gCRC(X) (2) where q(X) is the quotient of the division and b(x) is the remainder. The quotient is discarded, and only the parity bits identified in b(X) are encoded for transmission. To facilitate the convolutional coder, these parity bits are placed into the array of class 1 bits. Figure 7. Error Protection Adds 101 Extra Bits per Speech Frame Error Protection Adds 101 Bits/20 ms Error Protection 7.950 kbps 13 kbps In short, as shown in Figure 7, error protection adds 101 bits every 20 ms, or an additional 5050 bps. 18 Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ x0 x26 x52 x78 x104 x130 x156 x182 x208 y1 y27 y53 y79 y105 y131 y157 y183 y209 y235 x2 x28 x54 x80 x106 x132 x158 x184 x210 x236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x12 x38 x64 x90 x116 x142 x168 x194 x220 x246 y13 y39 y65 y91 y117 y143 y169 y195 y221 y247 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x24 x50 x76 x102 x128 x154 x180 x206 x232 x258 y25 y51 y77 y103 y129 y155 y181 y207 y233 19 x234 y259 Table 4. Interleaving of Two Adjacent Speech Frames, x and y Table 4 shows how the data is interleaved when y is the current frame and x is the previous frame. Note that the speech data is entered into the interleaving array by columns. 40 ms Speech Frames x and y Speech Frames y and z Figure 8. Interleaving Adjacent Frames for Error Protection As explained earlier, data from each frame is now divided and spread across two transmit slots. This is done because fading might destroy a frame, but it is unlikely that it will destroy two frames in succession. As a result, not all bits from a speech frame are lost by one bad slot. Figure 8 shows how the data is interleaved when x, y, and z are three speech frames in succession. Interleaving The 159 bits from a speech frame are classified as class 1 and class 2 bits; data is placed into the interleaving array in such a way that class 2 bits are intermixed with class 1 bits. Class 2 bits are sequentially placed into the array and occupy the following numbered locations: Á Á ÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁ Á Á Á 0, 26, 93 78 through 130, 223 Control Signal Multiplexing 52, 156, 129 182, 208 through 259 Control signal information is added to the interleaved data. Control information includes · · · · Slow associated control channel (SACCH) Fast associated control channel (FACCH) Digital verification color code (DVCC) Synchronization word (SYNC) Figure 9 shows how all this control information is multiplexed. Figure 9. Control-Signal Multiplexing DVCC/SYNC Data FACCH Data 13 kbps 16.2 kbps S Combined Data Speech Data SACCH Data Slow associated control channel (SACCH) is a signaling channel in parallel with the speech path used for the transmission of control and supervisory messages between the base station and the mobile unit. SACCH messages are continuously mixed with the channel data; 12 bits are allocated for SACCH. Fast associated control channel (FACCH) is a signaling channel for the transmission of control and supervisory messages between the base station and the mobile unit. FACCH messages are not mixed with the user information bits; they replace the user information block whenever necessary. 20 Digital verification color code (DVCC) is an 8-bit code that is sent by the base station to the mobile unit and is used to generate coded digital verification color code (CDVCC). CDVCC is a 12-bit field that includes the 8-bit DVCC; CDVCC is sent in each slot from the base station to the mobile unit and vice versa. The CDVCC is used by the receiver to distinguish the current traffic channel from traffic cochannels. Synchronization word (SYNC) is a 14-symbol field that is used for slot synchronization, equalizer training, and time slot identification. Mobile Assisted Handoff Mobile Assisted Handoff (MAHO) is a new feature of IS-54 IS-54. The base station can command the mobile unit to perform signal quality measurements on the current forward channel and any other 12 forward channels. The mobile unit can measure two quantities: 1. 2. Received signal strength indicator (RSSI), which is a measure of the signal strength expressed in dB. Bit error rate (BER), which is an estimate of the bit error information obtained by measuring the correctness of the data stream at the input to the mobile unit's channel decoder. These channel quality measurements (RSSI and BER) are sent to the base station to assist it in handoff. This reduces the overhead on the base station. RSSI and BER are usually sent via SACCH, although they could be sent via FACCH during discontinuous transmission (DTX). DTX is a mode of operation in which a mobile unit transmitter autonomously switches between two transmitter power levels while the mobile unit is in the conversation state on an analog voice channel or a digital traffic channel. Burst Generator After the data has been compressed and error-protected, the bit stream is compressed (in time only) into a burst format. Burst timing offsets may be applied to facilitate dynamic time alignment. Figure 10 shows how the data is compressed and time-aligned to allow the data to be sent using one-third of the 48.6-kbps channel. Figure 10. Burst Generator 16.2 kbps Speech FACCH SACCH 48.6 kbps Burst Temporary Storage To RF Modulator 20 ms 6.67-ms Pulse Delay 29­44 Symbols End of Receive Burst 48.6 kbps Transmitter /4 DQPSK Modulator and RF Amplifier The 48.6-kbps data is now input to a differential quaternary phase-shift keying (DQPSK) modulator. This phase modulator groups two bits at a time to create a symbol. This results in four levels of modulation, as shown in Figure 11. Hence, the name quaternary. The term differential is used because symbols are transmitted as relative phase changes, rather than absolute phase values. 21 Figure 11. A 4-Level Modulator Groups Two Bits to Form a Symbol cosct (0,1) (­1,0) (1,0) sinct (0,­1) Figure 11 shows that for certain transitions, the origin will have to be crossed. This implies that the power envelope at the decoder will be 0 when the origin is crossed; this can have an undesired impact on the filters. To alleviate this, a /4 scheme is used. This is shown in Figure 12. The transitions in this scheme are either +/­45 degrees or +/­135 degrees, and the origin is never traversed in transition from one state to another. This results in eight points on the circle, as shown in Figure 12. Figure 12. /4 Differential Quaternary PSK Modulator States Q S2 S6 S5 S3 S1 I S7 S8 S4 Figure 13 shows how the input serial data is now presented as 2-bit parallel data and is supplied to the multipliers after digital-to-analog conversion. Since two digital-to-analog converters (DACs) are needed, they are sometimes referred to as dual DACs. Binary signals vary the phase-shifted signals via the multipliers. Filters limit the impulse response of the binary signals to ensure that the RF carrier occupies the allocated bandwidth. The two signals are then summed together to form the final phase-shifted carrier. The conversion from baseband to RF (that is, frequency translation of the modulated carrier) is typically carried in several stages in order to reach the 800-MHz range. 22 Figure 13. /4 DQPSK Modulator Q Yk D/A Multiplier cosct 90° Phase Shift 48.6 kbps + ~ Xk sinct I D/A Multiplier RF Amplifier The RF amplifier boosts the RF-modulated signal to output levels, as specified by the base station. Unlike analog transmission, which uses FM, the RF amplifier for DQPSK carrier must be linear. In FM, class C push-pull nonlinear amplifiers are used for amplification purposes. These nonlinear amplifiers are efficient (about 50%) in order to conserve power. However, nonlinear amplifiers cannot be used in DQPSK, because they would cause phase distortion. Linear amplifiers used for DQPSK are less efficient (30%). Figure 14 shows an RF amplifier. Figure 14. Linear RF Amplifiers Are Needed for IS-54 IS-54 Cellular Phone 600 mW Linear RF Amplifier 30% Efficient Receiver TR Switch While a duplexer is required for the analog section of the dual-mode phone, it is not required for the digital portion, because in this case the transmitter and the receiver do not operate simultaneously. A simple PN switch is enough to isolate the receiver from the transmitter, allowing the duplexer to be removed from the digital portion. Removing the duplexer has added benefits: when DQPSK signals are passed through a 23 duplexer, a phase distortion occurs because of group delay; in addition, there is some power loss, which, in turn, requires a higher-rated power amplifier. Hence, removing the duplexer reduces the rating on the power amplifier, which extends the battery life of the mobile unit. Receiver The receiver functions in the following order: 1. Amplifies the received radio signal 2. Superheterodynes the RF signal to a lower workable frequency range 3. Demodulates the signal 4. Equalizes or compensates to mitigate the effects of distortions introduced by the radio channel 5. Detects errors 6. Decodes the speech signal 7. Converts it back into analog form and eventually feeds it to a speaker The receiver consists of several functional components: · Receiver RF amplifier · Mixer section · Demodulator · Channel decoder · Speech decoder Receiver RF Amplifier This section of the receiver amplifies the low-level DQPSK RF carrier, which could be as weak as a few picowatts (116 dBm). The RF amplifier increases this weak RF signal to a workable range before feeding it to the mixer section. The receiver RF amplifier is a broadband RF amplifier, which has a variable gain controlled by an automatic gain controller (AGC). The AGC compensates for the large dynamic range of the received signal, which is approximately 70 dB. The AGC also reduces the gain of the sensitive RF amplifier so that as the input signal increases, no distortions due to overdriving the receiver occur. Figure 15 shows the RF portion of the receiver. Figure 15. RF Portion of Receiver Section of Dual-Mode Cellular Phone 48.6-kbps Burst RF Amplifier AGC DQPSK Demodulator Equalizer Mixer The frequency of the received carrier is in the range of 869­894 MHz. It is not cost-effective to directly demodulate this RF signal at this frequency range. Typically, the received signal is stepped down to a lower 24 frequency, called the intermediate frequency (IF), by mixing it with a local oscillator (refer to Figure 2). The oscillator source may be varied so that the IF is a constant frequency, which simplifies the IF amplifier design. Typically, a second mixer superheterodynes the first IF with another oscillator source to produce a much lower frequency than the first IF. A lower frequency enables the design and use of narrow-band filters. Demodulator A DQPSK demodulator extracts data from the IF signal. Typically, a local oscillator with a 90-degree phase-shifted signal is used. The demodulator determines which decision point the phase has moved to; it then determines which symbol is transmitted by calculating the difference between the current phase and