SPRS039C LC545 LC546 LC549 LC548 VC549 TMS320C541 TMS320LC541 TMS320C542 - Datasheet Archive

 

FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 D Advanced Multibus Architecture

 

TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 D Advanced Multibus Architecture With Three D D D D D D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Data Bus With a Bus Holder Feature Address Bus With a Bus Holder Feature ('548 and '549 Only) Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space ('548 and '549 Only) 192K × 16-Bit Maximum Addressable Memory Space (64K Words Program, 64K Words Data, and 64K Words I/O) On-Chip ROM with Some Configurable to Program/Data Memory Dual-Access On-Chip RAM Single-Access On-Chip RAM ('548/'549) Single-Instruction Repeat and Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better Program and Data Management Instructions With a 32-Bit Long Word Operand Instructions With Two- or Three-Operand Reads Arithmetic Instructions With Parallel Store and Parallel Load Conditional Store Instructions D Fast Return From Interrupt D On-Chip Peripherals D D D D D D D D ­ Software-Programmable Wait-State Generator and Programmable Bank Switching ­ On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source ­ Full-Duplex Serial Port to Support 8- or 16-Bit Transfers ('541, 'LC545 LC545, and 'LC546 LC546 Only) ­ Time-Division Multiplexed (TDM) Serial Port ('542, '543, '548, and '549 Only) ­ Buffered Serial Port (BSP) ('542, '543, 'LC545 LC545, 'LC546 LC546, '548, and '549 Only) ­ 8-Bit Parallel Host-Port Interface (HPI) ('542, 'LC545 LC545, '548, and '549) ­ One 16-Bit Timer ­ External-Input/Output (XIO) Off Control to Disable the External Data Bus, Address Bus and Control Signals Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic 25-ns Single-Cycle Fixed-Point Instruction Execution Time [40 MIPS] for 5-V Power Supply ('C541 and 'C542 Only) 20-ns and 25-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS and 40 MIPS) for 3.3-V Power Supply ('LC54x) 15-ns Single-Cycle Fixed-Point Instruction Execution Time (66 MIPS) for 3.3-V Power Supply ('LC54xA, '548, 'LC549 LC549) 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) for 3.3-V Power Supply ('LC548 LC548, 'LC549 LC549) 10-ns and 8.3-ns Single-Cycle Fixed-Point Instruction Execution Time (100 and 120 MIPS) for 3.3-V Power Supply (2.5-V Core) ('VC549 VC549) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 1 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 description The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (hereafter referred to as the '54x unless otherwise specified) are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors also provide an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction set, which is the basis of the operational flexibility and speed of these DSPs. Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the 'C54x, 'LC54x, and 'VC54x versions include the control mechanisms to manage interrupts, repeated operations, and function calls. Table 1 provides an overview of the '54x generation of DSPs. The table shows significant features of each device including the capacity of on-chip RAM and ROM memories, the peripherals, the execution time of one machine cycle, and the type of package with its total pin count. Table 1. Characteristics of the '54x Processors DSP TYPE NOMINAL VOLTAGE (V) ON-CHIP MEMORY PERIPHERALS RAM (Word) ROM (Word) SERIAL PORT TMS320C541 TMS320C541 5.0 5K TMS320LC541 TMS320LC541 3.3 5K 28K 28K TMS320LC541Bh 3.3 5K 28K TMS320C542 TMS320C542 5.0 10K 2K TMS320LC542 TMS320LC542 3.3 10K 2K TMS320LC543 TMS320LC543 3.3 10K 2K 48K# TMS320LC545 TMS320LC545 3.3 6K TMS320LC545Ah 3.3 6K 48K# 48K# CYCLE TIME (ns) PACKAGE TYPE TIMER HPI 2§ 2§ 1 No 25 100-pin TQFP 1 No 20/25 100-pin TQFP 2§ 2¶ 1 No 20/25 100-pin TQFP 1 Yes 25 144-pin TQFP 2¶ 2¶ 1 Yes 20/25 128-pin TQFP/144-pin TQFP 1 No 20/25 100-pin TQFP 2|| 2|| 1 Yes 20/25 128-pin TQFP 1 Yes 15/20/25 128-pin TQFP 2|| 2|| 1 Yes 15/20/25 128-pin TQFP 1 No 20/25 100-pin TQFP 1 No 15/20/25 100-pin TQFP 100-pin TQFP TMS320LC545Bh 3.3 6K TMS320LC546 TMS320LC546 3.3 6K TMS320LC546Ah 3.3 6K 48K# 48K# 2|| 2|| TMS320LC546Bh 3.3 6K 48K# 1 No 15/20/25 TMS320LC548h 3.3 32K 2K 3k 1 Yes 12.5/15/20 144-pin TQFP/144-pin BGA TMS320LC549h 3.3 32K 16K 3k 1 Yes 12.5/15 144-pin TQFP/144-pin BGA TMS320VC549h 3.3 (2.5 core) 32K 16K 3k 1 Yes 8.3/10/12.5 144-pin TQFP/144-pin BGA Legend: TQFP = Thin Quad Flatpack BGA = MicroStar BGATM (Ball Grid Array) The dual-access RAM (single access RAM on '548 and '549 devices) can be configured as data memory or program/data memory. For 'C541/ C541/'LC541 LC541, 8K words of ROM can be configured as program memory or program/data memory. § Two standard (general-purpose) serial ports ¶ One TDM and one BSP # For 'LC545/ LC545/'LC546 LC546, 16K words of ROM can be configured as program memory or program/data memory. || One standard and one BSP k One TDM and two BSPs h Refer to separate data sheet for electrical specifications. MicroStar BGA is a trademark of Texas Instruments Incorporated. 2 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 D13 D12 D11 D10 D9 D8 D7 D6 DV DD 84 82 80 77 76 78 D15 D14 86 79 DVDD VSS VSS CVDD 90 81 A0 91 83 A2 A1 93 85 A3 94 87 A4 95 88 A5 96 89 A7 A6 98 92 A8 99 97 A9 100 TMS320C541 TMS320C541, TMS320LC541 TMS320LC541 PZ PACKAGE (TOP VIEW) VSS A10 A11 1 75 2 74 3 73 D5 D4 D3 A12 A13 4 72 D2 5 71 A14 6 70 D1 D0 A15 7 69 CVDD 8 68 RS X2/CLKIN VSS CLKMD3 CLKMD2 CLKMD1 50 49 EMU0 TOUT CNT INT3 CV DD VSS 40 48 51 47 25 46 52 INT2 53 24 45 54 23 44 22 NMI IAQ HOLD BIO MP/MC INT0 INT1 55 43 56 21 42 20 HOLDA IACK TDO EMU1/OFF 41 57 DX0 DX1 19 39 58 38 18 FSX1 TDI IOSTRB MSC XF DVDD VSS 59 37 TRST 17 FSX0 60 36 16 35 TCK R/W MSTRB 34 61 33 15 CLKX0 CLKX1 VSS CV DD TMS IS 32 62 31 VSS 14 30 CVDD 63 DR0 DR1 64 13 FSR1 12 PS DS 29 READY FSR0 CLKOUT VSS 28 65 CLKR1 11 27 X1 66 26 67 10 VSS CLKR0 9 VSS CVDD DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. The '54x signal descriptions table lists each terminal name, function, and operating mode(s) for the TMS320C541PZ/TMS320LC541PZ TMS320C541PZ/TMS320LC541PZ (100-pin TQFP packages). For the 'C541/ C541/'LC541 LC541 (100-pin packages), no letter in front of CLKRn, FSRn, DRn, CLKXn, FSXn, and DXn pin names denotes standard serial port (where n = 0 or 1 port). POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 3 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 109 111 110 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 74 36 73 VSS VSS NC VSS DVDD D5 D4 D3 D2 D1 D0 RS X2 / CLKIN X1 HD3 CLKOUT VSS HPIENA CVDD VSS TMS TCK TRST TDI TDO EMU1 / OFF EMU0 TOUT HD2 CNT CLKMD3 CLKMD2 CLKMD1 VSS DVDD NC VSS 72 75 35 71 76 34 70 77 33 69 78 32 68 79 31 67 80 30 66 81 29 65 82 28 64 83 27 63 84 26 62 85 25 61 86 24 60 87 23 59 88 22 58 89 21 57 90 20 56 91 19 55 92 18 54 93 17 53 94 16 52 95 15 51 96 14 50 97 13 49 98 12 48 99 11 47 100 10 46 101 9 45 102 8 44 103 7 43 104 6 42 105 5 41 106 4 40 3 39 107 38 108 2 37 1 NC HCNTL0 VSS BCLKR TCLKR BFSR TFSR / TADD BDR HCNTL1 TDR BCLKX TCLKX VSS HINT CVDD BFSX TFSX / TFRM HRDY DV DD V SS HD0 BDX TDX IACK HBIL NMI INT0 INT1 INT2 INT3 CVDD HD1 VSS NC VSS VSS NC VSS DVDD A10 HD7 A11 A12 A13 A14 A15 CVDD HAS VSS VSS CVDD HCS HR / W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP / MC DVDD VSS NC VSS 143 144 VSS NC CV DD A9 A8 A7 A6 A5 A4 HD6 A3 A2 A1 A0 DVDD HDS2 VSS HDS1 VSS CVDD HD5 D15 D14 D13 HD4 D12 D11 D10 D9 D8 D7 D6 DV DD VSS NC VSS TMS320C542/TMS320LC542 TMS320C542/TMS320LC542 PGE PACKAGE (TOP VIEW) NC = No connection DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. The '54x signal descriptions table lists each terminal name, function, and operating mode(s) for the TMS320C542PGE/ TMS320C542PGE/'LC542PGE LC542PGE (144-pin TQFP packages). For the 'C542/ C542/'LC542 LC542 (144-pin TQFP packages), the letter B in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes buffered serial port (BSP). The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes time-division multiplexed (TDM) serial port. 4 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 CVDD A9 A8 A7 A6 A5 A4 HD6 A3 A2 A1 A0 DV DD HDS2 VSS HDS1 VSS CVDD HD5 D15 D14 D13 HD4 D12 D11 D10 D9 D8 D7 D6 DVDD VSS TMS320LC542 TMS320LC542 PBK PACKAGE ( TOP VIEW ) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 VSS DVDD A10 HD7 A11 A12 A13 A14 A15 CVDD HAS VSS VSS CVDD HCS HR / W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP / MC DVDD VSS 1 96 2 95 3 94 4 93 5 92 6 91 7 90 8 89 9 88 10 87 11 86 12 85 13 84 14 83 15 82 16 81 17 80 18 79 19 78 20 77 21 76 22 75 23 74 24 73 25 72 26 71 27 70 28 69 29 68 30 67 31 66 65 32 VSS DVDD D5 D4 D3 D2 D1 D0 RS X2 / CLKIN X1 HD3 CLKOUT VSS HPIENA CVDD VSS TMS TCK TRST TDI TDO EMU1 / OFF EMU0 TOUT HD2 CNT CLKMD3 CLKMD2 CLKMD1 VSS DVDD HCNTL0 V SS BCLKR TCLKR BFSR TFSR / TADD BDR HCNTL1 TDR BCLKX TCLKX V SS HINT CV DD BFSX TFSX / TFRM HRDY DV DD VSS HD0 BDX TDX IACK HBIL NMI INT0 INT1 INT2 INT3 CVDD HD1 VSS 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. The '54x signal descriptions table lists each terminal name, function, and operating mode(s) for the TMS320LC542PBK TMS320LC542PBK (128-pin TQFP package). For the 'LC542 LC542 (128-pin TQFP package), the letter B in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes buffered serial port (BSP). The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes time-division multiplexed (TDM) serial port. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 5 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 D13 D12 D11 D10 D9 D8 D7 D6 DV DD 84 82 80 77 76 78 D15 D14 86 79 DVDD V SS V SS CVDD 90 81 A0 91 83 A2 A1 93 85 A3 94 87 A4 95 88 A5 96 89 A7 A6 98 92 A8 99 97 A9 100 TMS320LC543 TMS320LC543 PZ PACKAGE (TOP VIEW) VSS A10 A11 1 75 2 74 3 73 D5 D4 D3 A12 A13 4 72 D2 5 71 A14 6 70 D1 D0 A15 7 69 CVDD 8 68 RS X2/CLKIN VSS 51 CLKMD3 CLKMD2 CLKMD1 50 40 EMU0 TOUT CNT INT3 CV DD V SS BFSX BCLKX TCLKX VSS CV DD 49 25 48 52 47 53 24 46 54 23 INT2 22 45 IAQ HOLD BIO MP/MC 44 55 NMI 56 21 INT0 INT1 20 HOLDA 43 TDO EMU1/OFF 42 57 IACK 19 41 58 BDX TDX 18 39 TDI IOSTRB MSC XF 38 59 TFSX TRST 17 DVDD VSS 60 37 16 36 TCK R/W MSTRB 35 61 34 15 33 TMS IS 32 62 31 VSS 14 30 CVDD 63 BDR TDR 64 13 TFSR 12 PS DS 29 READY BFSR CLKOUT VSS 28 65 TCLKR 11 27 X1 66 26 67 10 VSS BCLKR 9 VSS CVDD DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. The '54x signal descriptions table lists each terminal name, function, and operating mode(s) for the TMS320LC543PZ TMS320LC543PZ (100-pin TQFP package). For the 'LC543 LC543 (100-pin TQFP package), the letter B in front of CLKR, FSR, DR, CLKX, FSX, and DX denotes buffered serial port (BSP). The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX denotes time-division multiplexed (TDM) serial port. 6 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 CVDD A9 A8 A7 A6 A5 A4 HD6 A3 A2 A1 A0 DVDD HDS2 VSS HDS1 VSS CV DD HD5 D15 D14 D13 HD4 D12 D11 D10 D9 D8 D7 D6 DVDD VSS TMS320LC545 TMS320LC545 PBK PACKAGE ( TOP VIEW ) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 VSS DVDD A10 HD7 A11 A12 A13 A14 A15 CVDD HAS VSS VSS CVDD HCS HR / W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP / MC DVDD VSS 1 96 2 95 3 94 4 93 5 92 6 91 7 90 8 89 9 88 10 87 11 86 12 85 13 84 14 83 15 82 16 81 17 80 18 79 19 78 20 77 21 76 22 75 23 74 24 73 25 72 26 71 27 70 28 69 29 68 30 67 31 66 65 32 VSS DVDD D5 D4 D3 D2 D1 D0 RS X2 / CLKIN X1 HD3 CLKOUT VSS HPIENA CVDD VSS TMS TCK TRST TDI TDO EMU1 / OFF EMU0 TOUT HD2 CNT CLKMD3 CLKMD2 CLKMD1 VSS DVDD HCNTL0 VSS BCLKR CLKR BFSR FSR BDR HCNTL DR BCLKX CLKX VSS HINT CVDD BFSX FSX HRDY DVDD VSS HD0 BDX DX IACK HBIL NMI INT0 INT1 INT2 INT3 CVDD HD1 VSS 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. The '54x signal descriptions table lists each terminal name, function, and operating mode(s) for the for the TMS320LC545PBK TMS320LC545PBK (128-pin TQFP package). For the 'LC545 LC545 (128-pin TQFP package), the letter B in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes buffered serial port (BSP). No letter in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes standard serial port. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 7 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 D13 D12 D11 D10 D9 D8 D7 D6 DV DD 84 82 80 77 76 78 D15 D14 86 79 V DD V SS V SS CVDD 90 81 A0 91 83 A2 A1 93 85 A3 94 87 A4 95 88 A5 96 89 A7 A6 98 92 A8 99 97 A9 100 TMS320LC546 TMS320LC546 PZ PACKAGE (TOP VIEW) VSS A10 A11 1 75 2 74 3 73 D5 D4 D3 A12 A13 4 72 D2 5 71 A14 6 70 D1 D0 A15 7 69 CVDD 8 68 RS X2/CLKIN VSS 51 CLKMD3 CLKMD2 CLKMD1 50 40 EMU0 TOUT CNT INT3 CV DD V SS BFSX BCLKX CLKX VSS CV DD 49 25 48 52 47 53 24 46 54 23 INT2 22 45 IAQ HOLD BIO MP/MC 44 55 NMI 56 21 INT0 INT1 20 HOLDA 43 TDO EMU1/OFF 42 57 IACK 19 41 58 BDX DX 18 39 TDI IOSTRB MSC XF 38 59 FSX TRST 17 DVDD VSS 60 37 16 36 TCK R/W MSTRB 35 61 34 15 33 TMS IS 32 62 31 VSS 14 30 CVDD 63 FSR 64 13 BDR DR 12 PS DS 29 READY BFSR CLKOUT VSS 28 65 CLKR 11 27 X1 66 26 67 10 VSS BCLKR 9 VSS CVDD DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. The '54x signal descriptions table lists each terminal name, function, and operating mode(s) for the for the TMS320LC546PZ TMS320LC546PZ (100-pin TQFP package). For the 'LC546 LC546 (100-pin TQFP package), the letter B in front of CLKR, FSR, DR, FSX, and DX denotes buffered serial port (BSP). No letter in front of CLKR, FSR, DR, FSX, and DX denotes standard serial port. 8 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 109 111 110 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 75 35 74 36 73 A18 A17 VSS A16 D5 D4 D3 D2 D1 D0 RS X2 / CLKIN X1 HD3 CLKOUT VSS HPIENA CVDD VSS TMS TCK TRST TDI TDO EMU1 / OFF EMU0 TOUT HD2 TEST1 CLKMD3 CLKMD2 CLKMD1 VSS DVDD BDX1 BFSX1 VSS BCLKR1 HCNTL0 VSS BCLKR0 TCLKR BFSR0 TFSR / TADD BDR0 HCNTL1 TDR BCLKX0 TCLKX VSS HINT CVDD BFSX0 TFSX / TFRM HRDY DVDD VSS HD0 BDX0 TDX IACK HBIL NMI INT0 INT1 INT2 INT3 CVDD HD1 VSS BCLKX1 VSS 72 76 34 71 77 33 70 78 32 69 79 31 68 80 30 67 81 29 66 82 28 65 83 27 64 84 26 63 85 25 62 86 24 61 87 23 60 88 22 59 89 21 58 90 20 57 91 19 56 92 18 55 93 17 54 94 16 53 95 15 52 96 14 51 97 13 50 98 12 49 99 11 48 100 10 47 101 9 46 102 8 45 103 7 44 104 6 43 105 5 42 106 4 41 3 40 107 39 108 2 38 1 37 VSS A22 VSS DVDD A10 HD7 A11 A12 A13 A14 A15 CVDD HAS VSS VSS CVDD HCS HR / W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP / MC DVDD VSS BDR1 BFSR1 143 144 V SS A21 CV DD A9 A8 A7 A6 A5 A4 HD6 A3 A2 A1 A0 DVDD HDS2 V SS HDS1 V SS CVDD HD5 D15 D14 D13 HD4 D12 D11 D10 D9 D8 D7 D6 DVDD VSS A20 A19 TMS320LC548 TMS320LC548, TMS320LC549 TMS320LC549, and TMS320VC549 TMS320VC549 PGE PACKAGE (TOP VIEW) NC = No connection DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. The '54x signal descriptions table lists each terminal name, function, and operating mode(s) for the TMS320LC548PGE TMS320LC548PGE (144-pin TQFP package). For the 'LC548 LC548, 'LC549 LC549 and 'VC549 VC549 (144-pin TQFP package), the letter B in front of CLKRn, FSRn, DRn, CLKXn, FSXn, and DXn pin names denotes buffered serial port (BSP), where n = 0 or 1 port. The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes time-division multiplexed (TDM) serial port. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 9 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 TMS320LC548 TMS320LC548, TMS320LC549 TMS320LC549, TMS320VC549 TMS320VC549 GGU PACKAGE ( BOTTOM VIEW ) 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N The pin assignments table to follow lists each signal quadrant and BGA ball pin number for the TMS320LC548 TMS320LC548, TMS320LC549 TMS320LC549, and TMS320VC549 TMS320VC549 (144-pin BGA package). The '54x signal descriptions table lists each terminal name, function, and operating mode(s) for the TMS320LC548GGU TMS320LC548GGU, TMS320LC549GGU TMS320LC549GGU, and TMS320VC549GGU TMS320VC549GGU. 10 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 Pin Assignments for the TMS320LC548GGU TMS320LC548GGU, TMS320LC549GGU TMS320LC549GGU, and TMS320VC549GGU TMS320VC549GGU (144-Pin BGA Package) SIGNAL QUADRANT 1 BGA BALL # SIGNAL QUADRANT 2 BGA BALL # VSS A22 A1 BFSX1 N13 B1 BDX1 VSS DVDD C2 C1 DVDD VSS A10 D4 CLKMD1 HD7 D3 SIGNAL QUADRANT 3 BGA BALL # SIGNAL QUADRANT 4 BGA BALL # N1 A19 A13 M13 VSS BCLKR1 N2 A20 A12 L12 HCNTL0 M3 B11 L13 N3 K10 VSS BCLKR0 VSS DVDD K4 D6 D10 CLKMD2 K11 TCLKR L4 D7 C10 A11 A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10 A12 D1 TEST1 K13 TFSR/TADD N4 D9 A10 A13 E4 HD2 J10 BDR0 K5 D10 D9 A14 E3 TOUT J11 HCNTL1 L5 D11 C9 A15 E2 EMU0 J12 TDR M5 D12 B9 CVDD E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9 HAS F4 TDO H10 TCLKX K6 D13 D8 VSS VSS F3 TDI H11 L6 D14 C8 F2 TRST H12 VSS HINT M6 D15 B8 CVDD F1 TCK H13 CVDD N6 HD5 A8 HCS G2 TMS G12 BFSX0 M7 CVDD B7 HR/W G1 G13 TFSX/TFRM N7 READY G3 VSS CVDD G11 HRDY L7 VSS HDS1 C7 PS G4 HPIENA G10 DVDD K7 DS H1 F13 N8 VSS HDS2 A7 D7 IS H2 VSS CLKOUT F12 VSS HD0 A6 M8 DVDD B6 R/W H3 HD3 F11 BDX0 L8 A0 C6 MSTRB H4 X1 F10 TDX K8 A1 D6 IOSTRB J1 X2/CLKIN E13 IACK N9 A2 A5 MSC J2 RS E12 HBIL M9 A3 B5 XF J3 D0 E11 NMI L9 HD6 C5 HOLDA J4 D1 E10 INT0 K9 A4 D5 IAQ K1 D2 D13 INT1 N10 A5 A4 HOLD K2 D3 D12 INT2 M10 A6 B4 BIO K3 D4 D11 INT3 L10 A7 C4 MP/MC L1 D5 C13 CVDD N11 A8 A3 DVDD L2 A16 C12 HD1 M11 A9 B3 VSS BDR1 L3 C11 CVDD C3 B13 VSS BCLKX1 L11 M1 VSS A17 N12 A21 A2 BFSR1 M2 A18 B12 VSS M12 VSS B2 DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 11 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 '54x Signal Descriptions TERMINAL NAME TYPE DESCRIPTION DATA SIGNALS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (MSB) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Parallel port address bus A22 (MSB) through A0 (LSB). The sixteen LSBs (A15­A0) are multiplexed to address external data/program memory or I/O. A15­A0 are placed in the high-impedance state in the hold mode. A15­A0 also go into the high-impedance state when EMU1/OFF is low. The seven MSBs (A22 to A16) are used for extended program memory addressing ('548 and '549 only). On the '548 and '549 devices, the address bus have a feature called bus holder that eliminates passive components and the power dissipation associated with it. The bus holders keep the address bus at the previous logic level when the bus goes into a high-impedance state. The bus holders on the address bus are always enabled. (MSB) O/Z (LSB) I/O/Z Parallel port data bus D15 (MSB) through D0 (LSB). D15­D0 are multiplexed to transfer data between the core CPU and external data/program memory or I/O devices. D15­D0 are placed in the high-impedance state when not output or when RS or HOLD is asserted. D15­D0 also go into the high-impedance state when EMU1/OFF is low. The data bus has a feature called bus holder that eliminates passive components and the power dissipation associated with it. The bus holders keep the data bus at the previous logic level when the bus goes into a high-impedance state. These bus holders are enabled or disabled by the BH bit in the bank switching control register (BSCR). (LSB) INITIALIZATION, INTERRUPT AND RESET OPERATIONS IACK O/Z Interrupt acknowledge signal. IACK indicates the receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15­0. IACK also goes into the high-impedance state when EMU1/OFF is low. INT0 External user interrupt inputs. INT0­INT3 are prioritized and are maskable by the interrupt mask register and the INT1 I interrupt mode bit. INT0 ­INT3 can be polled and reset by the interrupt flag register. INT2 INT3 I = Input, O = Output, Z = High impedance 12 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 '54x Signal Descriptions (Continued) TERMINAL NAME TYPE DESCRIPTION INITIALIZATION, INTERRUPT AND RESET OPERATIONS (CONTINUED) NMI I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI is activated, the processor traps to the appropriate vector location. RS I Reset input. RS causes the DSP to terminate execution and forces the program counter to 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of the program memory. RS affects various registers and status bits. MP/MC I Microprocessor/microcomputer mode-select pin. If active-low at reset (microcomputer mode), MP/MC causes the internal program ROM to be mapped into the upper program memory space. In the microprocessor mode, off-chip memory and its corresponding addresses (instead of internal program ROM) are accessed by the DSP. CNT I I/O level select. For 5-V operation, all input and output voltage levels are TTL-compatible when CNT is pulled down to a low level. For 3-V operation with CMOS-compatible I/O interface levels, CNT is pulled to a high level. I Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC instruction, and all other instructions sample BIO during the read phase of the pipeline. O/Z External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by RSBX XF instruction or by loading the ST1 status register. XF is used for signaling other processors in multiprocessor configurations or as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset. DS PS IS O/Z Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating to a particular external space. Active period corresponds to valid address information. Placed into a high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state when EMU1/OFF is low. MSTRB O/Z Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the high-impedance state when OFF is low. I Data-ready input. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready-detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states. R/W O/Z Read/write signal. R/W indicates transfer direction during communication to an external device and is normally high (in read mode), unless asserted low when the DSP performs a write operation. Placed in the high-impedance state in hold mode, R/W also goes into the high-impedance state when EMU1/OFF is low. IOSTRB O/Z I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an I/O device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state when EMU1/OFF is low. I Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the '54x, these lines go into high-impedance state. HOLDA O/Z Hold acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and control lines are in a high-impedance state, allowing them to be available to the external circuitry. HOLDA also goes into the high-impedance state when EMU1/OFF is low. MSC O/Z Microstate complete signal. Goes low on CLKOUT falling at the start of the first software wait state. Remains low until one CLKOUT cycle before the last programmed software wait state. If connected to the READY line, MSC forces one external wait state after the last internal wait state has been completed. MSC also goes into the high-impedance state when EM1/OFF is low. MULTIPROCESSING SIGNALS BIO XF MEMORY CONTROL SIGNALS READY HOLD I = Input, O = Output, Z = High impedance POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 13 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 '54x Signal Descriptions (Continued) TERMINAL NAME TYPE DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) IAQ O/Z Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus and goes into the high-impedance state when EMU1/OFF is low. OSCILLATOR/TIMER SIGNALS CLKOUT O/Z Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the falling edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF is low. CLKMD1 CLKMD2 CLKMD3 I Clock mode external/internal input signals. CLKMD1, CLKMD2, and CLKMD3 allow you to select and configure different clock modes, such as crystal, external clock, and various PLL factors. Refer to PLL section for a detailed functional description of these pins. X2/CLKIN I Input pin to internal oscillator from the crystal. If the internal (crystal) oscillator is not being used, a clock can become input to the device using this pin. The internal machine cycle time is determined by the clock operating-mode pins (CLKMD1, CLKMD2 and CLKMD3). X1 O Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low. O/Z Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT-cycle wide. TOUT also goes into the high-impedance state when EMU1/OFF is low. I Receive clocks. External clock signal for clocking data from the data-receive (DR) pin into the buffered serial port receive shift registers (RSRs). Must be present during buffered serial port transfers. If the buffered serial port is not being used, BCLKR0 and BCLKR1 can be sampled as an input by way of IN0 bit of the SPC register. I/O/Z Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit (DX) pin. BCLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven by the device at 1/(CLKDV + 1) where CLKDV range is 0­31 CLKOUT frequency when MCM is set to 1. If the buffered serial port is not used, BCLKX can be sampled as an input by way of IN1 of the SPC register. BCLKX0 and BCLKX1 go into the high-impedance state when OFF is low. TOUT BUFFERED SERIAL PORT 0 AND BUFFERED SERIAL PORT 1 SIGNALS BCLKR0 BCLKR1 BCLKX0 BCLKX1 BDR0 BDR1 I BDX0 BDX1 O/Z Buffered serial-port-transmit output. Serial data is transmitted from the XSR by way of BDX. BDX0 and BDX1 are placed in the high-impedance state when not transmitting and when EMU1/OFF is low. I Frame synchronization pulse for receive input. The falling edge of the BFSR pulse initiates the data-receive process, beginning the clocking of the RSR. I/O/Z Frame synchronization pulse for transmit input/output. The falling edge of the BFSX pulse initiates the data-transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of BFSX is an input. BFSX0 and BFSX1 can be selected by software to be an output when TXM in the serial control register is set to 1. This pin goes into the high-impedance state when EMU1/OFF is low. BFSR0 BFSR1 BFSX0 BFSX1 Buffered serial-data-receive input. Serial data is received in the RSR by BDR0/BDR1. SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS CLKR0 CLKR1 CLKX0 CLKX1 DR0 DR1 I Receive clocks. External clock signal for clocking data from the data receive (DR) pin into the serial port receive shift register (RSR). Must be present during serial port transfers. If the serial port is not being used, CLKR0 and CLKR1 can be sampled as an input via IN0 bit of the SPC register. I/O/Z Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit (DX) pin. CLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven by the device at 1/4 CLKOUT frequency when MCM is set to 1. If the serial port is not used, CLKX can be sampled as an input via IN1 of the SPC register. CLKX0 and CLKX1 go into the high-impedance state when EMU1/OFF is low. I Serial-data-receive input. Serial data is received in the RSR by DR. I = Input, O = Output, Z = High impedance 14 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 '54x Signal Descriptions (Continued) TERMINAL NAME TYPE DESCRIPTION SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS (CONTINUED) DX0 DX1 FSR0 FSR1 FSX0 FSX1 O/Z Serial port transmit output. Serial data is transmitted from the XSR via DX. DX0 and DX1 are placed in the high-impedance state when not transmitting and when EMU1/OFF is low. I Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive process, beginning the clocking of the RSR. I/O/Z Frame synchronization pulse for transmit input/output. The falling edge of the FSX pulse initiates the data transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of FSX is an input. FSX0 and FSX1 can be selected by software to be an output when TXM in the serial control register is set to 1. This pin goes into the high-impedance state when EMU1/OFF is low. TDM SERIAL PORT SIGNALS TCLKR I TDM receive clock input TDR I TDM serial data-receive input TFSR/TADD I/O TDM receive frame synchronization or TDM address TCLKX I/O/Z TDM transmit clock TDX O/Z TDM serial data-transmit output TFSX/TFRM I/O/Z TDM transmit frame synchronization I/O/Z Parallel bidirectional data bus. HD0­HD7 are placed in the high-impedance state when not outputting data. The signals go into the high-impedance state when EMU1/OFF is low. These pins each have bus holders similar to those on the address/data bus, but which are always enabled. HOST-PORT INTERFACE SIGNALS HD0­HD7 HCNTL0 HCNTL1 I Control inputs HBIL I Byte-identification input HCS I Chip-select input HDS1 HDS2 I Data strobe inputs HAS I Address strobe input HR/W I Read/write input HRDY O/Z Ready output. This signal goes into the high-impedance state when EMU1/OFF is low. HINT O/Z Interrupt output. When the DSP is in reset, this signal is driven high. The signal goes into the high-impedance state when EMU1/OFF is low. I HPI module select input. This signal must be tied to a logic 1 state to have HPI selected. If this input is left open or connected to ground, the HPI module will not be selected, internal pullup for the HPI input pins are enabled, and the HPI data bus has keepers set. This input is provided with an internal pull-down resistor which is active only when RS is low. HPIENA is sampled when RS goes high and ignored until RS goes low again. Refer to the Electrical Characteristics section for the input current requirements for this pin. HPIENA SUPPLY PINS CVDD Supply DVDD Supply +VDD. CVDD is the dedicated power supply for the core CPU. +VDD. DVDD is the dedicated power supply for I/O pins. VSS Supply Ground. VSS is the dedicated power ground for the device. I = Input, O = Output, Z = High impedance POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 15 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 '54x Signal Descriptions (Continued) TERMINAL NAME TYPE DESCRIPTION IEEE1149 IEEE1149.1 TEST PINS TCK I IEEE standard 1149.1 test clock. Pin with internal pullup device. This is normally a free-running clock signal with a 50% duty cycle. The changes on the test-access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI I IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO O/Z IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when EMU1/OFF is low. TMS I IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. TRST I IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. EMU0 I/O/Z Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. I/O/Z Emulator interrupt 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following conditions apply: TRST = low, EMU0 = high EMU1/OFF = low EMU1/OFF DEVICE TEST PIN TEST1 I Test1 ­ Reserved for internal use only ('LC548 LC548, 'LC549 LC549, and 'VC549 VC549 only). This pin must not be connected (NC). I = Input, O = Output, Z = High impedance architecture The '54x DSPs use an advanced, modified Harvard architecture that maximizes processing power by maintaining three separate bus structures for data memory and one for program memory. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. For example, two read and one write operations can be performed in a single cycle. Instructions with parallel store and application-specific instructions fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the '54x include the control mechanisms to manage interrupts, repeated operations, and function calls. The functional block diagram includes the principal blocks and bus structure in the '54x devices. 16 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 functional block diagram of the '54x internal hardware Program Address Generation Logic (PAGEN) System Control Interface Data Address Generation Logic (DAGEN) ARAU0, ARAU1, AR0­AR7 ARP, BK, DP, SP PC, IPTR, RC, BRC, RSA, REA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PAB PB CAB CB DAB DB EAB EB EXP Encoder X D A Memory And External Interface Peripherals (Serial Ports, HPI, etc.) B MUX T Register T D A A Sign Ctr P C D T A B C A(40) Sign Ctr Multiplier (17 × 17) Sign Ctr B A C D S Sign Ctr Sign Ctr MUX 0 A Fractional B Barrel Shifter ALU(40) A M U B A B MUX Adder(40) ZERO B(40) D SAT ROUND Legend: A Accumulator A B Accumulator B C CB Data Bus D DB Data Bus E EB Data Bus M MAC Unit P PB Program Bus S Barrel Shifter T T Register U ALU POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 MUX S COMP TRN MSW/LSW Select E TC 17 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 central processing unit (CPU) The CPU of the '54x devices contains: D D D D D A 40-bit arithmetic logic unit (ALU) Two 40-bit accumulators A barrel shifter A 17 × 17-bit multiplier/adder A compare, select and store unit (CSSU) arithmetic logic unit (ALU) The '54x devices perform 2s-complement arithmetic using: a 40-bit arithmetic logic unit (ALU) and two 40-bit accumulators (ACCA and ACCB). The ALU also can perform Boolean operations. The ALU can function as two 16-bit ALUs and perform two 16-bit operations simultaneously when the C16 bit in status register 1 (ST1) is set. accumulators The accumulators, ACCA and ACCB, store the output from the ALU or the multiplier / adder block; the accumulators can also provide a second input to the ALU or the multiplier / adder. The accumulators are divided into three parts: D Guard bits (bits 32­39) D A high-order word (bits 16­31) D A low-order word (bits 0­15) Instructions are provided for storing the guard bits, the high- and the low-order accumulator words in data memory, and for manipulating 32-bit accumulator words in or out of data memory. Also, any of the accumulators can be used as temporary storage for the other. barrel shifter The '54x 's barrel shifter has a 40-bit input connected to the accumulator, or data memory (CB, DB) and a 40-bit output connected to the ALU, or data memory (EB). The barrel shifter produces a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input data. The shift requirements are defined in the shift-count field (ASM) of ST1 or defined in the temporary register (TREG), which is designated as a shift-count register. This shifter and the exponent detector normalize the values in an accumulator in a single cycle. The least significant bits (LSBs) of the output are filled with 0s and the most significant bits (MSBs) can be either zero-filled or sign-extended, depending on the state of the sign-extended mode bit (SXM) of ST1. Additional shift capabilities enable the processor to perform numerical scaling, bit extraction, extended arithmetic, and overflow prevention operations. multiplier/ adder The multiplier / adder performs 17 × 17-bit 2s-complement multiplication with a 40-bit accumulation in a single instruction cycle. The multiplier / adder block consists of several elements: a multiplier, adder, signed / unsigned input control, fractional control, a zero detector, a rounder (2s-complement), overflow / saturation logic, and TREG. The multiplier has two inputs: one input is selected from the TREG, a data-memory operand, or an accumulator; the other is selected from the program memory, the data memory, an accumulator, or an immediate value. The fast on-chip multiplier allows the '54x to perform operations such as convolution, correlation, and filtering efficiently. In addition, the multiplier and ALU together execute multiply / accumulate (MAC) computations and ALU operations in parallel in a single instruction cycle. This function is used in determining the Euclid distance, and in implementing symmetrical and least mean square (LMS) filters, which are required for complex DSP algorithms. 18 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 compare, select and store unit (CSSU) The compare, select and store unit (CSSU) performs maximum comparisons between the accumulator's high and low word, allows the test / control (TC) flag bit of status register 0 (ST0) and the transition (TRN) register to keep their transition histories, and selects the larger word in the accumulator to be stored in data memory. The CSSU also accelerates Viterbi-type butterfly computation with optimized on-chip hardware. program control Program control is provided by several hardware and software mechanisms: D The program controller decodes instructions, manages the pipeline, stores the status of operations, and decodes conditional operations. Some of the hardware elements included in the program controller are the program counter, the status and control register, the stack, and the address-generation logic. D Some of the software mechanisms used for program control include branches, calls, conditional instructions, a repeat instruction, reset, and interrupts. power-down modes There are three power-down modes, activated by the IDLE1, IDLE2, and IDLE3 instructions. In these modes, the '54x devices enter a dormant state and dissipate considerably less power than in normal operation. The IDLE1 instruction is used to shut down the CPU. The IDLE2 instruction is used to shut down the CPU and on-chip peripherals. The IDLE3 instruction is used to shut down the '54x processor completely. This instruction stops the PLL circuitry as well as the CPU and peripherals. bus structure The '54x device architecture is built around eight major 16-bit buses: D One program-read bus (PB), which carries the instruction code and immediate operands from program memory D Two data-read buses (CB, DB) and one data-write bus (EB), which interconnect to various elements, such as the CPU, data-address generation logic, program-address generation logic, on-chip peripherals, and data memory ­ The CB and DB carry the operands read from data memory. ­ The EB carries the data to be written to memory. D Four address buses (PAB, CAB, DAB, and EAB), which carry the addresses needed for instruction execution The '54x devices have the capability to generate up to two data-memory addresses per cycle, which are stored into two auxiliary register arithmetic units (ARAU0 and ARAU1). The PB can carry data operands stored in program space (for instance, a coefficient table) to the multiplier for multiply/ accumulate operations or to a destination in data space for the data move instruction. This capability allows implementation of single-cycle three-operand instructions such as FIRS. The '54x devices also have an on-chip bidirectional bus for accessing on-chip peripherals; this bus is connected to DB and EB through the bus exchanger in the CPU interface. Accesses using this bus can require more than two cycles for reads and writes depending on the peripheral's structure. The '54x devices can have bus keepers connected to the data bus. Bus keepers ensure that the data bus does not float. When bus keepers are enabled, the data bus maintains its previous level. Setting bit 1 of the bank switching control register (BSCR) enables bus keepers and clearing bit 1 disables the bus keepers. A reset automatically disables the bus keepers. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 19 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 bus structure (continued) The '548 and '549 devices also have equivalent bus keepers connected to the address bus. The bus keepers ensure the address bus does not float when in high-impedance. For the '548 and '549 devices, the bus keepers are always enabled. Table 2 summarizes the buses used by various types of accesses. Table 2. Bus Usage for Accesses PROGRAM BUS ADDRESS BUS ACCESS TYPE PAB Program read Program write CAB DAB EAB PB DATA BUS CB DB Data single read Data long (32-bit) read (lw) (hw) (lw) Data single write Data read/data write Dual read/coefficient read Peripheral read (hw) Data dual read EB Peripheral write Legend: hw = high 16-bit word lw = low 16-bit word memory The total memory address range for the host of '54x devices is 192K 16-bit words. The '548 and '549 devices have 8M-word program memory. The memory space is divided into three specific memory segments: 64K-word program, 64K-word data, and 64K-word I / O. The program memory space contains the instructions to be executed as well as tables used in execution. The data memory space stores data used by the instructions. The I / O memory space interfaces to external memory-mapped peripherals and can also serve as extra data storage space. The parallel nature of the architecture of these DSPs allows them to perform four concurrent memory operations in any given machine cycle: fetching an instruction, reading two operands, and writing an operand. The four parallel buses are the program-read bus (PB), the data-write bus (EB) and the two data-read buses (CB and DB). Each bus accesses different memory spaces for different aspects of the DSP's operation. Additionally, this architecture allows dual-operand reads, 32-bit-long word accesses, and a single read with a parallel store. The '54x DSPs include on-chip memory to aid in system performance and integration. on-chip ROM The 'C541 and 'LC541 LC541 feature a 28K-word × 16-bit on-chip maskable ROM. 8K words of the 'C541 and 'LC541 LC541 ROM can be mapped into program and data memory space if the data ROM (DROM) bit in the processor mode status (PMST) register is set. This allows an instruction to use data stored in the ROM as an operand. The 'LC545/ LC545/'LC546 LC546 all feature a 48K-word × 16-bit on-chip maskable ROM. 16K words of the ROM on these devices can be mapped into program and data memory space if the DROM bit in the PMST register is set. The 'C542/ C542/'LC542/ LC542/'LC543 LC543 / 'LC548 LC548 all feature 2K-word × 16-bit on-chip ROM. The 'LC549 LC549 and 'VC549 VC549 feature 16K-word x 16-bit on-chip ROM. 20 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 on-chip ROM (continued) Customers can arrange to have the ROM of the '54x programmed with contents unique to any particular application. on-chip dual-access RAM (DARAM) The '541 devices have a 5K-word × 16-bit on-chip DARAM (5 blocks of 1K-word each). The '542 and '543 devices have a 10K-word × 16-bit on-chip DARAM (5 blocks of 2K-word each). The '545 and '546 devices have a 6K-word × 16-bit on-chip DARAM (3 blocks of 2K-word each). The '548 and '549 devices have a 8K-word × 16-bit on-chip DARAM (4 blocks of 2K-word each). Each of these RAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory space. DARAM can be mapped into program / data memory space by setting the OVLY bit in the PMST register. on-chip single-access RAM (SARAM) The '548 and '549 devices have a 24K word × 16 bit on-chip SARAM (three blocks of 8K words each). Each of these SARAM blocks is a single-access memory. This memory is intended primarily to store data values; however, it can be used to store program as well. At reset, the SARAM is mapped into data memory space (2000h­7FFFh). SARAM can be mapped into program / data memory space by setting the OVLY bit in the PMST register. on-chip memory security The '54x devices have a maskable option to protect the contents of on-chip memories. When the related bit is set, no externally originating instruction can access the on-chip memory spaces. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 21 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 memory (continued) Program Hex 0000 Program Hex 0000 Reserved (OVLY = 1) or External (OVLY = 0) Reserved (OVLY = 1) or External (OVLY = 0) 007F 0080 007F 0080 On-Chip DARAM (OVLY = 1) or External (OVLY = 0) On-Chip DARAM (OVLY = 1) or External (OVLY = 0) 13FF 1400 External 8FFF 9000 On-Chip ROM (28K Words) FF7F FF80 FF7F FF80 Interrupts and Reserved (External) FFFF Interrupts and Reserved (On-Chip) FFFF MP / MC = 1 (Microprocessor Mode) 005F 0060 Data Memory-Mapped Registers Scratch-Pad RAM 007F 0080 On-Chip DARAM (5K Words) 13FF 1400 External 13FF 1400 External Hex 0000 DFFF E000 FEFF FF00 FFFF On-Chip ROM (DROM = 1) or External (DROM = 0) Reserved (DROM = 1) or External (DROM = 0) MP / MC = 0 (Microcomputer Mode) Figure 1. Memory Map ('541 only) Hex 0000 Program Hex 0000 Reserved (OVLY=1) or External (OVLY=0) Reserved (OVLY=1) or External (OVLY=0) 007F 0080 007F 0080 EFFF F000 F7FF F800 FF7F FF80 Interrupts and Reserved (External) FFFF MP / MC = 1 (Microprocessor Mode) Scratch-Pad RAM On-Chip DARAM (10K Words) 27FF 2800 Reserved External On-Chip ROM (2K Words) Interrupts and Reserved (On-Chip) MP / MC = 0 (Microcomputer Mode) Figure 2. Memory Map ('542 and '543 only) POST OFFICE BOX 1443 Data Memory-Mapped Registers 007F 0080 External External 22 005F 0060 27FF 2800 27FF 2800 FFFF Hex 0000 On-Chip DARAM (OVLY=1) or External (OVLY=0) On-Chip DARAM (OVLY=1) or External (OVLY=0) FF7F FF80 Program · HOUSTON, TEXAS 77251­1443 FFFF TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 memory (continued) Hex 0000 Program Hex 0000 Reserved (OVLY = 1) or External (OVLY = 0) Reserved (OVLY = 1) or External (OVLY = 0) 007F 0080 Program 007F 0080 On-Chip DARAM (OVLY = 1) or External (OVLY = 0) On-Chip DARAM (OVLY = 1) or External (OVLY = 0) 17FF 1800 17FF 1800 External 3FFF 4000 FFFF Interrupts and Reserved (External) MP / MC = 1 (Microprocessor Mode) FF7F FF80 FFFF 005F 0060 Data Memory-Mapped Registers Scratch-Pad RAM 007F 0080 On-Chip DARAM (6K Words) 17FF 1800 External External On-Chip ROM (48K Words) FF7F FF80 Hex 0000 Interrupts and Reserved (On-Chip) BFFF C000 FEFF FF00 FFFF On-Chip ROM (DROM = 1) or External (DROM = 0) Reserved (DROM = 1) or External (DROM = 0) MP / MC = 0 (Microcomputer Mode) Figure 3. Memory Map ('545 and '546 only) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 23 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 memory (continued) Program Hex 0000 Reserved (OVLY = 1) or External (OVLY = 0) 007F 0080 On-Chip DARAM (OVLY = 1) or External (OVLY = 0) 1FFF 2000 On-Chip SARAM (OVLY = 1) or External (OVLY = 0) 7FFF 8000 Hex 0000 007F 0080 Program Reserved (OVLY = 1) or External (OVLY = 0) On-Chip DARAM (OVLY = 1) or External (OVLY = 0) 1FFF 2000 On-Chip SARAM (OVLY = 1) or External (OVLY = 0) 7FFF 8000 Hex 0000 005F 0060 Data Memory-Mapped Registers Scratch-Pad RAM 007F 0080 On-Chip DARAM (8K Words) 1FFF 2000 On-Chip SARAM (24K Words) 7FFF 8000 External External EFFF F000 Reserved F7FF F800 FF7F FF80 FFFF Interrupts and Reserved (External) MP / MC = 1 (Microprocessor Mode) FF7F FF80 FFFF External On-Chip ROM (2K Words) Interrupts and Reserved (On-Chip) FFFF MP / MC = 0 (Microcomputer Mode) Figure 4. Memory Map ('548 only) (In the case of a 64K Program Word Address Reach) 24 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 memory (continued) Program Hex 0000 Hex 0000 Reserved (OVLY = 1) or External (OVLY = 0) 007F 0080 007F 0080 On-Chip DARAM (OVLY = 1) or External (OVLY = 0) 1FFF 2000 7FFF 8000 Memory-Mapped Registers 005F 0060 Scratch-Pad RAM 007F 0080 On-Chip DARAM (8K Words) 1FFF 2000 On-Chip SARAM (OVLY = 1) or External (OVLY = 0) 7FFF 8000 Data Hex 0000 On-Chip DARAM (OVLY = 1) or External (OVLY = 0) 1FFF 2000 On-Chip SARAM (OVLY = 1) or External (OVLY = 0) Program Reserved (OVLY = 1) or External (OVLY = 0) On-Chip SARAM (24K Words) 7FFF 8000 External External BFFF C000 BFFF C000 External On-Chip ROM (DROM = 1) or External (DROM = 0) On-Chip ROM (16K Words) FF7F FF80 FFFF FEFF FF00 Interrupts and Reserved (External) FEFF FF00 Interrupts and Reserved (On-Chip) FFFF Reserved (DROM = 1) or External (DROM = 0) FFFF MP / MC = 0 (Microcomputer Mode) MP / MC = 1 (Microprocessor Mode) Figure 5. Memory Map ('549 only) xx 0000 01 0000 02 0000 7F 0000 Page 0 Page 1 Page 2 Page 127 32K Words 32K Words 32K Words 32K Words xx 7FFF 01 FFFF 02 FFFF 01 8000 00 8000 7F FFFF 02 8000 7F 8000 Page 0 Page 2 Page 127 32K Words 00 FFFF Page 1 32K Words 32K Words 32K Words 01 FFFF 02 FFFF 7F FFFF XPC = 0 XPC = 1 XPC = 2 XPC = 127 See Figure 4 and Figure 5 for more information about this on-chip memory region. These pages available when OVLY = 0 when on-chip RAM is not mapped in program space or data space. When OVLY = 1 the first 32K words are all on page 0 when on-chip RAM is mapped in program space or data space. NOTE A: When the on-chip RAM is enabled in program space, all accesses to the region xx 0000 ­ xx 7FFF, regardless of page number, are mapped to the on-chip RAM at 00 0000 ­ 00 7FFF. Figure 6. Extended Program Memory ('548 and '549 only) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 25 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 program memory The external program memory space on the '54x devices addresses up to 64K 16-bit words. Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: D Higher performance because no wait states are required D Lower cost than external memory D Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space. program memory address map The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft - meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction, and either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine without the overhead. At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. For example: STM #05800h,PMST ;Remapped vectors to start at 5800h. This example moves the interrupt vectors to program space at address 05800h. Any subsequent interrupt (except for a device reset) fetches its interrupt vector from that new location. For example, if, after loading the IPTR, an INT2 occurs, the interrupt service routine vector is fetched from location 5848h in program space as opposed to location FFC8h. This feature facilitates moving the desired vectors out of the boot ROM and then removing the ROM from the memory map. Once the system code is booted into the system from the boot-loader code resident in ROM, the application reloads the IPTR with a value pointing to the new vectors. In the previous example, the STM instruction is used to modify the PMST. Note that the STM instruction modifies not only the IPTR but other status / control bits in the PMST register. NOTE: The hardware reset (RS) vector cannot be remapped, because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space. In addition, for the '54x, 128 words are reserved in the on-chip ROM for device-testing purposes. Application code written to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h­FF7Fh in program space. extended program memory ('548 and '549 only) The '548 and '549 devices use a paged extended memory scheme in program space to allow access of up to 8M of program memory. This extended program memory is organized into 128 pages (0­127), each 64K in length. To implement the extended program memory scheme, the '548 and '549 device includes the following additional features: D Seven additional address lines (for a total of 23) D An extra memory-mapped register [program counter extension register (XPC)] 26 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 extended program memory ('548 and '549 only) (continued) D Six new instructions for addressing extended program memory space: ­ FB[D] - Far branch ­ FBACC[D] - Far branch to the location specified by the value in accumulator A or accumulator B ­ FCALA[D] - Far call to the location specified by the value in accumulator A or accumulator B ­ FCALL[D] - Far call ­ FRET[D] - Far return ­ FRETE[D] - Far return with interrupts enabled D Two '54x instructions are extended to use the 23 bits in the '548 and '549 devices: ­ READA - Read program memory addressed by accumulator A and store in data memory ­ WRITA - Write data to program memory addressed by accumulator A For more information on these six new instructions and the two extended instructions, refer to the instruction set summary table in this data sheet and to the TMS320C54x DSP Reference Set, Volume 2, Mnemonic Instruction Set, literature number SPRU172 SPRU172. And for more information on extended program memory, refer to the TMS320C54x DSP Reference Set, Volume 1, CPU and Peripherals, literature number SPRU131 SPRU131. data memory The data memory space on the '54x device addresses contains up to 64K of 16-bit words. The 'devices automatically access the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: D D D D Higher performance because no wait states are required Higher performance because of better flow within the pipeline of the CALU Lower cost than external memory Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space. bootloader A bootloader is available in the standard '54x on-chip ROM. This bootloader can be used to transfer user code from an external source to anywhere in the program memory at power up automatically. If MP / MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard '54x devices provide different ways to download the code to accommodate various system requirements: D D D D D Parallel from 8-bit or 16-bit-wide EPROM Parallel from I/O space 8-bit or 16-bit mode Serial boot from serial ports 8-bit or 16-bit mode Host-port interface boot ('542, '545, '548, and '549 devices only) Warm boot POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 27 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 bootloader (continued) The bootloader provided in the on-chip ROM of the '548 and '549 devices implements several enhanced features. These include the addition of BSP and TDM boot modes. To accommodate these new boot modes, the encoding of the boot-mode selection word has been modified. For a detailed description of bootloader functionality, refer to the TMS320C54x DSP Reference Set, Volume 4: Applications Guide (literature number SPRU173 SPRU173). For a detailed description of the enhanced bootloader functionality, refer to the TMS320x548/'549 Bootloader Technical Reference. on-chip peripherals All the '54x devices have the same CPU structure; however, they have different on-chip peripherals connected to their CPUs. The on-chip peripheral options provided are: D D D D D D Software-programmable wait-state generator Programmable bank switching Parallel I / O ports Serial ports (standard, TDM, and BSP) A hardware timer A clock generator [with a multiple phase-locked loop (PLL) on '549 devices] software-programmable wait-state generators Software-programmable wait-state generators can be used to extend external bus cycles up to seven machine cycles to interface with slower off-chip memory and I / O devices. The software wait-state generators are incorporated without any external hardware. For off-chip memory access, a number of wait states can be specified for every 32K-word block of program and data memory space, and for one 64K-word block of I / O space within the software wait-state (SWWSR) register. programmable bank-switching Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from program-memory space to data-memory space ('54x) or one program memory page to another program memory page ('548 and '549 only). This extra cycle allows memory devices to release the bus before other devices start driving the bus; thereby avoiding bus contention. The size of memory bank for the bank-switching is defined by the bank-switching control register (BSCR). parallel I / O ports Each '54x device has a total of 64K I / O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read / write operation through an I / O port. The devices can interface easily with external devices through the I / O ports while requiring minimal off-chip address-decoding circuits. host-port interface ('542, '545, '548, and '549 only) The host-port interface (HPI) is an 8-bit parallel port used to interface a host processor to the DSP device. Information is exchanged between the DSP device and the host processor through on-chip memory that is accessible by both the host and the DSP device. The DSP devices have access to the HPI control (HPIC) register and the host can address the HPI memory through the HPI address register (HPIA). HPI memory is a 2K-word DARAM block that resides at 1000h to 17FFh in data memory and can also be used as general-purpose on-chip data or program DARAM. 28 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 host-port interface ('542, '545, '548, and '549 only) (continued) Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin (HBIL) indicating whether the high or low byte is being transmitted. Two control pins, HCNTL1 and HCNTL0, control host access to the HPIA, HPI data (with an optional automatic address increment), or the HPIC. The host can interrupt the DSP device by writing to HPIC. The DSP device can interrupt the host with a dedicated HINT pin that the host can acknowledge and clear. The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). In SAM, the normal mode of operation, both the DSP device and the host can access HPI memory. In this mode, asynchronous host accesses are resynchronized internally and, in case of conflict, the host has access priority and the DSP device waits one cycle. The HOM capability allows the host to access HPI memory while the DSP device is in IDLE2 (all internal clocks stopped) or in reset mode. The host can therefore access the HPI RAM while the DSP device is in its optimal configuration in terms of power consumption. The HPI control register has two data strobes, HDS1 and HDS2, a read / write strobe HR / W, and an address strobe HAS, to enable a glueless interface to a variety of industry-standard host devices. The HPI is interfaced easily to hosts with multiplexed address /data bus, separate address and data buses, one data strobe and a read / write strobe, or two separate strobes for read and write. The HPI supports high-speed back-to-back accesses. D In the SAM, the HPI can handle one byte every five DSP device periods-that is, 64 MBps with a 40-MIPS 40-MIPS DSP, or 160 MBps with a 100-MIPS 100-MIPS DSP. The HPI is designed so that the host can take advantage of this high bandwidth and run at frequencies up to (f n) ÷ 5, where n is the number of host cycles for an external access and f is the DSP device frequency. D In HOM, the HPI supports high-speed back-to-back host accesses at 1 byte every 50 ns-that is, 160 MBps with a -40 or faster DSP. serial ports The '54x devices provide high-speed full-duplex serial ports that allow direct interface to other '54x devices, codecs, and other devices in a system. There is a standard serial port, a time-division-multiplexed (TDM) serial port, and a buffered serial port (BSP). The '549 devices provides a misalignment detection feature to that allows the device to detect when a word or words are lost in the serial data line. The general-purpose serial port utilizes two memory-mapped registers for data transfer: the data-transmit register (DXR) and the data-receive register (DRR). Both of these registers can be accessed in the same manner as any other memory location. The transmit and receive sections of the serial port each have associated clocks, frame-synchronization pulses, and serial-shift registers; and serial data can be transferred either in bytes or in 16-bit words. Serial port receive and transmit operations can generate their own maskable transmit and receive interrupts (XINT and RINT), allowing serial-port transfers to be managed through software. The '54x serial ports are double-buffered and fully static. The TDM port allows the device to communicate through time-division multiplexing with up to seven other '54x devices with TDM ports. Time-division multiplexing is the division of time intervals into a number of subintervals with each subinterval representing a prespecified communications channel. The TDM port serially transmits 16-bit words on a single data line ( TDAT ) and destination addresses on a single address line ( TADD). Each device can transmit data on a single channel and receive data from one or more of the eight channels, providing a simple and efficient interface for multiprocessing applications. A frame synchronization pulse occurs once every 128 clock cycles, corresponding to the transmission of one 16-bit word on each of the eight channels. Like the general-purpose serial port, the TDM port is double-buffered on both input and output data. The buffered serial port (BSP) consists of a full-duplex double-buffered serial-port interface and an auto-buffering unit (ABU). The serial port block of the BSP is an enhanced version of the standard serial port. The ABU allows the serial port to read / write directly to the '54x internal memory using a dedicated bus independent of the CPU. This results in minimal overhead for serial port transactions and faster data rates. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 29 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 serial ports (continued) When auto-buffering capability is disabled (standard mode), serial port transfers are performed under software control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and WRINT) provided by the serial port are sent to the CPU as transmit interrupt (XINT ) and receive interrupt (RINT ). When auto buffering is enabled, word transfers are done directly between the serial port and the '54x internal memory using ABU-embedded address generators. The ABU has its own set of circular-addressing registers with corresponding address-generation units. Memory for the buffers resides in 2K words of the '54x internal memory. The length and starting addresses of the buffers are user-programmable. A buffer-empty / buffer-full interrupt can be posted to the CPU. Buffering is easily halted by an auto-disabling capability. Auto-buffering capability can be enabled separately for transmit and receive sections. When auto buffering is disabled, operation is similar to that of the general-purpose serial port. The BSP allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a frame synchronization pulse for every packet. In continuous mode, the frame synchronization pulse occurs when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequencyand polarity-programmable. The BSP is fully static and operates at arbitrarily low clock frequencies. The maximum operating frequency for '54x devices up to 50 MIPs is CLKOUT. For higher-speed '54x devices, the maximum operating frequency is 50 MBps at 20 ns. buffer misalignment (BMINT) interrupt ('549 only) The BMINT interrupt is generated when a frame sync occurs and the ABU transmit or receive buffer pointer is not at the top of the buffer address. This is useful for detecting several potential error conditions on the serial interface, including extraneous and missed clocks and frame sync pulses. A BMINT interrupt, therefore, indicates that one or more words may have been lost on the serial interface. BMINT is useful for detecting buffer misalignment only when the buffer pointer(s) are initially loaded with the top of buffer address, and a frame of data contains the same number of words as the buffer length. These are the only conditions under which a frame sync occurring at a buffer address, other than the top of buffer, constitute an error condition. In cases where these conditions are met, a frame sync always occurs when the buffer pointer is at the top of buffer address, if the interface is functioning properly. If BMINT is enabled under conditions other than those stated above, interrupts may be generated under circumstances other than actual buffer misalignment. In these cases, BMINT should generally be masked in the IMR register so that the processor will ignore this interrupt. BMINT is available when operating auto-buffering mode with continuous transfers, the FIG bit cleared to 0, and external serial clocks or frames. The BSP0 and BSP1 BMINT bits in the IMR and IFR registers are bits 12 and 13, respectively, (bit 15 is the MSB), and their interrupt vector locations are 070h and 074h, respectively. 30 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 serial ports (continued) Table 3 provides a comparison of the serial ports available in the '54x devices. Table 3. Serial Port Configurations for the '54x NO. OF STANDARD SERIAL PORTS NO. OF BSPs (BSP ADDRESS RANGES) NO. OF TDM SERIAL PORTS TMS320C541 TMS320C541 TMS320LC541 TMS320LC541 2 ­ ­ TMS320C542 TMS320C542 TMS320LC542 TMS320LC542 ­ 1 (0800h ­ 0FFFh) 1 TMS320LC543 TMS320LC543 ­ 1 (0800h ­ 0FFFh) 1 TMS320LC545 TMS320LC545 TMS320LC545A TMS320LC545A 1 1 (0800h ­ 0FFFh) ­ TMS320LC546 TMS320LC546 TMS320LC546A TMS320LC546A 1 1 (0800h ­ 0FFFh) ­ TMS320LC548 TMS320LC548 ­ 2 (0800h ­ 0FFFh and 1800h ­ 1FFFh) 1 TMS320LC549 TMS320LC549 TMS320VC549 TMS320VC549 ­ 2 (0800h ­ 0FFFh and 1800h ­ 1FFFh) 1 DEVICE hardware timer The '54x devices feature a 16-bit timing circuit with a four-bit prescaler. The timer counter is decremented by one at every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits. clock generator The clock generator provides clocks to the '54x device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock input is then either divided by two (or by four on the '545A, '546A, '548, and '549) to generate clocks for the '54x device, or the PLL circuit can be used to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the '54x device. Two types of PLL are available: a hardware-programmable PLL and a software-programmable PLL. All '54x devices have the hardware-programmable PLL except the '545A, '546A, '548, and '549, which have the software-programmable PLL. On the hardware-programmable PLL, an external delay must be provided before the device is released from reset in order for the PLL to achieve lock. With the software-programmable PLL, a lock timer is provided to implement this delay automatically. Note that both the hardware- and the software-programmable PLLs require the device to be reset after power up to begin functioning properly. hardware-programmable PLL The '54x can use either the internal oscillator or an external frequency source for an input clock. The clock generation mode is determined by the CLKMD1, CLKMD2 and CLKMD3 clock mode pins except on the '545A, the '546A, the '548, and the '549 (see software-programmable PLL description below). Table 4 outlines the selection of the clock mode by these pins. Note that both the hardware- and the software-programmable PLLs require the device to be reset after power up to begin functioning properly. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 31 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 hardware-programmable PLL (continued) Table 4. Clock Mode Configurations MODE-SELECT PINS CLOCK MODE CLKMD1 CLKMD2 CLKMD3 OPTION 1 OPTION 2 0 0 0 PLL × 3 with external source PLL × 5 with external source 1 1 0 PLL × 2 with external source PLL × 4 with external source 1 0 0 PLL × 3, internal oscillator enabled PLL × 5, internal oscillator enabled 0 1 0 PLL × 1.5 with external source PLL × 4.5 with external source 0 0 1 0 1 1 Divide-by-two with external source Stop mode Divide-by-two with external source Stop mode 1 0 1 PLL × 1 with external source PLL × 1 with external source 1 1 1 Divide-by-two, internal oscillator enabled Divide-by-two, internal oscillator enabled Option: Option 1 or option 2 is selected when ordering the device. Stop mode: The function of the stop mode is equivalent to that of the power-down mode of IDLE3; however, the IDLE3 instruction is recommended rather than stop mode to realize full power saving, since IDLE3 stops clocks synchronously and can be exited with an interrupt. software-programmable PLL ('545A, '546A, '548, and '549) The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes: D PLL mode. The input clock (X2 / CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved using the PLL circuitry. D DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation. The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. The CLKMD register fields are shown in Figure 7 and described below. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 ­ CLKMD3 pins (see Table 6). Bit # 15­12 11 10­3 2 1 0 PLLMUL R/W PLLDIV R/W PLLCOUNT R/W PLLON/OFF R/W PLLNDIV PLLSTATUS R/W R R = read, W = write When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don't cares, and their contents are indeterminate. Figure 7. Clock Mode Control Register (CLKMD) 32 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 software-programmable PLL ('545A, '546A, '548, and '549) (continued) Bits 15 ­12 PLLMUL. PLL multiplier. Defines the frequency multiplier in conjunction with PLLDIV and PLLNDIV, as shown in Table 5. Bit 11 PLLDIV. PLL divider. Defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV, as shown in Table 5. 0 = an integer multiply factor is used. 1 = a non-integer multiply factor is used. Bits 10 ­3 PLLCOUNT. PLL counter value. Specifies the number of input clock cycles (in increments of 16 cycles) for the PLL lock timer to count before the PLL begins clocking the processor after the PLL is started. The PLL counter is a down-counter, which is driven by the input clock divided by 16; therefore, for every 16 input clocks, the PLL counter decrements by one. The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked, so that only valid clock signals are sent to the device. Bit 2 PLLON/OFF. PLL on/off. Enables or disables the PLL part of the clock generator in conjunction with the PLLNDIV bit. Note that PLLON/OFF and PLLNDIV can both force the PLL to run; when PLLON/OFF is high, the PLL runs independently of the state of PLLNDIV. PLLON/OFF 0 Off 1 0 On 0 1 On 1 Bit 1 PLLNDIV 0 PLL STATE 1 On PLLNDIV. PLL clock generator select. Determines whether the clock generator works in PLL mode or in divider (DIV) mode, thereby defining the frequency multiplier in conjunction with PLLMUL and PLLDIV. 0 = Divider mode is used 1 = PLL mode is used Bit 0 PLLSTATUS. PLL status. Indicates the mode in which the clock generator is operating. 0 = DIV mode 1 = PLL mode Table 5. PLL Multiplier Ratio as a Function of PLLNDIV, PLLDIV, and PLLMUL MULTIPLIER PLLNDIV PLLDIV PLLMUL 0 x 0 ­ 14 0.5 0 x 15 0.25 1 0 0 ­ 14 PLLMUL + 1 1 0 15 Reserved 1 1 0 or even (PLLMUL + 1) B 2 1 odd PLLMUL B 4 1 CLKOUT = CLKIN x multiplier POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 33 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 software-programmable PLL ('545A, '546A, '548, and '549) (continued) Immediately following reset, the clock mode is determined by the values of the three external pins: CLKMD1, CLKMD2, and CLKMD3. The modes corresponding to the CLKMD pins are shown in Table 6. Table 6. Clock Mode Settings at Reset CLKMD1 CLKMD2 CLKMD3 CLKMD REGISTER RESET VALUE CLOCK MODE 0 0 0 0000h Divide-by-two, with external source 0 0 1 1000h Divide-by-two, with external source 0 1 0 2000h Divide-by-two, with external source 1 0 0 4000h Divide-by-two, internal oscillator enabled 1 1 0 6000h Divide-by-two, with external source 1 1 1 7000h Divide-by-two, internal oscillator enabled 1 0 1 0007h PLL × 1 with external source 0 1 1 - Stop mode Reserved mode ('549 only). Do not use in normal operation. Following reset, the software-programmable PLL can be programmed to any configuration desired, as described above. Note that when the PLL × 1 with external source option (CLKMD[1­3]=101) is selected during reset, the internal PLL lock-count timer is not active; therefore, the system must delay releasing reset in order to allow for the PLL lock-time delay. Also, note that both the hardware- and the software-programmable PLLs require the device to be reset after power up to begin functioning properly. programming considerations when using the software-programmable PLL The software-programmable PLL offers many different options in startup configurations, operating modes, and power-saving features. Programming considerations and several software examples are presented here to illustrate the proper use of the software-programmable PLL at start-up, when switching between different clocking modes, and before and after IDLE1/IDLE2/IDLE3 instruction execution. use of the PLLCOUNT programmable lock timer During the lockup period, the PLL should not be used to clock the '54x. The PLLCOUNT programmable lock timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is achieved. The PLL lock timer is a counter, loaded from the PLLCOUNT field in the CLKMD register, that decrements from its preset value to 0. The timer can be preset to any value from 0 to 255, and its input clock is CLKIN divided by 16. The resulting lockup delay can therefore be set from 0 to 255 16 CLKIN cycles. The lock timer is activated when the clock generator operating mode is switched from DIV to PLL (see the section describing switching from DIV mode to PLL mode). During the lockup period, the clock generator continues to operate in DIV mode; after the PLL lock timer has decremented to zero, the PLL begins clocking the '54x. Accordingly, the value loaded into PLLCOUNT is chosen based on the following relationship: PLLCOUNT > Lockup Time / (16 tCLKIN) where tCLKIN is the input reference clock period and lockup time is the required PLL lockup time as shown in Figure 8. 34 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 use of the PLLCOUNT programmable lock timer (continued) 60 59 55 50 44 Lockup Time (µs) 45 40 35 35 '549 Only 30 20 29 23 25 22 17 16 24 16 19 15 10 5 0 2.5 10 20 30 40 50 60 70 80 100 CLKOUT Frequency (MHz) Figure 8. PLL Lockup Time Versus CLKOUT Frequency switching from DIV mode to PLL mode Several circumstances may require switching from DIV mode to PLL mode; however, note that if the PLL is not locked when switching from DIV mode to PLL mode, the PLL lockup time delay must be observed before the mode switch occurs to ensure that only proper clock signals are sent to the device. It is, therefore, important to know whether or not the PLL is locked when switching operating modes. The PLL is unlocked on power-up, after changing the PLLMUL or PLLDIV values, after turning off the PLL (PLLON/OFF = 0), or after loss of input reference clock. Once locked, the PLL remains locked even in DIV mode as long as the PLL had been previously locked and has not been turned off (PLLON/OFF stays 1), and the PLLMUL and PLLDIV values have not been changed since the PLL was locked. Switching from DIV mode to PLL mode (setting PLLNDIV to 1) activates the PLLCOUNT programmable lock timer (when PLLCOUNT is preloaded with a non-zero value), and this can be used to provide a convenient method for implementing the lockup time delay. The PLLCOUNT lock timer feature should be used in the situations described above, where the PLL is unlocked unless a reset delay is used to implement the lockup delay, or the PLL is not used. Switching from DIV mode to PLL mode is accomplished by loading the CLKMD register. The following procedure describes switching from DIV mode to PLL mode when the PLL is not locked. When performing this mode switch with the PLL already locked, the effect is the same as when switching from PLL to DIV mode, but in the reverse order. In this case, the delays of when the new clock mode takes effect are the same. When switching from DIV to PLL mode with the PLL unlocked, or when the mode change will result in unlocked operation, the PLLMUL[3­0], PLLDIV, and PLLNDIV bits are set to select the desired frequency multiplier as described in Table 5, and the PLLCOUNT[7­0] bits are set to select the required lockup time delay. Note that PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF can only be modified when in DIV mode. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 35 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 switching from DIV mode to PLL mode (continued) Once the PLLNDIV bit is set, the PLLCOUNT timer begins being decremented from its preset value. When the PLLCOUNT timer reaches zero, the switch to PLL mode takes effect after six CLKIN cycles plus 3.5 PLL cycles (CLKOUT frequency). When the switch to PLL mode is completed, the PLLSTATUS bit in the CLKMD register is read as 1. Note that during the PLL lockup period, the '54x continues operating in DIV mode. The following software example shows an instruction that can be used to switch from DIV mode to PLL with a CLKIN frequency of 13 MHz and PLLCOUNT = 41 (decimal). STM 3, #0010000101001111b, CLKMD switching clock mode from PLL to DIV When switching from PLL mode to DIV mode, the PLLCOUNT delay does not occur, and the switch between the two modes takes place after a short transition delay. The switch from PLL mode to DIV mode is also accomplished by loading the CLKMD register. The PLLNDIV bit is set to 0, selecting DIV mode, and the PLLMUL bits are set to select the desired frequency multiplier as shown in Table 5. The switch to DIV mode takes effect in 6 CLKIN cycles plus 3.5 PLL cycles (CLKOUT frequency) for all PLLMUL values except 1111b. With a PLLMUL value of 1111b, the switch to DIV mode takes effect in 12 CLKIN cycles plus 3.5 PLL cycles (CLKOUT frequency). When the switch to DIV mode is completed, the PLLSTATUS bit in the CLKMD register is read as 0. The following software example shows a code sequence that can be used to switch from PLL × 3 to divide-by-two mode. Note that the PLLSTATUS bit is polled to determine when the switch to DIV mode has taken effect, and then the STM instruction is used to turn off the PLL at this point. TstStatu: STM LDM AND BC STM #0b, CLKMD CLKMD, A #01b, A TstStatu, ANEQ #0b, CLKMD ;switch to DIV mode ;poll STATUS bit ;reset PLLON_OFF when STATUS ;is DIV mode switching mode from one PLL multiplier to another When switching from one PLL multiplier ratio to another is required, the clock generator must be switched from PLL mode to DIV mode before selecting the new multiplier ratio; switching directly from one PLL multiplier ratio to another is not supported. In order to switch from one PLL multiplier ratio to another, the following steps must be followed: 1. Set the PLLNDIV bit to 0, selecting DIV mode. 2. Poll the PLLSTATUS bit until a 0 is obtained, indicating that DIV mode is enabled and that PLLMUL, PLLDIV, and PLLCOUNT can be updated. 3. Modify the CLKMD register to set the PLLMUL[3­0], PLLDIV, and PLLNDIV bits to the desired frequency multiplier as defined in Table 5, and the PLLCOUNT[7­0] bits to the required lock-up time. When the PLLNDIV bit is set to one in step three, the PLLCOUNT timer begins decrementing from its preset value. Once the PLLCOUNT timer reaches zero, the new PLL mode takes effect after six CLKIN cycles plus 3.5 PLL cycles (CLKOUT frequency). 36 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C SPRS039C ­ FEBRUARY 1996 ­ REVISED DECEMBER 1999 switching mode from one PLL mult