SPRU159A TMS320C40 TMS320C44 XDS510 TMS320 SPRU063 SPRU075 SPRA031 SPRU035 - Datasheet Archive

 

Applications User's Guide 1999 Digital Signal Processing Solutions Printed in U.S.A., May 1999 SPRU159A TMS320C4x General Purpose

 

TMS320C4x GeneralPurpose Applications User's Guide 1999 Digital Signal Processing Solutions Printed in U.S.A., May 1999 SPRU159A SPRU159A TMS320C4x General Purpose Applications 1999 User's Guide TMS320C4x GeneralPurpose Applications User's Guide SPRU159A SPRU159A May 1999 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright © 1999, Texas Instruments Incorporated Preface Read This First About This Manual This user's guide serves as an applications reference book for the TMS320C40 TMS320C40 and TMS320C44 TMS320C44 digital signal processors (DSP). Throughout the book, all references to the TMS320C4x apply to both devices (exceptions are noted). Specifically, this book complements the TMS320C4x User's Guide by providing information to assist managers and hardware/software engineers in application development. It includes example code and hardware connections for various applications. The guide shows how to use the instruction set, the architecture, and the 'C4x interface. It presents examples for frequently used applications and discusses more involved examples and applications. It also defines the principles involved in many applications and gives the corresponding assembly language code for instructional purposes and for immediate use. Whenever the detailed explanation of the underlying theory is too extensive to be included in this manual, appropriate references are given for further information. How to Use This Manual The following table summarizes the information contained in this user's guide: If you are looking for information about: Turn to these chapters: Arithmetic Chapter 3, Logical and Arithmetic Operations Communication Ports Chapter 8, Using the Communication Ports Companding Chapter 6, Applications-Oriented Operations Development Support Chapter 10, Development Support and Part Order Information If you are looking for information about: Turn to these chapters: DMA Coprocessor Chapter 7, Programming the DMA Coprocessor FTTs Chapter 6, Applications-Oriented Operations Filters Chapter 6, Applications-Oriented Operations Ordering Parts Chapter 10, Development Support and Part Order Information Repeat Modes Chapter 2, Program Control Reset Chapter 1, Processor Initialization Stacks Chapter 2, Program Control Tips Chapter 5, Programming Tips Wait States Chapter 4, Memory Interfacing XDS510 XDS510 Emulator Chapter 11, XDS510 XDS510 Emulator Design Considerations Style and Symbol Conventions This document uses the following conventions: - Program listings, program examples, file names, and symbol names are shown in a special font. Examples use a bold version of the special font for emphasis. Here is a sample program listing segment: * LOOP1 RPTB CMPF MAX LDFLT B LOOP2 RPTB CMPF MIN LDFLT NEXT . . - iv MAX *AR0,R0 *AR0,R0 NEXT MIN *AR0+(1),R0 *­AR0(1),R0 ;Compare number to the maximum ;If greater, this is a new max ;Compare number to the minimum ;If smaller, this is new minimum Throughout this book MSB indicates the most significant bit and LSB indicates the least significant bit. MS indicates the most significant byte and LS indicates the least significant byte. Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. v Related Documentation From Texas Instruments The following books describe the TMS320 TMS320 floating-point devices and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477­8924. When ordering, please identify the book by its title and literature number. TMS320C4x User's Guide (literature number SPRU063 SPRU063) describes the 'C4x 32-bit floating-point processor, developed for digital signal processing as well as parallel processing applications. Covered are its architecture, internal register structure, instruction set, pipeline, specifications, and operation of its six DMA channels and six communication ports. TMS320C4x Parallel Processing Development System Technical Reference (literature number SPRU075 SPRU075) describes the TMS320C4x parallel processing system, a system with four C4xs with shared and distributed memory. Parallel Processing with the TMS320C4x (literature number SPRA031 SPRA031) describes parallel processing and how the 'C4x can be used in parallel processing. Also provides sample parallel processing applications. TMS320C3x/C4x Assembly Language Tools User's Guide (literature number SPRU035 SPRU035) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the 'C3x and 'C4x generations of devices. TMS320 TMS320 Floating-Point DSP Optimizing C Compiler User's Guide (literature number SPRU034 SPRU034) describes the TMS320 TMS320 floating-point C compiler. This C compiler accepts ANSI standard C source code and produces TMS320 TMS320 assembly language source code for the 'C3x and 'C4x generations of devices. TMS320C4x C Source Debugger User's Guide (literature number SPRU054 SPRU054) tells you how to invoke the 'C4x emulator and simulator versions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, command entry, code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionality. TMS320C4x Technical Brief (literature number SPRU076 SPRU076) gives a condensed overview of the 'C4x DSP and its development tools. It also lists TMS320C4x third parties. vi TMS320 TMS320 Family Development Support Reference Guide (literature number SPRU011 SPRU011) describes the '320 family of digital signal processors and the various products that support it. This includes code-generation tools (compilers, assemblers, linkers, etc.) and system integration and debug tools (simulators, emulators, evaluation modules, etc.). This book also lists related documentation, outlines seminars and the university program, and gives factory repair and exchange information. TMS320 TMS320 Third-Party Support Reference Guide (literature number SPRU052 SPRU052) alphabetically lists over 100 third parties that supply various products that serve the family of '320 digital signal processors-software and hardware development tools, speech recognition, image processing, noise cancellation, modems, etc. TMS320 TMS320 DSP Designer's Notebook: Volume 1 (literature number SPRT125 SPRT125) presents solutions to common design problems using 'C2x, 'C3x, 'C4x, 'C5x, and other TI DSPs. Related Articles and Books A wide variety of related documentation is available on digital signal processing. These references fall into one of the following application categories: - General-Purpose DSP Graphics/Imagery Speech/Voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development Support In the following list, references appear in alphabetical order according to author. The documents contain beneficial information regarding designs, operations, and applications for signal-processing systems; all of the documents provide additional references. Texas Instruments strongly suggests that you refer to these publications. General-Purpose DSP: 1) Antoniou, A., Digital Filters: Analysis and Design, New York, NY: McGraw-Hill Company, Inc., 1979. 2) Brigham, E.O., The Fast Fourier Transform, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1974. vii 3) Burrus, C.S., and T.W. Parks, DFT/FFT and Convolution Algorithms, New York, NY: John Wiley and Sons, Inc., 1984. 4) Chassaing, R., Horning, D.W., " Digital Signal Processing with Fixed and Floating-Point Processors." CoED, USA, Volume 1, Number 1, pages 1­4, March 1991. 5) Defatta, David J., Joseph G. Lucas, and William S. Hodgkiss, Digital Signal Processing: A System Design Approach, New York: John Wiley, 1988. 6) Erskine, C., and S. Magar, "Architecture and Applications of a SecondGeneration Digital Signal Processor." Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, USA, 1985. 7) Essig, D., C. Erskine, E. Caudel, and S. Magar, "A Second-Generation Digital Signal Processor." IEEE Journal of Solid-State Circuits, USA, Volume SC­21, Number 1, pages 86­91, February 1986. 8) Frantz, G., K. Lin, J. Reimer, and J. Bradley, "The Texas Instruments TMS320C25 TMS320C25 Digital Signal Microcomputer." IEEE Microelectronics, USA, Volume 6, Number 6, pages 10­28, December 1986. 9) Gass, W., R. Tarrant, T. Richard, B. Pawate, M. Gammel, P. Rajasekaran, R. Wiggins, and C. Covington, "Multiple Digital Signal Processor Environment for Intelligent Signal Processing." Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1246­1259, September 1987. 10) Gold, Bernard, and C.M. Rader, Digital Processing of Signals, New York, NY: McGraw-Hill Company, Inc., 1969. 11) Hamming, R.W., Digital Filters, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977. 12) IEEE ASSP DSP Committee (Editor), Programs for Digital Signal Processing, New York, NY: IEEE Press, 1979. 13) Jackson, Leland B., Digital Filters and Signal Processing, Hingham, MA: Kluwer Academic Publishers, 1986. 14) Jones, D.L., and T.W. Parks, A Digital Signal Processing Laboratory Using the TMS32010 TMS32010, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 15) Lim, Jae, and Alan V. Oppenheim, Advanced Topics in Signal Processing, Englewood Cliffs, NJ: Prentice- Hall, Inc., 1988. 16) Lin, K., G. Frantz, and R. Simar, Jr., "The TMS320 TMS320 Family of Digital Signal Processors." Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1143­1159, September 1987. viii 17) Lovrich, A., Reimer, J., "An Advanced Audio Signal Processor." Digest of Technical Papers for 1991 International Conference on Consumer Electronics, June 1991. 18) Magar, S., D. Essig, E. Caudel, S. Marshall and R. Peters, "An NMOS Digital Signal Processor with Multiprocessing Capability." Digest of IEEE International Solid-State Circuits Conference, USA, February 1985. 19) Morris, Robert L., Digital Signal Processing Software, Ottawa, Canada: Carleton University, 1983. 20) Oppenheim, Alan V. (Editor), Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. 21) Oppenheim, Alan V., and R.W. Schafer, Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975 and 1988. 22) Oppenheim, A.V., A.N. Willsky, and I.T. Young, Signals and Systems, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983. 23) Papamichalis, P.E., and C.S. Burrus, "Conversion of Digit-Reversed to BitReversed Order in FFT Algorithms." Proceedings of ICASSP 89, USA, pages 984­987, May 1989. 24) Papamichalis, P., and R. Simar, Jr., "The TMS320C30 TMS320C30 Floating-Point Digital Signal Processor." IEEE Micro Magazine, USA, pages 13­29, December 1988. 25) Parks, T.W., and C.S. Burrus, Digital Filter Design, New York, NY: John Wiley and Sons, Inc., 1987. 26) Peterson, C., Zervakis, M., Shehadeh, N., "Adaptive Filter Design and Implementation Using the TMS320C25 TMS320C25 Microprocessor." Computers in Education Journal, USA, Volume 3, Number 3, pages 12­16, July­September 1993. 27) Prado, J., and R. Alcantara, "A Fast Square-Rooting Algorithm Using a Digital Signal Processor." Proceedings of IEEE, USA, Volume 75, Number 2, pages 262­264, February 1987. 28) Rabiner, L.R. and B. Gold, Theory and Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975. 29) Simar, Jr., R., and A. Davis, "The Application of High-Level Languages to Single-Chip Digital Signal Processors." Proceedings of ICASSP 88, USA, Volume D, page 1678, April 1988. 30) Simar, Jr., R., T. Leigh, P. Koeppen, J. Leach, J. Potts, and D. Blalock, "A 40 MFLOPS Digital Signal Processor: the First Supercomputer on a Chip." Proceedings of ICASSP 87, USA, Catalog Number 87CH2396 87CH2396 ­0, Volume 1, pages 535­538, April 1987. ix 31) Simar, Jr., R., and J. Reimer, "The TMS320C25 TMS320C25: a 100 ns CMOS VLSI Digital Signal Processor." 1986 Workshop on Applications of Signal Processing to Audio and Acoustics, September 1986. 32) Texas Instruments, Digital Signal Processing Applications with the TMS320 TMS320 Family, 1986; Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 33) Treichler, J.R., C.R. Johnson, Jr., and M.G. Larimore, A Practical Guide to Adaptive Filter Design, New York, NY: John Wiley and Sons, Inc., 1987. Graphics/Imagery: 1) Andrews, H.C., and B.R. Hunt, Digital Image Restoration, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977. 2) Gonzales, Rafael C., and Paul Wintz, Digital Image Processing, Reading, MA: Addison-Wesley Publishing Company, Inc., 1977. 3) Papamichalis, P.E., "FFT Implementation on the TMS320C30 TMS320C30." Proceedings of ICASSP 88, USA, Volume D, page 1399, April 1988. 4) Pratt, William K., Digital Image Processing, New York, NY: John Wiley and Sons, 1978. 5) Reimer, J., and A. Lovrich, "Graphics with the TMS32020 TMS32020." WESCON/85 WESCON/85 Conference Record, USA, 1985. Speech/Voice: 1) DellaMorte, J., and P. Papamichalis, "Full-Duplex Real-Time Implementation of the FED-STD-1015 FED-STD-1015 LPC-10e Standard V.52 on the TMS320C25 TMS320C25." Proceedings of SPEECH TECH 89, pages 218­221, May 1989. 2) Frantz, G.A., and K.S. Lin, "A Low-Cost Speech System Using the TMS320C17 TMS320C17." Proceedings of SPEECH TECH '87, pages 25­29, April 1987. 3) Gray, A.H., and J.D. Markel, Linear Prediction of Speech, New York, NY: Springer-Verlag, 1976. 4) Jayant, N.S., and Peter Noll, Digital Coding of Waveforms, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984. 5) Papamichalis, Panos, Practical Approaches to Speech Coding, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 6) Papamichalis, P., and D. Lively, "Implementation of the DOD Standard LPC­10/52E 10/52E on the TMS320C25 TMS320C25." Proceedings of SPEECH TECH '87, pages 201­204, April 1987. 7) Pawate, B.I., and G.R. Doddington, "Implementation of a Hidden Markov Model-Based Layered Grammar Recognizer." Proceedings of ICASSP 89, USA, pages 801­ 804, May 1989. 8) Rabiner, L.R., and R.W. Schafer, Digital Processing of Speech Signals, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. x 9) Reimer, J.B. and K.S. Lin, "TMS320 TMS320 Digital Signal Processors in Speech Applications." Proceedings of SPEECH TECH '88, April 1988. 10) Reimer, J.B., M.L. McMahan, and W.W. Anderson, "Speech Recognition for a Low-Cost System Using a DSP." Digest of Technical Papers for 1987 International Conference on Consumer Electronics, June 1987. Control: 1) Ahmed, I., "16-Bit DSP Microcontroller Fits Motion Control System Application." PCIM, October 1988. 2) Ahmed, I., "Implementation of Self Tuning Regulators with TMS320 TMS320 Family of Digital Signal Processors." MOTORCON '88, pages 248­262, September 1988. 3) Ahmed, I., and S. Lindquist, "Digital Signal Processors: Simplifying HighPerformance Control." Machine Design, September 1987. 4) Ahmed, I., and S. Meshkat, "Using DSPs in Control." Control Engineering, February 1988. 5) Allen, C. and P. Pillay, "TMS320 TMS320 Design for Vector and Current Control of AC Motor Drives." Electronics Letters, UK, Volume 28, Number 23, pages 2188­2190, November 1992. 6) Bose, B.K., and P.M. Szczesny, "A Microcomputer-Based Control and Simulation of an Advanced IPM Synchronous Machine Drive System for Electric Vehicle Propulsion." Proceedings of IECON '87, Volume 1, pages 454­463, November 1987. 7) Hanselman, H., "LQG-Control of a Highly Resonant Disc Drive Head Positioning Actuator." IEEE Transactions on Industrial Electronics, USA, Volume 35, Number 1, pages 100­104, February 1988. 8) Jacquot, R., Modern Digital Control Systems, New York, NY: Marcel Dekker, Inc., 1981. 9) Katz, P., Digital Control Using Microprocessors, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1981. 10) Kuo, B.C., Digital Control Systems, New York, NY: Holt, Reinholt, and Winston, Inc., 1980. 11) Lovrich, A., G. Troullinos, and R. Chirayil, "An All-Digital Automatic Gain Control." Proceedings of ICASSP 88, USA, Volume D, page 1734, April 1988. 12) Matsui, N. and M. Shigyo, "Brushless DC Motor Control Without Position and Speed Sensors." IEEE Transactions on Industry Applications, USA, Volume 28, Number 1, Part 1, pages 120­127, January­February 1992. xi 13) Meshkat, S., and I. Ahmed, "Using DSPs in AC Induction Motor Drives." Control Engineering, February 1988. 14) Panahi, I. and R. Restle, "DSPs Redefine Motion Control." Motion Control Magazine, December 1993. 15) Phillips, C., and H. Nagle, Digital Control System Analysis and Design, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984. Multimedia: 1) Reimer, J., "DSP-Based Multimedia Solutions Lead Way Enhancing Audio Compression Performance." Dr. Dobbs Journal, December 1993. 2) Reimer, J., G. Benbassat, and W. Bonneau Jr., "Application Processors: Making PC Multimedia Happen." Silicon Valley PC Design Conference, July 1991. Military: 1) Papamichalis, P., and J. Reimer, "Implementation of the Data Encryption Standard Using the TMS32010 TMS32010." Digital Signal Processing Applications, 1986. Telecommunications: 1) Ahmed, I., and A. Lovrich, "Adaptive Line Enhancer Using the TMS320C25 TMS320C25." Conference Records of Northcon/86, USA, 14/3/1­10, September/October 1986. 2) Casale, S., R. Russo, and G. Bellina, "Optimal Architectural Solution Using DSP Processors for the Implementation of an ADPCM Transcoder." Proceedings of GLOBECOM '89, pages 1267­1273, November 1989. 3) Cole, C., A. Haoui, and P. Winship, "A High-Performance Digital Voice Echo Canceller on a SINGLE TMS32020 TMS32020." Proceedings of ICASSP 86, USA, Catalog Number 86CH2243 86CH2243­4, Volume 1, pages 429­432, April 1986. 4) Cole, C., A. Haoui, and P. Winship, "A High-Performance Digital Voice Echo Canceller on a Single TMS32020 TMS32020." Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, USA, 1986. 5) Lovrich, A., and J. Reimer, "A Multi-Rate Transcoder." Transactions on Consumer Electronics, USA, November 1989. 6) Lovrich, A. and J. Reimer, "A Multi-Rate Transcoder." Digest of Technical Papers for 1989 International Conference on Consumer Electronics, June 7­9, 1989. xii 7) Lu, H., D. Hedberg, and B. Fraenkel, "Implementation of High-Speed Voiceband Data Modems Using the TMS320C25 TMS320C25." Proceedings of ICASSP 87, USA, Catalog Number 87CH2396 87CH2396­0, Volume 4, pages 1915­1918, April 1987. 8) Mock, P., "Add DTMF Generation and Decoding to DSP­ µP Designs." Electronic Design, USA, Volume 30, Number 6, pages 205­213, March 1985. 9) Reimer, J., M. McMahan, and M. Arjmand, "ADPCM on a TMS320 TMS320 DSP Chip." Proceedings of SPEECH TECH 85, pages 246­249, April 1985. 10) Troullinos, G., and J. Bradley, "Split-Band Modem Implementation Using the TMS32010 TMS32010 Digital Signal Processor." Conference Records of Electro/86 and Mini/Micro Northeast, USA, 14/1/1­21, May 1986. Automotive: 1) Lin, K., "Trends of Digital Signal Processing in Automotive." International Congress on Transportation Electronic (CONVERGENCE '88), October 1988. Consumer: 1) Frantz, G.A., J.B. Reimer, and R.A. Wotiz, "Julie, The Application of DSP to a Product." Speech Tech Magazine, USA, September 1988. 2) Reimer, J.B., and G.A. Frantz, "Customization of a DSP Integrated Circuit for a Customer Product." Transactions on Consumer Electronics, USA, August 1988. 3) Reimer, J.B., P.E. Nixon, E.B. Boles, and G.A. Frantz, "Audio Customization of a DSP IC." Digest of Technical Papers for 1988 International Conference on Consumer Electronics, June 8­10 1988. Medical: 1) Knapp and Townshend, "A Real-Time Digital Signal Processing System for an Auditory Prosthesis." Proceedings of ICASSP 88, USA, Volume A, page 2493, April 1988. 2) Morris, L.R., and P.B. Barszczewski, "Design and Evolution of a PocketSized DSP Speech Processing System for a Cochlear Implant and Other Hearing Prosthesis Applications." Proceedings of ICASSP 88, USA, Volume A, page 2516, April 1988. xiii Development Support: 1) Mersereau, R., R. Schafer, T. Barnwell, and D. Smith, "A Digital Filter Design Package for PCs and TMS320 TMS320." MIDCON/84 MIDCON/84 Electronic Show and Convention, USA, 1984. 2) Simar, Jr., R., and A. Davis, "The Application of High-Level Languages to Single-Chip Digital Signal Processors." Proceedings of ICASSP 88, USA, Volume 3, pages 1678­1681, April 1988. If You Need Assistance. . . If you want to. . . Do this. . . Request more information about Texas Instruments Digital Signal Processing (DSP) products Write to: Texas Instruments Incorporated Market Communications Manager MS 736 P.O. Box 1443 Houston, Texas 77251­1443 Order Texas Instruments documentation Call the TI Literature Response Center: (800) 477­8924 Ask questions about product operation or report suspected problems Contact the DSP hotline: Phone: (713) 274­2320 FAX: (713) 274­2324 Electronic Mail: 4389750@mcimail.com. Obtain the source code in this user's guide. Call the TI BBS: (713) 274­2323 Ftp from: ftp.ti.com log in as user ftp cd to /mirrors/tms320bbs Visit TI online, including TI&ME , your own customized web page. Point your browser at: http://www.ti.com Report mistakes or make comments about this or any other TI documentation. Send electronic mail to: comments@books.sc.ti.com t xiv Send printed comments to: Texas Instruments Incorporated Technical Publications Mgr., MS 702 P.O. Box 1443 Houston, Texas 77251­1443 Trademarks MS is a registered trademark of Microsoft Corp. MS-Windows is a registered trademark of Microsoft Corp. MS-DOS is a registered trademark of Microsoft Corp. OS/2 is a trademark of International Business Machines Corp. Sun and SPARC are trademarks of Sun Microsystems, Inc. VAX and VMS are trademarks of Digital Equipment Corp. xv Contents Contents 1 Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides examples for initializing the processor. 1.1 1.2 1.3 1.4 2 Reset Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiprocessing System Reset Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Initialize the Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-3 1-5 1-6 Program Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Provides examples for initializing the processor and discusses program control features. 2.1 2.2 2.3 2.4 2.5 2.6 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 Regular Subroutine Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 Zero-Overhead Subroutine Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Stacks and Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.1 System Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.2 User Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3 Queues and Double-Ended Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Interrupt Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.1 Correct Interrupt Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.2 Software Polling of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.3 Using One Interrupt for Two Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.4 Nesting Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Context Switching in Interrupts and Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.1 Block Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.2 Delayed Block Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.3 Single-Instruction Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Computed GOTOs to Select Subroutines at Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 xvii Contents 3 Logical and Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Provides examples for performing logical and arithmetic operations. 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4 Memory Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Provides examples for TMS320C4x System Configuration, Memory Interfaces, and Reset. 4.1 4.2 4.3 4.4 4.5 4.6 5 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 External Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Global and Local Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Zero Wait-State Interfacing to RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4.1 Consecutive Reads Followed by a Write Interface Timing . . . . . . . . . . . . . . . . . 4-6 4.4.2 Consecutive Writes Followed by a Read Interface Timing . . . . . . . . . . . . . . . . . 4-7 4.4.3 RAM Interface Using One Local Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.4 RAM Interface Using Both Local Strobes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Wait States and Ready Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.5.1 ORing of the Ready Signals (STRBx SWW = 10) . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.5.2 ANDing of the Ready Signals (STRBx SWW = 11) . . . . . . . . . . . . . . . . . . . . . . 4-12 4.5.3 External Ready Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.5.4 Ready Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.5.5 Example Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.5.6 Page Switching Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Parallel Processing Through Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.6.1 Shared Global-Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.6.2 Shared-Memory Interface Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Programming Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Provides hints for writing more efficient C and assembly-language code. 5.1 5.2 xviii Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Block Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Byte and Half-Word Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1 CPU Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.2 DMA Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Integer and Floating-Point Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.1 Integer Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.2 Computation of Floating-Point Inverse and Division . . . . . . . . . . . . . . . . . . . . . 3-12 Calculating a Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Extended-Precision Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Floating-Point Format Conversion: IEEE to/From 'C4x . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Hints for Optimizing C Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Hints for Optimizing Assembly-Language Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Contents 6 Applications-Oriented Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Describes common algorithms and provides code for implementing them. 6.1 6.2 6.3 6.4 6.5 6.6 7 Programming the DMA Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Provides examples for programming the TMS320C4x's on-chip peripherals. 7.1 7.2 7.3 7.4 8 Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 FIR, IIR, and Adaptive Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.1 FIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.2 IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.2.3 Adaptive Filters (LMS Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Lattice Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Matrix-Vector Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Fast Fourier Transforms (FFTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.5.1 Complex Radix-2 DIF FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.5.2 Complex Radix-4 DIF FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6.5.3 Faster Complex Radix-2 DIT FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6.5.4 Real Radix-2 FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 'C4x Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86 Hints for DMA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . When a DMA Channel Finishes a Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Assembly Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA C-Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7-3 7-4 7-9 Using the Communication Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Describes how to interface with the TMS320C4x communication ports. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 Communication Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Signal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Interfacing With a Non-'C4x Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Terminating Unused Communication Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Commport to Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.6.1 Simplified Hardware Interface for 'C40 PG w 3.3, or 'C44 devices . . . . . . . . . 8-10 8.6.2 Improved Drive and Sense Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3 How the Circuit Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.6.4 The Interface Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 An I/O Coprocessor­'C4x Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Implementing a Token Forcer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Implementing a CSTRB Shortener Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Parallel Processing Through Communication Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Broadcasting Messages From One 'C4x to Many 'C4x Devices . . . . . . . . . . . . . . . . . . 8-20 Contents xix Contents 9 'C4x Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Explains the current consumption of .the 'C4x and also provides information about current consumption by components. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Capacitive and Resistive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Basic Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.1 Current Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.2 Current Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.3 Algorithm Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.2.4 Test Setup Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Current Requirement of Internal Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.3.1 Quiescent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.3.2 Internal Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.3.3 Internal Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Current Requirement of Output Driver Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.1 Local or Global Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.4.2 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.4.3 Communication Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.4.4 Data Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.5 Capacitive Loading Dependence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 Calculation of Total Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.5.1 Combining Supply Current Due to All Components . . . . . . . . . . . . . . . . . . . . . . 9-20 9.5.2 Supply Voltage, Operating Frequency, and Temperature Dependencies . . . 9-21 9.5.3 Design Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 9.5.4 Average Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 9.5.5 Thermal Management Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 Example Supply Current Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.6.1 Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.6.2 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.6.3 Average Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 9.6.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 9.7.1 System Clock and Signal Switching Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 9.7.2 Capacitive Loading of Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 9.7.3 DC Component of Signal Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 10 Development Support and Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Describes 'C4x support available from TI and third-part vendors. 10.1 xx Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 The DSP Hotline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 The Bulletin Board Service (BBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4 Internet Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Technical Training Organization (TTO) TMS320 TMS320 Workshops . . . . . . . . . . . . . . 10-2 10-3 10-3 10-4 10-4 10-5 Contents 10.2 10.3 Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.2.1 Tool-Activated ZIF PGA Socket (TAZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.2.2 Handle-Activated ZIF PGA Socket (HAZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.3.1 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.3.2 Device and Development Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 11 XDS510 XDS510 Emulator Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Describes the JTAG emulator cable. Tells you how to construct a 14-pin connector on your target system and how to connect the target system to the emulator. 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 A Designing Your Target System's Emulator Connector (14-Pin Header) . . . . . . . . . . . . 11-2 Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 IEEE 1149.1 Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 JTAG Emulator Cable Pod Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 JTAG Emulator Cable Pod Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Emulation Timing Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Connections Between the Emulator and the Target System . . . . . . . . . . . . . . . . . . . . . 11-8 11.7.1 Buffering Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.7.2 Using a Target-System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.3 Configuring Multiple Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Mechanical Dimensions for the 14-Pin Emulator Connector . . . . . . . . . . . . . . . . . . . . 11-12 Emulation Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.9.1 Using Scan Path Linkers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.9.2 Emulation Timing Calculations for SPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.9.3 Using Emulation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.9.4 Performing Diagnostic Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contents xxi Figures Figures 1­1 1­2 2­1 2­2 2­3 3­1 4­1 4­2 4­3 4­4 4­5 4­6 4­7 4­8 4­9 4­10 6­1 6­2 6­3 6­4 6­5 6­6 6­7 8­1 8­2 8­3 8­4 8­5 8­6 8­7 8­8 8­9 9­1 9­2 9­3 9­4 xxii Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Voltage on the RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 System Stack Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Implementations of High-to-Low Memory Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Implementations of Low-to-High Memory Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 DMA Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Possible System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Consecutive Reads Followed by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Consecutive Writes Followed by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 'C4x Interface to Eight Zero-Wait-State SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 'C4x Interface to Zero-Wait-State SRAMs, Two Strobes . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Logic for Generation of 0, 1, or 2 Wait States for Multiple Devices . . . . . . . . . . . . . . . . . . 4-14 Page Switching for the CY7B185 CY7B185 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Timing for Read Operations Using Bank Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 'C4x Shared/Distributed-Memory Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Data Memory Organization for an FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Data Memory Organization for a Single Biquad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Data Memory Organization for N Biquads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Structure of the Inverse Lattice Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Data Memory Organization for Inverse Lattice Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Structure of the Forward Lattice Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Data Memory Organization for Matrix-Vector Multiplication . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Impedance Matching for 'C4x Communication-Port Design . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Better Commport Signal Splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Improved Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 A 'C32 to 'C4x Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 A Token Forcer Circuit (Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Communication-Port Driver Circuit (Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 CSTRB Shortener Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 'C4x Parallel Connectivity Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Message Broadcasting by One 'C4x to Many 'C4x Devices . . . . . . . . . . . . . . . . . . . . . . . . 8-21 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Internal and Quiescent Current Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Internal Bus Current Versus Transfer Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Internal Bus Current Versus Data Complexity Derating Curve . . . . . . . . . . . . . . . . . . . . . . 9-10 Figures 9­5 9­6 9­7 9­8 9­9 9­10 9­11 9­12 9­13 10­1 10­2 10­3 11­1 11­2 11­3 11­4 11­5 11­6 11­7 11­8 11­9 11­10 11­11 Local/ Global Bus Current Versus Transfer Rate and Wait States . . . . . . . . . . . . . . . . . . . 9-14 Local/ Global Bus Current Versus Transfer Rate at Zero Wait States . . . . . . . . . . . . . . . . 9-15 DMA Bus Current Versus Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 Communication Port Current Versus Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 Local/ Global Bus Current Versus Data Complexity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 Pin Current Versus Output Load Capacitance (10 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 Current Versus Frequency and Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 Change in Operating Temperature (5C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 Load Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 Tool-Activated ZIF Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Handle-Activated ZIF Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 14-Pin Header Signals and Header Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 JTAG Emulator Cable Pod Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 JTAG Emulator Cable Pod Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Target-System-Generated Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Multiprocessor Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Pod/Connector Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 14-Pin Connector Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Connecting a Secondary JTAG Scan Path to an SPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 EMU0/1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Suggested Timings for the EMU0 and EMU1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11­12 EMU0/1 Configuration Without Global Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11­13 TBC Emulation Connections for n JTAG Scan Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Contents xxiii Tables Tables 1­1 4­1 4­2 6­1 6­2 9­1 9­2 10­1 10­2 10­3 10­4 11­1 11­2 xxiv RESET Vector Locations in the 'C40 and 'C44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Local/Global Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Page Switching Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 'C4x Application Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86 FFT Timing Benchmarks (Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87 Wait State Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Current Equation Typical Values (FCLK = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 Sockets that Accept the 325-pin 'C40 and the 304-pin 'C44 . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Manufacturer Phone Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Device Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Development Support Tools Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 14-Pin Header Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Emulator Cable Pod Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Examples Examples 1­1 1­2 1­3 2­1 2­2 2­3 2­4 2­5 2­6 2­7 2­8 2­9 2­10 3­1 3­2 3­3 3­4 3­5 3­6 3­7 3­8 3­9 3­10 3­11 3­12 3­13 3­14 4­1 5­1 5­2 5­3 6­1 6­2 6­3 6­4 6­5 Processor Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Linker Command File for Linking the Previous Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Enabling the Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Regular Subroutine Call (Dot Product) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Zero-Overhead Subroutine Call (Dot Product) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Use of Interrupts for Software Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Use of One Interrupt Signal for Two Different Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Context Save and Context Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Use of Block Repeat to Find a Maximum or a Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Loop Using Delayed Block Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Loop Using Single Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Computed GOTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Use of TSTB for Software-Controlled Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Copy a Bit from One Location to Another . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Block Move Under Program Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Use of Packing Data From Half-Word FIFO to 32-Bit Data Memory . . . . . . . . . . . . . . . . . . 3-4 Use of Unpacking 32-Bit Data Into Four-Byte-Wide Data Array . . . . . . . . . . . . . . . . . . . . . . 3-5 CPU Bit-Reversed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Integer Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Inverse of a Floating-Point Number With 32-Bit Mantissa Accuracy . . . . . . . . . . . . . . . . . 3-14 Reciprocal of the Square Root of a Positive Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 64-Bit Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 64-Bit Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 32-Bit by 32-Bit Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 IEEE to 'C4x Conversion Within Block Memory Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 'C4x to IEEE Conversion Within Block Memory Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 PLD Equations for Ready Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Exchanging Objects in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Optimizing a Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Allocating Large Array Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 m-Law Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 m-Law Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 A-Law Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 A-Law Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Contents xxv Examples 6­6 6­7 6­8 6­9 6­10 6­11 6­12 6­13 6­14 6­15 6­16 6­17 6­18 7­1 7­2 7­3 7­4 7­5 7­6 7­7 7­8 7­9 7­10 7­11 7­12 8­1 8­2 xxvi IIR Filter (One Biquad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 IIR Filter (N > 1 Biquads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Adaptive FIR Filter (LMS Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Inverse Lattice Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Lattice Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Matrix Times a Vector Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Complex Radix-2 DIF FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 Table With Twiddle Factors for a 64-Point FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Complex Radix-4 DIF FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 Faster Version Complex Radix-2 DIT FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 Bit-Reversed Sine Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 Real Forward Radix-2 FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 Real Inverse Radix-2 FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73 Array initialization With DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 DMA Transfer With Communication-Port ICRDY Synchronization . . . . . . . . . . . . . . . . . . . 7-5 DMA Split-Mode Transfer With External-Interrupt Synchronization . . . . . . . . . . . . . . . . . . . 7-6 DMA Autoinitialization With Communication Port ICRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Single-Interrupt-Driven DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Unified-Mode DMA Using Read Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Unified-Mode DMA Using Autoinitialization (Method 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Unified-Mode DMA Using Autoinitialization (Method 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Split-Mode Auxiliary DMA Using Read Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Split-Mode Auxiliary and Primary Channel DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 Split-Mode DMA Using Autoinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 Include File for All C Examples (dma.h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Read Data from Communication Port With CPU ICFULL Interrupt . . . . . . . . . . . . . . . . . . . 8-3 Write Data to Communication Port With Polling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Chapter 1 Processor Initialization Before you execute a DSP algorithm, it is necessary to initialize the processor. Initialization brings the processor to a known state. Generally, initialization takes place any time after the processor is reset. This chapter reviews the concepts explained in the user's guide and provides examples. Topic Page 1.1 Reset Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Reset Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Multiprocessing System Reset Considerations . . . . . . . . . . . . . . . . . . 1-5 1.4 How to Initialize the Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Chapter Title-Attribute Reference 1-1 Reset Process 1.1 Reset Process After RESET is applied, the 'C4x jumps to the address stored in the reset vector location and starts execution from that point. In order to reset the 'C4x correctly, you need to comply with several hardware and software requirements: - Select the reset vector location: J J - If the DSP is in microcomputer mode (ROMEN pin =1), RESETLOC(1,0) must be equal to 0,0 for the boot loader to operate correctly. If the DSP is in microcomputer mode, set the IIOFx pins as discussed in the bootloader chapter TMS320C4x User's Guide so that the bootloader works properly. Provide the correct reset vector value: J J J - The RESET vector of the 'C4x can be mapped to one of four different locations that are controlled by the value of the RESETLOC(1,0) pins at RESET. Table 1­1 shows possible reset vectors for the 'C40 and 'C44. The RESET vector normally contains the address of the system initialization routine. In microcomputer mode the reset vector is initialized automatically by the processor to point to the beginning of the on­chip boot loader code. No user action is required. In microprocessor mode, the reset vector is typically stored in an EPROM. Example 1­1 shows how you can initialize that vector. Apply a low level to the RESET input. (See section 1.2). Table 1­1. RESET Vector Locations in the 'C40 and 'C44 Value at RESETLOCx Pin Get Reset Vector From Hex Memory Address Bus 0 00000 0000 Local 0 1 07FFF 07FFF FFFF Local 1 0 08000 0000 Global 1 1 0FFFF FFFF Global RESETLOC1 RESETLOC0 0 This corresponds to the 32-bit address that the processor accesses. However, in the 'C44 only the 24-LSBs of the reset address are driven on pins A0­A23 and pins LA0­LA23. The corresponding LSTRBx pins are also activated. 1-2 Reset Signal Generation 1.2 Reset Signal Generation Several aspects of 'C4x system hardware design are critical to overall system operation. One such aspect is reset signal generation. The reset input controls initialization of internal 'C4x logic and execution of the system initialization software. For proper system initialization, the RESET signal must be applied for at least ten H1 cycles, that is, 400 ns for a 'C4x operating at 50 MHz. Upon power up, however, it can take 20 ms or more before the system oscillator reaches a stable operating state. Therefore, the power-up reset circuit should generate a low pulse on the RESET pin for 100 to 200 ms. Once a proper reset pulse has been applied, the processor fetches the reset vector from location zero, which contains the address of the system initialization routine. Figure 1­1 shows a circuit that will generate an appropriate power-up or push-button reset signal. Figure 1­1. Reset Circuit TMS320C4x Reset +5 V R1 = 100 k 74ALS34 74ALS34 C1 = 4.7 µF The voltage on the RESET pin is controlled by the R1C1 network. After a reset, this voltage rises exponentially according to the time constant R1C1, as shown in Figure 1­2. In Figure 1­1, the 74ALS34 74ALS34 provides a clean RESET signal to the 'C4x. Processor Initialization 1-3 Reset Signal Generation Figure 1­2. Voltage on the RESET Pin Voltage V = VCC (1 ­ e ­ t / ) VCC V1 Time t 0 = 0 t1 The duration of the low pulse on the RESET pin is approximately t1, which is the time it takes for the capacitor C1 to be charged to 1.5 V. This is approximately the voltage at which the reset input switches from a logic 0 to a logic 1. The capacitor voltage is expressed as V +V CC * e *t t 1 (5) where = R1C1 is the reset circuit time constant. Solving (5) for t results in t + * R C ln 1 * VV 1 1 (6) CC Setting the following: R1 = 100 k C1 = 4.7 µF VCC = 5 V V = V1 = 1.5 V results in t = 167 ms. Therefore, the reset circuit of Figure 1­1 provides a low pulse for a long enough time to ensure the stabilization of the system oscillator upon powerup. Note: Reset does not have internal Schmidt hysteresis. To ensure proper reset operation, avoid low rise and fall times. Rise/fall time should not exceed one CLKIN cycle. 1-4 Multiprocessing System Reset Considerations 1.3 Multiprocessing System Reset Considerations If synchronization of multiple 'C4x DSPs is required, all processors should be provided with the same input clock and the same reset signal. After powerup, when the clock has stabilized, set RESET high for a few H1/H3 cycles and then set it low to synchronize their H1/H3 clock phases. Following the falling edge, RESET should remain low for at least ten H1 cycles and then be driven high. The circuit in Figure 1­1 can be used for RESET generation. Pullup resistors are recommended at each end of the connection to avoid unintended triggering after reset when RESET going low is not received on all 'C4x devices at the same time. It is recommended that you power up the system with RESET low. This prevents 'C4x asynchronous signals from driving unknown values before RESET goes low, which could create bus contention in communication-port pins, resulting in damage to the device. Processor Initialization 1-5 How to Initialize the Processor 1.4 How to Initialize the Processor After reset, the C4x jumps to the address stored in the reset vector location and starts execution from that point. The RESET vector normally contains the address of the system initialization routine. The initialization routine should typically perform several tasks: - Set the DP register. Set the stack pointer. Set the interrupt vector table. Set the trap vector table. Set the memory control register. Clear/enable cache. Note: When running under microcomputer mode (ROMEN = 1). The address stored in the reset vector location points to the beginning of the bootloader code. The on-chip bootloader automatically initializes the memory-control register values from the bootloader table The following examples illustrate how to initialize the 'C4x when using assembly language and when using C. Processor initialization under assembly language If you are running under an assembly-only environment, Example 1­1 provides a basic initialization routine. This example shows code for initializing the 'C4x to the following machine state: - Timer 0 interrupt is enabled. Trap 0 is initialized. The program cache is enabled. The DP is initialized to point to the .text section. The stack pointer is initialized to the beginning of the mystack section. The memory control registers are initialized. The 'C4x is initialized to run in microcontroller mode with the reset vector located at address 08000 0000h (RESETLOC(1,0)=1,0). The program has already been loaded into memory location at address = 0x4000 0000. You need to allocate the section addresses using a linker command file (see the TMS320 TMS320 Floating-Point DSP Assembly Language Tools User's Guide book for more information about linker command files) as shown in Example 1­2. 1-6 How to Initialize the Processor Example 1­1.Processor Initialization Example ; ; ; Create Reset Vector .sect "rst_sect" ;Named section for RESET vector reset .word init ;RESET vector ; ; Create Interrupt Vector Table ; _myvect .sect "myvect" ;Named section for int. vectors .space 2 ;Reserved space .word tint0 ;Timer 0 ISR address ; ; Create Trap Vector Table ; _mytrap .sect "mytrap" ; named section for trap vectors .word trap0 ;Trap 0 subroutine address ; ; Create Stack ; _mystack .usect "mystack",500 ; reserve 500 locations for ; stack .text stacka .word _mystack ; address of mystack section ivta .word _myvect ; address of myvect section tvta .word _mytrap ; address of mytrap section ieval .word 1 ; IE register value gctrl .word ? ; target board specific lctrl .word ? ; target board specific mctrla .word 100000h ; address of the global memory ; control register init: ; ; Initialize the DP Register ; ldp stacka ; ; ; Set Expansion Register IVTP LDI LDPE ; ; ; @ivta,AR0 AR0,IVTP Set Expansion Register TVTP LDI LDPE @tvta,AR0 AR0,TVTP Processor Initialization 1-7 How to Initialize the Processor Example 1­1. Processor Initialization Example (Continued) ; ; ; Initialize global memory interface control ldi LDI STI @mctrla,ar0 @gctrl,R0 R0,*AR0 ; ; Initialize local memory interface control ; LDI @lctrl,R0 STI R0,*+AR0(4) ; ; Initialize the Stack Pointer ; LDI @stacka,SP ; ; Enable timer interrupt ; This is equivalent to ldi 1,iie ; LDI @ieval,IIE ; ; Clear/Enable Cache and Enable Global Interrupts ; OR 3800H 3800H,ST ; ; ; Global interrupt enable ; BR BEGIN ; Branch to the beginning of ; the application . begin < this is your application code> trap0 . < this is your trap0 trap code> reti tint0 . < this is your tint0 interrupt service routine> reti .end 1-8 How to Initialize the Processor Example 1­2.Linker Command File for Linking the Previous Example MEMORY { EPROM: org = 0x80000000 len = 0x10 RAM: org = 0x40000000 len = 0x100 } /* EPROM reset vector location */ /* extend RAM */ /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ SECTIONS { rst_sect: > EPROM myvect: > RAM mystack: > RAM .text: > RAM mytrap: > RAM } Processor initialization under C language If you are running under a C environment, your initialization routine is typically boot.asm (from the RTS40 RTS40.LIB library that comes with the floating-point compiler). In addition to initializing global variables, boot.asm initializes the DP register (pointing to the .bss section) and the SP register (pointing to the .stack section). You need to enable the cache, as shown in Example 1­3, and setup your interrupts inside your main routine before you enable interrupts. See the Application Report, Setting Up TMS320 TMS320 DSP Interrupts in C (SPRA036 SPRA036), for more information. Example 1­3.Enabling the Cache main() { asm(" or 1800,st") ; enable cache /* asm(" or 3800,st") */ ; enable cache and interrupts } Processor Initialization 1-9 1-10 Chapter 2 Program Control Several 'C4x instructions provide program control and facilitate high-speed processing. These instructions directly handle: - Regular and zero-overhead subroutine calls Software stack Interrupts Delayed branches Single- and multiple-instruction loops without overhead Topic Page 2.1 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Stacks and Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3 Interrupt Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.4 Context Switching in Interrupts and Subroutines . . . . . . . . . . . . . . . 2-14 2.5 Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.6 Computed GOTOs to Select Subroutines at Runtime . . . . . . . . . . . . 2-21 Chapter Title-Attribute Reference 2-1 Subroutines 2.1 Subroutines The 'C4x provides two ways to invoke subroutine calls: regular calls and zerooverhead calls. The regular and zero-overhead subroutine calls use the software stack and extended-precision register R11, respectively, to save the return address. The following subsections use example programs to explain how this works. 2.1.1 Regular Subroutine Calls The 'C4x has a 32-bit program counter (PC) and a virtually unlimited software stack. The CALL and CALLcond subroutine calls increment the stack pointer and store the contents of the next value of the PC counter on the stack. At the end of the subroutine, RETScond performs a conditional return. Example 2­1 illustrates the use of a subroutine to determine the dot product of two vectors. Given two vectors of length N, represented by the arrays a[0], a[1], ., a[N­1] and b[0], b[1],., b[N­1], the dot product is computed from the expression d = a[0] b[0] + a[1] b[1] + . + a[N­1] b[N­1] Processing proceeds in the main routine to the point where the dot product is to be computed. It is assumed that the arguments of the subroutine have been appropriately initialized. At this point, a CALL is made to the subroutine, transferring control to that section of the program memory for execution, then returning to the calling routine via the RETS instruction when execution has completed. Note that for this particular example, it would suffice to save the register R2. However, a larger number of registers are saved for demonstration purposes. The saved registers are stored on the system stack, which should be large enough to accommodate the maximum anticipated storage requirements. Other methods of saving registers could be used equally well. 2-2 Subroutines Example 2­1.Regular Subroutine Call (Dot Product) * * * * * * TITLE REGULAR SUBROUTINE CALL (DOT PRODUCT) MAIN ROUTINE THAT CALLS THE SUBROUTINE `DOT' TO COMPUTE THE DOT PRODUCT OF TWO VECTORS. . . LDI @blk0,AR0 ;AR0 points to vector a LDI @blk1,AR1 ;AR1 points to vector b ;RC contains the number of elements LDI N,RC CALL DOT . . * * *SUBROUTINE DOT * * *EQUATION: d = a(0) * b(0) + a(1) * b(1) + . + a(N­1) * b(N­1) * * *THE DOT PRODUCT OF a AND b IS PLACED IN REGISTER R0. N MUST *BE GREATER THAN OR EQUAL TO 2. * * * ARGUMENT ASSIGNMENTS: * ARGUMENT | FUNCTION * ­­­­­­­­­­­­­­ +­­­­­­­­­­­­­­­­­­­­­­­­­ * AR0 | ADDRESS OF a(0) * AR1 | ADDRESS OF b(0) * RC | LENGTH OF VECTORS (N) * * * REGISTERS USED AS INPUT: AR0, AR1, RC * REGISTER MODIFIED: R0 * REGISTER CONTAINING RESULT: R0 * * .global DOT * DOT PUSH ST ;Save status register PUSH R2 ;Use the stack to save R2's PUSHF R2 ;bottom 32 and top 32 bits PUSH AR0 ;Save AR0 PUSH AR1 ;Save AR1 PUSH RC ;Save RC PUSH RS PUSH RE * * * Initialize R0: MPYF3 *AR0,*AR1,R0 ;a(0) * b(0) ­> R0 Program Control 2-3 Subroutines Example 2­1.Regular Subroutine Call (Dot Product) (Continued) || SUBF SUBI R2,R2,R2 2,RC ;Initialize R2. ;Set RC = N­2 * * * DOT PRODUCT (1 R0 ; a(i­1)*b(i­1) + R2 ­> R2 ; a(N­1)*b(N­1) + R2 ­> R0 ;Restore ;Restore ;Restore ;Restore ;Restore ;Restore ;Return RC AR1 AR0 top 32 bits of R2 bottom 32 bits of R2 ST Zero-Overhead Subroutine Calls Two instructions, link and jump (LAJ) and link and jump conditional (LAJcond), implement zero-overhead subroutine calls to be implemented on the 'C4x. Unlike CALL and CALLcond, which put the value of PC + 1 into the software stack, LAJ and LAJcond put the value of PC + 4 into extended-precision register R11. Three instructions following LAJ or LAJcond are executed before going to the subroutine. The restriction that applies to these three instructions is the same as that of the three instructions following a delayed branch. At the end of the subroutine, you can use a delayed branch conditional, Bcond D, in the register addressing mode with R11 as source, to perform a zero-overhead subroutine return. For comparison, the same dot product example with a zero-overhead subroutine call is given in the following example program. 2-4 Subroutines Example 2­2.Zero-Overhead Subroutine Call (Dot Product) * * * * * * TITLE ZERO-OVERHEAD SUBROUTINE CALL (DOT PRODUCT) MAIN ROUTINE THAT CALLS THE SUBROUTINE `DOT' TO COMPUTE THE DOT PRODUCT OF TWO VECTORS. . . . LAJ LDI LDI LDI . . . DOT @blk0,AR0 @blk1,AR1 N,RC ; AR0 points to vector a ; AR1 points to vector b ; RC contains the number of elements * *SUBROUTINE DOT * *EQUATION: d = a(0) * b(0) + a(1) * b(1) + . + a(N­1) * b(N­1) * * THE DOT PRODUCT OF a AND b IS PLACED IN REGISTER R0. N MUST * BE GREATER THAN OR EQUAL TO 2. * * ARGUMENT ASSIGNMENTS: * ARGUMENT | FUNCTION * ­­­­­­­­­­­­­­­ +­­­­­­­­­­­­­­­­­­­­­­­­­ * AR0 | ADDRESS OF a(0) * AR1 | ADDRESS OF b(0) * RC | LENGTH OF VECTORS (N) * * * * * * REGISTERS USED AS INPUT: AR0, AR1, RC REGISTER MODIFIED: R0 REGISTER CONTAINING RESULT: R0 * .global DOT * DOT PUSH PUSH PUSHF PUSH PUSH PUSH PUSH PUSH ST R2 R2 AR0 AR1 RC RS RE ;Save status register ;Use the stack to save R2's ;bottom 32 and top 32 bits ;Save AR0 ;Save AR1 ;Save RC Program Control 2-5 Subroutines Example 2­2.Zero-Overhead Subroutine Call (Dot Product) (Continued) * Initialize R0: MPYF3 *AR0,*AR1,R0 || SUBF R2,R2,R2 SUBI 2,RC * * * ;a(0) * b(0) ­> R0 ;Initialize R2. ;Set RC = N­2 DOT PRODUCT (1 R0 R0,R2,R2 ; a(i­1)*b(i­1) + R2 ­> R2 R0,R2,R0 RETURN SEQUENCE POP POP POP POP POP BUD POPF POP POP * * * end .end 2-6 ; a(N­1)*b(N­1) + R2 ­> R0 RE RS RC AR1 AR0 R11 R2 R2 ST ;Restore ;Restore ;Restore ;Return ;Restore ;Restore ;Restore RC AR1 AR0 top 32 bits of R2 bottom 32 bits of R2 ST Stacks and Queues 2.2 Stacks and Queues The 'C4x provides a dedicated stack pointer (SP) for building stacks in memory. Also, the auxiliary registers can be used to build user stacks and a variety of more general linear lists. This section discusses the implementation of the following types of linear lists: Stack Queue A linear list for which all insertions are made at one end of the list, and all deletions are made at the other end. Dequeue 2.2.1 A linear list for which all insertions and deletions are made at one end of the list. A double-ended queue linear list for which insertions and deletions are made at either end of the list. System Stacks A stack in the 'C4x fills from a low-memory address to a high-memory address, as is shown in Figure 2­1. A system stack stores addresses and data during subroutine calls, traps, and interrupts. The stack pointer (SP) is a 32-bit register that contains the address of the top of the system stack. The SP always points to the last element pushed onto the stack. A push performs a preincrement, and a pop performs a postdecrement of the SP. Provisions should be made to accommodate your software's anticipated storage requirements. The stack pointer (SP) can be read from as well as written to; multiple stacks can be created by updating the SP. The SP is not initialized by the hardware during reset; it is important to remember to initialize its value so that the it points to a predetermined memory location. Example 1­1 on page 1-7, shows how to initialize the SP. You must initialize the stack to a valid free memory space. Otherwise, use of the stack could corrupt data or program memory. The program counter is pushed onto the system stack on subroutine calls, traps, and interrupts. It is popped from the system stack on returns. The PUSH, POP, PUSHF, and POPF instructions push and pop the system stack. The stack can be used inside of subroutines as a place of temporary storage of registers, as is the case shown in Example 2­1, on page 2-3. Program Control 2-7 Stacks and Queues Two instructions, PUSHF and POPF, are for floating-point numbers. These instructions can pop and push floating-point numbers to registers R0 - R11. This feature is very useful for saving the extended-precision registers (see Example 2­1 and Example 2­2). PUSH saves the lower 32 bits of an extendedprecision register, and PUSHF saves the upper 32 bits. To recover this extended-precision number, execute a POPF followed by POP. It is important to perform the integer and floating-point PUSH and POP in the above order, since POPF forces the last eight bits of the extended-precision registers to zero. Figure 2­1. System Stack Configuration Low Memory Bottom of stack . . . SP Top of stack (Free) High Memory 2.2.2 User Stacks User stacks can be built to store data from low-to-high memory or from high-tolow memory. Two cases for each type of stack are shown. You can build stacks by using the preincrement/decrement and postincrement/decrement modes of modifying the auxiliary registers (AR). You can implement stack growth from high to low memory in two ways: Case 1: Store to memory using *­ ­ ARn to push data onto the stack, and read from memory using *ARn + to pop data off the stack. Case 2: Store to memory using *ARn ­ ­ to push data onto the stack, and read from memory using * + ARn to pop data off the stack. Figure 2­2 illustrates these two cases. The only difference is that in case 1, the AR always points to the top of the stack, and in case 2, the AR always points to the next free location on the stack. 2-8 Stacks and Queues Figure 2­2. Implementations of High-to-Low Memory Stacks Low Memory (Free) Low Memory ARn (Free) Top of stack Top of stack Bottom of stack Bottom of stack High Memory High Memory Case 1 ARn Case 2 You can implement stack growth from low to high memory in two ways: Case 3: Store to memory using *+ ARn to push data onto the stack, and read from memory using *ARn ­ ­ to pop data off the stack. Case 4: Store to memory using *ARn + to push data onto the stack, and read from memory using *­ ­ ARn to pop data off the stack. Figure 2­3 shows these two cases. In case 3, the AR always points to the top of the stack. In case 4, the AR always points to the next free location on the stack. Figure 2­3. Implementations of Low-to-High Memory Stacks Low Memory Bottom of stack Bottom of stack . . . . . ARn Low Memory . Top of stack Top of stack (Free) ARn (Free) High Memory Case 3 2.2.3 High Memory Case 4 Queues and Double-Ended Queues The implementations of queues and double-ended queues is based upon the manipulation of the auxiliary registers for user stacks. Program Control 2-9 Stacks and Queues For queues, two auxiliary registers are used: one to mark the front of the queue from which data is popped and the other to mark the rear of the queue to where data is pushed. For double-ended queues, two auxiliary registers are also necessary. One register marks one end of the double-ended queue, and the other register marks the other end. Data can be popped from or pushed onto either end. 2-10 Interrupt Examples 2.3 Interrupt Examples When using interrupts, you must consider several issues. This section offers examples of several interrupt-related topics: 2.3.1 Interrupt Service Routines Context Switching Interrupt-Vector Table (IVTP) Interrupt Priorities Correct Interrupt Programming For interrupts to work properly you need to execute the following sequence of steps, as is shown in Example 1­1: 1) 2) 3) 4) 5) 6) 2.3.2 Set the interrupt-vector table in a 512-word boundary. Initialize the IVTP register. Create a software stack. Enable the specific interrupt. Enable global interrupts. Generate the interrupt signal. Software Polling of Interrupts The interrupt flag register can be polled, and action can be taken, depending on whether an interrupt has occurred. This is true even when maskable interrupts are disabled.This can be useful when an interrupt-driven interface is not implemented. Example 2­3 shows the case in which a subroutine is called when external interrupt 1 has not occurred. Example 2­3.Use of Interrupts for Software Polling * TITLE INTERRUPT POLLING . . . TSTB 40H,IIF ;Test if interrupt 1 has occurred CALLZ SUBROUTINE ;If not, call subroutine . . . When interrupt processing begins, the program counter is pushed onto the stack, and the interrupt vector is loaded in the program counter. Interrupts are disabled when GIE is cleared to 0 and the program continues from the address loaded in the program counter. Because all maskable interrupts are disabled, interrupt processing can proceed without further interruption unless the interrupt service routine re-enables interrupts, or the NMI occurs. Program Control 2-11 Interrupt Examples 2.3.3 Using One Interrupt for Two Services The IVTP can be changed to point to alternate interrupt-vector tables. This relocatable feature of the table allows you to use a single interrupt signal for more than one service. In Example 2­4, the IVTP is reset in the external INT0 interrupt service routines EINT0A and EINT0B. After the value of the IVTP is changed, the CPU goes to a different interrupt service routine when the same interrupt signal reoccurs. Example 2­4.Use of One Interrupt Signal for Two Different Services * * * * * * * * * * * * * * TITLE USE OF ONE INTERRUPT SIGNAL FOR TWO DIFFERENT SERVICES IN THIS EXAMPLE, THE ADDRESS OF EINT0A AND EINT0B ARE IN MEMORY LOCATION 03H AND 1003H 1003H, RESPECTIVELY. ASSUME THE IVTP HAS NOT BEEN CHANGED AFTER DEVICE RESET AND THE EXTERNAL INTERRUPT IIOF0 IS ENABLED. WHEN THE FIRST IIOF0 INTERRUPT SIGNAL COMES IN, THE EINT0A ROUTINE WILL BE EXECUTED AND THEN IF THE NEXT IIOF0 INTERRUPT SIGNAL OCCURS, THE EINT0B ROUTINE WILL BE EXECUTED, AND SO ON. THE EINT0A AND EINT0B ROUTINES WILL TAKE TURNS TO BE EXECUTED WHEN THE IIOF0 INTERRUPT SIGNAL OCCURS. External IIOF0 interrupt service routine A EINT0A: .global EINT0A . . . . LDI 1000H 1000H,R0 LDPE R0,IVTP . . ;Change IVTP to point to 1000H 1000H * RETI ;Return and enable interrupts * * * External IIOF0 interrupt service routine A EINT0B: .global EINT0B . . . . LDI 0,R0 LDPE R0,IVTP . . ;Change IVTP to point to 0 * RETI 2-12 ;Return and enable interrupts Interrupt Examples 2.3.4 Nesting Interrupts In Example 2­5, the interrupt service routine for INT2 temporarily modifies the interrupt enable register (IIE) and interrupt flag register (IIF) to permit interrupt processing when an interrupt to INT0 or NMI (but no other interrupt) occurs. When the routine finishes processing, the IIE register is restored to its original state. Notice that the RETIcond instruction not only pops the next program counter address from the stack, but also restores GIE and CF bits from the PGIE and PCF bits. This re-enables all interrupts that were enabled before the INT2 interrupt was serviced. Example 2­5.Interrupt Service Routine * TITLE INTERRUPT SERVICE ROUTINE .global ISR2 * ENABLE .set 2000h MASK .set 9h * * INTERRUPT PROCESSING FOR EXTERNAL INTERRUPT INT2­ * ISR2: PUSH ST ;Save status register PUSH DP ;Save data page pointer PUSH IIE ;Save interrupt enable register PUSH IIF PUSH R0 ;Save lower 32 bits and PUSHF R0 ;upper 32 bits of R0 PUSH R1 ;Save lower 32 bits and PUSHF R1 ;upper 32 bits of R1 LDI 0,IIE ;Unmask all internal interrupts LDI MASK, R0 MH0 R0, IIF ;Enable INT2 OR ENABLE,ST ;Enable all interrupts * * MAIN PROCESSING SECTION FOR ISR2 . . . XOR POPF POP POPF POP POP POP POP POP ENABLE,ST R1 R1 R0 R0 IIF IIE DP ST ;Disable all interrupts ;Restore upper 32 bits and ;lower 32 bits of R1 ;Restore upper 32 bits and ;lower 32 bits of R0 ;Restore interrupt enable register ;Restore data page register ;Restore status register * RETI ;Return and enable interrupts Program Control 2-13 Context Switching in Interrupts and Subroutines 2.4 Context Switching in Interrupts and Subroutines Context switching is commonly required when a subroutine call or interrupt is processed. It can be extensive or simple, depending on system requirements. For the 'C4x, the program counter is automatically pushed onto the stack. Important information in other 'C4x registers, such as the status, auxiliary, or extended-precision registers, must be saved in the stack with PUSH/PUSHF and recovered later with POP/POPF instructions. You need to preserve only the registers that are modified inside of your subroutine or interrupt/trap service routine and that could potentially affect the previous context environment. Note: The status register should be saved first and restored last to preserve the processor status without any further change caused by other context-switching instructions. If the previous context environment was in C, then your program must perform one of two tasks: - If the program is in a subroutine, it must preserve the dedicated C registers: Save as integers Save as floating-point R4 AR4 AR5 AR6 AR7 FP DP (small model only) SP - RS R6 R7 R8 (`C4x only) If the program is in an interrupt service routine, it must preserve all of the 'C4x registers, as Example 2­6 shows. If the previous context environment was in assembly language, you need to determine which registers you must save based on the operations of your assembly-language code. 2-14 Context Switching in Interrupts and Subroutines Example 2­6.Context Save and Context Restore * .global ISR1 * * TOTAL CONTEXT SAVE ON INTERRUPT. * ISR1: PUSH ST ;Save status register * * SAVE THE EXTENDED PRECISION REGISTERS * PUSH R0 ;Save the lower 32 bits PUSHF R0 ;and the upper 32 bits PUSH R1 ;Save the lower 32 bits PUSHF R1 ;and the upper 32 bits PUSH R2 ;Save the lower 32 bits PUSHF R2 ;and the upper 32 bits PUSH R3 ;Save the lower 32 bits PUSHF R3 ;and the upper 32 bits PUSH R4 ;Save the lower 32 bits PUSHF R4 ;and the upper 32 bits PUSH R5 ;Save the lower 32 bits PUSHF R5 ;and the upper 32 bits PUSH R6 ;Save the lower 32 bits PUSHF R6 ;and the upper 32 bits PUSH R7 ;Save the lower 32 bits PUSHF R7 ;and the upper 32 bits PUSH R8 ;Save the lower 32 bits PUSHF R8 ;and the upper 32 bits PUSH R9 ;Save the lower 32 bits PUSHF R9 ;and the upper 32 bits PUSH R10 ;Save the lower 32 bits PUSHF R10 ;and the upper 32 bits PUSH R11 ;Save the lower 32 bits PUSHF R11 ;and the upper 32 bits * * SAVE THE AUXILIARY REGISTERS * PUSH AR0 ;Save AR0 PUSH AR1 ;Save AR1 PUSH AR2 ;Save AR2 PUSH AR3 ;Save AR3 PUSH AR4 ;Save AR4 PUSH AR5 ;Save AR5 PUSH AR6 ;Save AR6 PUSH AR7 ;Save AR7 * of R0 of R1 of R2 of R3 of R4 of R5 of R6 of R7 of R8 of R9 of R10 of R11 Program Control 2-15 Context Switching in Interrupts and Subroutines Example 2­6.Context Save and Context Restore (Continued) * * SAVE THE REST OF THE REGISTERS FROM THE REGISTER FILE PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH ;Save ;Save ;Save ;Save ;Save ;Save ;Save ;Save PUSH PUSH * * * * * DP IR0 IR1 BK IIE IIF DIE RS RE RC ;Save repeat end address ;Save repeat counter SAVE IS COMPLETE YOUR INTERRUPT SERVICE ROUTINE CODE GOES HERE* .global * * data page pointer index register IR0 index register IR1 block-size register interrupt enable register interrupt flag register DMA interrupt enable register repeat start address RESTR CONTEXT RESTORE AT THE END OF A SUBROUTINE CALL OR INTERRUPT. RESTR: * * RESTORE THE REST REGISTERS FROM THE REGISTER FILE * POP RC ;Restore repeat counter POP RE ;Restore repeat end address POP RS ;Restore repeat start address POP DIE ;Restore DMA interrupt enable register POP IIF ;Restore interrupt flag register POP IIE ;Restore interrupt enable register POP BK ;Restore block-size register POP IR1 ;Restore index register IR1 POP IR0 ;Restore index register IR0 POP DP ;Restore data page pointer * * RESTORE THE AUXILIARY REGISTERS * POP AR7 ;Restore AR7 POP AR6 ;Restore AR6 POP AR5 ;Restore AR5 POP AR4 ;Restore AR4 POP AR3 ;Restore AR3 POP AR2 ;Restore AR2 POP AR1 ;Restore AR1 POP AR0 ;Restore AR0 * 2-16 Context Switching in Interrupts and Subroutines Example 2­6.Context Save and Context Restore (Continued) * * RESTORE THE EXTENDED PRECISION REGISTERS POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POP * * * R11 R11 R10 R10 R9 R9 R8 R8 R7 R7 R6 R6 R5 R5 R4 R4 R3 R3 R2 R2 R1 R1 R0 R0 ST ;Restore the upper 32 bits ;the lower 32 bits of R11 ;Restore the upper 32 bits ;the lower 32 bits of R10 ;Restore the upper 32 bits ;the lower 32 bits of R9 ;Restore the upper 32 bits ;the lower 32 bits of R8 ;Restore the upper 32 bits ;the lower 32 bits of R7 ;Restore the upper 32 bits ;the lower 32 bits of R6 ;Restore the upper 32 bits ;the lower 32 bits of R5 ;Restore the upper 32 bits ;the lower 32 bits of R4 ;Restore the upper 32 bits ;the lower 32 bits of R3 ;Restore the upper 32 bits ;the lower 32 bits of R2 ;Restore the upper 32 bits ;the lower 32 bits of R1 ;Restore the upper 32 bits ;the lower 32 bits of R0 ;Restore status register and and and and and and and and and and and and RESTORE IS COMPLETE RETI Program Control 2-17 Repeat Modes 2.5 Repeat Modes The RPTB, RPTBD, and RPTS instructions support looping without overhead. Loop execution parameters are specified by three registers, as can be seen in the following examples: - RS (Repeat start address) RE (Repeat end address) RC (Repeat counter) In principle, it is possible to nest repeat blocks. However, there is only one set of control registers: RS, RE, and RC. It is, therefore, necessary to save these registers before entering an inside loop and to restore these registers after completing the inside loop. It takes four cycles of overhead to save and restore these registers. Hence, sometimes it may be more economical to implement a nested loop by the more traditional method of using a register as a counter and then using a delayed branch, rather than by using the nested repeat block approach. Often, implementing the outer loop as a counter and the inner loop as a RPTB/RPTBD instruction produces the fastest execution. 2.5.1 Block Repeat Example 2­7 shows the use of the block repeat to find the maximum or the minimum value of 147 numbers. The elements of the array are either all positive or all negative numbers. Because the loop cannot be predetermined, the RPTBD instruction is not suitable here. Example 2­7.Use of Block Repeat to Find a Maximum or a Minimum * * * * TITLE USE OF BLOCK REPEAT TO FIND A MAXIMUM OR A