NM6404 NM6403 HQFP304 - Datasheet Archive

 

PRELIMINARY ASIC & System Design Service Updated: 04 July 2000 NeuroMatrix(r) NM6404 is a high performance DSP oriented RISC

 

http://www.module.ru PRELIMINARY ASIC & System Design Service Updated: 04 July 2000 NeuroMatrix(r) NM6404 NM6404 is a high performance DSP oriented RISC processor. The architecture is based on VLIW/SIMD NMC core and includes two main units: 32-bit RISC and patented 64-bit VECTOR coprocessor to support vector operations with elements of variable bit length. NM6404 NM6404 is a binary compatible with NM6403 NM6403 processor. The NM6404 NM6404 has 2Mbit on-chip memory, two 16/32/64-bit interfaces with external SDRAM and Flash memory and two communication ports hardware compatible with TI DSP TMS320C4x. Features: · · · · · · · Clock frequency - 133 MHz (8 ns instruction cycle time) Technology used CMOS 0.25 um. HQFP304 HQFP304 package Voltage operation, Core-2.5 V, I/O-3.3/5 V Power consumption approx. 2 W Temperature range: -40 +80 ° C RISC · 5-stage pipelined 32-bit RISC · Processor instructions are 32 and 64 bit wide (usually two operations are executed by each instruction) · 2Mbit On-chip memory · Access to neighbors On-chip RAM · Two address generation units, address space 16 GB · Two 16/32/64 bit programmable interfaces with SDRAM/SRAM/DRAM/Flash ROM shared memory · 4 memory accesses at a time · Broadcast External Memory Access · 64K On-chip Boot ROM · Data format: 32-bit digit integers · 4 DMA channels · Two high speed I/O communication ports hardware compatible with those of TMS320C4x with boot-loading capability · Serial Debug Interface, JTAG compatible · Power Management VECTOR co-processor · 1-64 bit word length of vector operands and the products · · · · Data format: integer data packed into 64-bit blocks in the form of variable length words from 1 to 64 bits each Hardware support of vector-matrix or matrixmatrix multiplication 16 cycles for weight matrix reload Weight matrixes swapping On-chip saturation and threshold functions Applications: · · · · Accelerators for PCs and workstations for: - signal processing - image processing - neural net emulation - acceleration of vector and matrix calculations CDMA & TDMA Wireless Base Station Embedded systems Basic block for building large super parallel computing systems Performance: · · · Scalar operations: 133 MIPS 399 MOPS for 32 bit data Vector operations: from 133 up to 38.000+ MMACS (million multiplication and accumulation per second) I/O and interfaces: - two programmable external memory 64-bit interfaces deliver up to 2128 MB/sec throughput - I/O communication ports up to 20MB/sec throughput each Module® and NeuroMatrix® are registered trademarks of Research Center MODULE. All other trademarks are the exclusive property of their respective owners.