SMJ320F240 SGUS029A MIL-PRF-38535 SMJ320C25 SMJ320C50 XDS510 TMS320 MILPRF38535 - Datasheet Archive

 

DSP CONTROLLER SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 D Processed to MIL-PRF-38535 (QML) D High-Performance Static

 

SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 D Processed to MIL-PRF-38535 MIL-PRF-38535 (QML) D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D ­ Object Compatible With the TMS320C2xx Family ­ Source Code Compatible With SMJ320C25 SMJ320C25 ­ Upwardly Compatible With SMJ320C50 SMJ320C50 ­ 50-ns Instruction Cycle Time Memory ­ 544 Words × 16 Bits of On-Chip Data/Program Dual-Access RAM ­ 16K Words × 16 Bits of On-Chip Program Flash EEPROM ­ 224K Words × 16 Bits of Total Memory Address Reach (64K Data, 64K Program and 64K I/O, and 32K Global Memory Space) Event-Manager Module ­ 12 Compare/Pulse-Width Modulation (PWM) Channels ­ Three 16-Bit General-Purpose Timers With Six Modes, Including Continuous Upand Up/Down Counting ­ Three 16-Bit Full-Compare Units With Deadband ­ Three 16-Bit Simple-Compare Units ­ Four Capture Units (Two With Quadrature Encoder-Pulse Interface Capability) D Dual 10-Bit Analog-to-Digital Conversion D D D D D D D D D D D Module 28 Individually Programmable, Multiplexed I/O Pins Phase-Locked-Loop (PLL)-Based Clock Module Watchdog Timer Module (With Real-Time Interrupt) Serial Communications Interface (SCI) Module Serial Peripheral Interface (SPI) Module Six External Interrupts (Power Drive Protect, Reset, NMI, and Three Maskable Interrupts) Four Power-Down Modes for Low-Power Operation Scan-Based Emulation Development Tools Available: ­ Texas Instruments (TI) ANSI C Compiler, Assembler/Linker, and C-Source Debugger ­ Scan-Based Self-Emulation (XDS510 XDS510) ­ Third-Party Digital Motor Control and Fuzzy-Logic Development Support ­55°C to 125°C Operating Temperature Range, QML Processing 132-Pin Ceramic Quad Flat Package (HFP Suffix) description The SMJ320F240 SMJ320F240 is the first member of a new family of digital signal processor (DSP) controllers based on the TMS320C2xx generation of 16-bit fixed-point DSPs. This new family is optimized for digital motor/motion control applications and contains 16K words of flash memory on chip. The DSP controller combines the enhanced TMS320 TMS320 architectural design of the 'C2xLP core CPU for low-cost, high-performance processing capabilities and several advanced peripherals optimized for motor/motion control applications. These peripherals include the event manager module, which provides general-purpose timers and compare registers to generate up to 12 PWM outputs, and a dual 10-bit analog-to-digital converter (ADC), which can perform two simultaneous conversions within 6.1 µs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI and XDS510 XDS510 are trademarks of Texas Instruments Incorporated. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 On products compliant to MILPRF38535 MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. · HOUSTON, TEXAS 77251­1443 1 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Terminal Functions Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Reset and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Functional Block Diagram of the CPU . . . . . . . . . . . . . . . . . . . 30 DSP Core CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Scan-based Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SMJ320F240 SMJ320F240 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . 57 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Memory and Peripheral Interface Timing . . . . . . . . . . . . . . . . . 66 I/O Timing Variation: SPICE Simulation Results . . . . . . . . . . . 70 READY Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS and PORESET Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . XF, BIO, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Event Manager Interface . . . . . . . . . . . . . . . . . . . . . . . . PWM/CMP Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capture and QEP Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input/Output Timings . . . . . . . . . . . . . . . . . . Serial Communications Interface (SCI) I/O Timings . . . . . . . . Timing Characteristics for SCI . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Master Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . SPI Slave Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . 10-Bit Dual Analog-to-Digital Converter (ADC) . . . . . . . . . . . . ADC Input Pin Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash-write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 72 73 75 75 76 76 77 78 78 79 83 87 87 88 90 90 90 90 91 98 description (continued) Table 1. Characteristics of the 'F240 DSP Controller ON-CHIP MEMORY (WORDS) FLASH EEPROM RAM DEVICE DATA SMJ320F240 SMJ320F240 DATA/PROG 256 16K CYCLE TIME (ns) PACKAGE TYPE PIN COUNT 5 50 HFP 132­P PROG 288 POWER SUPPLY (V) The functional block diagram provides a high-level description of each component in the 'F240 DSP controller. The SMJ320F240 SMJ320F240 device is composed of three main functional units: a 'C2xx DSP core, internal memory, and peripherals. In addition to these three functional units, there are several system-level features of the 'F240 that are distributed. These system features include the memory map, device reset, interrupts, digital input/output (I/O), clock generation, and low-power operation. 2 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 A7 A6 A8 DVDD V SS A10 A9 A13 A12 A11 DS A15 A14 DVDD WE W/R PS IS STRB BR R/W V SS DVDD D3 D2 D1 D0 CV SS CVDD POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 A5 A4 A3 VSS A2 A1 A0 TMRCLK/IOPB7 TMRDIR/IOPB6 T3PWM/T3CMP/IOPB5 T2PWM/T2CMP/IOPB4 T1PWM/T1CMP/IOPB3 VSS DVDD PWM9/CMP9/IOPB2 PWM8/CMP8/IOPB1 PWM7/CMP7/IOPB0 PWM6/CMP6 PWM5/CMP5 PWM4/CMP4 PWM3/CMP3 PWM2/CMP2 PWM1/CMP1 DVDD VSS ADCIN8/IOPA3 ADCIN9/IOPA2 ADCIN10 ADCIN10 ADCIN11 ADCIN11 VSSA VREFLO VREFHI VCCA ADCIN12 ADCIN12 ADCIN6 ADCIN7 ADCIN15 ADCIN15 ADCIN14 ADCIN14 ADCIN13 ADCIN13 ADCIN2 ADCIN3 ADCIN4 ADCIN5 ADCIN1/IOPA1 ADCIN0/IOPA0 CAP2/QEP2/IOPC5 CAP3/IOPC6 CAP4/IOPC7 V SS CLKOUT/IOPC1 XF/IOPC2 BIO/IOPC3 CAP1/QEP1/IOPC4 DVDD ADCSOC/IOPC0 CVDD V SS XINT3/IO OSCBYP XTAL2 XTAL1/CLKIN V SS 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118 131 129 127 125 123 121 119 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 PDPINT XINT1 XINT2/IO VSS DVDD D9 D10 D11 D12 D13 D14 D15 VSS TCK TDI TRST TMS TDO RS READY MP/MC EMU0 EMU1/OFF NMI PORESET RESERVED SCIRXD/IO SCITXD/IO SPISIMO/IO VSS DVDD SPISOMI/IO SPICLK/IO VCCP/WDDIS 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SPISTE/IO D7 D8 D4 V SS D6 D5 pinout 3 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 Terminal Functions TERMINAL NAME NO. TYPE DESCRIPTION EXTERNAL INTERFACE DATA/ADDRESS SIGNALS A0 (LSB) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 (MSB) 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 (MSB) 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 DS PS IS O/Z Parallel address bus A0 [least significant bit (LSB)] through A15 [most significant bit (MSB)]. A15­A0 are multiplexed to address external data/program memory or I/O. A15­A0 are placed in the high-impedance state when EMU1/OFF is active low and hold their previous states in power-down modes. I/O/Z Parallel data bus D0 (LSB) through D15 (MSB). D15­D0 are multiplexed to transfer data between the SMJ320F240 SMJ320F240 and external data/program memory and I/O space (devices). D15­D0 are placed in the high-impedance state when not outputting, when in power-down mode, when reset (RS) is asserted, or when EMU1/OFF is active low. 129 131 130 O/Z Data, program, and I/O space select signals. DS, PS, and IS are always high unless low-level asserted for communication to a particular external space. They are placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. READY 36 I Data ready. READY indicates that an external device is prepared for the bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. R/W 4 O/Z Read/write signal. R/W indicates transfer direction during communication to an external device. It is normally in read mode (high), unless low level is asserted for performing a write operation. It is placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. STRB 6 O/Z Strobe. STRB is always high unless asserted low to indicate an external bus cycle. It is placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. EXTERNAL INTERFACE CONTROL SIGNALS WE 1 O/Z Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15­D0). Data can be latched by an external device on the rising edge of WE. WE is active on all external program, data, and I/O writes. WE goes in the high-impedance state following reset and when EMU1/OFF is active low. W/R 132 O/Z Write/read. W/R is an inverted form of R/W and can connect directly to the output enable of external devices. W/R is placed in the high-impedance state following reset and when EMU1/OFF is active low. I = input, O = output, Z = high impedance 4 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 Terminal Functions (Continued) TERMINAL NAME NO. TYPE DESCRIPTION EXTERNAL INTERFACE CONTROL SIGNALS (CONTINUED) BR VCCP/WDDIS 5 50 O/Z Bus request. BR is asserted during access of external global data memory space. BR can be used to extend the data memory address space by up to 32K words. BR goes in the high-impedance state during reset, power down, and when EMU1/OFF is active low. I Flash-programming voltage supply. If VCCP = 5 V, then WRITE/ERASE can be made to the ENTIRE on-chip flash memory block-that is, for programming the flash. If VCCP = 0 V, then WRITE/ERASE of the flash memory is not allowed, thereby protecting the entire memory block from being overwritten. WDDIS also functions as a hardware watchdog disable. The watchdog timer is disabled when VCCP/WDDIS = 5 V and bit 6 in WDCR is set to 1. ADC INPUTS (UNSHARED) ADCIN2 74 I ADCIN3 75 I ADCIN4 76 I ADCIN5 77 I ADCIN6 78 I ADCIN7 79 I ADCIN10 ADCIN10 89 I ADCIN11 ADCIN11 88 I ADCIN12 ADCIN12 83 I ADCIN13 ADCIN13 82 I ADCIN14 ADCIN14 81 I ADCIN15 ADCIN15 80 I Analog inp ts to the first ADC inputs Analog inp ts to the second ADC inputs BIT I/O AND SHARED FUNCTIONS PINS ADCIN0/IOPA0 72 I/O Bidirectional digital I/O. Analog input to the first ADC. ADCIN0/IOPA0 is configured as a digital input by all device resets. ADCIN1/IOPA1 73 I/O Bidirectional digital I/O. Analog input to the first ADC. ADCIN1/IOPA1 is configured as a digital input by all device resets. ADCIN9/IOPA2 90 I/O Bidirectional digital I/O. Analog input to the second ADC. ADCIN9/IOPA2 is configured as a digital input by all device resets. ADCIN8/IOPA3 91 I/O Bidirectional digital I/O. Analog input to the second ADC. ADCIN8/IOPA3 is configured as a digital input by all device resets. PWM7/CMP7/IOPB0 100 I/O/Z Bidirectional digital I/O. Simple compare/PWM 1 output. The state of PWM7/CMP7/IOPB0 is determined by the simple compare/PWM and the simple action control register (SACTR). It goes to the high-impedance state when unmasked PDPINT goes active low. PWM7/CMP7/IOPB0 is configured as a digital input by all device resets. PWM8/CMP8/IOPB1 101 I/O/Z Bidirectional digital I/O. Simple compare/PWM 2 output. The state of PWM8/CMP8/IOPB1 is determined by the simple compare/PWM and the SACTR. It goes to the high-impedance state when unmasked PDPINT goes active low. PWM8/CMP8/IOPB1 is configured as a digital input by all device resets. PWM9/CMP9/IOPB2 102 I/O/Z Bidirectional digital I/O. Simple compare/PWM 3 output. The state of PWM9/CMP9/IOPB2 is determined by the simple compare/PWM and SACTR. It goes to the high-impedance state when unmasked PDPINT goes active low. PWM9/CMP9/IOPB2 is configured as a digital input by all device resets. I = input, O = output, Z = high impedance POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 5 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 Terminal Functions (Continued) TERMINAL NAME NO. TYPE DESCRIPTION BIT I/O AND SHARED FUNCTIONS PINS (CONTINUED) T1PWM/T1CMP/ IOPB3 105 I/O/Z Bidirectional digital I/O. Timer 1 compare output. T1PWM/T1CMP/IOPB3 goes to the high-impedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. T2PWM/T2CMP/ IOPB4 106 I/O/Z Bidirectional digital I/O. Timer 2 compare output. T2PWM/T2CMP/IOPB4 goes to the highimpedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. T3PWM/T3CMP/ IOPB5 107 I/O/Z Bidirectional digital I/O. Timer 3 compare output. T3PWM/T3CMP/IOPB5 goes to the high-impedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. TMRDIR/IOPB6 108 I/O Bidirectional digital I/O. Direction signal for the timers. Up-counting direction if TMRDIR/IOPB6 is low, down-counting direction if this pin is high. This pin is configured as a digital input by all device resets. TMRCLK/IOPB7 109 I/O Bidirectional digital I/O. External clock input for general-purpose timers. This pin is configured as a digital input by all device resets. ADCSOC/IOPC0 63 I/O Bidirectional digital I/O. External start of conversion input for ADC. This pin is configured as a digital input by all device resets. CAP1/QEP1/IOPC4 67 I/O Bidirectional digital I/O. Capture 1 or QEP 1 input. This pin is configured as a digital input by all device resets. CAP2/QEP2/IOPC5 68 I/O Bidirectional digital I/O. Capture 2 or QEP 2 input. This pin is configured as a digital input by all device resets. CAP3/IOPC6 69 I/O Bidirectional digital I/O. Capture 3 input. This pin is configured as a digital input by all device resets. CAP4/IOPC7 70 I/O Bidirectional digital I/O. Capture 4 input. This pin is configured as a digital input by all device resets. XF/IOPC2 65 I/O Bidirectional digital I/O. External flag output (latched software-programmable signal). XF is used for signaling other processors in multiprocessing configurations or as a general-purpose output pin. This pin is configured as an external flag output by all device resets. BIO/IOPC3 66 I/O Bidirectional digital I/O. Branch control input. BIO is polled by the BIOZ instruction. If BIO is low, the CPU executes a branch. If BIO is not used, it should be pulled high. This pin is configured as a branch-control input by all device resets. CLKOUT/IOPC1 64 I/O Bidirectional digital I/O. Clock output. Clock output is selected by the CLKSRC bits in the SYSCR register. This pin is configured as a DSP clock output by a power-on reset. SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS SCITXD/IO 44 I/O SCI asynchronous serial port transmit data, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. SCIRXD/IO 43 I/O SCI asynchronous serial port receive data, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. I = input, O = output, Z = high impedance 6 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 Terminal Functions (Continued) TERMINAL NAME NO. TYPE DESCRIPTION SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS SPISIMO/IO 45 I/O SPI slave in, master out , or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. SPISOMI/IO 48 I/O SPI slave out, master in, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. SPICLK/IO 49 I/O SPI clock, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. SPISTE/IO 51 I/O SPI slave transmit enable (optional), or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. COMPARE SIGNALS PWM1/CMP1 PWM2/CMP2 PWM3/CMP3 PWM4/CMP4 PWM5/CMP5 PWM6/CMP6 94 95 96 97 98 99 O/Z Compare units compare or PWM outputs. The state of these pins is determined by the compare/PWM and the full action control register (ACTR). CMP1­CMP6 go to the high-impedance state when unmasked PDPINT goes active low, and when reset (RS) is asserted. INTERRUPT AND MISCELLANEOUS SIGNALS RS 35 I/O Reset input. RS causes the SMJ320F240 SMJ320F240 to terminate execution and sets PC = 0. When RS is brought to a high level, execution begins at location zero of program memory. RS affects (or sets to zero) various registers and status bits. In addition, RS is a bidirectional (open-drain output) pin. If RS is left undriven, then a 20-K pull-up resistor should be used. MP/MC 37 I MP/MC (microprocessor/microcomputer) select. If MP/MC is low, internal program memory is selected. If it is high, external program memory is selected. NMI 40 I Nonmaskable interrupt. When NMI is activated, the device is interrupted regardless of the state of the INTM bit of the status register. NMI has programmable polarity. PORESET 41 I Power-on reset. PORESET causes the SMJ320F240 SMJ320F240 to terminate execution and sets PC = 0. When PORESET is brought to a high level, execution begins at location zero of program memory. PORESET affects (or sets to zero) the same registers and status bits as RS. In addition, PORESET initializes the PLL control registers. XINT1 53 I External user interrupt no. 1 XINT2/IO 54 I/O External user interrupt no. 2. General-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. XINT3/IO 55 I/O External user interrupt no. 3. General-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. PDPINT 52 I Maskable power-drive protection interrupt. If PDPINT is unmasked and it goes active low, the timer compare outputs immediately go to the high-impedance state. CLOCK SIGNALS XTAL2 57 O XTAL1/CLKIN 58 I/Z OSCBYP 56 I I = input, O = output, Z = high impedance PLL oscillator output. XTAL2 is tied to one side of a reference crystal when the device is in PLL mode (CLKMD[1:0] = 1x, CKCR0.7­6). This pin can be left unconnected in oscillator bypass mode (OSCBYP VIL). This pin goes in the high-impedance state when EMU1/OFF is active low. PLL oscillator input. XTAL1/CLKIN is tied to one side of a reference crystal in PLL mode (CLKMD[1:0] = 1x, CKCR0.7­6), or is connected to an external clock source in oscillator bypass mode (OSCBYP VIL). Bypass oscillator if low POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 7 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 Terminal Functions (Continued) TERMINAL NAME NO. TYPE DESCRIPTION SUPPLY SIGNALS CVSS 8 I Digital core logic ground reference VSS 3 14 20 29 46 59 61 71 92 104 113 120 I Digital logic gro nd reference ground VSSA 87 I Analog ground reference DVDD (See Note 1) 2 13 21 47 62 93 103 121 I Digital I/O logic supply voltage I Digital core logic supply voltage s ppl oltage CVDD (See Note 1) 7 60 VCCA VREFHI 84 I Analog supply voltage 85 I ADC analog voltage reference high VREFLO 86 I ADC analog voltage reference low TEST SIGNALS TCK 30 I IEEE standard test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test data register of the 'C2xx core on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI 31 I IEEE standard test data input (TDI). TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 34 O/Z IEEE standard test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state when OFF is active low. TMS 33 I IEEE standard test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK. I = input, O = output, Z = high impedance NOTE 1: VDD refers to supply voltage types CVDD (digital core supply voltage), DVDD (digital I/O supply voltage), and VDDP (programming voltage supply). All voltages are measured with respect to VSS. 8 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 Terminal Functions (Continued) TERMINAL NAME NO. TYPE DESCRIPTION TEST SIGNALS (CONTINUED) TRST 32 I IEEE standard test reset. TRST, when active low, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. EMU0 38 I/O/Z Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output through the scan. I/O/Z Emulator pin 1/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output through JTAG scan. When TRST is driven low, this pin is configured as OFF. When EMU1/OFF is active low, it puts all output drivers in the high-impedance state. OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications); therefore, for OFF condition, the following conditions apply: TRST = low, EMU0 = high, EMU1/OFF = low. EMU1/OFF 39 RESERVED 42 I Reserved for test. This pin has an internal pulldown and must be left unconnected for the 'F240. I = input, O = output, Z = high impedance POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 9 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 functional block diagram Data Bus 7 Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á Á Á ÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ Á ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á DARAM B0 ÁÁ Flash EEPROM DARAM B1/B2 Program Bus Memory Control Á Á Á Á Interrupts Initialization Program Controller ARAU Input Shifter ALU TREG Auxiliary Registers Accumulator PREG MemoryMapped Registers Output Shifter Event Manager Multiplier Status/ Control Registers 41 Software Wait-State Generation 'C2xx CPU Instruction Register External Memory Interface ÁÁÁ Test/ Emulation Product Shifter GeneralPurpose Timers Compare Units Capture/ Quadrature Encoder Pulse (QEP) 4 9 4 PDPINT 4 3 Clock Module 20 System-Interface Module Interrupts Digital Input/Output Reset Peripheral Bus Dual 10-Bit Analogto-Digital Converter SerialPeripheral Interface 16 10 POST OFFICE BOX 1443 4 SerialCommunications Interface 2 · HOUSTON, TEXAS 77251­1443 Watchdog Timer SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 device memory map The SMJ320F240 SMJ320F240 implements three separate address spaces for program memory, data memory, and I/O. Each space accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to 32K words at the top of the address range can be defined to be external global memory in increments of powers of two, as specified by the contents of the global memory allocation register (GREG). Access to global memory is arbitrated using the global memory bus request (BR) signal. On the 'F240, the first 96 (0­5Fh) data memory locations are either allocated for memory-mapped registers or are reserved. This memory-mapped register space contains various control and status registers including those for the CPU. All the on-chip peripherals of the 'F240 device are mapped into data memory space. Access to these registers is made by the CPU instructions addressing their data-memory locations. Figure 1 shows the memory map. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 11 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 device memory map (continued) Program Hex 0000 003F 0040 Interrupts (External) Program Hex 0000 003F 0040 Interrupts (On-Chip) On-Chip Flash EEPROM (8 x 2K Segments) External Data Hex 0000 005F 0060 On-Chip DARAM B2 007F 0080 3FFF 4000 Reserved External FDFF FE00 On-Chip DARAM B0 (CNF = 1) or FEFF External (CNF = 0) FDFF FE00 On-Chip DARAM B0 (CNF = 1) or External (CNF = 0) FEFF FF00 FF00 Reserved Reserved FFFF Flash memory includes address range 0000h­003Fh FFFF MP/MC = 1 Microprocessor Mode Memory-Mapped Registers and Reserved MP/MC = 0 Microcomputer Mode 01FF 0200 On-Chip DARAM B0 (CNF = 0) or Reserved (CNF = 1) 02FF 0300 On-Chip DARAM B1 03FF 0400 Reserved 07FF 0800 Illegal 6FFF 7000 I/O Hex 0000 73FF 7400 External 743F 7440 FEFF Reserved 7FFF 8000 Flash Control Mode Register FFFF FF10 Reserved FFFE Wait-state Generator Control Register Figure 1. SMJ320F240 SMJ320F240 Memory Map 12 Reserved Illegal FF0E FFFF Peripheral Memory-Mapped Registers (Event Manager) 77FF 7800 FF00 FF0F Peripheral MemoryMapped Registers (System, WD, ADC, SPI, SCI, Interrupts, I/O) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 External SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 peripheral memory map The SMJ320F240 SMJ320F240 system and peripheral control register frame contains all the data, status, and control bits to operate the system and peripheral modules on the device (excluding the event manager). Hex Reserved Interrupt-Mask Register Global-Memory Allocation Register 0005 Memory-Mapped Registers and Reserved Interrupt Flag Register 0006 Emulation Registers and Reserved 0007 On-Chip DARAM B2 Hex 0000 005F 0060 007F 0080 02FF 0300 005F Illegal 7000­700F System Configuration and Control Registers 7010­701F Watchdog Timer and PLL Control Registers 7020­702F ADC 7030­703F Reserved 01FF 0200 0000 0003 0004 On-Chip DARAM B0 (CNF = 0) Reserved (CNF = 1) On-Chip DARAM B1 SPI 7040­704F SCI 7050­705F Illegal 7060­706F External-Interrupt Registers 7070­707F Illegal 7080­708F Digital-I/O Control Registers 7090­709F Illegal 70A0­73FF General-Purpose Timer Registers 7400­740C Reserved 740D­7410 Compare, PWM, and Deadband Registers 03FF 0400 7411­741C Reserved 07FF 0800 6FFF 7000 73FF 7400 743F 7440 77FF 7800 7FFF 8000 Illegal Peripheral Frame 1 Peripheral Frame 2 Reserved Illegal Reserved 7420­7426 Reserved 7427­742B Interrupt Mask, Vector and Flag Registers 742C­7434 Reserved FFFF 741D­741F Capture & QEP Registers External 7435­743F Figure 2. Peripheral Memory Map POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 13 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 digital I/O and shared pin functions The 'F240 has a total of 28 pins shared between primary functions and I/Os. These pins are divided into two groups: D Group1 - Primary functions shared with I/Os belonging to dedicated I/O ports, Port A, Port B, and Port C. D Group2 - Primary functions belonging to peripheral modules which also have a built-in I/O feature as a secondary function (for example, SCI, SPI, external interrupts, and PLL clock modules). group1 shared I/O pins The control structure for Group1 type shared I/O pins is shown in Figure 3. The only exception to this configuration is the CLKOUT/IOPC1 pin. In Figure 3, each pin has three bits that define its operation: D Mux control bit - this bit selects between the primary function (1) and I/O function (0) of the pin. D I/O direction bit - if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines whether the pin is an input (0) or an output (1). D I/O data bit - if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected is an input, data is read from this bit; if the direction selected is an output, data is written to this bit. The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers. IOP Data Bit (Read/Write) In Primary Function Out IOP DIR Bit 0 = Input 1 = Output Note: When the MUX control bit = 1, the primary function is selected in all cases except for the following pins: 1. XF/IOPC2 (0 = Primary Function) 2. BIO/IOPC3 (0 = Primary Function) 0 Primary Function or I/O Pin 1 MUX Control Bit 0 = I/O Function 1 = Primary Function Pin Figure 3. Shared Pin Configuration A summary of Group1 pin configurations and associated bits is shown in Table 2. 14 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 group1 shared I/O pins (continued) Table 2. Group1 Shared Pin Configurations I/O PORT DATA AND DIRECTION MUX CONTROL REGISTER (name.bit #) (CRx.n = 1) (CRx.n = 0) REGISTER DATA BIT # DIR BIT # 72 OCRA.0 ADCIN0 IOPA0 PADATDIR 0 8 73 OCRA.1 ADCIN1 IOPA1 PADATDIR 1 9 90 OCRA.2 ADCIN9 IOPA2 PADATDIR 2 10 91 OCRA.3 ADCIN8 IOPA3 PADATDIR 3 11 100 OCRA.8 PWM7/CMP7 IOPB0 PBDATDIR 0 8 101 OCRA.9 PWM8/CMP8 IOPB1 PBDATDIR 1 9 102 OCRA.10 PWM9/CMP9 IOPB2 PBDATDIR 2 10 105 OCRA.11 T1PWM/T1CMP IOPB3 PBDATDIR 3 11 106 OCRA.12 T2PWM/T2CMP IOPB4 PBDATDIR 4 12 107 OCRA.13 T3PWM/T3CMP IOPB5 PBDATDIR 5 13 108 OCRA.14 TMRDIR IOPB6 PBDATDIR 6 14 109 OCRA.15 TMRCLK IOPB7 PBDATDIR 7 15 63 OCRB.0 ADCSOC IOPC0 PCDATDIR 0 8 64 SYSCR.7­6 PIN # PIN FUNCTION SELECTED 00 IOPC1 PCDATDIR 1 9 01 WDCLK - - - 10 SYSCLK - - - 11 CPUCLK - - - 10 65 OCRB.2 IOPC2 XF PCDATDIR 2 66 OCRB.3 IOPC3 BIO PCDATDIR 3 11 67 OCRB.4 CAP1/QEP1 IOPC4 PCDATDIR 4 12 68 OCRB.5 CAP2/QEP2 IOPC5 PCDATDIR 5 13 69 OCRB.6 CAP3 IOPC6 PCDATDIR 6 14 CAP4 IOPC7 PCDATDIR 7 15 70 OCRB.7 Valid only if the I/O function is selected on the pin. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 15 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 group2 shared I/O pins Group2 shared pins belong to peripherals that have built-in general-purpose I/O capability. Control and configuration for these pins are achieved by setting the appropriate bits within the control and configuration registers of the peripherals. Table 3 lists the Group2 shared pins. Table 3. Group2 Shared Pin Configurations PIN # PRIMARY FUNCTION REGISTER ADDRESS PERIPHERAL MODULE 43 SCIRXD SCIPC2 705Eh SCI 44 SCITXD SCIPC2 705Eh SCI 45 SPISIMO SPIPC2 704Eh SPI 48 SPISOMI SPIPC2 704Eh SPI 49 SPICLK SPIPC1 704Dh SPI 51 SPISTE SPIPC1 704Dh SPI 54 XINT2 XINT2CR 7078h External Interrupts 55 XINT3 XINT3CR 707Ah External Interrupts digital I/O control registers Table 4 lists the registers available to the digital I/O module. As with other 'F240 peripherals, the registers are memory-mapped to the data space. Table 4. Addresses of Digital I/O Control Registers ADDRESS REGISTER NAME 7090h OCRA I/O mux control register A 7092h OCRB I/O mux control register B 7098h PADATDIR I/O port A data and direction register 709Ah PBDATDIR I/O port B data and direction register 709Ch PCDATDIR I/O port C data and direction register device reset and interrupts The SMJ320F240 SMJ320F240 software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The 'F240 recognizes three types of interrupt sources: D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any other executing functions. All maskable interrupts are disabled until the reset service routine enables them. D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two types: ­ ­ 16 External interrupts are generated by one of five external pins corresponding to the interrupts XINT1, XINT2, XINT3, PDPINT, and NMI. The first four can be masked both by dedicated enable bits and by the CPU's interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. NMI, which is not maskable, takes priority over peripheral interrupts and software-generated interrupts. It can be locked out only by an already executing NMI or a reset. Peripheral interrupts are initiated internally by these on-chip peripheral modules: the event manager, SPI, SCI, watchdog/real-time interrupt (WD/RTI), and ADC. They can be masked both by enable bits for each event in each peripheral and by the CPU's IMR, which can mask each maskable interrupt line at the DSP core. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 device reset and interrupts (continued) D Software-generated interrupts for the 'F240 device include: ­ The INTR instruction. This instruction allows initialization of any 'F240 interrupt with software. Its operand indicates to which interrupt vector location the CPU branches. This instruction globally disables maskable interrupts (sets the INTM bit to 1). ­ The NMI instruction. This instruction forces a branch to interrupt vector location 24h, the same location used for the nonmaskable hardware interrupt NMI. NMI can be initiated by driving the NMI pin low or by executing an NMI instruction. This instruction globally disables maskable interrupts. ­ The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU branches to the interrupt service routine, that routine can be interrupted by the maskable hardware interrupts. ­ An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction. reset The reset operation ensures an orderly startup sequence for the device. There are five possible causes of a reset, as shown in Figure 4. Three of these causes are internally generated; the other two causes, the RS and PORESET pins, are controlled externally. To Device Watchdog Timer Reset Software-Generated Reset Illegal Address Reset Reset (RS) Pin Active Power-On Reset (PORESET) Pin Active Reset Signal To Reset Out Figure 4. Reset Signals The five possible reset signals are generated as follows: D Watchdog timer reset. A watchdog-timer-generated reset occurs if the watchdog timer overflows or an improper value is written to either the watchdog key register or the watchdog control register. (Note that when the device is powered on, the watchdog timer is automatically active.) D Software-generated reset. This is implemented with the system control register (SYSCR). Clearing the RESET0 bit (bit 14) or setting the RESET1 bit (bit 15) causes a system reset. D Illegal address reset. The system and peripheral module control register frame address map contains unimplemented address locations in the ranges labeled illegal. Any access to an address located in the Illegal ranges generate an illegal-address reset. D Reset pin active. To generate an external reset pulse on the RS pin, a low-level pulse duration of as little as a few nanoseconds is usually effective; however, pulses of one SYSCLK cycle are necessary to ensure that the device recognizes the reset signal. D Power-on reset pin active. To generate a power-on reset pulse on the PORESET pin, a low-level pulse of one SYSCLK cycle is necessary to ensure that the device recognizes the reset signal. Once a reset source is activated, the external RS pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the SMJ320F240 SMJ320F240 device to reset external system components. Additionally, if a brown-out condition (VCC < VCCmin for several microseconds causing PORESET to go low) occurs or the RS pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 17 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 reset (continued) The occurrence of a reset condition causes the SMJ320F240 SMJ320F240 to terminate program execution and affects various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are affected by a reset are initialized to their reset state. In the case of a power-on reset, the PLL control registers are initialized to zero. The program needs to recognize power-on resets and configure the PLL for correct operation. After a reset, the program can check the power-on reset flag (PORST flag, SYSSR.15), the illegal address flag (ILLADR flag, SYSSR.12), the software reset flag (SWRST flag, SYSSR.10), and the watchdog reset flag (WDRST flag, SYSSR.9) to determine the source of the reset. A reset does not clear these flags. RS and PORESET must be held low until the clock signal is valid and VCC is within the operating range. In addition, PORESET must be driven low when VCC drops below the minimum operating voltage. hardware-generated interrupts All the hardware interrupt lines of the DSP core are given a priority rank from 1 to 10 (1 being highest). When more than one of these hardware interrupts is pending acknowledgment, the interrupt of highest rank gets acknowledged first. The others are acknowledged in order after that. Of those ten lines, six are for maskable interrupt lines (INT1­INT6) and one is for the nonmaskable interrupt (NMI) line. INT1­INT6 and NMI have the priorities shown in Table 5. Table 5. Interrupt Priorities at the Level of the DSP Core INTERRUPT PRIORITY AT THE DSP CORE RESET 1 TI RESERVED 2 NMI 3 INT1 4 INT2 5 INT3 6 INT4 7 INT5 8 INT6 9 TI RESERVED 10 TI Reserved means that the address space is reserved for Texas Instruments. The inputs to these lines are controlled by the system module and the event manager as summarized in Table 6 and shown in Figure 5. Table 6. Interrupt Lines Controlled by the System Module and Event Manager PERIPHERAL INTERRUPT LINES System Module Event Manager 18 INT1 INT5 INT6 INT2 INT3 INT4 POST OFFICE BOX 1443 NMI · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 hardware-generated interrupts (continued) DSP Core Address Lines 5­1 IACK INT6 INT5 INT4 INT3 INT2 INT1 NMI 5 NC Address Lines 5­1 IACK NC NC INT6 INT5 INT4 INT3 INT2 INT1 NMI System Module INTC INTB INTA Event Manager Figure 5. DSP Interrupt Structure At the level of the system module and the event manager, each of the maskable interrupt lines (INT1­INT6) is connected to multiple maskable interrupt sources. Sources connected to interrupt line INT1 are called Level 1 interrupts; sources connected to interrupt line INT2 are called Level 2 interrupts; and so on. For each interrupt line, the multiple sources also have a set priority ranking. The source with the highest priority has its interrupt request responded to by the DSP core first. Figure 6 shows the sources and priority ranking for the interrupts controlled by the system module. For each interrupt chain, the interrupt source of highest priority is at the top. Priority decreases from the top of the chain to the bottom. Figure 7 shows the interrupt sources and priority ranking for the event manager interrupts. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 19 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 hardware-generated interrupts (continued) To DSP INT6 To DSP INT5 NC NC NC To DSP INT1 To DSP NMI INT6 INT5 INT4 INT3 INT2 INT1 NMI System Module IRQ6 IACK6 IRQ5 IACK5 IRQ4 IACK4 IRQ3 IACK3 IRQ2 IACK2 NC NC NC NC NC IRQ1 IACK1 NC Dual ADC Interrupt SPI Interrupt (low priority) System-Module External Interrupt XINT1 (high priority) System-Module External Interrupt XINT1 (low priority) SCI Receiver Interrupt (low priority) System-Module External Interrupt XINT2 (high priority) System-Module External Interrupt XINT2 (low priority) SCI Transmitter Interrupt (low priority) System-Module External Interrupt XINT3 (high priority) System-Module External Interrupt XINT3 (low priority) Watchdog Timer Interrupt SPI Interrupt (high priority) SCI Receiver Interrupt (high priority) SCI Transmitter Interrupt (high priority) Legend: NC = No connection IACK = interrupt acknowledge IRQ = interrupt request Figure 6. System-Module Interrupt Structure 20 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 IRQ_NMI IACK_NMI System-Module External Interrupt NMI SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 hardware-generated interrupts (continued) To DSP INT4 To DSP INT3 To DSP INT2 INTC INTB INTA Event Manager IRQC IACKC IRQB IACKB IRQA IACKA Capture 1 Interrupt Power-Drive Protection Interrupt Capture 2 Interrupt Timer 2 Compare Interrupt Compare1 Interrupt Capture 3 Interrupt Timer 2 Underflow Interrupt Compare 2 Interrupt Capture 4 Interrupt Timer 2 Overflow Interrupt Compare 3 Interrupt Timer 3 Period Interrupt Legend: Timer 2 Period Interrupt SimpleCompare 1 Interrupt Timer 3 Compare Interrupt SimpleCompare 2 Interrupt Timer 3 Underflow Interrupt SimpleCompare 3 Interrupt Timer 3 Overflow Interrupt Timer 1 Period Interrupt IACK = Interrupt acknowledge IRQ = Interrupt request Timer 1 Compare Interrupt Timer 1 Underflow Interrupt Timer 1 Overflow Interrupt Figure 7. Event-Manager Interrupt Structure POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 21 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 hardware-generated interrupts (continued) Each of the interrupt sources has its own control register with a flag bit and an enable bit. When an interrupt request is received, the flag bit in the corresponding control register is set. If the enable bit is also set, a signal is sent to arbitration logic, which can simultaneously receive similar signals from one or more of the other control registers. The arbitration logic compares the priority level of competing interrupt requests, and it passes the interrupt of highest priority to the CPU. The corresponding flag is set in the interrupt flag register (IFR), indicating that the interrupt is pending. The CPU then must decide whether to acknowledge the request. Maskable hardware interrupts are acknowledged only after certain conditions are met: D Priority is highest. When more than one hardware interrupt is requested at the same time, the 'F240 services them according to the set priority ranking. D INTM bit is 0. The interrupt mode (INTM) bit, bit 9 of status register ST0, enables or disables all maskable interrupts: ­ When INTM = 0, all unmasked interrupts are enabled. ­ When INTM = 1, all unmasked interrupts are disabled. INTM is set to 1 automatically when the CPU acknowledges an interrupt (except when initiated by the TRAP instruction) and at reset. It can be set and cleared by software. D IMR mask bit is 1. Each of the maskable interrupt lines has a mask bit in the interrupt mask register (IMR). To unmask an interrupt line, set its IMR bit to 1. When the CPU acknowledges a maskable hardware interrupt, it jams the instruction bus with the INTR instruction. This instruction forces the PC to the appropriate address from which the CPU fetches the software vector. This vector leads to an interrupt service routine. Usually, the interrupt service routine reads the peripheral-vector-address offset from the peripheral-vectoraddress register (see Table 7) to branch to code that is meant for the specific interrupt source that initiated the interrupt request. The 'F240 includes a phantom-interrupt vector offset (0000h), which is a system interrupt integrity feature that allows a controlled exit from an improper interrupt sequence. If the CPU acknowledges a request from a peripheral when, in fact, no peripheral has requested an interrupt, the phantom-interrupt vector is read from the interrupt-vector register. Table 7 summarizes the interrupt sources, overall priority, vector address/offset, source, and function of each interrupt available on the SMJ320F240 SMJ320F240. 22 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 hardware-generated interrupts (continued) Table 7. 'F240 Interrupt Locations and Priorities OVERALL PRIORITY DSP-CORE INTERRUPT, AND ADDRESS PERIPHERAL VECTOR ADDRESS 1 Highest RS 0000h N/A RESERVED 2 INT7 0026h N/A NMI 3 NMI 0024h N/A XINT1 XINT2 XINT3 4 5 6 SPIINT 7 INTERRUPT NAME RS N Core, SD External, system reset (RESET) N/A N DSP Core Emulator trap 0002h N Core, SD External user interrupt Y SD High-priority external user interrupts 0005h SYSIVR (701Eh) MASKABLE? 'F240 SOURCE PERIPHERAL MODULE 0001h 0011h 001Fh INT1 0002h PERIPHERAL VECTOR ADDRESS OFFSET Y SPI High-priority SPI interrupt 0006h Y SCI SCI receiver interrupt (high priority) SCI SCI transmitter interrupt (high priority) Watchdog timer interrupt FUNCTION INTERRUPT RXINT 8 TXINT 9 0007h Y WDTINT 10 0010h Y WDT PDPINT 11 0020h Y External CMP1INT 12 0021h Y EV.CMP1 Full Compare 1 interrupt CMP2INT 13 0022h Y EV.CMP2 Full Compare 2 interrupt CMP3INT 14 0023h Y EV.CMP3 Full Compare 3 interrupt SCMP1INT 15 0024h Y EV.CMP4 Simple compare 1 interrupt SCMP2INT 16 0025h Y EV.CMP5 Simple compare 2 interrupt SCMP3INT 17 0026h Y EV.CMP6 Simple compare 3 interrupt TPINT1 18 0027h Y EV.GPT1 Timer1-period interrupt TCINT1 19 0028h Y EV.GPT1 Timer1-compare interrupt TUFINT1 20 0029h Y EV.GPT1 Timer1-underflow interrupt TOFINT1 21 002Ah Y EV.GPT1 Timer1-overflow interrupt TPINT2 22 002Bh Y EV.GPT2 Timer2-period interrupt TCINT2 23 002Ch Y EV.GPT2 Timer2-compare interrupt 002Dh Y EV.GPT2 Timer2-underflow interrupt 002Eh Y EV.GPT2 Timer2-overflow interrupt 002Fh Y EV.GPT3 Timer3-period interrupt (System) INT2 0004h (Event ( e Manager Group A) EVIVRA (7432h) INT3 0006h Power-drive protection Int. TUFINT2 24 TOFINT2 25 TPINT3 26 TCINT3 27 0030h Y EV.GPT3 Timer3-compare interrupt TUFINT3 28 0031h Y EV.GPT3 Timer3-underflow interrupt TOFINT3 29 0032h Y EV.GPT3 Timer3-overflow interrupt CAPINT1 30 INT4 0033h Y EV.CAP1 Capture 1 interrupt CAPINT2 31 0008h 0034h Y EV.CAP2 Capture 2 interrupt CAPINT3 32 0035h Y EV.CAP3 Capture 3 interrupt CAPINT4 33 (Event Manager Group C) 0036h Y EV.CAP4 Capture 4 interrupt ( (Event Manager M Group B) EVIVRB (7433h) EVIVRC (7434h) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 23 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 hardware-generated interrupts (continued) Table 7. 'F240 Interrupt Locations and Priorities (Continued) SPIINT OVERALL PRIORITY DSP-CORE INTERRUPT, AND ADDRESS 34 INTERRUPT NAME PERIPHERAL VECTOR ADDRESS OFFSET MASKABLE? 'F240 SOURCE PERIPHERAL MODULE INT5 0005h Y SPI Low-priority SPI interrupt 0006h Y SCI SCI receiver interrupt (low priority) 0007h Y SCI SCI transmitter interrupt (low priority) SYSIVR 0004h Y ADC Analog-to-digital interrupt 0001h 0011h 001Fh Y Y Y External pins DSP Core PERIPHERAL VECTOR ADDRESS SYSIVR (701Eh) RXINT 35 TXINT 36 ADCINT 37 XINT1 XINT2 XINT3 38 39 40 000Ch (System) (701Eh) RESERVED 41 000Eh N/A Y TRAP N/A 0022h N/A N/A 000Ah (System) INT6 FUNCTION INTERRUPT Low riority Low-priority external user interrupts Used for analysis TRAP instruction vector external interrupts The 'F240 has five external interrupts. These interrupts include: D XINT1. Type A interrupt. The XINT1 control register (at 7070h) provides control and status for this interrupt. XINT1 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a general-purpose input pin. XINT1 can also be programmed to trigger an interrupt on either the rising or the falling edge. D NMI. Type A interrupt. The NMI control register (at 7072h) provides control and status for this interrupt. NMI is a nonmaskable external interrupt or a general-purpose input pin. NMI can also be programmed to trigger an interrupt on either the rising or the falling edge. D XINT2. Type C interrupt. The XINT2 control register (at 7078h) provides control and status for this interrupt. XINT2 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a general-purpose I/O pin. XINT2 can also be programmed to trigger an interrupt on either the rising or the falling edge. D XINT3. Type C interrupt. The XINT3 control register (at 707Ah) provides control and status for this interrupt. XINT3 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a general-purpose I/O pin. XINT3 can also be programmed to trigger an interrupt on either the rising or the falling edge. D PDPINT. This interrupt is provided for safe operation of the power converter and motor drive. This maskable interrupt can put the timers and PWM output pins in the high-impedance state and inform the CPU in case of motor drive abnormalities such as overvoltage, overcurrent, and excessive temperature rise. PDPINT is a Level 2 interrupt. 24 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 external interrupts (continued) Table 8 is a summary of the external interrupt capability of the 'F240. Table 8. External Interrupt Types and Functions EXTERNAL INTERRUPT CONTROL REGISTER NAME CONTROL REGISTER ADDRESS INTERRUPT TYPE CAN DO NMI? DIGITAL I/O PIN MASKABLE? XINT1 XINT1CR 7070h A No Input only Yes (Level 1 or 6) NMI NMICR 7072h A Yes Input only No XINT2 XINT2CR 7078h C No I/O Yes (Level 1 or 6) XINT3 XINT3CR 707Ah C No I/O Yes (Level 1 or 6) PDPINT EVIMRA 742Ch N/A N/A N/A Yes (Level 2) clock generation The SMJ320F240 SMJ320F240 has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The only external component necessary for this module is an external fundamental crystal, or oscillator. The PLL-based clock module provides two basic modes of operation: oscillator mode and clock-in mode. D oscillator mode This mode allows the use of a 4-, 6-, or 8-MHz external reference crystal to provide the time base to the device. The internal oscillator circuitry is initialized by software to select the desired CPUCLK frequency, which can be the input clock frequency, the input clock frequency divided by 2 (default), or a clock frequency determined by the PLL. D Clock-in mode This mode allows the internal crystal oscillator circuitry to be bypassed. The device clocks are generated from an external clock source input on the XTAL1/CLKIN pin. The device can be configured by software to operate on the input clock frequency, the input clock frequency divided by 2, or a clock frequency determined by the PLL. The 'F240 runs on two clock frequencies: the CPU clock (CPUCLK) frequency, and the system clock (SYSCLK) frequency. The CPU, memories, external memory interface, and event manager run at the CPUCLK frequency. All other peripherals run at the SYSCLK frequency. The CPUCLK runs at 2x or 4x the frequency of the SYSCLK; for example, for 2x, CPUCLK = 20 MHz and SYSCLK = 10 MHz. There is also a clock for the watchdog timer, WDCLK. This clock has a nominal frequency of 16384 Hz (214 Hz) when XTAL1/CLKIN is a power of two or a sum of two powers of two; for example, 4194304 Hz (222 Hz), 6291456 (222 + 221 Hz), or 8388608 Hz (223 Hz). The clock module includes three external pins: 1. XTAL1/CLKIN clock source/crystal input 2. XTAL2 output to crystal 3. OSCBYP oscillator bypass For the external pins, if OSCBYP VIH, then the oscillator is enabled and if OSCBYP VIL, then the oscillator is bypassed and the device is in clock-in mode. In clock-in mode, an external TTL clock must be applied to the XTAL1/CLKIN pin. The XTAL2 pin can be left unconnected. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 25 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 clock generation (continued) ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Á Á ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ OSCBYP Div 2 XTAL OSC XTAL2 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ XTAL1/CLKIN PLL divide-by-2 bit (CKCR1.3) MUX Synchronizing CPUCLK Clock Switch Div 2 MUX Phase Detector VCO Clock Mode Bits (CKCR0.7­6) PLL Feedback Divider Div 1, 2, 3, 4, 5, or 9 PLL multiply ratio (CKCR1.2­0) Clock Frequency and PLL Multiply Bits (CKCR1.7­4) ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 1-MHz Clock Prescaler SYSCLK Prescaler Div 2 or 4 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Prescale Bit (CKCR0.0) ACLK Watchdog Clock Prescaler WDCLK SYSCLK Figure 8. PLL Clock Module Block Diagram low-power modes The SMJ320F240 SMJ320F240 has four low-power modes (idle 1, idle 2, PLL power down, and oscillator power down). The low-power modes reduce the operating power by reducing or stopping the activity of various modules (by stopping their clocks). The two PLLPM bits of the clock module control register, CKCR0, select which of the low-power modes the device enters when executing an IDLE instruction. Reset or an unmasked interrupt from any source causes the device to exit from idle 1 low-power mode. A real-time interrupt from the watchdog timer module causes the device to exit from all low-power modes except oscillator power down. This is a wake-up interrupt. When enabled, reset or any of the four external interrupts (NMI, XINT1, XINT2, or XINT3) causes the device to exit from any of the low-power modes (idle 1, idle 2, PLL power down, and oscillator power down). The external interrupts are all wake-up interrupts. The maskable external interrupts (XINT1, XINT2, and XINT3) must be enabled individually and globally to bring the device out of a low-power mode properly. It is, therefore, important to ensure that the desired low-power-mode exit path is enabled before entering a low-power mode. Figure 9 shows the wake-up sequence from a power down. Table 9 summarizes the low-power modes. 26 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 low-power modes (continued) Watchdog Timer and Real-Time Interrupt Module Wake-up Signal Wake-up Signal to CPU NMI XINT1 XINT2 XINT3 External-Interrupt Logic Reset Signal Reset Logic System Module Figure 9. Waking Up the Device From Power Down Table 9. Low-Power Modes LOWPOWER MODE PLLPM(x) BITS IN CKCR0[2:3] CPUCLK STATUS SYSCLK STATUS WDCLK STATUS PLL STATUS OSC STATUS Run XX On On On On EXIT CONDITION TYPICAL POWER On - 80 mA 50 mA Idle 1 00 Off On On On On Any interrupt or reset Idle 2 01 Off Off On On On Wake-up interrupt or reset 7 mA PLL Power Down 10 Off Off On Off On Wake-up interrupt or reset 1 mA OSC Power Down 11 Off Off Off Off Off Wake-up interrupt or reset 400 mA POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 27 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 low-power modes (continued) Table 10. Legend for the 'F240 Internal Hardware Functional Block Diagram SYMBOL NAME DESCRIPTION ACC Accumulator 32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift and rotate capabilities ARAU Auxiliary Register Arithmetic Unit An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs and outputs AUX REGS Auxiliary Registers 0­7 These 16-bit registers are used as pointers to anywhere within the data space address range. They are operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used as an index value for AR updates of more than one and as a compare value to AR. BR Bus Request Signal BR is asserted during access of the external global data memory space. READY is asserted to the device when the global data memory is available for the bus transaction. BR can be used to extend the data memory address space by up to 32K words. C Carry Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator shifts and rotates. CALU Central Arithmetic Logic Unit 32-bit-wide main arithmetic logic unit for the SMJ320C2xx core. The CALU executes 32-bit operations in a single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and provides status results to PCTRL. DARAM Dual Access RAM If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM (DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2 are mapped to data memory space only, at addresses 0300­03FF and 0060­007F, respectively. Blocks 0 and 1 contain 256 words, while Block 2 contains 32 words. DP Data Memory Page Pointer The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. GREG Global Memory Allocation Register GREG specifies the size of the global data memory space. IMR Interrupt Mask Register IMR individually masks or enables the seven interrupts. IFR Interrupt Flag Register The 7-bit IFR indicates that the SMJ320C2xx has latched an interrupt from one of the seven maskable interrupts. INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available. ISCALE Input Data-Scaling Shifter 16 to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations. MPY Multiplier 16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either signed or unsigned 2s-complement arithmetic multiply. MSTACK Micro Stack MSTACK provides temporary storage for the address of the next instruction to be fetched when program address-generation logic is used to generate sequential addresses in data space. MUX Multiplexer Multiplexes buses to a common input NPAR Next Program Address Register NPAR holds the program address to be driven out on the PAB on the next cycle. OSCALE Output Data-Scaling Shifter 16 to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the Data-Write Data Bus (DWEB). PAR Program Address Register PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory operations scheduled for the current bus cycle. PC Program Counter PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential data-transfer operations. PCTRL Program Controller PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations. 28 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 low-power modes (continued) Table 10. Legend for the 'F240 Internal Hardware Functional Block Diagram (Continued) SYMBOL NAME DESCRIPTION PREG Product Register 32-bit register holds results of 16 × 16 multiply. PSCALE Product-Scaling Shifter 0-, 1- or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the 32-bit product shifter and from either the CALU or the Data-Write Data Bus (DWEB), and requires no cycle overhead. STACK Stack STACK is a block of memory used for storing return addresses for subroutines and interrupt-service routines, or for storing data. The 'C20x stack is 16-bit wide and eight-level deep. TREG Temporary Register 16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 29 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 functional block diagram of the SMJ320F240 SMJ320F240 DSP CPU Program Bus IS DS PS 16 PC PAR MSTACK MUX W/R WE NMI RS MP/MC XINT[1­3] NPAR Data Bus Control X1 CLKOUT1 CLKIN/X2 Program Bus MUX R/W STRB READY BR XF Stack 8 × 16 3 FLASH EEPROM MUX A15­A0 16 Program Control (PCTRL) 16 16 16 16 16 MUX D15­D0 16 16 Data Bus 16 Data Bus 16 16 9 3 AR0(16) DP(9) AR1(16) 16 7 LSB from IR 16 16 AR2(16) ARP(3) 16 MUX MUX AR3(16) 3 16 16 9 AR4(16) 3 AR5(16) ARB(3) TREG0(16) AR6(16) Multiplier AR7(16) 3 ISCALE (0­16) PREG(32) 16 32 PSCALE (­6,0,1,4) 32 32 16 MUX ARAU(16) MUX 32 CALU(32) 16 32 Memory Map Register 32 MUX MUX Data/Prog DARAM B0 (256 × 16) Data DARAM B2 (32 × 16) IFR (16) GREG (16) C ACCH(16) ACCL(16) 32 B1 (256 × 16) MUX OSCALE (0­7) 16 16 16 16 NOTES: A. Symbol descriptions appear in Table 10. B. For clarity the data and program buses are shown as single buses although they include address and data bits. 30 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 Program Bus IMR (16) SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 'F240 DSP core CPU The SMJ320F240 SMJ320F240 devices use an advanced Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures - program and data - for full-speed execution. This multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers between program memory and data memory. This architecture permits coefficients that are stored in program memory to be read in RAM, thereby eliminating the need for a separate coefficient that are ROM. This, coupled with a four-deep pipeline, allows the 'F240 devices to execute most instructions in a single cycle. status and control registers Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can be stored into data memory and loaded from data memory, thereby allowing the status of the machine to be saved and restored for subroutines. The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST) instruction is used to read from ST0 and ST1 - except for the INTM bit, which is not affected by the LST instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC instructions. Figure 10 shows the organization of status registers ST0 and ST1, indicating all status bits contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 11 lists status register field definitions. 15 ST0 13 15 ST1 13 ARB 11 10 9 OV ARP 12 OVM 1 8 7 6 5 INTM 4 3 2 1 0 DP 12 11 10 9 8 7 6 5 4 3 2 CNF TC SXM C 1 1 1 1 XF 1 1 1 0 PM Figure 10. Status and Control Register Organization Table 11. Status Register Field Definitions FIELD FUNCTION ARB Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP. ARP Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed. C Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow. Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these cases, the ADD can only set and the SUB only reset the carry bit, but cannot affect it otherwise. The single bit shift and rotate instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch on the status of C. C is set to 1 on a reset.0 CNF On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1 instructions. RS sets the CNF to 0. DP Data memory page pointer. The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. INTM Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled. INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS and IACK also set INTM. INTM has no effect on the unmaskable RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when a maskable interrupt trap is taken. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 31 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 status and control registers (continued) Table 11. Status Register Field Definitions (Continued) FIELD FUNCTION OV Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instructions clear OV. OVM Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset this bit, respectively. LST can also be used to modify the OVM. PM Product shift mode. If these two bits are 00, the multiplier's 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, PREG output is left-shifted by four bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of six bits, sign-extended. Note that the PREG contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the SPM and LST #1 instructions. PM is cleared by RS. SXM Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter. SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction suppresses sign extension regardless of SXM. SXM is set by the SETC SXM and reset by the CLRC SXM instructions, and can be loaded by the LST #1. SXM is set to 1 by reset. TC Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the two MSBs of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return instructions can execute based on the condition of TC. XF XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF and reset by the CLRC XF instructions. XF is set to 1 by reset. central processing unit The SMJ320F240 SMJ320F240 central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both the accumulator and the multiplier. This section describes the CPU components and their functions. The functional block diagram shows the components of the CPU. input scaling shifter The SMJ320F240 SMJ320F240 provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output connected to the CALU. This shifter operates as part of the path of data coming from program or data space to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations. The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros; the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit (sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to the system's performance. multiplier The SMJ320F240 SMJ320F240 devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. Two registers are associated with the multiplier: D 16-bit temporary register (TREG) that holds one of the operands for the multiplier D 32-bit product register (PREG) that holds the product 32 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 multiplier (continued) Four product shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode, as shown in Table 12. Table 12. PSCALE Product Shift Modes PM SHIFT DESCRIPTION 00 No shift 01 Left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product 10 Left 4 Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when using the multiply by a 13-bit constant 11 Right 6 Product feed to CALU or data bus with no shift Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY (multiply) instruction provides the second operand (also from the data bus). A multiplication also can be performed with a 13-bit immediate operand when using the MPY instruction. Then a product is obtained every two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining of the TREG load operations with CALU operations using the previous product. The pipeline operations that run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC (LTS). Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations can be transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient addresses are generated by program address generation (PAGEN) logic, while the data addresses are generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values from the coefficient table sequentially and step through the data in any of the indirect addressing modes. The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample. The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value. After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store product high) and SPL (store product low). Note: the transfer of PREG to either the CALU or data bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot be modeled POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 33 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 multiplier (continued) in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high half, then, is loaded using the LPH instruction. central arithmetic logic unit The SMJ320F240 SMJ320F240 central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU). Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier. The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the CALU is always provided from the accumulator, and the other input can be provided from the product register (PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator. The SMJ320F240 SMJ320F240 devices support floating-point operations for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the LACT/ADDT/SUBT (load/add to /subtract from accumulator with shift specified by TREG) instructions. These instructions are useful in floating-point arithmetic where a number needs to be denormalized - that is floating-point to fixed-point conversion. They are also useful in execution of an automatic gain control (AGC) going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of TREG. The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (Logical operations cannot result in overflow.) The CALU can execute a variety of branch instructions that depend on the status of the CALU and the accumulator. These instructions can be executed conditionally based on any meaningful combination of these status bits. For overflow management, these conditions include the OV (branch on overflow) and EQ (branch on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory. The CALU also has an associated carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It also is useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions. The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use the previous value of carry in their addition/subtraction operation. 34 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 central arithmetic logic unit (continued) The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it. Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing, based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the carry bit. The carry bit is set to one on a hardware reset. accumulator The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. When the post-scaling shifter is used on the high word of the accumulator (bits 16­31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0­15). When the post-scaling shifter is used on the low word, the LSBs are zero-filled. The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT) instructions can be used with the shift and rotate instructions for multiple-bit shifts. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The 'F240 provides a register file containing eight auxiliary registers (AR0­AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of these registers also can be stored in data memory or used as inputs to the CALU. The auxiliary register file (AR0­AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either by ±1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel. internal memory The SMJ320F240 SMJ320F240 devices are configured with the following memory modules: D Dual-access random-access memory (DARAM) D Flash EEPROM dual-access RAM (DARAM) There are 544 words × 16 bits of DARAM on the 'F240 device. The 'F240 DARAM allows writes to and reads from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and block 2 (B2). Block 1 contains 256 words and block 2 contains 32 words, and both blocks are located only in data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program memory space. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 35 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 dual-access RAM (DARAM) (continued) The SETC CNF (configure B0 as data memory) and CLRC CNF (configure B0 as program memory) instructions allow dynamic configuration of the memory maps through software. When using block 0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed. When using on-chip RAM, or high-speed external memory, the 'F240 runs at full speed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle coupled with the parallel nature of the 'F240 architecture enables the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY line can be used to interface the 'F240 to slower, less expensive external memory. Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system costs. flash EEPROM Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, flash is a nonvolatile memory type; however, it has the advantage of "in-target" reprogrammability. The SMJ320F240 SMJ320F240 incorporates one 16K 16-bit flash EEPROM module in program space. This type of memory expands the capabilities of the SMJ320F240 SMJ320F240 in the areas of prototyping, early field-testing, and single-chip applications. Unlike most discrete flash memory, the 'F240 flash does not require a dedicated state machine, because the algorithms for programming and erasing the flash are executed by the DSP core. This enables several advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming, the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the algorithms and flash code. Other key features of the flash include zero-wait-state access rate and single 5-V power supply. An erased bit in the SMJ320F240 SMJ320F240 flash is read as a logic 1, and a programmed bit is read as a logic 0. The flash requires a block-erase of the entire 16K module; however, any combination of bits can be programmed. The following four algorithms are required for flash operations: clear, erase, flash-write, and program. For an explanation of these algorithms and a complete description of the flash EEPROM, see the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282 SPRU282), which is available during the 2nd quarter of 1998. flash serial loader The on-chip flash is shipped with a serial bootloader code programmed at the following addresses: 0x0000­0x00FFh. All other flash addresses are in an erased state. The serial bootloader can be used to program the on-chip Flash memory with user's code. During the Flash programming sequence, the on-chip data RAM is used to load and execute the clear, erase, and program algorithms. See the TMS320F240 TMS320F240 Serial Bootloader application report (currently located at to understand on-chip flash programming using the serial bootloader code. Look for further C2000 C2000 information using the DSP link at www.ti.com. flash control mode register The flash control mode register is located at I/O address FF0Fh. This register offers two options: register access mode and array access mode. Register access mode gives access to the four control registers in the memory space decoded for the flash module. These registers are used to control erasing, programming, and testing of the flash array. Register access mode is enabled by activating an OUT command with dummy data. The OUT xxxx, FF0Fh instruction makes the flash registers accessible for reads and/or writes. After executing OUT xxxx, FF0Fh, the flash control registers are accessed in the memory space decoded for the flash module and the flash array cannot be accessed. The four registers are repeated every four address locations within the flash module's decoded range. After completing all the necessary reads and/or writes to the control registers, an IN xxxx, FF0Fh instruction (with dummy data) is executed to place the flash array back in array access mode. After executing the IN xxxx, FF0Fh instruction, the flash array is accessed in the decoded space and the flash registers are 36 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­ REVISED JULY 2002 flash control mode register (continued) not available. Switching between the register access mode and the array access mode is done by issuing the IN and OUT instructions. The memory content in these instructions (denoted by xxxx) is not relevant. See the TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282 SPRU282) for a detailed description of the flash programming algorithms. peripherals The integrated peripherals of the SMJ320F240 SMJ320F240 are described in the following subsections: D D D D D D External memory interface Event manager (EV) Dual analog-to-digital converter (ADC) Serial peripheral interface (SPI) Serial communications interface (SCI) Watchdog timer (WD) external memory interface The SMJ320F240 SMJ320F240 can address up to 64K words × 16 bits of memory or registers in each of the program, data, and I/O spaces. On-chip memory, when enabled, removes some of this off-chip range. In data space, the high 32K words can be mapped dynamically as either local or global using the GREG register. A data-memory access mapped as global asserts BR low (with timing similar to the address bus). The CPU of the SMJ320F240 SMJ320F240 schedules a program fetch, data read, and data write on the same machine cycle. This is because, from on-chip memory, the CPU can execute all three of these operations in the same cycle. However, the external interface multiplexes the internal buses to one address and one data bus. The external interface sequences these operations to complete the data write first, then the data read, and finally the program read. The 'F240 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along with the PS, DS, and IS space-select signals allow addressing of 64K 16-bit words in program and I/O space. Due to the on-chip peripherals, external data space is addressable to 32K 16-bit words. I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the processor's external address and data buses in the same manner as memory-mapped devices. The 'F240 external parallel interface provides control signals to facilitate interfacing to the device. The R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal provides a timing reference for all external cycles. Interface to memory and I/O devices of varying speeds is accomplished by using the READY input. When transactions are made with slower devices, the 'F240 processor waits until the other device completes its function and signals the processor by way of the READY input. Once a ready indication is provided from the external device, execution continues. On the 'F240 device, the READY input must be driven (active high) to complete reads or writes to internal data I/O-memory-mapped registers and all external addresses. The bus request (BR) signal is used in conjunction with the other 'F240 interface signals to arbitrate external global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted at the beginning of the access. When an external global-memory device receives the bus request, it responds by asserting the ready signal after the global-memory access is arbitrated and the global access is completed. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 37 SMJ320F240 SMJ320F240 DSP CONTROLLER SGUS029A SGUS029A ­ APRIL 1999 ­