TLCS-900/H1 TMP92CH21 TMP92CH21FG/JTMP92CH21 900/H1 TMP92CH21FG JTMP92CH21 - Datasheet Archive
TLCS-900/H1 Series TMP92CH21 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs.
TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 TLCS-900/H1 Series TMP92CH21 TMP92CH21 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". TMP92CH21 TMP92CH21 CMOS 32-bit Microcontroller TMP92CH21FG/JTMP92CH21 TMP92CH21FG/JTMP92CH21 1. Outline and Device Characteristics TMP92CH21 TMP92CH21 is high-speed advanced 32-bit Microcontroller developed for controlling equipment which processes mass data. TMP92CH21 TMP92CH21 is a Microcontroller which has a high-performance CPU (900/H1 900/H1 CPU) and various built-in I/Os. TMP92CH21FG TMP92CH21FG is housed in a 144-pin flat package. JTMP92CH21 JTMP92CH21 is a chip form product. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 900/H1 CPU) · Compatible with TLCS-900/L1 TLCS-900/L1 instruction code · 16 Mbytes of linear address space · General-purpose register and register banks · Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case) (2) Minimum instruction execution time: 50 ns (at fSYS = 20 MHz) (3) Internal memory · Internal RAM: 16 Kbytes (can be used for program, data and display memory) · Internal ROM: 8 Kbytes (used as boot program) Possible downloading user's download-program through either USB, UART or NAND flash. (4) External memory expansion · Expandable up to 512 Mbytes (shared program/data area) · Can simultaneously support 8- or 16- or 32-bit width external data bus . dynamic data bus sizing · Separate bus system (5) Memory controller · Chip select output: 4 channels 030619EBP1 030619EBP1 · The information contained herein is subject to change without notice. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. · For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 92CH21-1 92CH21-1 2004-09-01 TMP92CH21 TMP92CH21 (6) 8-bit timers: 4 channels (7) 16-bit timer/event counter: 1 channel (8) General-purpose serial interface: 2 channels · UART/synchronous mode: 2 channels (channel 0 and 1) · IrDA Ver.1.0 (115 kbps) mode selectable: 1 channel (channel 0) (9) USB (universal serial bus) controller: 1 channel · Compliant with USB rev1.1 · Full-speed (12 MHz) (Low-speed is not supported.) · Endpoints spec Endpoint 0: Control 64 bytes* 1-FIFO Endpoint 1: BULK (out) 64 bytes* 2-FIFO Endpoint 2: BULK (in) 64 bytes* 2-FIFO Endpoint 3: Interrupt (in) 8 bytes* 1-FIFO · Descriptor RAM: 384 bytes (10) I2S (Inter-IC sound) interface: 1 channel · I2S bus mode/SIO mode selectable (Master, transmission only) · 32-byte FIFO buffer (11) LCD controller · Supported up to 4096 color for TFT, 256 color, 16, 8, 4 gray levels and B/W for STN · Shift register/built-in RAM LCD driver (12) SDRAM controller: 1 channel · Supported 16 M, 64 M, 128 M, 256 M even 512-Mbit SDR (Single Data Rate)-SDRAM · Possible to execute instruction on SDRAM (13) Timer for real-time clock (RTC) (14) Key-on wakeup (Interrupt key input) (15) 10-bit AD converter: 4 channels (16) Touch screen interface · Available to reduce external components (17) Watchdog timer (18) Melody/alarm generator · Melody: Output of clock 4 to 5461 Hz · Alarm: Output of the 8 kinds of alarm pattern and 5 kinds of interval interrupt (19) MMU · Expandable up to 512 Mbytes (3 local area/8 bank method) · Independent bank for each program, read data, write data and LCD display data 92CH21-2 92CH21-2 2004-09-01 TMP92CH21 TMP92CH21 (20) Interrupts: 50 interrupts · 9 CPU interrupts: · 34 internal interrupts: Seven selectable priority levels · 7 external interrupts: Seven selectable priority levels (6-edge selectable) Software interrupt instruction and illegal instruction (21) Input/output ports: 126 pins (22) NAND flash interface: 2 channels · Available to connect directly with NAND flash · ECC calculation (for SLC- type) (23) Stand-by function · Three HALT modes: IDLE2 (programmable), IDLE1, STOP · Each pin status programmable for stand-by mode (24) Triple-clock controller · Clock doubler (PLL) supplies 48 MHz for USB, 36 MHz system-clock for others · Clock gear function: Select a high-frequency clock fc to fc/16 · RTC (fs = 32.768 kHz) (25) Operating voltage: · VCC = 3.0 V to 3.6 V (fc max = 40 MHz) · VCC = 2.7 V to 3.6 V (fc max = 27 MHz) (26) Package: · 144-pin QFP (P-LQFP144 P-LQFP144 -1616-0.40C) · 144-pin Chip form is also available. For details, contact your local Toshiba sales representative. 92CH21-3 92CH21-3 2004-09-01 TMP92CH21 TMP92CH21 PG0 to PG1 (AN0 to AN1) AN2, MX (PG2) AN3, MY, ADTRG (PG3) AVCC, AVSS VREFH, VREFL 10-bit 4-channel AD converter (PX, INT4) P96 (PY, INT5) P97 Touch screen I/F (TSI) (TXD0, TXD1) PF0 (RXD0, RXD1) PF1 (SCLK0,SCLK1) PF2 Serial I/O SIO0 Serial I/O SIO1 DVCC  DVSS  900/H1 900/H1 CPU XWA XBC XDE XHL XIX XIY XIZ XSP W A B C D E H L IX IY IZ SP 32 bits SR PLL H-OSC Clock gear L-OSC X1 X2 TEST XT1 XT2 RESET AM0 AM1 Interrupt controller F D0 to D7 PC D+ D- USB controller Port 1 Watchdog timer (I2SCKO, TXD0) P90 (I2SDO, RXD0) P91 (I2SWS, SCLK0, CTS0 ) P92 Port 2 I2S MMU (LGOE0) P93 (LGOE1) P94 (LGOE2, CLK32KO CLK32KO) P95 Port 3 Port 4 Port 5 8-bit timer (TIMERA0) (TA1OUT, INT0) PC0 Port 6 8-bit timer (TIMERA1) 8-bit timer (TIMERA2) (TA3OUT, INT1) PC1 8-bit timer (TIMERA3) (TB0OUT0, INT2) PC2 (INT3) PC3 Port 7 16-bit timer (TIMERB0) P70 ( RD ) P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) P73 (EA24) P74 (EA25) P75 (R/W, NDR/B) P76 ( WAIT ) NAND flash I/F (2 channel) P30, 33 P31, 34 P32, 35 (LCP0) PK0 (LLP) PK1 (LFR) PK2 (LBCD) PK3 PL0 to PL7 (LD0 to LD7) ( SDRAS , SRLLB ) PJ0 ( SDCAS , SRLUB ) PJ1 ( SDWE , SRWR ) PJ2 (SDLLDQM) PJ3 (SDLUDQM) PJ4 (NDALE, SDULDQM) PJ5 (NDCLE, SDUUDQM) PJ6 (SDCKE) PJ7 (SDCLK) PF7 P10 to P17 (D8 to D15) P20 to P27 (D16 to D23, KO0 to KO7) P30 to P37 (D24 to D31) P40 to P47 (A0 to A7) P50 to P57 (A8 to A15) P60 to P67 (A16 to A23) Port 8 LCD controller 16-Kbyte RAM Keyboard I/F RTC SDRAM controller 8-Kbyte mask ROM (Boot program) Melody/ alarm out P80 ( CS0 ) P81 ( CS1 , SDCS ) P82 ( CS2 , CSZA , SDCS ) P83 ( CS3 ) P84 ( CSZB , WRUL , ND0CE ) P85 ( CSZC , WRUU , ND1CE ) P86 ( CSZD , SRULB ) P87 ( CSZE , SRUUB ) PC7 ( CSZF , LCP1) PA0 to PA7 (KI0 to KI7, LD8 to LD11) PC6 (KO8, LDIV) PM2 ( ALARM , MLDALM ) PM1 (MLDALM) Figure 1.1 TMP92CH21 TMP92CH21 Block Diagram 92CH21-4 92CH21-4 2004-09-01 TMP92CH21 TMP92CH21 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CH21FG TMP92CH21FG, their names and functions are as follows: Pin Assignment 110 115 120 125 130 135 1 105 5 100 10 95 TMP92CH21FG TMP92CH21FG 15 QFP144 QFP144 90 20 Top View 85 25 80 30 75 70 65 60 55 50 P67, A23 P66, A22 P65, A21 P64, A20 DVCC3 P63, A19 P62, A18 P61, A17 P60, A16 P57, A15 P56, A14 P55, A13 P54, A12 P53, A11 P52, A10 P51, A9 P50, A8 P47, A7 P46, A6 P45, A5 P44, A4 P43, A3 P42, A2 P41, A1 P40, A0 P37, D31 P36, D30 DVSS3 P35, D29 P34, D28 P33, D27 P32, D26 P31, D25 P30, D24 P27, D23, KO7 P26, D22, KO6 PC3, INT3 DVSS2 DVCC2 D0 D1 D2 D3 D4 D5 D6 D7 P10, D8 P11, D9 P12, D10 P13, D11 P14, D12 P15, D13 P16, D14 P17, D15 P20, D16, KO0 P21, D17, KO1 P22, D18, KO2 P23, D19, KO3 P24, D20, KO4 P25, D21, KO5 RESET 45 D+ D- DVCC1 X1 DVSS1 X2 AM0 AM1 TEST 40 35 DVCC4 VREFL VREFH PG0, AN0 PG1, AN1 PG2, AN2, MX PG3, AN3, ADTRG , MY P96, PX, INT4 P97, PY, INT5 PA3, KI3, LD8 PA4, KI4, LD9 PA5, KI5, LD10 PA6, KI6, LD11 PA7, KI7 P90, TXD0, I2SCKO P91, RXD0, I2SDO P92, SCLK0, CTS0 , I2SWS P93, LGOE0 P94, LGOE1 P95, CLK32KO CLK32KO, LGOE2 PC2, TB0OUT0, INT2 PL0, LD0 PL1, LD1 PL2, LD2 PL3, LD3 PL4, LD4 PL5, LD5 PL6, LD6 PL7, LD7 PK0, LCP0 PK1, LLP PK2, LFR PK3, LBCD PM2, ALARM , MLDALM PM1, MLDALM XT1 XT2 140 AVCC AVSS PA2, KI2 PA1, KI1 PA0, KI0 PJ7, SDCKE PJ6, SDUUDQM, NDCLE PJ5, SDULDQM, NDALE PJ4, SDLUDQM PJ3, SDLLDQM PJ2, SDWE, SRWR PJ1, SDCAS, SRLUB PJ0, SDRAS, SRLLB PF7, SDCLK PC1, TA3OUT, INT1 PC0, TA1OUT, INT0 PF2, SCLK0, CTS0, SCLK1, CTS1 PF1, RXD0, RXD1 PF0, TXD0, TXD1 PC7, CSZF, LCP1 P87, CSZE, SRUUB P86, CSZD, SRULB P85, CSZC, WRUU, ND1CE P84, CSZB, WRUL, ND0CE P83, CS3 P82, CS2, CSZA, SDCS P81, CS1, SDCS PC6, KO8, LDIV P80, CS0 P76, WAIT P75, R/W, NDR/B P74, EA25 P73, EA24 P72, WRLU, NDWE P71, WRLL, NDRE P70, RD 2.1 Figure 2.1.1 Pin Assignment Diagram (144-pin QFP) 92CH21-5 92CH21-5 2004-09-01 TMP92CH21 TMP92CH21 2.2 PAD Assignment (Chip size 5.98 mm × 6.42 mm) Table 2.2.1 Pad Assignment Diagram (144-pin chip) Unit: µm Pin No Name X Y Pin X Y Pin Point Point No Point Point No 2671 2546 2421 2296 2171 2045 1920 1795 1270 1145 1020 895 769 644 519 394 269 144 18 -106 -231 -356 -481 -606 -732 -857 -982 -1107 -1232 -1357 -1482 -1608 -1892 -2017 49 50 51 DVSS2 DVCC2 D0 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -2279 -2138 -1982 -1831 -1687 -1562 -1437 -1311 -1186 -1061 97 98 99 P55 P56 P57 D1 D2 D3 D4 D5 D6 D7 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 DVSS3 P36 -488 -338 -200 -75 49 174 300 425 550 675 800 925 1050 1176 1301 1426 1551 1676 1801 1927 2052 2177 2303 2460 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Name 1 2 3 VREFL VREFH PG0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PG1 PG2 PG3 P96 P97 PA3 PA4 PA5 PA6 PA7 P90 P91 P92 P93 P94 P95 PC2 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PK0 PK1 PK2 PK3 PM2 PM1 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 35 XT1 -2852 -2142 83 P37 2848 -936 36 XT2 -2852 -2444 84 P40 2848 -811 37 DVCC4 -2465 -3072 85 P41 2848 -686 38 TEST -2339 -3072 86 P42 2848 39 D+ -2062 -3072 87 P43 2848 Name X Y Point Point P60 P61 P62 P63 DVCC3 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P80 PC6 P81 P82 P83 P84 P85 P86 P87 PC7 PF0 PF1 PF2 PC0 PC1 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2460 2295 2127 1964 1807 1654 1506 1361 1226 1101 976 851 726 600 475 350 225 100 -24 -150 -275 -400 815 941 1066 1191 1316 1441 1566 1692 1823 1974 2130 2292 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 131 PF7 -525 3065 132 PJ0 -650 3065 133 PJ1 -775 3065 -560 134 PJ2 -901 3065 -435 135 PJ3 -1026 3065 40 D- -1875 -3072 88 P44 2848 -310 136 PJ4 -1151 3065 41 DVCC1 -1598 -3072 89 P45 2848 -185 137 PJ5 -1276 3065 42 X1 -1472 -3072 90 P46 2848 -60 138 PJ6 -1401 3065 43 DVSS1 -1347 -3072 91 P47 2848 65 139 PJ7 -1526 3065 44 X2 -1126 -3072 92 P50 2848 190 140 PA0 -1652 3065 45 AM0 -1001 -3072 93 P51 2848 315 141 PA1 -1777 3065 46 AM1 -876 -3072 94 P52 2848 440 142 PA2 -1902 3065 47 RESET -750 -3072 95 P53 2848 565 143 AVSS -2275 3065 48 PC3 -625 -3072 96 P54 2848 690 144 AVCC -2400 3065 92CH21-6 92CH21-6 2004-09-01 TMP92CH21 TMP92CH21 2.3 Pin Names and Functions The following table shows the names and functions of the input/output pins Table 2.3.1 Pin Names and Functions (1/5) Pin Name D0 to D7 P10 to P17 D8 to D15 Number of Pins Function 8 8 I/O Data: Data bus 0 to 7 I/O Port 1: I/O port input or output specifiable in units of bits I/O Data: Data bus 8 to 15 I/O 8 P20 to P27 D16 to D23 I/O Port 2: I/O port input or output specifiable in units of bits I/O Data: Data bus 16 to 23 KO0 to KO7 Output P30 to P37 I/O Port 3: I/O port input or output specifiable in units of bits I/O Data24: Data bus 24 to 31 D24 to D31 P40 to P47 A0 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 P70 RD 8 8 8 8 1 WRLL 1 1 P74 EA25 1 1 1 NDR/B P76 WAIT Port 5: Output port Output I/O Address: Address bus 8 to 15 Port 6: I/O port input or output specifiable in units of bits Output Address: Address bus 16 to 23 Output Port70: Output port Output Read: Outputs strobe signal to read external memory Port 71: I/O port Output Write: Output strobe signal for writing data on pins D0 to D7 NAND flash read: Outputs strobe signal to read external NAND flash Port 72: I/O port Output Write: Output strobe signal for writing data on pins D8 to D15 Write Enable for NAND flash Output Port 73: Output port Output Extended Address 24 Output Port 74: Output port Output I/O P75 R/ W Output Output NDWE EA24 Address: Address bus 0 to 7 I/O P72 P73 Port 4: Output port Output Output NDRE WRLU Output I/O P71 Key output 0 to 7: Pins used of key-scan strobe (Open-drain output programmable) Output Input 1 I/O Input Extended Address 25 Port 75: I/O port Read/Write: 1 represents read or dummy cycle; 0 represents write cycle NAND flash ready (1)/Busy (0) input Port 76: I/O port Wait: Signal used to request CPU bus wait 92CH21-7 92CH21-7 2004-09-01 TMP92CH21 TMP92CH21 Table 2.3.2 Pin Names and Functions (2/5) Pin Name P80 CS0 Number of Pins Output Output Port80: Output port Chip select 0: Outputs "low" when address is within specified address area 1 Output Output Output Port81: Output port Chip select 1: Outputs "low" when address is within specified address area Chip select for SDRAM: Outputs "0" when address is within SDRAM address area 1 Output Output Output Output Port82: Output port Chip select 2: Outputs "Low" when address is within specified address area Expand chip select: ZA: Outputs "0" when address is within specified address area Chip select for SDRAM: Outputs "0" when address is within SDRAM address area 1 Output Output Port83: Output port Chip select 3: Outputs "low" when address is within specified address area 1 Output Output Output Output Port84: Output port Write: Output strobe signal for writing data on pins D16 to D23 Expand chip select: ZB: Outputs "0" when address is within specified address area Chip select for NAND flash 0: Outputs "0" when NAND flash 0 is enabled 1 Output Output Output Output Port85: Output port Write: Output strobe signal for writing data on pins D24 to D31 Expand chip select: ZC: Outputs "0" when address is within specified address area Chip select for NAND flash 1: Outputs "0" when NAND flash 1 is enabled 1 Output Output Output Port86: Output port Expand chip select: ZD: outputs "0" when address is within specified address area Data enable for SRAM on pins D16 to D23 1 Output Output Output Port87: Output port Expand chip select: ZE: Outputs "0" when address is within specified address area Data enable for SRAM on pins D24 to D31 I/O Output Output I/O Input Output I/O I/O Input Output Port90: I/O port Serial 0 send data: Open-drain output programmable 2 I S clock output Port91: I/O port (Schmitt-input) Serial 0 receive data 2 I S data output Port92: I/O port (Schmitt-input) Serial 0 clock I/O Serial 0 data send enable (Clear to send) 2 I S word select output SDCS P82 CS2 CSZA SDCS P83 CS3 P84 WRUL CSZB ND0CE P85 WRUU CSZC ND1CE P86 CSZD SRULB P87 CSZE SRUUB P90 TXD0 I2SCKO P91 RXD0 I2SDO P92 SCLK0 CTS0 I2SWS P93 LGOE0 P94 LGOE1 P95 CLK32KO CLK32KO LGOE2 P96 INT4 PX P97 INT5 PY PA0 to PA2 KI0 to KI2 PA3 to PA6 KI3 to KI6 LD8 to LD11 PA7 KI7 Function 1 P81 CS1 I/O 1 1 1 1 1 1 1 1 3 4 1 I/O Port93: I/O port Output Output enable-0 for external TFT-LCD driver I/O Port94: I/O port Output Output enable-1 for external TFT-LCD driver Output Port95: Output port Output Output fs (32.768 kHz) clock Output Output enable-2 for external TFT-LCD driver Port 96: Input port (Schmitt-input) Input Interrupt request pin4: Interrupt request with programmable rising/falling edge Input Output X-Plus: Pin connectted to X+ for touch screen panel Input Port 97: Input port (Schmitt-input) Input Interrupt request pin5: Interrupt request with programmable rising/falling edge Output Y-Plus: Pin connectted to Y+ for touch screen panel Input Port: A0 to A2 port: Pin used to input ports (Schmitt input, with pull-up resistor) Input Key input 0 to 2: Pin used of key-on wakeup 0 to 2 Input Port: A3 to A6 port: Pin used to input ports (Schmitt input, with pull-up resistor) Input Key input 3 to 6: Pin used of key-on wakeup 3 to 6 Output Data bus 8 to 11for LCD driver Input Port: A7 port: Pin used to input ports (Schmitt input, with pull-up resistor) Input Key input 7: Pin used of key-on wakeup 7 92CH21-8 92CH21-8 2004-09-01 TMP92CH21 TMP92CH21 Table 2.3.3 Pin Names and Functions (3/5) Pin Name Number of Pins I/O 1 Input PC0 INT0 I/O TA1OUT Output PC1 INT1 I/O 1 TA3OUT Output PC2 INT2 I/O 1 TB0OUT0 PC3 INT3 1 1 1 1 Timer B0 output Port C3: I/O port (Schmitt-input) Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge Port C6: I/O port Port C7: I/O port Expand chip select: ZF: Outputs "0" when address is within specified address area Shift-clock-1 for external TFT-LCD driver Port F0: I/O port (Schmitt-input) Output Serial 0 send data: Open-drain output programmable Serial 1 send data: Open-drain output programmable Input Port F1: I/O port (Schmitt-input) Serial 0 receive data Serial 1 receive data I/O 1 SCLK1 Port F2: I/O port (Schmitt-input) I/O SCLK0 Serial 0 clock I/O Input I/O Input CTS1 1 2 Serial 0 data send enable (Clear to send) Serial 1 clock I/O Serial 1 data send enable (Clear to send) Output Port F7: Output port Output Clock for SDRAM (When SDRAM is not used, SDCLK can be used as system clock) Input Port G0 to G1 port: Pin used to input ports 1 Input Analog input 0 to 1: Pin used to Input to AD conveter Input PG2 AN2 Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge Output Input PF2 AN0 to AN1 8-bit timer 3 output: Timer 3 output Port C2: I/O port (Schmitt-input) Data invert enable for external TFT-LCD driver I/O RXD1 PG0 to PG1 Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge Output PF1 SDCLK Port C1: I/O port (Schmitt-input) Key Output 8: Pin used of key-scan strobe (Open-drain output programmable) I/O TXD1 PF7 8-bit timer 1 output: Timer 1 output Output PF0 CTS0 Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge Output I/O 1 LCP1 RXD0 Input Port C0: I/O port (Schmitt-input) Output PC7 TXD0 I/O I/O LDIV CSZF Input Output PC6 KO8 Input Function Port G2 port: Pin used to input ports Input Analog input 2: Pin used to Input to AD conveter MX Output PG3 Input Port G3 port: Pin used to input ports Input Analog input 3: Pin used to input to AD conveter AN3 MY ADTRG 1 X-Minus: Pin connectted to X- for touch screen panel Output Y-Minus: Pin connectted to Y- for touch screen panel Intput AD trigger: Signal used to request AD start 92CH21-9 92CH21-9 2004-09-01 TMP92CH21 TMP92CH21 Table 2.3.4 Pin Names and Functions (4/5) Pin Name Number of Pins I/O Function Output Port J0: Output port Output Row address strobe for SDRAM SRLLB Output Data enable for SRAM on pins D0 to D7 PJ1 Output Port J1: Output port Output Column address strobe for SDRAM PJ0 SDRAS SDCAS 1 1 SRLUB Output Data enable for SRAM on pins D8 to D15 PJ2 Output Port J2: Output port Output Write enable for SDRAM SRWR Output Write for SRAM: Strobe signal for writing data PJ3 Output Port J3: Output port Output Data enable for SDRAM on pins D0 to D7 Output Port J4: Output port Output Data enable for SDRAM on pins D8 to D15 SDWE SDLLDQM PJ4 SDLUDQM 1 1 1 PJ5 SDULDQM I/O 1 PJ6 Data enable for SDRAM on pins D16 to D23 Output NDALE SDUUDQM Port J5: I/O port Output Address latch enable for NAND flash I/O Port J6: I/O port Output Data enable for SDRAM on pins D24 to D31 NDCLE Output Command latch enable for NAND flash PJ7 Output Port J7: Output port Output Clock enable for SDRAM Output Port K0: Output port Output LCD driver output pin Output Port K1: Output port Output LCD driver output pin Output Port K2: Output port Output LCD driver output pin Output Port K3: Output port Output LCD driver output pin Output Port L0 to L3: Output port SDCKE PK0 LCP0 PK1 LLP PK2 LFR PK3 LBCD PL0 to PL3 LD0 to LD3 PL4 to PL7 LD4 to LD7 TEST PM1 MLDALM 1 1 1 1 1 1 4 4 1 1 ALARM Note: I/O Output Input Output Data bus for LCD driver Port L4 to L7: I/O port Data bus for LCD driver Connect to VCC. Port M1: Output port Melody/alarm output pin Port M2: Output port Output RTC alarm output pin Output 1 Output Output PM2 MLDALM Output Melody/alarm output pin (inverted) The output function SDULDQM, NDALE of PJ5-pin and SDUUDQM, NDCLE of PJ6-pin can not be used at the same time. Therefore, 32-bit SDRAM and NAND-Flash cannot be used at the same time. 92CH21-10 92CH21-10 2004-09-01 TMP92CH21 TMP92CH21 Table 2.3.5 Pin Names and Functions (5/5) Pin Name D+, D- Number of Pins I/O 2 I/O Function USB-data connecting pin In case of unusing USB, connect pull-up resistor to both pins to avoid through current. Operation mode: AM0, AM1 2 Input Fix to AM1 = "0", AM0 = "1" for 16-bit external bus starting Fix to AM1 = "1", AM0 = "0" for 32-bit external bus starting Fix to AM1 = "1", AM0 = "1" for BOOT (32-bit internal MROM) starting X1/X2 2 I/O High-frequency oscillator connection pins XT1/XT2 2 I/O Low-frequency oscillator connection pins RESET 1 Input Reset: Initializes TMP92CH21 TMP92CH21 (with pull-up resistor, schmitt input) VREFH 1 Input Pin for reference voltage input to AD converter (H) VREFL 1 Input Pin for reference voltage input to AD converter (L) AVCC 1 - Power supply pin for AD converter AVSS 1 - GND pin for AD converter (0 V) DVCC 4 - Power supply pins (All VCC pins should be connected with the power supply pin) DVSS 3 - GND pins (0 V), All pins should be connected with GND (0 V) Note: When the USB is used, cannnot 9.0 MHz oscillator to X1/X2-pin. 92CH21-11 92CH21-11 2004-09-01 TMP92CH21 TMP92CH21 3. Operation This section describes the basic components, functions and operation of the TMP92CH21 TMP92CH21. 3.1 CPU The TMP92CH21 TMP92CH21 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 TLCS-900/H1 CPU) 3.1.1 CPU Outline TLCS-900/H1 TLCS-900/H1 CPU is high-speed and high-performance CPU based on TLCS-900/L1 TLCS-900/L1 CPU. TLCS-900/H1 TLCS-900/H1 CPU has expanded 32-bit internal data bus to process instructions more quickly. Outline is as follows: Table 3.1.1 TMP92CH21 TMP92CH21 Outline Parameter TMP92CH21 TMP92CH21 Width of CPU address bus 24 bits Width of CPU data bus 32 bits Internal operating frequency Max 20 MHz Minimum bus cycle 1-clock access (50 ns at fSYS = 20MHz) Internal RAM 32-bit 1-clock access Internal boot ROM 32-bit 2-clock access 8- or 16-bit 2-clock access or Internal I/O 8- or 16-bit 5 to 6-clock access External SRAM, Masked ROM External SDRAM 8- or 16- or 32-bit 2-clock access (can insert some waits) 16- or 32-bit min. 1-clock access 8-bit min. 4-clock access External NAND flash (can insert some waits) Minimum instruction 1-clock (50 ns at fSYS =20MHz) execution cycle 2-clock (100 ns at fSYS =20MHz) Conditional jump Instruction queue buffer 12 bytes Compatible with TLCS-900/L1 TLCS-900/L1 Instruction set (LDX instruction is deleted) CPU mode Only maximum mode Micro DMA 8 channels 92CH21-12 92CH21-12 2004-09-01 TMP92CH21 TMP92CH21 3.1.2 Reset Operation When resetting the TMP92CH21 TMP92CH21, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input low for at least 20 system clocks (16 µs at fc = 40 MHz). At reset, since the clock doubler (PLL) is bypassed and clock-gear is set to 1/16, system clock operates at 1.25 MHz (fc = 40 MHz). When the reset has been accepted, the CPU performs the following: · Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H FFFF00H to FFFF02H FFFF02H: PC PC PC data in location FFFF00H FFFF00H data in location FFFF01H FFFF01H data in location FFFF02H FFFF02H · Sets the stack pointer (XSP) to 00000000H 00000000H. · Sets bits of the status register (SR) to 111 (thereby setting the interrupt level mask register to level 7). · Clears bits of the status register to 00 (there by selecting register bank 0). When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. · Initializes the internal I/O registers as table of "special function register" in section 5. · Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Internal reset is released as soon as external reset is released. The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP92CH21 TMP92CH21 may be spoiled because the control signals are unstable until power supply becomes stable after power on reset. VCC (3.3 V) RESET High-frequency oscillation stabilized time +20 system clock 0 s (Min) Figure 3.1.1 Power on Reset Timing Example 92CH21-13 92CH21-13 2004-09-01 TMP92CH21 TMP92CH21 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins like Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup Input Pin Operation Mode AM1 AM0 16-bit external bus starting (MULTI 16 mode) 0 1 32-bit external bus starting (MULTI 32 mode) 1 0 Boot (32-bit internal MROM) starting (BOOT mode) 1 1 RESET 92CH21-14 92CH21-14 2004-09-01 TMP92CH21 TMP92CH21 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92CH21 TMP92CH21. 000000H 000000H Internal I/O (8 Kbytes) Direct area (n) 000100H 000100H 001D00H 001D00H 002000H 002000H 006000H 006000H 64-Kbyte area (nn) Internal RAM (16 Kbytes) 010000H 010000H 3FE000H 3FE000H Boot (Internal MROM) (8 Kbytes) (Note 1) 400000H 400000H External memory F00000H F00000H Provisional emulator control (64 Kbytes) (Note 2) 16-Mbyte area (R) (-R) (R+) (R + R8/16 R8/16) (R + d8/16) (nnn) F10000H F10000H External memory FFFF00H FFFF00H Vector table (256 bytes) (Note 3) FFFFFFH ( = Internal area) Figure 3.2.1 Memory Map Note 1: Boot program (Internal MROM) is mapped only for BOOT mode. At another starting mode, its area (3FE000H 3FE000H to 3FFFFFH) is mapped to external-memory. Note 2: Provisional emulator control area is for an emulator, it is mapped F00000H F00000H to F0FFFFH after reset. On emulator WR signal and RD signal are asserted, when this area is accessed. Be carefull to use external memory. Note 3: Don't use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved for an emulator. 92CH21-15 92CH21-15 2004-09-01 TMP92CH21 TMP92CH21 3.3 Clock Function and Stand-by Function TMP92CH21 TMP92CH21 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and (4) noise reducing circuit. They are used for low power, low noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFR 3.3.3 System clock controller 3.3.4 Clock doubler (PLL) 3.3.5 Noise reducing circuits 3.3.6 Stand-by controller 92CH21-16 92CH21-16 2004-09-01 TMP92CH21 TMP92CH21 The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual clock mode (X1, X2, XT1 and XT2 pins) and (c) triple clock mode (X1, X2, XT1 and XT2 pins and PLL). Figure 3.3.1 shows a transition figure. IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt IDLE1 mode (Operate only oscillator) Reset (fOSCH/32) Release reset Instruction NORMAL mode Interrupt Instruction Instruction Interrupt STOP mode (Stops all circuits) Dual clock mode transition figure Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) Interrupt STOP mode (Stops all circuits) Note Instruction Instruction Instruction NORMAL mode (4 × fOSCH/gear value/2) Note Instruction Interrupt Instruction SLOW mode (fs/2) Interrupt Instruction Interrupt Using PLL (c) Note 1: Interrupt SLOW mode (fs/2) Instruction IDLE1 mode Instruction (Operate oscillator and PLL) Interrupt STOP mode (Stops all circuits) (fOSCH/gear value/2) Instruction Interrupt Instruction Interrupt Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Instruction IDLE2 mode (I/O operate) Instruction Interrupt NORMAL mode (fOSCH/gear value/2) Instruction Interrupt Instruction Interrupt (b) IDLE2 mode (I/O operate) Reset (fOSCH/32) Release reset IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Triple clock mode transition figure It's prohibited to control PLL in SLOW mode when shifting from SLOW mode to NORMAL mode with use of PLL. (PLL start up/stop/change write to PLLCR0, PLLCR1 register) Note 2: If you shift from NORMAL mode with use of PLL to NORMAL mode, execute following setting in the same order. 1) Change CPU clock (PLLCR0 "0") 2) Stop PLL circuit (PLLCR1 "0") Note 3: It's prohibited to shift from NORMAL mode with use of PLL to STOP mode directly. You should set NORMAL mode once, and then shift to STOP mode. (You should stop high-frequency oscillator after you stop PLL.) Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 is called the system clock fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is defined to as one state. 92CH21-17 92CH21-17 2004-09-01 TMP92CH21 TMP92CH21 3.3.1 Block Diagram of System Clock SYSCR0 SYSCR2 Warm-up timer (High/low-frequency oscillator) T T0 fFPH Lock up timer (PLL) ÷4 ÷8 SYSCR0 XT1 XT2 Low-frequency oscillator fs PLLCR1, PLLCR0 fs SYSCR0 X2 Clock doubler (PLL) fc/4 Selector ÷2 fc/8 ÷4 ÷8 ÷16 Clock-gear SYSCR1 PLLCR0 USB Controller fUSB (48 MHz) = fOSCH × 16/3 USBCR1 fSYS CPU RAM, ROM TMRA0 to 3,TMRB0 T0 LCDC Memory controller Interrupt controller FIO fIO SYSCR1 fc/16 ÷2 High-frequency oscillator fOSCH fSYS fc/2 fPLL = fOSCH × 4 X1 ÷2 fc NAND flash controller Prescaler SIO0 to SIO1 2 IS Prescaler I/O ports TSI SDRAMC RTC fs MLD/ALM ADC WDT Figure 3.3.2 Block Diagram of System Clock Table 3.3.1 Selection Example for fOSCH High-frequency Oscillation: fOSCH (a) Needed USB with PLL (b) No needed USB with PLL (c) No needed USB without PLL System Clock: fSYS USB Clock: fUSB 9.0 MHz 10.0 MHz (max) 40.0 MHz (max) 18 MHz 20 MHz (max) 20 MHz (max) 48 MHz - - Note: To use USB, high-frequency oscillator should be 9.0 MHz. 92CH21-18 92CH21-18 2004-09-01 TMP92CH21 TMP92CH21 3.3.2 SFR 7 SYSCR0 (10E0H 10E0H) Bit symbol XEN Read/Write After reset 6 4 3 XTEN 2 1 0 WUEF R/W R/W 1 1 Highfrequency oscillator (fc) Lowfrequency oscillator (fs) 0: Stop 1: Oscillation Function 5 0 0: Stop 1: Oscillation Warm-up timer 0: Write don't care 1: Write start timer 0: Read end warm-up 1: Read do not end warm-up 7 3 2 1 0 Bit symbol SYSCK GEAR2 GEAR1 GEAR0 Read/Write R/W After reset SYSCR1 (10E1H 10E1H) 6 5 4 0 Function 0 0 Select Select gear value of high-frequency (fc) system clock 000: fc 0: fc 001: fc/2 1: fs 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (10E2H 10E2H) R/W 1 6 5 4 3 2 Bit symbol - WUPTM1 WUPTM0 HALTM1 R/W R/W R/W R/W R/W 1 0 1 0 HALTM0 Read/Write 1 1 After reset Function 0 Always write "0" Warm-up timer 00: Reserved 8 01: 2 /input frequency 14 10: 2 /input frequency 16 11: 2 /input frequency HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode Note 1: The unassigned register, SYSCR0, SYSCR0, SYSCR1, and SYSCR2 are read as undefined value. Note 2: By reset, low-frequency oscillator is enabled. Figure 3.3.3 SFR for System Clock 92CH21-19 92CH21-19 2004-09-01 TMP92CH21 TMP92CH21 7 6 5 4 3 2 1 0 Bit symbol PROTECT EXTIN Read/Write R R/W R/W R/W After reset 0 0 1 1 Protect flag 0: OFF 1: ON 1: External clock Fc oscillator driver ability Fs oscillator driver ability 1: Normal 1: Normal 0: Weak EMCCR0 (10E3H 10E3H) 0: Weak Function EMCCR1 (10E4H 10E4H) Bit symbol Read/Write After reset Function EMCCR2 (10E5H 10E5H) DRVOSCH DRVOSCL Bit symbol Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write Read/Write After reset Function Figure 3.3.4 SFR for System Clock 92CH21-20 92CH21-20 2004-09-01 TMP92CH21 TMP92CH21 7 5 Bit symbol FCSEL LUPFG Read/Write R/W R After reset PLLCR0 (10E8H 10E8H) 6 0 0 Function Select fc clock 0: fOSCH 1: fPLL 4 3 2 1 0 3 2 1 0 Lock up timer status flag 0: Not end 1: End Note: Be carefull that logic of PLLCR0 is different from 900/L1 900/L1's DFM. 7 PLLCR1 (10E9H 10E9H) 6 Bit symbol 4 PLLON Read/Write 5 R/W After reset Function 0 Control on/off 0: OFF 1: ON Figure 3.3.5 SFR for PLL 7 PxDR (xxxxH) Bit symbol 6 5 4 3 2 1 0 Px7D Px6D Px5D Px4D Px3D Px2D Px1D Px0D 1 1 1 1 1 1 1 1 Read/Write After reset R/W Function Output/input buffer drive-register for stand-by mode (Purpose and how to use) This register is used to set each pin status at stand-by mode. All ports have this format's register. ("x" means port name.) For each register, refer to "3.5 Function of ports". Before "Halt" instruction is executed, set each register according to the expected pin-status. They will be effective after CPU executed "Halt" instruction. It is not depend on stand-by mode (IDLE2, IDLE1 or STOP). The table to control output/input buffer is below. OE PxnD Output Buffer Input Buffer 0 0 OFF OFF 0 1 OFF ON 1 0 OFF OFF 1 1 ON OFF Note 1: OE means an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note 2: "n" in PxnD means bit number of PORTx. Figure 3.3.6 SFR for Drive Register 92CH21-21 92CH21-21 2004-09-01 TMP92CH21 TMP92CH21 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 changes the system clock to either fc or fs, SYSCR0 and SYSCR0 control enabling and disabling of each oscillator, and SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The combination of settings = 1, = 0 and = 100 will cause the system clock (fSYS) to be set to fc/32 (fc/16 × 1/2) after reset. For example, fSYS is set to 1.25 MHz when the 40 MHz oscillator is connected to the X1 and X2 pins. (1) Switching from normal mode to slow mode When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. The warm-up time can be selected using SYSCR2. This warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2. Table 3.3.2 shows the warm-up time. Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.2 Warm-up Times at fOSCH = 40 MHz, fs = 32.768 kHz Warm-up Time SYSCR2 Change to Normal Mode 8 6.4 (µs) 14 409.6 (µs) 01 (2 /frequency) 10 (2 /frequency) 16 11 (2 /frequency) 1.638 (ms) 92CH21-22 92CH21-22 Change to Slow Mode 7.8 (ms) 500 (ms) 2000 (ms) 2004-09-01 TMP92CH21 TMP92CH21 Example 1: Setting the clock Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 SYSCR1 SYSCR2 WUP: EQU EQU EQU LD SET SET BIT JR SET RES 10E0H 10E0H 10E1H 10E1H 10E2H 10E2H (SYSCR2), 0 X 1 1 - - X X B ; 6, (SYSCR0) ; 2, (SYSCR0) ; 2, (SYSCR0) ; NZ, WUP ; 3, (SYSCR1) ; 7, (SYSCR0) ; 16 Sets warm-up time to 2 /fs. Enables low-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fc to fs. Disables high-frequency oscillation. X: Don't care, -: No change X1, X2 pins XT1, XT2 pins Warm-up timer Counts up by fSYS Counts up by fs End of warm-up timer fs fc System clock fSYS Clears and starts Enables low-frequency warm-up timer Chages fSYS from fc to fs Disabiles high-frequency End of warm-up timer 92CH21-23 92CH21-23 2004-09-01 TMP92CH21 TMP92CH21 Example 2: Setting the clock Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 SYSCR1 SYSCR2 WUP: EQU EQU EQU LD SET SET BIT JR RES RES 10E0H 10E0H 10E1H 10E1H 10E2H 10E2H (SYSCR2), 0 X 1 0 - - X X B ; 7, (SYSCR0) ; 2, (SYSCR0) ; 2, (SYSCR0) ; NZ, WUP ; 3, (SYSCR1) ; 6, (SYSCR0) ; 14 Sets warm-up time to 2 /fc. Enables high-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fs to fc. Disables low-frequency oscillation. X: Don't care, -: No change X1, X2 pins XT1, XT2 pins Warm-up timer Counts up by fc Counts up by fSYS End of warm-up timer fs fc System Clock fSYS Enables Clears and starts high-frequency warm-up timer Changes fSYS from fs to fc End of warm-up timer 92CH21-24 92CH21-24 Disables low-frequency 2004-09-01 TMP92CH21 TMP92CH21 (2) Clock gear controller fFPH is set according to the contents of the clock gear select register SYSCR1 to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. Example 3: Changing to a high-frequency gear SYSCR1 EQU 10E1H 10E1H LD (SYSCR1), XXXX0000B XXXX0000B ; Changes fSYS to fc/2. X: Don't care (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 register.It is necessary the warm-up time until changing after writing the register value. There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing.To execute the instruction next to the clock gear switching instruction by the clock gear after changing, input the dummy instruction as follows (instruction to execute the write cycle). Example: SYSCR1 EQU LD LD 10E1H 10E1H (SYSCR1), XXXX0001B XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed 92CH21-25 92CH21-25 2004-09-01 TMP92CH21 TMP92CH21 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. It can use the low-speed-frequency oscillator, even though the internal clock is high-frequency. A reset initializes PLL to stop status, setting to PLLCR0, PLLCR1 register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lock up time and it is measured by 16-stage binary counter. Lock up time is about 1.6 ms at fOSCH = 10 MHz. Note 1: Input frequency limitation for PLL The limitation of input frequency (High-frequency oscillation) for PLL is following. fOSCH = 6 to 10 MHz (VCC = 3.0 to 3.6 V) Note 2: PLLCR0 The logic of PLLCR0 is different from 900/L1 900/L1's DFM. Be careful to judge an end of lock up time. The following is an setting example for PLL starting and PLL stopping. Example 1: PLL starting PLLCR0 PLLCR1 LUP: EQU EQU LD BIT JR LD 10E8H 10E8H 10E9H 10E9H (PLLCR1), 1 X X X X X X X B 5, (PLLCR0) Z, LUP (PLLCR0), X 1 X X X X X X B ; ; ; ; Enables PLL operation and starts lock up. Detects end of lock up. Changes fc from 10 MHz to 40 MHz. X: Don't care PLL output: fPLL Lock up timer Counts up by fOSCH During lock up After lock up System clock fSYS Starts PLL operation and starts lock up 92CH21-26 92CH21-26 Changes from 10 MHz to 40 MHz Ends of lock up 2004-09-01 TMP92CH21 TMP92CH21 Example 2: PLL stopping PLLCR0 PLLCR1 EQU EQU LD LD 10E8H 10E8H 10E9H 10E9H (PLLCR0), X0XXXXXXB (PLLCR1), 0XXXXXXXB ; ; Changes fc from 40 MHz to10 MHz. Stop PLL. X: Don't care PLL output: fPLL System clock fSYS Changes from 40 MHz to 10 MHz Stops PLL operation 92CH21-27 92CH21-27 2004-09-01 TMP92CH21 TMP92CH21 Limitation point on the use of PLL 1. It's prohibited to execute PLL enable/disable control in the SLOW mode (fs) (writing to PLLCR0 and PLLCR1). You should control PLL in the NORMAL mode. 2. If you stop PLL operation during using PLL, you should execute following setting in the same order. LD LD 3. (PLLCR0), 00H (PLLCR1), 00H ; ; Change the clock fPLLto fOSCH PLL stop If you stop high-frequency oscillator during using PLL, you should stop PLL before you stop high-frequency oscillator. Examples of settings are below. (1) Start up/change control (OK) WUP: LUP: LD BIT JR LD LD BIT JR LD (OK) Low-frequency oscillator operation mode (fs) (high-frequency oscillator STOP) High-frequency oscillator start up High-frequency oscillator operation mode (fOSCH) PLL start up PLL use mode (fPLL) (SYSCR0), 2, (SYSCR0) NZ, WUP (SYSCR1), (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), 1 1 - - - 1 - - B ; ; ; - - - - 0 - - - B ; 1 - - - - - - - B ; ; ; - 1 - - - - - - B ; High-frequency oscillator start/warm-up start Check for the flag of warm-up end Change the system clock fs to fOSCH PLL start-up/lock up start Check for the flag of lock up end Change the system clock fOSCH to fPLL Low-frequency oscillator operation mode (fs) (high-frequency oscillator Operate) High-frequency oscillator operation mode (fOSCH) PLL start up PLL use mode (fPLL) LUP: LD LD BIT JR LD (SYSCR1), (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), - - - - 0 - - - B ; 1 - - - - - - - B ; ; ; - 1 - - - - - - B ; Change the system clock fs to fOSCH PLL start-up/lock up start Check for the flag of lock up end Change the system clock fOSCH to fPLL (Error) Low-frequency oscillator operation mode (fs) (high-frequency oscillator STOP) High-frequency oscillator start up PLL start up PLL use mode (fPLL) WUP: LUP: LD BIT JR LD BIT JR LD LD (SYSCR0), 2, (SYSCR0) NZ, WUP (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), (SYSCR1), 1 1 - - - 1 - - B ; ; ; 1 - - - - - - - B ; ; ; - 1 - - - - - - B ; - - - - 0 - - - B ; 92CH21-28 92CH21-28 High-frequency oscillator start/warm-up start Check for the flag of warm-up end PLL start-up/lock up start Check for the flag of lock up end Change the internal clock fOSCH to fPLL Change the system clock fs to fPLL 2004-09-01 TMP92CH21 TMP92CH21 (2) Change/stop control (OK) LD LD LD LD PLL use mode (fPLL) High-frequency oscillator operation mode (fOSCH) PLL Stop Low-frequency oscillator operation mode (fs) High-frequency oscillator stop (PLLCR0), (PLLCR1), (SYSCR1), (SYSCR0), - 0 - 0 0 - - - - - - - - - - - - - 1 - - - - - - - - - - - - - B B B B ; ; ; ; Change the system clock fPLL to fOSCH PLL stop Change the system clock fOSCH to fs High-frequency oscillator stop (Error) PLL use mode (fPLL) Low-frequency oscillator operation mode (fs) PLL stop High-frequency oscillator stop LD LD LD LD (OK) (SYSCR1), (PLLCR0), (PLLCR1), (SYSCR0), - - 0 0 - 0 - - - - - - - - - - 1 - - - - - - - - - - - - - - - B B B B ; ; ; ; Change the system clock fPLL to fs Change the internal clock (fC) fPLL to fOSCH PLL stop High-frequency oscillator stop PLL use mode (fPLL) Set the STOP mode High-frequency oscillator operation mode (fOSCH) PLL stop Halt (High-frequency oscillator stop) LD (SYSCR2), - - - - 0 1 - - B ; LD LD HALT (PLLCR0), (PLLCR1), - 0 - - - - - - B ; 0 - - - - - - - B ; ; Set the STOP mode (This command can execute before use of PLL) Change the system clock fPLL to fOSCH PLL stop Shift to STOP mode (Error) PLL use mode (fPLL) Set the STOP mode Halt (High-frequency oscillator stop) LD (SYSCR2), - - - - 0 1 - - B ; HALT ; 92CH21-29 92CH21-29 Set the STOP mode (This command can execute before use of PLL) Shift to STOP mode 2004-09-01 TMP92CH21 TMP92CH21 3.3.5 Noise Reduction Circuits Noise reduction circuits are built-in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 X1 pin Enable oscillation Resonator EMCCR0 C2 X2 pin (Setting method) The drive ability of the oscillator is reduced by writing "0" to EMCCR0 register. By reset, is initialized to "1" and the oscillator starts oscillation by normal drivability when the power-supply is on. Note: This function (EMCCR0 = "0") is available to use in case of fOSCH = 6 to 10 MHz condition. 92CH21-30 92CH21-30 2004-09-01 TMP92CH21 TMP92CH21 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Enable oscillation Resonator EMCCR0 C2 XT2 pin fS (Setting method) The drive ability of the oscillator is reduced by writing 0 to the EMCCR0 register. By reset, is initialized to "1". (3) Single drive for high-frequency oscillator (Purpose) Not need twin drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 register. X2 pin is always outputted "1". By reset, is initialized to "0". 92CH21-31 92CH21-31 2004-09-01 TMP92CH21 TMP92CH21 (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is in the state which is fetch impossibility by stopping of clock, memory control register (memory controller, MMU) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR, BROMCR 2. MMU LOCALPX/PY/PZ, LOCALLX/LY/LZ, LOCALRX/RY/RZ, LOCALWX/WY/WZ, 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 4. PLL PLLCR0, PLLCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0. By reset, protection becomes OFF. And INTP0 interruption occurs when write operation to specified SFR was executed with protection on state. 92CH21-32 92CH21-32 2004-09-01 TMP92CH21 TMP92CH21 3.3.6 Stand-by Controller (1) HALT modes and port drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 register and each pin-status is set according to PxDR register. 7 PxDR (xxxxH) 5 4 3 2 1 0 Px7D Px6D Px5D Px4D Px3D Px2D Px1D Px0D 1 Bit symbol 6 1 1 1 1 1 1 1 Read/Write R/W After reset Function Output/input buffer drive register for stand-by mode (Purpose and how to use) · This register is used to set each pin status at stand-by mode. · All ports have this format's register. ("x" means port name.) · For each register, refer to 3.5 function of ports. · Before "Halt" instruction is executed, set each register according to the expected pin status. They will be effective after CPU executed "Halt" instruction. · It is not depend on stand-by mode (IDLE2, IDLE1 or STOP). · The table to control Output/Input buffer is below. OE Output Buffer Input Buffer 0 0 OFF OFF 0 1 OFF ON 1 0 OFF OFF 1 Note 1: PxnD 1 ON OFF OE means an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note 2: "n" in PxnD means bit number of PORTx The subsequent actions performed in each mode are as follows: 1. IDLE2: only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. Table 3.3.3 shows the registers of setting operation during IDLE2 mode. Table 3.3.3 SFR Setting Operation during IDLE2 Mode Internal I/O SFR TMRA01 TMRA01 TA01RUN TA01RUN TMRA23 TMRA23 TA23RUN TA23RUN TMRB0 TB0RUN SIO0 SC0MOD1 SIO1 SC1MOD1 AD converter ADMOD1 WDT WDMOD 2. IDLE1: Only the oscillator, RTC (real-time clock), USBC and MLD continue to operate. 3. STOP: All internal circuits stop operating. 92CH21-33 92CH21-33 2004-09-01 TMP92CH21 TMP92CH21 The operation of each of the different HALT modes is described in Table 3.3.4. Table 3.3.4 I/O Operation during HALT Modes HALT Mode IDLE2 IDLE1 STOP SYSCR2 11 10 01 CPU Stop I/O ports Depend on PxDR register setting TMRA, TMRB SIO Block AD converter Available to select operation block Stop WDT I2S, LCDC, SDRAMC, Interrupt controller Operate USBC, RTC, MLD Operate (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register and the HALT modes. The details for releasing the halt status are shown in Table 3.3.4. · Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status.When the interrupt request level set before executing the HALT instruction exceeds the value of interrupt mask register, the interrupt due to the source is processed after releasing the HALT mode, and CPU status executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not executed. (in non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 to INT4, INTKEY, INTRTC, INTALM and INTUSB interrupts, even if the interrupt request level set before executing the halt instruction is less than the value of the interrupt mask register, releasing the the HALT mode is executed. In this case, interrupt processing, and CPU starts executing the instruction next to the halt instruction, but the interrupt request flag is held at "1". · Releasing by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessry enough resetting time (see Table 3.3.6) to set the operation of the oscillator to be stable. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the HALT instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the HALT instruction is executed.) 92CH21-34 92CH21-34 2004-09-01 TMP92CH21 TMP92CH21 Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation Interrupt Enabled HALT Mode Interrupt Disabled (Interrupt level) (Interrupt mask) Status of Received Interrupt (Interrupt level) < (Interrupt mask) IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP × × - - - *1 × * 1 INTALM0 to INTALM4 INTTA0 to INTTA3, INTTB0 to INTTB1 × × × × × INTRX0 to INTRX1, TX0 to TX1 × × × × × INTTBO0, INTI2S × × × × × INTAD, INT5 × × × × × INTKEY *1 INTRTC *1 INTUSB *1 * 1 * 1 * 1 INTLCD Interrupt INT0 to INT4 (Note 1) Source of Halt State Clearance INTWD × × × × × RESET × Initialize LSI : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the Halt instruction. ×: It can not be used to release the HALT mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. Example: Releasing IDLE1 mode An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8203H 8203H 8206H 8206H 8209H 8209H 820BH 820BH 820EH 820EH LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; ; ; ; ; Selects INT0 interrupt rising edge. Sets INT0 interrupt level to 6. Sets interrupt level to 5 for CPU. Sets HALT mode to IDLE1 mode. Halts CPU. INT0 INT0 interrupt routine RETI 820FH 820FH LD XX, XX 92CH21-35 92CH21-35 2004-09-01 TMP92CH21 TMP92CH21 (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D31 Data Data RD WR Interrupt for release IDLE2 mode Figure 3.3.7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC, USBC and MLD continue to operate. The system clock stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.8 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 D0 to D31 Data Data RD WR Interrupt for release IDLE1 mode Figure 3.3.8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 92CH21-36 92CH21-36 2004-09-01 TMP92CH21 TMP92CH21 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.9 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time X1 A0 to A23 D0 to D31 Data Data RD WR Interrupt for release STOP mode Figure 3.3.9 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.6 Example of Warm-up Time after Releasing STOP Mode at fOSCH = 40 MHz, fs = 32.768 kHz SYSCR2 SYSCR1 01 (2 ) 10 (214) 0 (fc) 6.4 µs 409.6 µs 1.638 ms 1 (fs) 7.8 ms 500 ms 2000 ms 8 92CH21-37 92CH21-37 11 (216) 2004-09-01 TMP92CH21 TMP92CH21 Table 3.3.7 Input Buffer State Table Input Buffer State Input Function Name During Reset D0 to D7 D0 to D7 OFF P10 to P17 D8 to D15 16bit start : OFF 32bit start : OFF Port Name In HALT mode (IDLE1/2/STOP) When the CPU is operating = 1 = 0 P30 to P37 D24 to D31 P60 to P67 - P71 to P72 When used as When used as Input pin Function pin Input pin Function pin Input pin - OFF - OFF - - 16bit start : OFF 32bit start : OFF Boot start : ON ON upon external read OFF OFF - - - - - ON OFF - WAIT P90 When used as ON NDRB P76 16bit start : ON 32bit start : OFF Boot start : ON - P75 When used as - Boot start : ON D16 to D23 When used as Function pin P20 to P27 When used as - - P91 RXD0 P92 CTS0, SCLK0 ON - - - - ON ON OFF P93 to P94 1 P96 * ON ON ON OFF INT4 P97 INT5 1 PA0 to PA7* KI0-KI7 PC0 INT1 PC2 INT2 PC3 ON INT0 PC1 OFF INT3 PC6 to PC7 - - - - PF0 - - - - PF1 RXD0/1 PF2 CTS0/1 SCLK0/1 ON ON OFF 2 PG0 to PG2* PG3 *2 - ADTRG PJ5 to PJ6 - PL4 to PL7 - OFF ON - ON ON upon port read - ON - ON - - ON - ON: The buffer is always turned on. A current flows the input buffer if the input pin is not driven. OFF ON - ON - - *1: Port having a pull-up/pull-down resistor. *2: AIN input does not cause a current to flow through the OFF: The buffer is always turned off. -: No applicable buffer. 92CH21-38 92CH21-38 2004-09-01 TMP92CH21 TMP92CH21 Table 3.3.8 Output Buffer State Table (1/2) Output Buffer State Port Name Output Function Name During Reset In HALT mode (IDLE1/2/STOP) When the CPU is operating =1 =0 D0~D7 When used as When used as When used as When used as When used as Function pin Output pin Function pin Output pin Function pin Output pin - D0~D7 P10~P17 When used as D8~D15 P20~P27 D16~D23, OFF KO0~KO7 P30~P37 - OFF D24~D31 P40~P47 - ON upon external write A0-A7 P50~P57 A8~A15 P60~P67 A16~A23 P70 WRLL , NDRE P72 WRLU , NDWE P73 EA24 P74 EA25 P75 R/W P76 - OFF RD P71 ON P80 ON ON - - ON OFF CS1 , SDCS - CS0 P81 OFF P82 P83 P84 P85 ON ON OFF CS2 , CSZA , SDCS CS3 CSZB , WRUL , ON ND0CE CSZC , WRUU , ND1CE P86 CSZD , SRULB P87 CSZE , SRUUB P90 TXD0, I2SCKO P91 SCLK0, I2SWS P93 ON OFF I2SDO P92 ON LGOE0 P94 P95 1 OFF LGOE1 LGOE2, CLK32KO CLK32KO P96* PX P97 PY ON: The buffer is always turned on. OFF: The buffer is always turned off. -: No applicable ON OFF - - - *1: Port having a pull-up/pull-down resistor. 92CH21-39 92CH21-39 2004-09-01 TMP92CH21 TMP92CH21 Table 3.3.9 Output Buffer State Table (2/2) Output Buffer State Output Function Name Port Name During Reset In HALT mode (IDLE1/2/STOP) When the CPU is operating =1 =0 PA3~PA6 When used as When used as When used as When used as When used as Function pin *1 When used as Output pin Function pin Output pin Function pin Output pin - LD8~LD11 PC0 TA1OUT PC1 TA3OUT PC2 - - TB0OUT0 PC3 - PC6 KO8, LDIV PC7 OFF CSZF , LCP1 PF0 ON ON OFF - - - TXD0, TXD1 PF1 - PF2 ON ON ON PF7 SDCLK MX PG3 MY PJ0 OFF SDWE , SRWR ON SDCAS , SRLUB PJ2 - SDRAS , SRLLB PJ1 - OFF SCLK0, SCLK1 PG2 - ON PJ3 - - ON SDLLDQM PJ4 - OFF SDLUDQM PJ5 PJ6 SDULDQM, NDALE SDUUDQM, OFF OFF NDCLE PJ7 PK0 ON SDCKE ON ON ON OFF LCP0 PK1 LLP PK2 ON LFR PK3 LBCD PL0~PL3 LD0~LD3 ON PL4~PL7 LD4~LD7 OFF PM1 MLDALM PM2 MLDALM , ON ALARM X2 - XT2 - ON ON: The buffer is always turned on. OFF: The buffer is always turned off. -: No applicable - - IDLE2/1:ON, STOP:output "H" IDLE2/1:ON, STOP:output "HZ" *1: Port having a pull-up/pull-down resistor. 92CH21-40 92CH21-40 2004-09-01 TMP92CH21 TMP92CH21 3.4 Interrupts Interrupts are controlled by the CPU Interrupt mask register (bits12 to 14 of the status register) and by the built-in interrupt controller. The TMP92CH21 TMP92CH21 has a total of 50 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources · Software interrupts: 8 sources · Illegal instruction interrupt: 1 source Internal interrupts: 34 sources · Internal I/O interrupts: 26 sources · Micro DMA transfer end interrupts: 8 sources External interrupts: 7 sources · Interrupts on external pins (INT0 to INT5, INTKEY) A fixed individual interrupt vector number is assigned to each interrupt source. Any one of seven levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. When more than one interrupt are generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU interrupt mask register . If the priority level of the interrupt is greater than or equal to the value in the interrupt mask register, the CPU accepts the interrupt. However, software interrupts and illegal instruction interrupts generated by the CPU are processed irrespective of the value in . The value in the interrupt mask register can be changed using the EI instruction (EI num sets to num). For example, the command EI 3 enables the acceptance of all non-maskable interrupts and of maskable interrupts whose priority level, as set in the interrupt controller, is 3 or higher. The commands EI and EI 0 enable the acceptance of all non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence both are equivalent to the command EI 1). The DI instruction (sets to 7) is exactly equivalent to the EI 7 instruction. The DI instruction is used to disable all maskable interrupts (since the priority level for maskable interrupts ranges from 0 to 6). The EI instruction takes effect as soon as it is executed. 92CH21-41 92CH21-41 2004-09-01 TMP92CH21 TMP92CH21 In addition to the general purpose interrupt processing mode described above, there is also a micro DMA processing mode. In micro DMA mode the CPU automatically transfers data in one-byte, two-byte or four-byte blocks; this mode allows high-speed data transfer to and from internal and external memory and internal I/O ports. In addition, the TMP92CH21 TMP92CH21 also has a software start function in which micro DMA processing is requested in software rather than by an interrupt. Figure 3.4.1 is a flowchart showing overall interrupt processing. Micro DMA soft start request Interrupt processing Interrupt specified by micro DMA start vector ? YES Clear interrupt request flag NO Interrupt vector calue "V" read interrupt request F/F clear Data transfer by micro DMA Micro DMA processing General-purpose interrupt processing PUSH PC PUSH SR SR Level of accepted interrupt + 1 INTNEST INTNEST + 1 COUNT COUNT - 1 COUNT = 0 YES NO Clear vector register generating micro DMA transfer end interrupt (INTTC0 to 7) PC (FFFF00H FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 92CH21-42 92CH21-42 2004-09-01 TMP92CH21 TMP92CH21 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3). And executes only steps (2), (4) and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level have been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: the smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (pointed to by XSP). (3) The CPU sets the value of the CPU's interrupt mask register to the priority level for the accepted interrupt plus 1. However, if the priority level for the accepted interrupt is 7, the register's value is set to 7. (4) The CPU increments the interrupt nesting counter INTNEST by 1. (5) The CPU jumps to the address given by adding the contents of address FFFF00H FFFF00H + the interrupt vector, then starts the interrupt processing routine. On completion of interrupt processing, the RETI instruction is used to return control to the main routine. RETI restores the contents of the program counter and the status register from the stack and decrements the interrupt nesting counter INTNEST by 1. Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request is received for an interrupt with a priority level equal to or greater than the value set in the CPU interrupt mask register , the CPU will accept the interrupt. The CPU interrupt mask register is then set to the value of the priority level for the accepted interrupt plus 1. If during interrupt processing, an interrupt is generated with a higher priority than the interrupt currently being processed, or if, during the processing of a non-maskable interrupt processing, a non-maskable interrupt request is generated from another source, the CPU will suspend the routine which it is currently executing and accept the new interrupt. When processing of the new interrupt has been completed, the CPU will resume processing of the suspended interrupt. If the CPU receives another interrupt request while performing processing steps (1) to (5), the new interrupt will be sampled immediately after execution of the first instruction of its interrupt processing routine. Specifying DI as the start instruction disables nesting of maskable interrupts. After a reset, initializes the interrupt mask register to 111, disabling all maskable interrupts. Table 3.4.1 shows the TMP92CH21 TMP92CH21 interrupt vectors and micro DMA start vectors. FFFF00H FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area. 92CH21-43 92CH21-43 2004-09-01 TMP92CH21 TMP92CH21 Table 3.4.1 TMP92CH21 TMP92CH21 Interrupt Vectors and Micro DMA Start Vectors Default Priority Type Interrupt Source and Source of Micro DMA Request Vector Value Micro Address Refer DMA Start to Vector Vector 1 Reset or [SWI0] instruction 0000H 0000H FFFF00H FFFF00H 2 [SWI1] instruction 0004H 0004H FFFF04H FFFF04H 3 Illegal instruction or [SWI2] instruction 0008H 0008H FFFF08H FFFF08H 4 [SWI3] instruction 000CH 000CH FFFF0CH 5 Non- [SWI4] instruction 0010H 0010H FFFF10H FFFF10H 6 maskable [SWI5] instruction 0014H 0014H FFFF14H FFFF14H 7 [SWI6] instruction 0018H 0018H FFFF18H FFFF18H 8 [SWI7] instruction 001CH 001CH FFFF1CH 9 (Reserved) 0020H 0020H FFFF20H FFFF20H 10 INTWD: Watchdog Timer 0024H 0024H FFFF24H FFFF24H - Micro DMA 11 - - - (Note1) INT0: INT0 pin input 0028H 0028H FFFF28H FFFF28H 0AH (Note 2) 12 INT1: INT1 pin input 002CH 002CH FFFF2CH 0BH 13 INT2: INT2 pin input 0030H 0030H FFFF30H FFFF30H 0CH 14 INT3: INT3 pin input 0034H 0034H FFFF34H FFFF34H 0DH 15 INT4: INT4 pin input (TSI) 0038H 0038H FFFF38H FFFF38H 0EH 16 INTALM0: ALM0 (8 kHz) 003CH 003CH FFFF3CH 0FH 17 INTALM1: ALM1 (512 Hz) 0040H 0040H FFFF40H FFFF40H 10H 18 INTALM2: ALM2 (64 Hz) 0044H 0044H FFFF44H FFFF44H 11H 19 INTALM3: ALM3 (2 Hz) 0048H 0048H FFFF48H FFFF48H 12H 20 INTALM4: ALM4 (1 Hz) 004CH 004CH FFFF4CH 13H 21 INTP0: Protect0 (Write to special SFR) 0050H 0050H FFFF50H FFFF50H 14H 22 (Reserved) 0054H 0054H FFFF54H FFFF54H 15H 23 INTTA0: 8-bit timer 0 0058H 0058H FFFF58H FFFF58H 16H 24 INTTA1: 8-bit timer 1 005CH 005CH FFFF5CH 17H 25 INTTA2: 8-bit timer 2 0060H 0060H FFFF60H FFFF60H 18H 26 INTTA3: 8-bit timer 3 0064H 0064H FFFF64H FFFF64H 19H 27 INTTB0: 16-bit timer 0 0068H 0068H FFFF68H FFFF68H 1AH 28 INTTB1: 16-bit timer 0 006CH 006CH FFFF6CH 1BH 29 INTKEY: Key-on wakeup 0070H 0070H FFFF70H FFFF70H 1CH 30 INTRTC: RTC (Alarm interrupt) 0074H 0074H FFFF74H FFFF74H 1DH 31 INTTBO0: 16-bit timer 0 (Overflow) 0078H 0078H FFFF78H FFFF78H 1EH 32 INTLCD: LCDC/LP pin 007CH 007CH FFFF7CH 1FH 33 INTRX0: Serial receive (Channel 0) 0080H 0080H FFFF80H FFFF80H 20H (Note 2) 34 INTTX0: Serial transmission (Channel 0) 0084H 0084H FFFF84H FFFF84H 21H 35 INTRX1: Serial receive (Channel 1) 0088H 0088H FFFF88H FFFF88H 22H (Note 2) 36 INTTX1: Serial transmission (Channel 1) 008CH 008CH FFFF8CH 23H 37 (Reserved) 0090H 0090H FFFF90H FFFF90H 24H 38 (Reserved) 0094H 0094H FFFF94H FFFF94H 25H 39 INT5: INT5 pin input 0098H 0098H FFFF98H FFFF98H 26H 40 INTI2S: I S (Channel 0) 009CH 009CH FFFF9CH 27H 41 INTNDF0 (NAND flash controller channel 0) 00A0H 00A0H FFFFA0H 28H 42 INTNDF1 (NAND flash controller channel 1) 00A4H 00A4H FFFFA4H 29H 43 (Reserved) 00A8H 00A8H FFFFA8H 2AH 44 (Reserved) 00ACH 00ACH FFFFACH 2BH 45 (Reserved) 00B0H 00B0H FFFFB0H 2CH 46 (Reserved) 00B4H 00B4H FFFFB4H 2DH 47 (Reserved) 00B8H 00B8H FFFFB8H 2EH 48 INTUSB: USB 00BCH 00BCH FFFFBCH 2FH 49 (Reserved) 00C0H 00C0H FFFFC0H 30H 50 (Reserved) 00C4H 00C4H FFFFC4H 31H Maskable 2 92CH21-44 92CH21-44 2004-09-01 TMP92CH21 TMP92CH21 Default Priority Type Interrupt Source and Source of Micro DMA Request Vector Value Micro Address Refer DMA Start to Vector Vector 51 (Reserved) 00C8H 00C8H FFFFC8H 32H 52 INTAD: AD conversion end 00CCH 00CCH FFFFCCH 33H 53 INTTC0: Micro DMA end (Channel 0) 00D0H 00D0H FFFFD0H 34H 54 INTTC1: Micro DMA end (Channel 1) 00D4H 00D4H FFFFD4H 35H 55 INTTC2: Micro DMA end (Channel 2) 00D8H 00D8H FFFFD8H 36H INTTC3: Micro DMA end (Channel 3) 00DCH 00DCH FFFFDCH 37H INTTC4: Micro DMA end (Channel 4) 00E0H 00E0H FFFFE0H 38H 58 INTTC5: Micro DMA end (Channel 5) 00E4H 00E4H FFFFE4H 39H 59 INTTC6: Micro DMA end (Channel 6) 00E8H 00E8H FFFFE8H 3AH 60 INTTC7: Micro DMA end (Channel 7) 00ECH 00ECH FFFFECH 3BH 00F0H 00F0H FFFFF0H - : : to 00FCH 00FCH FFFFFCH - 56 57 Maskable - to (Reserved) - Note 1: Micro DMA default priority. Micro DMA stands up prior to other maskable interrupt. Note 2: When standing-up micro DMA, set at edge detect mode. 92CH21-45 92CH21-45 2004-09-01 TMP92CH21 TMP92CH21 3.4.2 Micro DMA Processing In addition to general purpose interrupt processing, the TMP92CH21 TMP92CH21 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU is a stand-by state by Halt instruction, the requirement of micro DMA will be ignored (pending). Micro DMA is supported 8 channels and can be transferred continuously by specifying the micro DMA burst function in the following. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to eight types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte or two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: the lower the channel number, the higher the priority (channel 0 thus has the highest priority and channel 7 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (e.g., interrupt requests should be disabled). If micro DMA and general purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. In this case, edge triggered interrupts are the only kinds of general interrupts which can be accepted. 92CH21-46 92CH21-46 2004-09-01 TMP92CH21 TMP92CH21 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (1), detailed description of the transfer mode register. Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (provided that the transfer counter for the source is initially set to 0000H 0000H). Micro DMA processing can be initiated by any one of 34 different interrupts the 33 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode (micro DMA transfers are the same in every mode except counter mode). (The conditions for this cycle are as follows: Both source and destination memory are internal RAM and multiples by 4 numbered source and destination addresses.) 1 state (1) (2) (3) (4) src (5) dst fSYS A23 to A0 Note: Actually, src and dst address are not output to A23 to A0 pins because they are address of internal RAM. Figure 3.4.2 Timing for Micro DMA Cycle State (1), (2): Instruction fetch cycle (Prefetches the next instruction code) State (3): Micro DMA read cycle State (4): Micro DMA write cycle State (5): (The same as in state (1), (2) 92CH21-47 92CH21-47 2004-09-01 TMP92CH21 TMP92CH21 (2) Soft start function The TMP92CH21 TMP92CH21 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. When a burst is specified by the register DMAB, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is 0. Symbol DMAR Name Request 7 6 5 4 3 2 1 0 109H DMA Address DREQ7 DREQ6 DREQ5 DREQ4 DREQ3 DREQ2 DREQ1 DREQ0 (Prohibit RMW) 0 0 0 0 0 0 0 R/W 0 (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr, r can be used to set these registers. Channel 0 DMAS0 DMA source address register 0 DMAD0 DMA destination address register 0 DMAC0 DMAM0 DMA counter register 0 DMA mode register 0 Channel 7 DMAS7 DMA source address register 7 DMAD7 DMA destination address register 7 DMAC7 DMAM7 DMA counter register 7 DMA mode register 7 8 bits 16 bits 32 bits 92CH21-48 92CH21-48 2004-09-01 TMP92CH21 TMP92CH21 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAMn[4:0] 000zz 001zz 010zz 011zz 100zz 101zz 110zz 11100 ZZ: DMAM0 to DMAM7 Mode Description Execution State Number Destination INC mode (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn 5 states Destination DEC mode (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn 5 states Source INC mode (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INTTCn 5 states Source DEC mode (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INTTCn 5 states Source and destination INC mode (DMADn+) (DMASn+) DMACn DMACn - 1 If DMACn = 0 then INTTCn 6 states Source and destination DEC mode (DMADn-) (DMASn-) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source and destination Fixed mode (DMADn) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTCn Counter mode DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INTTCn 6 states 5 states 5 states 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (Reserved) Note1: N stands for the micro DMA channel number (0 to 7) DMADn+/DMASn+: Post-increment (register value is incremented after transfer) DMADn-/DMASn-: Post-decrement (register value is decremented after transfer) "I/O" signifies fixed memory addresses; "memory" signifies incremented or decremented memory addresses. Note2: The transfer mode register should not be set to any value other than those listed above. Note3: The execution state number shows number of best case (1-state memory access). 92CH21-49 92CH21-49 2004-09-01 TMP92CH21 TMP92CH21 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left hand side of the diagram shows the interrupt controller circuit. The right hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 52 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing a micro DMA start vector to the INTCLR register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12 INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupt (watchdog timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bit of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt's vector address to the CPU. The CPU compares the mask value set in of the status register (SR) with the priority level of the requested interrupt; if the latter is higher, the interrupt is accepted. Then the CPU sets SR to the priority level of the accepted interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests with a priority value equal to or higher than the value set in SR (e.g., interrupts with a priority higher than the interrupt being processed) will be accepted. When interrupt processing has been completed (e.g., after execution of a RETI instruction), the CPU restores to SR the priority value which was saved on the stack before the interrupt was generated. The interrupt controller also includes eight registers which are used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (see Table 3.4.1), enables the corresponding interrupts to be processed by micro DMA processing. The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD) prior to micro DMA processing. 92CH21-50 92CH21-50 2004-09-01 92CH21-51 92CH21-51 Micro DMA counter zero interrupt INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 INT1 INT2 INT3 INT4 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INT0 INTWD RESET D5 D4 D3 D2 D1 D0 Dn + 3 Interrupt request F/F C B A Y1 Y2 Y3 Y4 Y5 Y6 Decoder INTTC0 D Q CLR 6 51 Selector S V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH 6 V = 20H V = 24H DMA0V DMA1V : DMA7V Soft start Interrupt vector read Micro DMA acknowledge S Q R Interrupt request F/F D Q CLR Micro DMA start vector setting register Reset Dn + 2 Dn + 1 Dn Q Priority setting register RESET interrupt vector read S R Interrupt request F/F Interrupt controller 8 1 7 0 1 2 3 4 5 6 7 A B C D2 D3 D4 D5 D6 D7 D0 D1 3 INTRQ2 to 0 3 Interrupt vector read Interrupt vector generator 8 input OR 45 1 A 2 Highest priority B 3 interrupt 4 level select C 5 6 7 Micro DMA channel priority decoder 6 1 Interrupt request Priority encoder signal to CPU Interrupt level detect 3 if IFF = 7 then 0 Micro DMA channel specification Micro DMA request INT01 INT01 to INT4, INTKEY,INTRTC, INTALM, INTUSB RESET Halt release During IDLE1 During STOP Interrupt request signal EI 1 to 7 DI RESET If INTRQ2 to 0 IFF 2 to 0 then 1. 3 3 IFF2 to 0 Interrupt mask F/F CPU TMP92CH21 TMP92CH21 Figure 3.4.3 Block Diagram of Interrupt Controller 2004-09-01 TMP92CH21 TMP92CH21 (1) Interrupt level setting registers Symbol INTE0AD Name INT0 & INTAD Address 7 6 5 IADC IADM2 F0H INT2 & I2C & D0H D1H I4C II2SC & INTTA3 D4H ITA1C INTTB1 D5H 0 0 I3C 0 0 II2SM1 II2SM0 I5C 0 0 R/W 0 ITA1M1 0 0 ITA3M1 R ITA1M0 0 ITB1M2 D8H 0 ITB1M1 R & 0 0 0 I5M2 DAH - - ITA0C ITA0M2 ITX1C 0 0 ITA3M0 ITA2C ITA2M2 0 ITX1M2 R - - 0 0 ITB1M0 ITB0C ITB0M2 0 R 0 0 0 0 - ITBO0C ITBO0M2 0 ITBO0M1 ITBO0M0 0 R/W 0 0 ITX0M0 IRX0C 0 0 IRX0M2 R 0 IRX0M1 IRX0M0 R/W 0 0 ITX1M0 IRX1C IRX1M2 R 0 IRX1M1 IRX1M0 R/W 0 0 0 0 - - IUSB0C IUSBM2 0 0 IUSBM1 IUSBM0 INTUSB R/W 0 INTALM1 INTEALM01 INTEALM01 E5H enable IA1M2 R 0 INTALM0 IA1M1 IA1M0 R/W 0 0 IA0C IA0M2 R 0 0 INTALM2 & INTALM3 enable E6H IA3C IA3M2 R 0 IA0M0 0 0 0 IA2M1 IA2M0 INTALM2 IA3M1 IA3M0 R/W 0 IA0M1 R/W INTALM3 INTEALM23 INTEALM23 ITB0M0 R/W R IA1C 0 ITB0M1 Note: Always write 0 INTALM0 & INTALM1 ITA2M0 INTTB0 (TMRA 4) - E3H ITA2M1 INTRX1 ITX1M1 0 INTUSB 0 R/W 0 R/W 0 enable 0 INTTA2 (TMRA 2) R/W 0 R ITA0M0 R/W INTTX1 DCH ITA0M1 INTRX0 ITX0M1 R 0 0 INTTBO0 - ITX0M2 I5M0 0 R ITX0C I5M1 R/W INTTX0 DBH 0 0 - enable INTEUSB 0 0 R/W INTRX1 INTTX1 R/W 0 R R/W ITB1C I3M0 INTTA0 (TMRA 0) R/W ITA3M2 0 I3M1 I3M2 R INTTB1 (TMRA 4) enable INTES1 0 R Note: Always write 0 & 0 INT5 0 INTRX0 INTTX0 0 I4M0 R/W 0 ITA3C I1M0 R/W INT3 I4M1 ITA1M2 0 I1M1 R enable INTES0 0 INT1 I4M2 0 INTTBO0 (Overflow) I1M2 INTTA3 (TMRA 3) enable INTETBO0 I1C 0 R INTTB0 INTETB01 INTETB01 I2M0 0 0 enable & 0 INTTA1 (TMRA 1) INTTA2 INTETA23 INTETA23 0 R/W R 0 enable & 0 I2M1 II2SM2 I0M0 R/W INTI2S EBH I0M1 R 0 R 0 0 INT0 INT4 INTTA0 INTTA1 I0M2 R 0 enable INTETA01 INTETA01 I0C I2M2 INT5 INTI2S 1 INT2 enable INTE5I2S IADM0 0 INT3 INT4 IADM1 R/W 0 enable INTE34 INTE34 2 R INT1 INTE12 INTE12 3 INTAD enable & 4 0 92CH21-52 92CH21-52 IA2C IA2M2 R 0 0 R/W 0 0 0 2004-09-01 TMP92CH21 TMP92CH21 Symbol Name Address 7 6 - 5 - 4 3 2 - - IA4C IA4M2 - INTEALM4 INTALM4 enable E7H enable E8H 0 0 - IRC - IRM2 enable E9H - 0 0 - - - IKC enable EAH - INTEND01 INTEND01 INTNDF1 R/W - - IN1M2 - ILCD1C 0 IN1M0 R/W 0 0 INTP0 - - ILCDM2 EEH ILCDM1 ILCDM0 R/W 0 IN0C 0 0 IN0M2 IN0M1 IN0M0 R R/W 0 0 0 0 - - IP0C IP0M2 - enable 0 INTNDF0 IN1M1 R enable INTEP0 0 INTLCD R IN1C IKM0 0 INTNDF1 ECH 0 IKM1 R 0 Note: Always write 0 INTNDF0 & 0 IKM2 - INTLCD IRM0 R/W INTKEY Note: Always write 0 INTELCD 0 IRM1 R - INTKEY 0 INTRTC - Note: Always write 0 INTEKEY IA4M0 R/W - INTERTC IA4M1 R - 0 INTALM4 Note: Always write 0 INTRTC 1 0 0 IP0M1 IP0M0 INTP0 R Note: Always write 0 0 R/W 0 0 0 lxxM2 lxxM0 0 0 0 1 Disables interrupt requests Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 Interrupt request flag lxxM1 0 0 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests 92CH21-53 92CH21-53 Function (Write) 2004-09-01 TMP92CH21 TMP92CH21 Symbol Name INTETC01 INTETC01 INTTC0 & INTTC1 enable INTETC23 INTETC23 INTETC45 INTETC45 INTTC2 & INTTC3 enable INTTC4 & INTTC5 enable Address 7 6 5 ITC1C ITC1M2 4 3 2 ITC1M0 ITC0C ITC0M2 INTTC1 (DMA1) F1H R/W 0 0 ITC3C ITC3M2 0 0 0 0 ITC3M0 ITC2C ITC2M2 ITC5C 0 ITC5M2 0 0 0 ITC5M0 0 ITC4C R/W 0 INTTC6 & INTTC7 F4H enable ITC7C ITC7M2 0 ITC4M2 0 ITC7M0 ITC6C INTWD enable F7H - 0 0 0 ITC6M1 R 0 - ITC4M0 0 ITC6M2 ITC6M0 R/W 0 0 0 - - - - - - - INTWDT ITC4M1 R/W 0 R/W 0 0 INTTC6 (DMA6) ITC7M1 R 0 0 R 0 INTTC7 (DMA7) INTETC67 INTETC67 ITC2M0 R/W INTTC4 (DMA4) ITC5M1 R 0 ITC2M1 R INTTC5 (DMA5) F3H 0 INTTC2 (DMA2) R/W 0 ITC0M0 R/W 0 ITC3M1 R ITC0M1 R INTTC3 (DMA3) F2H 0 INTTC0 (DMA0) ITC1M1 R 1 INTWD - - ITCWD R Note: Always write 0 0 lxxM2 lxxM0 0 0 0 0 0 1 Disables interrupt requests Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 Interrupt request flag lxxM1 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests 92CH21-54 92CH21-54 Function (Write) 2004-09-01 TMP92CH21 TMP92CH21 (2) External interrupt control Symbol 6 5 4 3 2 1 I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE - W Interrupt input mode control Address 7 I5EDGE IIMC Name 0 W W W W W R/W R/W 0 0 0 0 0 0 0 0 F6H INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0: INT0 (Prohibit edge 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising RMW) mode 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: INT0 level mode Always write "0" *INT0 level enable 0 Edge detect INT 1 "H" level INT Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense. Setting example: DI LD LD NOP NOP NOP EI (IIMC), XXXXXX00B XXXXXX00B ; Switches from level to edge. (INTCLR), 0AH ; Clears interrupt request flag. ; Wait EI execution X: Don't care, -: No change. Note 2: See electrical characteristics in section 4 for external interrupt input pulse width. Settings of External Interrupt Pin Function Interrupt Pin Name Mode Setting Method Rising edge Rising edge = 0 = 1 = 0 Falling edge = 1 Rising edge = 0 Falling edge = 1 Rising edge INT5 = 1 Rising edge INT4 = 0 Falling edge INT3 = 1 Falling edge INT2 = 0, = 1 Rising edge INT1 PC0 Falling edge High level INT0 = 0, = 0 = 0 Falling edge = 1 PC1 PC2 PC3 P96 P97 92CH21-55 92CH21-55 2004-09-01 TMP92CH21 TMP92CH21 (3) SIO receive interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 - SIO SIMC interrupt mode control F5H (Prohibit IR1LE IR0LE W W W 0 1 1 0: INTRX1 0: INTRX0 edge edge mode mode Always write "0" RMW) 1: INTRX1 1: INTRX0 level level mode mode INTRX1 level enable 0 Edge detect INTRX1 1 "H" level INTRX1 INTRX0 rising edge enable 0 Edge detect INTRX0 1 "H" level INTRX0 92CH21-56 92CH21-56 2004-09-01 TMP92CH21 TMP92CH21 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH Symbol Name Address F8H INTCLR Interrupt clear control Clears interrupt req