TLCS-900/H1 TMP92CF26AXBG TMP92CF26A 900/H1 TLCS-900/L1 20070701-EN 92CF26A-1 - Datasheet Archive

 

TLCS-900/H1 Series TMP92CF26AXBG Semiconductor Company TMP92CF26A CMOS 32-Bit Microcontroller TMP92CF26AXBG 1. Outline and

 

TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 TLCS-900/H1 Series TMP92CF26AXBG TMP92CF26AXBG Semiconductor Company TMP92CF26A TMP92CF26A CMOS 32-Bit Microcontroller TMP92CF26AXBG TMP92CF26AXBG 1. Outline and Features The TMP92CF26A TMP92CF26A is a high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. The TMP92CF26AXBG TMP92CF26AXBG is housed in a 228-pin BGA package. (1) CPU: 32-bit CPU (High-speed 900/H1 900/H1 CPU) · Compatible with TLCS-900/L1 TLCS-900/L1 instruction code · 16 Mbytes of linear address space · General-purpose register and register banks · Micro DMA: 8channels (62.5 ns/4 bytes at fSYS = 80 MHz, best case) (2) Minimum instruction execution time: 12.5 ns (at fSYS = 80 MHz) (3) Internal RAM: 144 Kbytes (can be used for program, data and display memory) Internal ROM: 8 Kbytes (memory for Boot only) Possible downloading of user program through either USB, UART. RESTRICTIONS ON PRODUCT USE 20070701-EN 20070701-EN · The information contained herein is subject to change without notice. · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer's own risk. · The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. · Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 92CF26A-1 92CF26A-1 2007-11-21 TMP92CF26A TMP92CF26A (4) External memory expansion · Expandable up to 3.1 Gbytes (shared program/data area) · Can simultaneously support 8-and 16-bit width external data buses . Dynamic data bus sizing · Separate bus system (5) Memory controller · Chip select output: 4 channels · One channel in 4 channels is enabled detailed AC enable setting (6) 8-bit timers: 8 channels (7) 16-bit timer/event counter: 2 channels (8) General-purpose serial interface: 1 channel · UART/synchronous mode · IrDA ver.1.0 (115.2 kbps) selectable (There is the restriction in the setting baud rate when use this function together other functions) (9) Serial bus interface: 1 channel · I2C bus mode only (10) USB (universal serial bus) controller: 1 channel · Supports USB (ver.1.1) · Full-speed (12 Mbps) (Low-speed is not supported.) · Endpoint 0: Control 64 bytes × 1 FIFO Endpoint 1: BULK (output) 64 bytes × 2 FIFOs Endpoint 2: BULK (input) 64 bytes × 2 FIFOs Endpoint 3: Interrupt (input) 8 bytes × 1 FIFO · Descriptor RAM: 384 bytes (11) I2S (Inter-IC Sound)interface: 2 channels · I2S bus mode selectable (Master, transmission only) · Data Format is supported Left/Right Justify · 128-byte FIFO buffer (64 bytes × 2) per channel (12) LCD controller · Supports monochrome, 4, 16 and 64 gray levels and 256/4096/65536 colors for STN · Supports 4096/65536/262144/16777216 colors for TFT · Supports PIP (Picture In Picture Display) · Supports H/W Rotation function for support to various LCDM (13) SDRAM controller: 1 channel · Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate) SDRAM · Possible to execute instruction on SDRAM (14) Timer for real-time clock (RTC) · Based on TC8521A TC8521A 92CF26A-2 92CF26A-2 2007-11-21 TMP92CF26A TMP92CF26A (15) Key-on wakeup (Interrupt key input) (16) 10-bit A/D converter (Built in Sample Hold circuit): 6 channels (17) Touch screen interface · Built-in Switch of Low-resistor, and available to reduce external components for shift change row/column (18) Watchdog timer (19) Melody/alarm generator · Melody: Output of a clock 4 to 5461-Hz clock · Alarm: Output of 8 kinds of alarm pattern · 5 kinds of interval interrupt (20) MMU · Expandable up to 3.1 Gbytes (3 local area/8 bank method) · Independent bank for each program, read data, write data, source and destination of DMAC (Odd channel/Even channel) and LCD display data (21) Interrupts: 56 interrupts · 9 CPU interrupts: Software interrupt instruction and illegal instruction · 38 internal interrupts: Seven selectable priority levels · 9 external interrupts: Seven selectable priority levels (8-edge selectable) (22) DMAC function: 6 channels · High-speed data transfer enable by controlling which convert micro DMA function and this function (23) Input/Output ports: 136 pins (Except Data bus (16-bit), Address bus (24-bit) and RD pin) (24) NAND Flash interface: 2 channels · Direct NAND flash connection capability · Supports SLC type and MLC type · Supports Data Bus 8/16 bits, Page Size 512/2048 bytes · Built-in Reed Solomon calculation circuits which enabled correct 4-address, and detect error more than 5-address (25) SPI controller: 1 channel · Supports SPI mode of SD card and MMC card · Built-in FIFO buffer of 32 bytes to each Input/Output (26) Product/Sum calculation: 1 channel · Supports calculation 32 × 32 + 64 = 64 bits, 64 - 32 × 32 = 64 bits and 32 × 32 - 64 =64 bits · I/O method · Supports Signed calculations 92CF26A-3 92CF26A-3 2007-11-21 TMP92CF26A TMP92CF26A (27) Standby function · Three Halt modes: IDLE2 (programmable), IDLE1, STOP · Each pin status programmable for standby mode · Built-in power supply management circuits (PMC) for leakage current provision (28) Clock controller · Two blocks of clock doubler (PLL) supplies 48 MHz for USB and 80 MHz for CPU from 10 MHz · Clock gear function: Selectable high-frequency clock fc to fc/16 · Clock for Timer (fs = 32.768 kHz) (29) Operating voltage: · Internal VCC= 1.5 V, External I/O Vcc = 3.0 to 3.6 V · 2 power supplies (Internal power supply (1.4 to 1.6 V), External power supply (3.0 to 3.6 V) (30) Package · 228-pin FBGA: P-FBGA228-1515-0 P-FBGA228-1515-0.80A5 92CF26A-4 92CF26A-4 2007-11-21 TMP92CF26A TMP92CF26A (AN0 to AN1)PG0 to PG1 (AN2, MX)PG2 (AN3, MY, ADTRG )PG3 (AN4 to AN5)PG4 to PG5 AVCC, AVSS VREFH, VREFL 10-bit 6ch AD Converter DVCC3A [12] DVCC3B [1] DVCC1A [5] DVCC1B [1] DVSSCOM 900/H1 900/H1 CPU XWA W A XBC B C XDE D E H L PLL H-OSC DVCC1C [1] DVSS1C [1] X1 X2 (PY) P97 Touch Screen I/F (TSI) (TXD0) P90 (RXD0) P91 SERIAL I/O SIO0 XHL XIX IX I2S (I S0) XIY IY AM [1:0] XIZ IZ XSP SP PZ0 (EI_PODDATA) PZ1 (EI_SYNCLK) PZ2 (EI_PODREQ) PZ3 (EI_REFCLK) PZ4 (EI_TRGIN) PZ5 (EI_COMRESET) PZ6 (EO_MCUDATA) PZ7 (EO_MCUREQ) (PX, INT4) P96 (CTS0, SCLK0) P92 (I2S0CKO) PF0 (I2S0DO) PF1 (I2S0WS) PF2 (I2S1CKO) PF3 (I2S1DO) PF4 (I2S1WS) PF5 (SDA) PV6 (SCL) PV7 D+ D(X1USB) PX5 (TA0IN, INT1) PC1 (TA1OUT, MLDALM) PM1 (TA2IN, INT3) PC3 (TA3OUT) PP1 (TA5OUT) PP2 (TA7OUT, INT5) PP3 (TB0IN0, INT6) PP4 (TB0OUT0) PP6 (TB1IN0, INT7) PP5 (TB1OUT0) PP7 (SPDI) PR0 (SPDO) PR1 ( SPCS ) PR2 (SPCLK) PR3 (LCP0) PK0 (LLOAD) PK1 (LFR) PK2 (LVSYNC) PK3 (LHSYNC) PK4 (LGOE2 to 0) PK7 to 5 (LD7 to 0) PL7 to 0 (LD15 to 8) PT7 to 0 (LD22 to 16) PU6 to 0 2 2 IS (I2S1) 2 SBI (I Cbus) DSU F USB Controller XT1 XT2 P C 8BIT TIMER (TMRA0) 8BIT TIMER (TMRA1) 8BIT TIMER (TMRA2) 8BIT TIMER (TMRA3) 8BIT TIMER (TMRA4) 8BIT TIMER (TMRA5) 8BIT TIMER (TMRA6) 8BIT TIMER (TMRA7) 16BIT 16BIT TIMER (TMRB0) 16BIT 16BIT TIMER (TMRB1) WATCH-DOG TIMER PMC PM7 (PWE) Interrupt Controller PC0 (INT0) PC2 (INT2) MAC DMAC PORT1 D0 to D7 P10 to P17 (D8 to D15) PORT4 MMU P40 to P47 (A0 to A7) PORT5 P50 to P57 (A8 to A15) PORT6 P60 to P67 (A16 to A23) KEY-BOARD I/F P70 ( RD ) P73 (EA24) P74 (EA25) P75 (R/ W , NDR/ B ) P76 ( WAIT ) P80 ( CS0 ) P81 ( CS1 , SDCS ) P82 ( CS2 , CSZA , SDCS ) P83 ( CS3 , CSXA ) P84 ( CSZB ) P85 ( CSZC ) P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) P86 ( CSZD , ND0CE ) P87 ( CSXB , ND1CE ) PJ5 (NDALE) PJ6 (NDCLE) PA0 to PA7 (KI0 to KI7) PN0 to PN7 (KO0 to KO7) PC7 (KO8) RTC PM2 ( ALARM , MLDALM ) PORT7 PORT8 SPI Controller 144KB 144KB RAM LCD Controller BOOT ROM 8KB NAND-FLASH I/F (2ch) MELODY/ ALARM-OUT (LD23, EO_TRGOUT) PU7 (CLKOUT, LDIV) PX4 PX7 ( SDRAS , SRLLB ) PJ0 ( SDCAS , SRLUB ) PJ1 ( SDWE , SRWR ) PJ2 (SDLLDQM) PJ3 (SDLUDQM) PJ4 (SDCKE) PJ7 (SDCLK) PF7 L-OSC RESET DBGE 32bit SR Clock gear PORTV PV3 PV4 PV0 (SCLK0) PV1 PV2 PW7 to PW0 PC4 (EA26) PC5 (EA27) PC6 (EA28) SDRAM Controller Figure 1.1 Block Diagram of TMP92CF26A TMP92CF26A 92CF26A-5 92CF26A-5 2007-11-21 TMP92CF26A TMP92CF26A 2. Pin Assignment and Pin Functions The assignment of input/output pins for TMP92CF26A TMP92CF26A, their names and functions are as follows; 2.1 Pin Assignment Diagram (Top View) Figure 2.1.1 shows the pin assignment of the TMP92CF26A TMP92CF26A. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D5 D6 D7 D8 D9 D10 D11 D12 D13 E1 E2 E3 E4 F1 F2 F3 F4 D15 D16 D17 E14 E15 E16 E17 F6 F7 F8 F9 F10 F11 F14 F15 F16 F17 G1 G2 G3 G4 G6 G7 G12 G14 G15 G16 G17 H1 H2 H3 H4 H6 H12 H14 H15 H16 H17 J1 J2 J3 J4 J6 J12 J14 J15 J16 J17 K12 K14 K15 K16 K17 L12 L14 L15 L16 L17 M6 M7 M8 M9 M10 M11 M12 M14 M15 M16 M17 K1 K2 K3 K4 L2 L3 L4 P-FBGA228 P-FBGA228 K6 L1 TMP92CF26A TMP92CF26A L6 M1 M2 M3 M4 N1 N2 N3 P1 P2 P3 R1 R2 R3 T1 T2 U1 U2 TOP VIEW N4 N14 N15 N16 N17 P5 P6 P7 P8 P9 P10 P11 P12 P13 P15 P16 P17 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Figure 2.1.1 Pin assignment diagram (P-FBGA228 P-FBGA228) 4 balls of A1, A17, U1 and U17 (most outside 4 corner of BGA package) are Dummy Balls. These balls are not connected with internal LSI chip, electrical characteristics. A1 and U1, A17 and U17 are shorted in internal package. It is recommended that using to OPEN check of mounting if mounting this LSI to Target board. Example: If checking signal (or voltage) via A1-U1-U17-A17 A1-U1-U17-A17, short U17 and U1 on Target board beforehand, and input signal (or voltage) from A1, and check voltage of A17. 92CF26A-6 92CF26A-6 2007-11-21 TMP92CF26A TMP92CF26A Table 2.1.1 Pin number and the name Ball Pin name No. Ball Ball Pin name No. Pin name No. Ball Pin name No. A1 Dummy1 D9 P73,EA24 J15 PT5,LD13 P15 A2 PG2,AN2, MX D10 PF4,I2S1DO J16 P47,A7 P16 P13,D11 A3 PA6,KI6 D11 PF7,SDCLK J17 P46,A6 P17 P14,D12 A4 PA5,KI5 D12 PN3,KO3 R1 X2 PA3,KI3 D13 PJ4,SDLUDQM P85, CSZC K1 A5 K2 PN4,KO4 R2 PC7,KO8 A6 PA1,KI1 D15 PU6,LD22 K3 PN5,KO5 R3 PC3,INT3,TA2IN A7 DVCC1A5 D16 P61,A17 K4 PN6,KO6 R4 PX5,X1USB A8 PF1,I2S0DO D17 P60,A16 K6 DVCC3A2 R5 PP7,TB1OUT0 A9 PJ6,NDCLE PJ1, SDCAS , SRLUB E1 P96,PX,INT4 K12 DVCC3A7 R6 PP1,TA3OUT A10 PK4,LHSYNC E2 PW1 K14 PT4,LD12 R7 PP3,INT5,TA7OUT E3 PW2 K15 PT3,LD11 R8 E4 PW3 K16 P45,A5 R9 PP5,INT7,TB1IN0 PR2, SPCS A12 P87, CSXB , ND1CE P83, CS3 , CSXA A13 P81, CS1 , SDCS E14 PU7,LD23,EO_TRGOUT K17 P44,A4 R10 PX7 A14 P72, WRLU , NDWE E15 PU4,LD20 L1 PK2,LFR R11 PZ0,EI_PODDATA A15 P70, RD E16 P57,A15 L2 PN7,KO7 R12 PZ2,EI_PODREQ A16 P65,A21 E17 P56,A14 L3 PM1,MLDALM,TA1OUT R13 PZ4,EI_TRGIN A17 Dummy3 F1 DVCC1B1 L4 PM7,PWE R14 PZ6,EO_MCUDATA B1 VREFH F2 PW6 L6 DVSS3 R15 PZ7,EO_MCUREQ B2 PG5,AN5 PG3,AN3,MY, ADTRG F3 PW5 L12 DVSS7 R16 P15,D13 F4 PW4 L14 PT2,LD10 R17 DVCC1A3 B4 PA7,KI7 F6 DVCC3A12 DVCC3A12 L15 PT1,LD9 T1 X1 B5 PA2,KI2 F7 DVCC3A11 DVCC3A11 L16 P43,A3 T2 AM0 B6 PA0,KI0 F8 DVSS11 DVSS11 L17 P42,A2 T3 AM1 B7 PF2,I2S0WS F9 DVCC3A10 DVCC3A10 M1 PK3,LVSYNC T4 PP6,TB0OUT0 B8 PF0,I2S0CKO F10 DVSS10 DVSS10 M2 T5 PL0,LD0 B9 F11 DVCC3A9 M3 T6 PL2,LD2 F14 PU5,LD21 M4 P90,TXD0 T7 PL4,LD4 B11 PJ5,NDALE PJ2, SDWE , SRWR PJ0, SDRAS , SRLLB PC0,INT0 PM2, ALARM , MLDALM F15 PU2,LD18 M6 DVCC3A3 T8 PL5,LD5 B12 P86. CSZD , ND0CE F16 P55,A13 M7 DVSS4 T9 PR1,SPDO B13 P82, CS2 , CSZA , SDCS F17 P54,A12 M8 DVCC3A4 T10 PL6,LD6 B14 P75,R/ W ,NDR/ B G1 DVCC3B1 M9 DVSS5 T11 PK1,LLOAD B15 P71, WRLL , NDRE G2 PW7 M10 DVCC3A5 T12 D0 B16 P64,A20 G3 PV0,SCLK0 M11 DVSS6 T13 D2 B17 DVCC1A4 G4 PV1 M12 DVCC3A6 T14 D4 C1 AVCC G6 DVSS1 M14 PK7,LGOE2 T15 D6 C2 VREFL G7 DVSS12 DVSS12 M15 PT0,LD8 T16 P11,D9 C3 PG4,AN4 G12 DVSS9 M16 P41,A1 T17 P12,D10 C4 PG1,AN1 G14 PU3,LD19 M17 P40,A0 U1 C5 PA4,KI4 G15 PU0,LD16 N1 DVCC1A1 U2 Dummy2 RESET C6 G16 P53,A11 N2 PC1,INT1,TA0IN U3 D+ G17 P52,A10 N3 P91,RXD0 U4 D- C8 PC5,EA27 P76, WAIT PF5,I2S1WS H1 PV7,SCL N4 DVSS1C U5 DVCC1A2 C9 PF3,I2S1CKO H2 PV6,SDA N14 PK6,LGOE1 U6 PL1,LD1 C10 PJ7,SDCKE H3 PV3 N15 PK5,LGOE0 U7 PL3,LD3 C11 H4 PV2 N16 P17,D15 U8 XT1 H6 DVCC3A1 N17 P16,D14 U9 XT2 C13 PJ3,SDLLDQM P84, CSZB P80, CS0 H12 DVCC3A8 P1 DVCC1C U10 PL7.LD7 C14 P67,A23 H14 PU1,LD17 P2 U11 PK0,LCP0 C15 P66,A22 H15 PT7,LD15 P3 PC2,INT2 P92,SCLK0, CTS0 U12 D1 C16 P63,A19 H16 P51,A9 P5 PX4,CLKOUT, LDIV U13 D3 C17 P62,A18 H17 P50,A8 P6 PP2,TA5OUT U14 D5 D1 P97,PY J1 PN2,KO2 P7 PP4,INT6,TB0IN0 U15 D7 D2 AVSS J2 PN1,KO1 P8 PR0,SPDI U16 P10,D8 D3 PW0 J3 PN0,KO0 P9 PR3,SPCLK U17 Dummy4 A11 B3 B10 C7 C12 D5 PG0,AN0 J4 PV4 P10 DBGE D6 PC6,EA28 J6 DVSS2 P11 PZ1,EI_SYNCLK D7 PC4,EA26 J12 DVSS8 P12 PZ3,EI_REFCLK D8 P74,EA25 J14 PT6,LD14 P13 PZ5,EI_COMRESET Note1: The P96, P97 and PG0~PG5 operate with the AVCC power supply. Note2: The PW0~PW7 and PV0~PV7 operate with the DVCC3B power supply. Note3: The X1 and X2 operate with the DVCC1C power supply. 92CF26A-7 92CF26A-7 2007-11-21 TMP92CF26A TMP92CF26A 2.2 Pin names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/6) Pin name D0 to D7 P10 to P17 D8 to D15 P40 to P47 A0 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 P70 Number of Pins 8 8 8 8 8 I/O Data: Data bus D0 to D7 I/O Port 1: I/O port input or output specifiable in units of bits I/O Data: Data bus D8 to D15 Output Port 4: Output port Output Address: Address bus A0 to A7 Output Port 5: Output port Output Address: Address bus A8 to A15 I/O Port 6: I/O port input or output specifiable in units of bits 1 Output Address: Address bus A16 to A23 Output Port 70: Output port Read: Outputs strobe signal to read external memory I/O WRLL Output NDRE Output P72 Functions Output 1 RD P71 I/O 1 I/O Port 71: Output port Write: Outputs strobe signal for writing data on pins D0 to D7 NAND Flash read: Outputs strobe signal to read external NAND-Flash Port 72: I/O port WRLU Output Write: Outputs strobe signal for writing data on pins D8 to D15 NDWE Output NAND Flash write: Write enable for NAND Flash P73 1 EA24 P74 1 EA25 P75 R/ W WAIT P80 I/O Output 1 I/O Output Input NDR/ B P76 I/O Output 1 1 I/O Input Output Port 73: I/O port Expanded address 24 Port 74: I/O port Expanded address 25 Port 75: I/O port Read/Write: "High" represents read or dummy cycle; "Low" represents write cycle NAND Flash Ready(1) / Busy(0) input Port 76: I/O port Wait: Signal used to request CPU bus wait Port 80: Output port Output Chip select 0: Outputs "Low" when address is within specified address area Output Port 81: Output port CS1 Output Chip select 1: Outputs "Low" when address is within specified address area SDCS Output Chip select for SDRAM: Outputs "Low" when the address is within SDRAM address area Output Port 82: Output port CS2 Output Chip select 2: Outputs "Low" when address is within specified address area CSZA Output Expanded address ZA: Outputs "Low" when address is within specified address area SDCS Output Chip select for SDRAM: Outputs "Low" when the address is within SDRAM address area Output Port 83: Output port CS3 Output Chip select 3: Outputs "Low" when address is within specified address area CSXA Output Expanded address XA: Outputs "Low" when address is within specified address area Output Port 84: Output port Output Expanded address ZB: Outputs "Low" when address is within specified address area Output Port 85: Output port Output Expanded address ZC: Outputs "Low" when address is within specified address area CS0 P81 P82 P83 P84 1 1 1 1 CSZB P85 CSZC 1 92CF26A-8 92CF26A-8 2007-11-21 TMP92CF26A TMP92CF26A Table 2.2.1 Pin names and functions (2/6) Pin name Number of Pins P86 CSZD I/O Functions Output 1 Port 86: Output port Output Expanded address ZD: Outputs "Low" when address is within specified address area ND0CE Output Chip select for NAND Flash 0: Outputs "Low" when NAND Flash 0 is enable P87 Output Port 87: Output port Output Expanded address XB: Outputs "Low" when address is within specified address area CSXB 1 Output ND1CE P90 TXD0 P91 RXD0 1 1 P92 SCLK0 1 PC0 INT0 1 8 1 INT2 1 EA26 PC5 EA27 PC6 EA28 PC7 KO8 Port 96: Input port (schmitt-input, with pull-up resistor) Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Input Input Input I/O Input X-Plus: Pin connected to X+ pin for Touch Screen I/F Port 97: Input port (schmitt input) Y-Plus: Pin connected to Y+ pin for Touch Screen I/F Port A0 to A7: Input port Key input 0 to 7: Pin used for key on wake-up 0 to 7 (Schmitt-input, with pull-up resistor) Port C0: I/O port (Schmitt-input) Interrupt request pin 0: Interrupt request pin with programmable rising/falling edge Port C1: I/O port (Schmitt-input) Input Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge Timer A0 input: Input pin for 8 bit timer 0 I/O Input I/O 1 Port C2: I/O port (Schmitt-input) Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge Port C3: I/O port (Schmitt-input) 1 1 1 1 Input Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge Input TA2IN PC4 Enable to send data for serial 0 (Clear to send) Input Input PC3 INT3 Clock I/O for serial 0 I/O 1 TA0IN PC2 Port 92: I/O port (Schmitt-input) Output PC1 INT1 Receive data for serial 0 I/O Output PY KI0 to KI7 Port 91: I/O port (Schmitt-input) Input 1 PX PA0 to PA7 I/O Input Transmit data for serial 0: programmable Open-drain output Input INT4 P97 Output Chip select for NAND Flash 1: Outputs "Low" when NAND Flash 1 is enable Port 90: I/O port I/O CTS 0 P96 I/O Timer A2 input: Input pin for 8 bit timer 2 I/O Output I/O Output I/O Output I/O Output Port C4: I/O port Expanded address 26 Port C5: I/O port Expanded address 27 Port C6: I/O port Expanded address 28 Port C7: I/O port Key output 8: Key scan strobe pin (programmable Open-drain output) 92CF26A-9 92CF26A-9 2007-11-21 TMP92CF26A TMP92CF26A Table 2.2.1 Pin names and functions (3/6) Pin name PF0 I2S0CKO PF1 I2S0DO PF2 I2S0WS PF3 I2S0WS PF4 I2S1CKO PF5 I2S1WS PF7 SDCLK PG0 to PG1 AN0 to AN1 Number of Pins 1 1 1 1 1 1 1 I/O Output I/O Output I/O Output I/O Output I/O Output I/O Functions Port F0: I/O port Outputs clock for I2S0 Port F1: I/O port Outputs data for I2S0 Port F2: I/O port Outputs word select signal for I2S0 Port F3: I/O port Outputs clock for I2S1 Port F4: I/O port Outputs data for I2S1 Port F5: I/O port Output Outputs word select signal for I2S1 Output Port F7: Output port Output Clock for SDRAM 1 Input Port G0 to G1: Input port Input Analog input pin 0 to 1: Input pin for AD converter Input 2 PG2 AN2 I/O Port G2: Input port Input Analog input pin 2: Input pin for AD converter MX Output PG3 Input Port G3: Input port AN3 Input Analog input pin 3: Input pin for A/D converter MY 1 Output X-Minus: Pin connected to X- pin for Touch Screen I/F Y-Minus: Pin connected to Y- pin for Touch Screen I/F ADTRG Input A/D Trigger: Request signal for A/D start PG4 to PG5 Input Port G4 to G5: Input port AN4 to AN5 2 PJ0 Input Analog input pin 4 to 5: Input pin for A/D converter Output Output Outputs strobe signal for SDRAM row address SRLLB Output Data enable signal for D0 to D7 for SRAM PJ1 Output Port J1: Output port Output Outputs strobe signal for SDRAM column address Output Data enable signal for D8 to D15 for SRAM Output Port J2: Output port Output Outputs write enable signal for SDRAM SRWR Output Write enable for SRAM: Outputs strobe signal to write data PJ3 Output Port J3: Output port Output Data enable signal for D0 to D7 for SDRAM Output Port J4: Output port SDRAS SDCAS 1 Port J0: Output port 1 SRLUB PJ2 SDWE SDLLDQM PJ4 SDLUDQM PJ5 NDALE PJ6 NDCLE PJ7 SDCKE 1 1 1 1 1 1 Output I/O Output I/O Data enable signal for D8 to D15 for SDRAM Port J5: I/O port Address latch enable signal for NAND Flash Port J6: I/O port Output Command latch enable signal for NAND Flash Output Port J7: Output port Output Clock enable signal for SDRAM 92CF26A-10 92CF26A-10 2007-11-21 TMP92CF26A TMP92CF26A Table 2.2.1 Pin names and functions (4/6) Pin name PK0 LCP0 PK1 LLOAD PK2 LFR PK3 LVSYNC PK4 LHSYNC PK5 Number of Pins 1 1 1 1 1 I/O Functions Output Port K0: Output port Output Signal for LCD driver Output Port K1: Output port Output Signal for LCD driver: Data load signal Output Port K2: Output port Output Signal for LCD driver Output Port K3: Output port Output Signal for LCD driver: Vertical sync signal Output Port K4: Output port Input Signal for LCD driver: Horizontal sync signal Output Port K5: Output port Output Signal for LCD driver Output Port K6: Output port Output Signal for LCD driver Output Port K7: Output port Output Signal for LCD driver Output Port L0 to L7: Output port Output Data bus for LCD driver: LD0 to LD7 Output Port M1: Output port Output Timer A1 output: Output pin for 8 bit timer 1 MLDALM Output Melody / Alarm output pin PM2 Output Port M2: Output port Output Alarm output from RTC LGOE0 PK6 LGOE1 PK7 LGOE2 PL0 to PL7 LD0 to LD7 1 1 1 8 PM1 TA1OUT ALARM 1 1 MLDALM Output Melody / Alarm output pin (inverted) PM7 Output Port M7: Output port Output External power supply control output: Pin to control ON/OFF for external power supply. In PWE 1 stand-by mode, outputs "L" level In other than stand-by mode, outputs "H" level PN0 to PN7 KO0 to KO7 PP1 TA3OUT PP2 TA5OUT 8 1 1 PP3 INT5 1 1 TB1OUT0 PR0 SPDI PR1 SPDO PR2 SPCS Input Key output 0 to 7: Key scan strobe pin (programmable Open-drain output) Port P1: I/O port Timer A3 output: Output pin for 8 bit timer 3 Port P2: I/O port Timer A5 output: Output pin for 8 bit timer 5 Port P3: I/O port (Schmitt-input) Interrupt request pin 5: Interrupt request pin with programmable rising/falling edge Timer A7 output: Output pin for 8 bit timer 7 Port P4: I/O port (Schmitt-input) Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Timer B0 input: Input pin for 16 bit timer 0 I/O 1 Port P5: I/O port (Schmitt-input) 1 1 1 1 1 Input Interrupt request pin 7: Interrupt request pin with programmable rising/falling edge Input TB1IN0 PP7 I/O Output Port N: I/O port Input PP5 TB0OUT0 Output I/O TB0IN0 PP6 I/O Output PP4 INT7 Output I/O TA7OUT INT6 I/O Timer B1 input: Input pin for 16 bit timer 1 Output Port P6: I/O port Output Timer B0 output: Output pin for 16 bit timer 0 Output Port P7: I/O port Output Timer B1 output: Output pin for 16 bit timer 1 I/O Input I/O Output I/O Output Port R0: I/O port Data input pin for SD card Port R1: I/O port Data output pin for SD card Port R2: I/O port Chip select signal for SD card 92CF26A-11 92CF26A-11 2007-11-21 TMP92CF26A TMP92CF26A Table 2.2.1 Pin names and functions (5/6) Pin name PR3 SPCLK PT0 to PT7 LD8 to LD15 PU0 to PU4,PU6 LD16 to LD20,LD22 PU5 LD21 Number of Pins 1 8 6 1 PU7 LD23 SCLK0 I/O Output I/O Output I/O Output I/O Output I/O 1 Functions Port R3: I/O port Clock output pin for SD card Port T0 to T7: I/O port Data bus for LCD driver: LD8 to LD15 Port U0 to U4 , U6: I/O port Data bus for LCD driver: LD16 to LD20, LD22 Port U5: I/O port Data bus for LCD driver: LD21 Port U7: I/O port 1 Output Data bus for LCD driver: LD23 Output EO_TRGOUT PV0 I/O Output pin for Debug mode I/O Output Port V0: I/O port Clock I/O for serial 0 PV1 1 I/O Port V1: I/O port PV2 1 I/O Port V2: I/O port PV3 to PV4 2 Output PV6 SDA PV7 SCL PW0 to PW7 1 1 8 PX4 CLKOUT X1USB PX7 PZ0 EI_PODDATA PZ1 EI_SYNCLK PZ2 EI_PODREQ PZ3 EI_REFCLK PZ4 EI_TRGIN PZ5 EI_COMRESET PZ6 EO_MCUDATA PZ7 EO_MCUREQ Port V6: I/O port I/O Send/receive data at I C mode I/O Port V7: I/O port I/O Input/output clock at I C mode I/O Port W0 to W7: I/O port 2 2 Output 1 1 1 1 1 1 1 1 1 1 Port X4: Output port Output Internal clock output pin Output 1 LDIV PX5 Port V3 to V4: Output port I/O Output pin for LCD driver I/O Input Port X5: I/O port Clock input pin for USB I/O Port X7: I/O port I/O Port Z0: I/O port (Schmitt-input) Input I/O Input I/O Input I/O Input I/O Input I/O Input I/O Output I/O Output Input pin for Debug mode Port Z1: I/O port (Schmitt-input) Input pin for Debug mode Port Z2: I/O port (Schmitt-input) Input pin for Debug mode Port Z3: I/O port (Schmitt-input) Input pin for Debug mode Port Z4: I/O port (Schmitt-input) Input pin for Debug mode Port Z5: I/O port (Schmitt-input) Input pin for Debug mode Port Z6: I/O port (Schmitt-input) Output pin for Debug mode Port Z7: I/O port (Schmitt-input) Output pin for Debug mode 92CF26A-12 92CF26A-12 2007-11-21 TMP92CF26A TMP92CF26A Table 2.2.1 Pin names and functions (6/6) Number of Pins I/O D+, D- 2 I/O CLKOUT 1 Output Pin name Functions USB-data connecting pin Connect pull-up(DVCC3A) or pull-down resistor to both pins to avoid through current when USB is not in use. Internal clock output pin Operation mode; Fix to AM1 = "0",AM0 = "1" for 16 bit external bus starting AM1,AM0 2 Input Fix to AM1 = "1",AM0 = "0" is prohibit to set Fix to AM1 = "1",AM0 = "1" for BOOT (32 bit internal Mask ROM) starting Fix to AM1 = "0",AM0 = "0" is prohibited to set DBGE 1 Input X1/X2 2 I/O High-frequency oscillator circuit connection pin XT1/XT2 2 I/O Low-frequency oscillator circuit connection pin Input pin in debug mode (This pin is set to "Debug mode" by input "0" ) RESET 1 Input Reset: Initialize TMP92CF26A TMP92CF26A (Schmitt-input , with pull-up resistor) VREFH 1 Input Pin for reference voltage input to AD converter(H) VREFL 1 Input Pin for reference voltage input to AD converter(L) AVCC 1 - Power supply pin for AD converter AVSS 1 - GND pin for AD converter (0V) DVCC3A 12 - Power supply pin for peripheral I/O-A (All DVCC3A pins should be connected to the power DVCC3B 1 - Power supply pin for peripheral I/O-B (All DVCC3B pins should be connected to the power DVCC1A 5 - Power supply pin for internal logic-A (All DVCC1A pins should be connected to the power DVCC1B 1 - Power supply pin for internal logic-B (Keep the voltage DVCC1A level ) DVSSCOM 12 - GND pin (0V) (All DVSS pins should be connected to GND(0V) ) DVCC1C 1 - Power supply pin for High speed oscillator (Keep the voltage DVCC1A level ) DVSS1C 1 - GND pin (0V) (DVSS1C pin should be connected to GND(0V) ) Dummy4-1 4 - Dummy1 and Dummy2, Dummy3 and Dummy4 are shorted in package (These pins are supply pin ) supply pin ) supply pin ) not connected with internal LSI chip ) Table 2.2.2 shows the range of operational voltage for power supply pins. Table 2.2.2 the range of operational voltage for power supply pins Power supply pin Range of operational voltage DVCC1A DVCC1B 1.4V~1.6V DVCC1C DVCC3A DVCC3B 3.0V~3.6V AVCC 92CF26A-13 92CF26A-13 2007-11-21 TMP92CF26A TMP92CF26A 3. Operation This section describes the basic components, functions and operation of the TMP92CF26A TMP92CF26A. 3.1 CPU The TMP92CF26A TMP92CF26A contains an advanced high-speed 32-bit CPU (TLCS-900/H1 TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the TLCS-900/L1 TLCS-900/L1 CPU. The TLCS-900/H1 TLCS-900/H1 CPU has an expanded 32-bit internal data bus to process Instructions more quickly. The following is an outline of the CPU: Table 3.1.1Outline of TMP92CF26A TMP92CF26A Parameter TMP92CF26A TMP92CF26A Width of CPU Address Bus Width of CPU Data Bus Internal Operating Frequency Minimum Bus Cycle Internal RAM Internal Boot ROM Internal I/O 24-bit 32-bit Max 80MHz 1-clock access (12.5ns at 80MHz) 32-bit 2-1-1-1 clock access 32 bit 2-clock access 8-bit, INTC,SDRAMC, 2-clock access MEMC,LCDC, TSI,PORT,PMC 16-bit, 2-clock access 32-bit, 2-clock access 32-bit, 1-clock access 8-bit, 5 to 6-clock access External memory (SRAM, MASKROM etc.) External memory (SDRAM) External memory (NAND FLASH) Minimum Instruction Execution Cycle Conditional Jump Instruction Queue Buffer Instruction Set CPU mode Micro DMA Hardware DMA 92CF26A-14 92CF26A-14 MMU,USB, NDFC,SPIC,DMAC 2 IS MAC TMRA,TMRB, SIO,RTC, MLD/ALM, SBI CGEAR,ADC,WDT 8/16-bit 2-clock access (waits can be inserted) 16-bit 1-clock access 8/16-bit 2-clock access (waits can be inserted) 1-clock (12.5ns at 80MHz) 2-clock (25.0ns at 80MHz) 12-byte Compatible with TLCS-900/L1 TLCS-900/L1 (LDX instruction is deleted) Maximum mode only 8-channel 6-channel 2007-11-21 TMP92CF26A TMP92CF26A 3.1.2 Reset Operation When resetting the TMP92CF26A TMP92CF26A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input Low for at least 20 system clocks (32µs at X1=10MHz). At reset, since the clock doublers (PLL0) is bypassed and the clock-gear is set to 1/16, the system clock operates at 625 kHz(X1=10MHz). When the Reset has been accepted, the CPU performs the following. CPU internal registers do not change when the Reset is released. · Sets the Stack Pointer (XSP) to 00000000H 00000000H. · Sets bits of the Status Register (SR) to "111" (thereby setting the Interrupt Level Mask Register to level 7). · Clears bits of the Status Register to "00" (thereby selecting Register Bank 0). When the Reset is released, the CPU starts executing instructions according to the Program Counter settings. · Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored at address FFFF00H FFFF00H~FFFF02H FFFF02H: PC data in location FFFF00H FFFF00H PC data in location FFFF01H FFFF01H PC data in location FFFF02H FFFF02H When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows. · Initializes the internal I/O registers as table of "Special Function Register" in Section 5. Note1: This LSI builds in RAM internally. However, the data in internal RAM may not be held by Reset operation. After reset, initialize the data in internal RAM. Note2: This LSI builds in PMC function (for reducing stand-by current by blocking the power supply of DVCC1A and DVCC1C). However, if executing reset operation without supplying DVCC1A and DVCC1C, the current may flow to internal. When reset this LSI, supply the power of DVCC1A and DVCC1C first and wait until the power supply stabilizes. Figure 3.1.1 shows reset timing chart. Figure 3.1.2 shows the example of order of supplying power and the timing of releasing reset. 92CF26A-15 92CF26A-15 2007-11-21 92CF26A-16 92CF26A-16 SRxxB SRWR : High-Z DATA-OUT DATA-IN Sampling Sampling fSYS×(15.516.5) Clock (After reset is released, it is started from 1 wait read cycle) DATA-IN 0FFFF00H 0FFFF00H Read WRxx D0D15 D0D15 SRxxB RD D0D15 D0D15 CS2 CS0,1, 3 A23A0 A23A0 RESET fSYS TMP92CF26A TMP92CF26A Write Figure 3.1.1 TMP92CF26A TMP92CF26A Reset timing chart 2007-11-21 TMP92CF26A TMP92CF26A This LSI has the restriction for the order of supplying power. Be sure to supply external 3.3V power with 1.5V power is supplied. When Powering on Power Cut Mode (PMC) When Powering off DVCC1A 1.5V Power DVCC1B DVCC1C 1.5-V rails should be Power should rise and stabilizes within 100 ms. Power should fall and stabilizes within 100 ms. turned on first, 3.3-V rails should be followed by the 3.3-V turned off first, followed by the 1.5-V rails. rails. 3.3V Power DVCC3A DVCC3B High-frequency Oscillation Stabilizing Time AVCC 20 system clock cycles RESET PWE terminal Note1: Although it is possible to turn on or off the 1.5-V and 3.3-V power supply rails simultaneously, it may cause external pins to temporarily become unstable. Therefore, if there is any possibility that this would affect peripheral devices connected with the TMP92CF26A TMP92CF26A, external power supplies should be turned on or off while the internal power supplies are stable, as indicated by the heavy lines in the diagram above. Note2: In the power-on sequence, the 3.3-V power supply rails must not be turned on before the ones of 1.5-V . In the power -off sequence, the 3.3-V power supply rails must not be turned off after the ones of 1.5-V. Figure 3.1.2 Power on Reset Timing Example 92CF26A-17 92CF26A-17 2007-11-21 TMP92CF26A TMP92CF26A 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup input pin RESET AM1 AM0 0 1 1 0 1 1 0 0 Operation Mode DBGE 0 1 0 1 0 1 0 1 Debug mode 16-bit external bus starting Test mode (Prohibit to set) Test mode (Prohibit to set) BOOT(32-bit internal-MROM ) starting (BOOT mode) Test mode (Prohibit to set) 92CF26A-18 92CF26A-18 2007-11-21 TMP92CF26A TMP92CF26A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92CF26A TMP92CF26A. 000000H 000000H Internal I/O (8 Kbyte) Direct area(n) 000100H 000100H 001FF0H 001FF0H 002000H 002000H 010000H 010000H 64Kbyte area (nn) Internal RAM (128 Kbyte) 021FFFH 021FFFH Don't access area 046000H 046000H (Internal Back Up RAM 16kbyte) 04A000H 04A000H External memory 16Mbyte area (R) F00000H F00000H Provisional Emulator Control Area (64kbyte) (-R) (R+) (Note1) (R + R8/16 R8/16) F10000H F10000H (R + d8/16) (nnn) External memory FFFF00H FFFF00H FFFFFFH Vector table (256 Byte) (Note2) ( = Internal area ) Figure 3.2.1 Memory Map Note1: The Provisional emulator control area, mapped F00000H F00000H to F0FFFFH after reset, is for a Debug mode use and so is not available Note2: Do not use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved as internal area. 92CF26A-19 92CF26A-19 2007-11-21 TMP92CF26A TMP92CF26A 3.3 Clock Function and Standby Function The TMP92CF26A TMP92CF26A contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4) noise reduction circuits. They are used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFRs 3.3.3 System clock controller 3.3.4 Prescaler clock controller 3.3.5 Noise reduction circuits 3.3.7 Standby controller 92CF26A-20 92CF26A-20 2007-11-21 TMP92CF26A TMP92CF26A The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only), (b) PLL-ON Mode (X1, X2, and PLL). Figure 3.3.1 shows a transition figure. Reset (fOSCH/16) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) release Reset instruction interrupt instruction interrupt (a) PLL-OFF mode (fOSCH/gear value) instruction interrupt STOP mode (Stops all circuits) PLL-OFF mode transition figure Reset (fOSCH/16) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) instruction interrupt instruction interrupt release Reset instruction PLL-OFF mode interrupt /gear value) (f OSCH STOP mode (Stops all circuits) Instruction (Note) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) instruction interrupt instruction interrupt PLL-ON mode (12 or 16)×fOSCH/gear value) (b) PLL-OFF , PLL-ON mode transition figure Note 1: When shifting from PLL-ON mode to PLL-OFF mode, execute the following setting in the same order. (1) Change CPU clock (Set "0" to PLLCR0) (2) Stop PLL circuit (Set "0" to PLLCR1) Note 2: It is not possible to shift from PLL-ON mode to STOP mode directly. PLL-OFF mode should be set once before shifting to STOP mode. Figure 3.3.1 System clock block diagram The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 is called the system clock fSYS. And one cycle of fSYS is defined to as one state. 92CF26A-21 92CF26A-21 2007-11-21 TMP92CF26A TMP92CF26A 3.3.1 Block diagram of system clock SYSCR0 SYSCR2 T0 ÷4 Warming up timer (High/Low frequency oscillator circuit) T0TMR ÷2 Lock up timer (PLL) ÷2 ÷8 SYSCR0 XT1 XT2 Low frequency Oscillator circuit SYSCR0 PLLCR1, PLLCR0 fs fs fc fc/2 fc/4 X1 X2 Clock Doubler0 (PLL0) × (12 or16) fSYS fc/8 fPLL ÷2 fc/16 ÷2 ÷2 High frequency Oscillator circuit fOSCH ÷4 ÷8 ÷16 fIO SYSCR1 Clock gear PLLCR0 SYSCR0 Clock Doubler1 (PLL1)× 24 ÷5 fPLLUSB fUSB X1USB fSYS LCDC RAM Memory Controller NAND-Flash I/O ports IS SDRAMC T0TMR CPU Interrupt Controller fio TSI DMAC SPIC TMRA0:7,TMRB0:1 Prescaler SIO0 T0 Controller 2 fPLL Prescaler SBI Prescaler MAC RTC fs MLD/ALM ADC WDT USB fUSB Figure 3.3.2 Block Diagram of System clock 92CF26A-22 92CF26A-22 2007-11-21 TMP92CF26A TMP92CF26A TMP92CF26A TMP92CF26A has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1). Each PLL can be controlled independently. Frequency of external oscillator is 6 to 10MHz. Don't connect oscillator more than 10MHz. When clock is input by using external oscillator, range of input frequency is 6 to 10MHz. Don't input the clock over 10MHz. Table 3.3.1 Setting example for fOSCH High frequency: fOSCH (a) USB in use, with PLL (PLL0 ON/PLL1 ON) (b) USB not in use, with PLL (PLL0 ON/PLL1 OFF) (c) USB not in use, without PLL (PLL0 OFF/PLL1 OFF) System clock: fSYS System clock: fSYS USB clock: fUSB 10.0 MHz Max 80 MHz Max 60 MHz 48 MHz Max 10.0 MHz Max 80 MHz Max 60 MHz - Max 10.0 MHz Max 10 MHz Max 10 MHz - Note: When using USB, the high-frequency oscillator should be 10.0 MHz. 92CF26A-23 92CF26A-23 2007-11-21 TMP92CF26A TMP92CF26A 3.3.2 SFR 7 SYSCR0 (10E0H 10E0H) 5 4 XTEN bit Symbol Read/write Reset State Function 6 USBCLK1 R/W 0 USBCLK0 1 3 2 1 0 WUEF R/W 0 Warm-up Timer 0 Low -frequency oscillator circuit (fs) Select the clock of USB(fUSB) 00:Disable 01: Reserved 10: X1USB 0: Stop 1: Oscillation 11: fPLLUSB PRCK R/W 0 Select Prescaler clock 0: fSYS/2 1: fSYS/8 0: Write Don't care Note3 1: Write start timer 0: Read end warm-up 1: Read do not end warm-up 7 SYSCR1 (10E1H 10E1H) 6 5 3 bit Symbol Read/write Reset State Function 2 1 0 GEAR2 bit Symbol Read/write Reset State Function GEAR1 R/W 0 GEAR0 1 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: Reserved 110: Reserved 111: Reserved 7 SYSCR2 (10E2H 10E2H) 4 6 ­ CKOSEL 0 Always write "0" 5 0 4 WUPTM1 WUPTM0 R/W 1 0 Select Warm-Up Timer CLKOUT 00: Reserved 0: fSYS 01: 28/inputted frequency 1: fS 10:214/inputted frequency 11:216/inputted frequency 3 2 HALTM1 HALTM0 1 1 0 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode Note1: The unassigned registers, SYSCR0,SYSCR1 and SYSCR2 are read as undefined value. Note2: Low frequency oscillator circuit is enabled on reset. Note3: Do not write SYSCR0 resiter during warming up. Because the warm-up end flag doesn't become enable if write "0" to SYSCR0 bit during warming up. (A read-modify­write operation cannot be performed for SYSCR0 register during warming up.) Figure 3.3.3 SFR for system clock 92CF26A-24 92CF26A-24 2007-11-21 TMP92CF26A TMP92CF26A 7 EMCCR0 Bit symbol (10E3H 10E3H) Read/Write Reset State Function EMCCR1 Bit symbol (10E4H 10E4H) Read/Write Reset State Function EMCCR2 Bit symbol (10E5H 10E5H) Read/Write Reset State Function 6 5 4 2 - PROTECT R 0 3 EXTIN 0 Protect flag 0: OFF 1: ON Always write "0". 1 0 1: External clock DRVOSCH DRVOSCL R/W 1 1 fc oscillator fs oscillator drive ability drive ability 1: NORMAL 0: WEAK st 0 1: NORMAL 0: WEAK nd Switch the protect ON/OFF by writing the following to 1 -KEY,2 -KEY st 1 -KEY: write in sequence EMCCR1=5AH,EMCCR2=A5H nd 2 -KEY: write in sequence EMCCR1=A5H,EMCCR2=5AH Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0, = "1". Figure 3.3.4 SFR for system clock 92CF26A-25 92CF26A-25 2007-11-21 TMP92CF26A TMP92CF26A 7 PLLCR0 (10E8H 10E8H) 6 FCSEL R/W 0 bit symbol Read/Write Reset State Function 5 LUPFG R 0 Select fc-clock 0 : fOSCH 1 : fPLL 4 3 2 1 0 1 0 Lock-up timer Status flag 0 : not end 1 : end Note: Ensure that the logic of PLLCR0 is different from 900/L1 900/L1's DFM. 7 PLLCR1 (10E9H 10E9H) bit symbol Read/Write Reset State Function 6 5 PLL0 PLL1 R/W 0 LUPSEL 0 PLL0 for CPU 0: Off 1: On PLL1 for USB 0: Off 1: On 4 3 2 PLLTIMES R/W 0 0 Select the number of PLL 0: ×12 1: ×16 Select stage of Lock up counter 0: 12 stage (for PLL0) 1:13 stage (for PLL1) Figure 3.3.5 SFR for PLL 7 PxDR (xxxxH) Read/Write System Reset State Hot Reset State Function 5 4 Px7D bit symbol 6 3 Px6D Px5D Px4D 2 1 0 Px3D Px2D Px1D Px0D R/W 1 1 1 1 1 1 1 1 - - - - - - - - Output/Input buffer drive-register for standby-mode (Purpose and using) · · · · · · This register is used to set each pin-status at stand-by mode. All ports have registers of the format shown above. ("x" indicates the port name.) For each register, refer to 3.5 Function of Ports. Before "HALT" instruction is executed, set each register pin-status. They will be effective after the CPU has executes the "HALT" instruction. This is the case regardless of stand-by modes (IDLE2, IDLE1 or STOP). This is the case regardless of using PMC function. For details, refer to PMC section. The Output/Input buffer control table is shown below. OE PxnD Output buffer Input buffer 0 0 OFF OFF 0 1 OFF ON 1 0 OFF OFF 1 1 ON OFF Note1: OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note2: "n" in PxnD denotes the bit number of PORTx. Figure 3.3.6 SFR for Drive register 92CF26A-26 92CF26A-26 2007-11-21 TMP92CF26A TMP92CF26A 3.3.3 System clock controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. SYSCR0 and SYSCR0 control enabling and disabling of each oscillator. SYSCR1 sets the high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8, fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The combination of settings = "1", = "0" and = "100" will be PLL-OFF mode and cause the system clock (fSYS) to be set to fc/16 after reset. For example, fSYS is set to 625 kHz when the 10MHz oscillator is connected to the X1 and X2 pins. (1) Clock gear controller fSYS is set according to the contents of the Clock Gear Select Register SYSCR1 to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fSYS reduces power consumption. (Example) Changing clock gear SYSCR1 EQU 10E1H 10E1H LD (SYSCR1),XXXXX001B XXXXX001B LD Changes system clock fSYS to fc/2 (DUMMY),00H ; Dummy instruction X: don't care (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 register. It is necessary for the warming up time to elapse before the change occurs after writing the register value. There is the possibility that the instruction following the clock gear changing instruction is executed by the clock gear before changing. To execute the instruction following the clock gear switching instruction by the clock gear after changing, input the dummy instruction as follows (instruction to execute the write cycle). (Example) SYSCR1 EQU 10E1H 10E1H LD (SYSCR1),XXXXX010B XXXXX010B ; Changes fSYS to fc/4 LD (DUMMY),00H ; Dummy instruction Instruction to be executed after clock gear changed 92CF26A-27 92CF26A-27 2007-11-21 TMP92CF26A TMP92CF26A 3.3.4 Clock doubler (PLL) PLL0 outputs the fPLL clock signal, which is 12 or 16 times as fast as fOSCH. A low-speed frequency oscillator can be used as external oscillator, even though the internal clock is high-frequency. Since Reset initializes PLL0 to stop status, so setting to PLLCR0 and PLLCR1-register is needed before use. As with an oscillator, this circuit requires time to stabilize. This is called the lock-up time and it is measured by a 12-stage binary counter. Lock-up time is about 0.41ms at fOSCH = 10MHz. PLL (PLL1) which is special for USB is built in. Lock-up time is about 0.82ms at fOSCH = 10MHz measured by 13-stage binary counter. Note1: Input frequency range for PLL The input frequency range (High frequency oscillation) for PLL is as follows: fOSCH = X to X MHz (Vcc = 1.4 to 1.6V) Note2: PLLCR0 The logic of PLLCR0 is different from 900/L1 900/L1's DFM. Exercise care in determining theend of lock-up time. Note3: PLLCR1, PLLCR1 It is not possible to turn ON both PLL0 and PLL1 simultaneously. If turning ON simultaneously, one PLL should be turn ON after finishing the lock up of the other PLL. Table 3.3.2 shows the frequency of fSYS when using PLL and clock gear at fOSCH =10MHz. Table 3.3.2 The frequency of fSYS at fOSCH =10MHz Frequency of fSYS fOSCH fPLL fc fc/2 fc/4 fc/8 fc/16 10MHz fOSCH 10MHz 10MHz 5MHz 2.5MHz 1.25MHz 625KHz ×12 120MHz 60MHz 30MHz 15MHz 7.5MHz 3.75MHz ×16 160MHz 80MHz 40MHz 20MHz 10MHz 5MHz 92CF26A-28 92CF26A-28 2007-11-21 TMP92CF26A TMP92CF26A The following is an example of settings for PLL0-starting and PLL0 stopping. (Example-1) PLL0-starting PLLCR0 EQU 10E8H 10E8H PLLCR1 EQU 10E9H 10E9H LD (PLLCR1),1XXXXXXXXB ; BIT 5,(PLLCR0) ; JR Z,LUP ; LD LUP: (PLLCR0), X1XXXXXXB Enables PLL0 operation and starts lock up. ; Detects end of lock-up Changes fc from 10 MHz to 60 MHz. X: Don't care PLL output: fPLL Lockup timer Counts up by fOSCH During lock-up After lock-up System clock fSYS Starts PLL0 operation and Starts lock-up. Changes from 10MHz to 60MHz. Ends of lock-up (Example-2) PLL0-stopping PLLCR0 EQU 10E8H 10E8H PLLCR1 EQU 10E9H 10E9H LD (PLLCR0),X0XXXXXXB ; Changes fc from 60 MHz to10 MHz. LD (PLLCR1),0XXXXXXXB ; Stop PLL X: Don't care PLL0 output: fPLL System clock fSYS Changes from 60MHz to 10 MHz. Stops PLL0 operation . Note: PLL1 operates as well. 92CF26A-29 92CF26A-29 2007-11-21 TMP92CF26A TMP92CF26A Limitations on the use of PLL0 1. When stopping PLL operation during PLL0 use, execute the following settings in the same order. LD (PLLCR0),X0XXXXXXB ; Change the clock fPLL to fOSCH LD (PLLCR1),0XXXXXXXB ; Stop PLL0 X: Don't care 2. When shifting to STOP mode during PLL use, execute the following settings in the same order. LD (SYSCR2),XXXX01XXB XXXX01XXB ; Set the STOP mode LD (PLLCR0), X0XXXXXXB ; Change the system clock fPLL to fOSCH LD (PLLCR1), 0XXXXXXXB ; Stop PLL0 ; Shift to STOP mode HALT X: Don't care Examples of settings are shown below: (1) Start Up / Change Control (OK) High frequency oscillator operation mode(fOSCH )PLL0 start up PLL0 use mode (fPLL ) LD (PLLCR1), 1XXXXXXXB ; BIT 5,(PLLCR0) ; JR Z,LUP ; Check for lock up end flag LD LUP: (PLLCR0), X1XXXXXXB ; Change the system clock fOSCH to fPLL PLL0 start up / lock up start X: Don't care (2) Change / Stop Control (OK) PLL0 use mode (fPLL ) High frequency oscillator operation mode(fOSCH ) PLL0 Stop LD (PLLCR0),X0XXXXXXB ; LD (PLLCR1),0XXXXXXXB ; Change the system clock fPLL to fOSCH Stop PLL0 X: Don't care (OK) PLL0 use mode (fPLL ) Set the STOP mode High frequency oscillator operation mode (fOSCH) PLL stop HALT(High frequency oscillator stop) LD (SYSCR2),XXXX01XXB XXXX01XXB ; LD (PLLCR0),X0XXXXXXB ; LD (PLLCR1),0XXXXXXXB ; Change the system clock fPLL to fOSCH Stop PLL0 ; Shift to STOP mode Set the STOP mode (This command can be executed before use of PLL0) HALT X: Don't care (NG) PLL0 use mode (fPLL) Set the STOP mode HALT(High frequency oscillator stop) LD (SYSCR2),XXXX01XXB XXXX01XXB ; Set the STOP mode (This command can be executed before use of PLL0) HALT ; Shift to STOP mode X: Don't care 92CF26A-30 92CF26A-30 2007-11-21 TMP92CF26A TMP92CF26A 3.3.5 Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator circuit (2) Reduced drivability for low-frequency oscillator circuit (3) Single drive for high-frequency oscillator circuit (4) Runaway prevention using SFR protection register These are set in EMCCR0 to EMCCR2 registers. (1) Reduced drivability for high-frequency oscillator circuit (Purpose) Reduces noise and power for oscillator when a resonator is used. (Clock diagram) fOSCH C1 X1 pin Enable oscillation Resonator EMCCR0 C2 X2 pin (Setting method) The drivability of the oscillator is reduced by writing"0" to EMCCR0 register. At reset, is initialized to "1" and the oscillator starts oscillation by normal-drivability when the power-supply is on. Note: This function (EMCCR0= "0") is available when fOSCH = 6 to 10MHz. 92CF26A-31 92CF26A-31 2007-11-21 TMP92CF26A TMP92CF26A (2) Reduced drivability for low-frequency oscillator circuit (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Enable oscillation Resonator EMCCR0 C2 fS XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0 register. At Reset, is initialized to "1". (3) Single drive for high-frequency oscillator circuit (Purpose) Remove the need for twin-drives and protect prevent operational errors caused by noise input to X2 pin when an external-oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 register. X2 pin's output is always "1". At reset, is initialized to "0". Note: Do not write EMCCR0 = "1" when using external resonator. 92CF26A-32 92CF26A-32 2007-11-21 TMP92CF26A TMP92CF26A (4) Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or by changes to the memory control register (Memory controller, MMU) which prevent fetch operations. Runaway error handling is also facilitated by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR, MEMCR0, CSTMGCR, WRTMGCR, RDTMGCR0 RDTMGCR1, BROMCR 2. MMU LOCALPX/PY/PZ, LOCALLX/LY/LZ, LOCALRX/RY/RZ, LOCALWX/WY/WZ, LOCALESX/ESY/ESZ, LOCALEDX/EDY/EDZ, LOCALOSX/OSY/OSZ, LOCALODX/ODY/ODZ 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 4. PLL PLLCR0,PLLCR1 5. PMC PMCCTL (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 registers. (Double key) 1st-KEY: writes in sequence, 5AH at EMCCR1 and A5H at EMCCR2 2nd-KEY: writes in sequence, A5H at EMCCR1 and 5AH at EMCCR2 Protection state can be confirmed by reading EMCCR0. At reset, protection becomes OFF. INTP0 interruption also occurs when a write operation to the specified SFR is executed with protection in the ON state. 92CF26A-33 92CF26A-33 2007-11-21 TMP92CF26A TMP92CF26A 3.3.6 Standby controller (1) HALT Modes and Port Drive-register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP Mode, depending on the contents of the SYSCR2 register and each pin-status is set according to the PxDR register, as shown below. 7 PxDR bit symbol (xxxxH) Read/Write System Reset State Hot Reset State Function 6 5 4 3 2 1 0 Px7D Px6D Px5D Px4D Px3D Px2D Px1D Px0D R/W 1 1 1 1 1 1 1 1 - - - - - - - - Output/Input buffer drive-register for standby-mode (Purpose and using) · · · · This register is used to set each pin-status at stand-by mode. All ports have this registers of the format shown above ("x" indicates the port-name.) For each register, refer to 3.5 Function of Ports. Before "HALT" instruction is executed, set each register pin-status. They will be effective after the CPU has executed the "HALT" instruction. · This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP). · This is the case regardless of using PMC function. For details, refer to PMC section. The Output/Input-buffer control table is shown below. OE PxnD Output buffer Input buffer 0 0 OFF OFF 0 1 OFF ON 1 0 OFF OFF 1 1 ON OFF Note1: OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note2: "n" in PxnD denotes the bit number of PORTx. The subsequent actions performed in each mode are as follows: a. IDLE2: Only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. Table 3.3.3 shows the registers setting operation during IDLE2 mode. Table 3.3.3 SFR setting operation during IDLE2 mode Internal I/O SFR TMRA01 TMRA01 TMRA23 TMRA23 TMRA45 TMRA45 TMRA67 TMRA67 TMRB0 TMRB1 SIO0 SBI A/D converter WDT TA01RUN TA01RUN TA23RUN TA23RUN TA45RUN TA45RUN TA67RUN TA67RUN TB0RUN TB1RUN SC0MOD1 SBIBR0 ADMOD1 WDMOD b. IDLE1: Only the oscillator, RTC (real-time clock), and MLD continue to operate. c. STOP: All internal circuits stop operating. 92CF26A-34 92CF26A-34 2007-11-21 TMP92CF26A TMP92CF26A The operation of each of the different Halt Modes is described in Table 3.3.4. Table 3.3.4 I/O operation during Halt Modes HALT Mode IDLE2 IDLE1 STOP SYSCR2 11 10 01 Block CPU, MAC I/O ports TMRA, TMRB SIO,SBI A/D converter WDT I2S, LCDC, SDRAMC, Interrupt controller, SPIC, DMAC, NDFC, USB RTC, MLD Stop Depends on PxDR register setting Available to select Operation block Stop Operate Operate (2) How to release the Halt mode These HALT states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination of the states of the interrupt mask register and the halt modes. The details for releasing the HALT status are shown in Table 3.3.5. · Release by interrupt requesting The HALT mode release method depends on the status of the enabled interrupt. When the interrupt request level set before executing the HALT instruction exceeds the value of the interrupt mask register, the interrupt is processed depending on its status after the HALT mode is released, and the CPU status executing the instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, HALT mode release is not executed.(in non-maskable interrupts, interrupt processing is processed after releasing the halt mode regardless of the value of the mask register.) However only for INT0 to INT5, INT6, INT7(unsynchronous interrupt), INTKEY,INTRTC, INTALM interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, HALT mode release is executed. In this case, the interrupt is processed, and the CPU starts executing the instruction following the HALT instruction, but the interrupt request flag is held at "1". · Release by resetting Release of all halt statuses is executed by resetting. When the STOP mode is released by RESET, it is necessary to allow enough resetting time for operation of the oscillator to stabilize. When releasing the halt mode by resetting, the internal RAM data keeps the state before the "HALT" instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the "HALT" instruction is executed.) 92CF26A-35 92CF26A-35 2007-11-21 TMP92CF26A TMP92CF26A Table 3.3.5 Source of Halt state clearance and Halt clearance operation Status of Received Interrupt Interrupt Enabled (interrupt level) (interrupt mask) HALT mode IDLE2 IDLE1 INT0 to 5 (Note1) INTKEY INTUSB STOP IDLE2 IDLE1 STOP × INTWDT × - - - *1 *2 *1 *2 × × *1 INT6 to 7(PORT) (Note1) × INT6 to 7(TMRB) Interrupt Source of Halt state clearance Interrupt Disabled (interrupt level) < (interrupt mask) × *1 × × × INTALM, INTRTC INTTA0 to 7, INTTP0 INTTB00 INTTB00 to 01, INTTB10 INTTB10 to 11 INTRX,INTTX, INTSBI INTI2S0 to 1, INTLCD, INTAD, INTADHP INTSPIRX,INTSPITX INTRSC, INTRDY INTDMA0 to 5 RESET × × × × × × × Reset initializes the LSI : After clearing the Halt mode, CPU starts interrupt processing. : After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT instruction. ×: Cannot be used to release the halt mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. This combination is not available. *1: Release of the HALT mode is executed after warm-up time has elapsed. *2: 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode, allowing for the construction of low power dissipation systems. However, the method of use is limited as below. · Shift to IDLE1 mode : Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is "1" ( SUSPEND state ) · Release from IDLE1 mode : Release Halt state by INT_RESUME or INT_CLKON request (release SUSPEND request) Release Halt state by INT_URST_STR or INT_URST_END request(RESET request) Note: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. 92CF26A-36 92CF26A-36 2007-11-21 TMP92CF26A TMP92CF26A (Example - releasing IDLE1 Mode) An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode. Address 8200H 8200H LD (PCFC), 02H ; Sets PC1 to INT0 interrupt. 8203H 8203H LD (IIMC0), 00H ; Select INT0 interrupt rising edge. 8206H 8206H LD (INTE0), 06H ; Sets INT0 interrupt level to 6. 8209H 8209H EI 5 ; Sets CPU interrupt level to 5. 820BH 820BH LD (SYSCR2), 28H 820EH 820EH HALT ; Sets Halt mode to IDLE1 mode. ; Halts CPU. INT0 INT0 interrupt routine. RETI 820FH 820FH LD XX, XX 92CF26A-37 92CF26A-37 2007-11-21 TMP92CF26A TMP92CF26A (3) Operation a. IDLE2 Mode In IDLE2 Mode, only specific internal I/O operations, as designated by the IDLE2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2 Mode Halt state by an interrupt. X1 A0~A23 D0~D31 Data Data RD WR Interrupt for releasing Halt IDLE2 mode Figure 3.3.7 Timing chart for IDLE2 Mode Halt state cleared by interrupt b. IDLE1 Mode In IDLE1 Mode, only the internal oscillator and the RTC and MLD continue to operate. The system clock stops. In the Halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (i.e. restart of operation) is synchronous with it. Figure 3.3.8 illustrates the timing for clearance of the IDLE1 Mode Halt state by an interrupt. X1 A0~A23 D0~D31 Data Data RD WR Interrupt for releasing Halt IDLE1 mode Figure 3.3.8 Timing chart for IDLE1 Mode Halt state cleared by interrupt 92CF26A-38 92CF26A-38 2007-11-21 TMP92CF26A TMP92CF26A c. STOP Mode When STOP Mode is selected, all internal circuits stop, including the internal oscillator. After STOP Mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.9 illustrates the timing for clearance of the STOP Mode Halt state by an interrupt. Warm-up time X1 A0~A23 D0~D31 Data Data RD WD Interrupt for releasing Halt STOP mode Figure 3.3.9 Timing chart for STOP Mode Halt state cleared by interrupt Table 3.3.6 Example of warming-up time after releasing STOP-mode @fOSCH =10 MHz SYSCR2 8 01 (2 ) 10 (214) 11 (216) 25.6 s 1.6384 ms 6.5536 ms 92CF26A-39 92CF26A-39 2007-11-21 TMP92CF26A TMP92CF26A Table 3.3.7 Input Buffer State Table Input Buffer State Port Name Input Function Name In HALT mode (IDLE2/1/STOP) When the CPU is operating =1 During Reset When Used as function Pin D0-D7 D0-D7 OFF P10-P17 P10-P17 D8-D15 D8-D15 16bit Start OFF Boot Start ON P60-P67 P60-P67 - 16bit Start OFF Boot Start ON P71-P74 P71-P74 ON upon external read function Pin - Input port function Pin - Input port - OFF OFF - - - - - ON ON OFF - NDR/ W P76 Input port =0 When Used as When Used as When Used as When Used as - - P75 When Used as - - ON OFF WAIT P90 - P91 RXD0 P92 CTS0 ON ,SCLK0 P96 *1 P97 - PA0-PA7 *1 ON INT4 KI0-KI7 PC0 - ON ON OFF - INT1,TA0IN PC2 ON - - - - INT0 PC1 ON INT2 PC3 INT3,TA2IN PC4-PC7 - PF0-PF5 - PG0-PG2 PG4,PG5 *2 - PG3 *2 ADTRG PJ5-PJ6 - - PP1-PP2 - OFF - - - ON OFF - INT7,TB1IN0 - ON INT6,TB0IN0 PP5 ON - - OFF INT5 PP4 ON - PP3 ON ON upon port read - PN0-PN7 OFF PR0 SPDI PR1-PR3 - PT0-PT7 - PU0-PU4, PU6,PU7 - PU5 - PV0-PV2 - PV6-PV7 ON - PX5 ON SDA, SCL PW0-PW7 ON X1USB PX7 - PZ0-PZ5 OFF EI_PODDATA, EI_SYNCLK, EI_PODREQ, EI_REFCLK, EI_TRGIN, EI_COMRESET PZ6-PZ7 - DBGE ON ON ON - D+, D- - AM0,AM1 - - - X1,XT1 - - RESET - Always ON IDLE2/DLE1: ON ON: The buffer is always turned on. A current flows through the input buffer if the input pin is not driven. *1: Port having a pull-up/pull-down resistor. *2: AIN input does not cause a current to flow through the buffer. OFF: The buffer is always turned off. - : Not applicable 92CF26A-40 92CF26A-40 2007-11-21 TMP92CF26A TMP92CF26A Table 3.3.8 Output buffer State Table (1/2) Output Buffer State Port Name Output Function Name OFF D8-D15 D8-D15 16bit Start OFF Boot Start OFF P40-P47 P40-P47 A0-A7 P50-P57 P50-P57 A8-A15 A8-A15 P60-67 P60-67 A16-A23 A16-A23 RD ON Output port ON upon external write function Pin - ON = 0 When Used as When Used as When Used as When Used as Output port P71 WRLL OFF WRLU Output port - ON ON , NDRE P72 function Pin - 16bit Start ON Boot Start OFF P70 When Used as function Pin D0-D7 P10-17 P10-17 = 1 During Reset When Used as D0-7 In HALT mode (IDLE2/1/STOP) When the CPU is operating OFF ON ON , NDWE P73 EA24 P74 EA25 P75 R/ W P76 - OFF - P80 - ON - OFF CS0 P81 ON CS1 , SDCS P82 CS 2 , CSZA SDCS P83 CS3 , CSXA P84 CSZB P85 CSZC P86 CSZD P87 CSXB P90 ON ON ON OFF - - - , ND0CE , ND1CE TXD0 P91 - P92 SCLK0 P96 PX P97 PY OFF PC0-PC3 - PC4 - ON - - EA28 PC7 KO8 PF0 I2S0DO PF2 ON ON OFF - - - I2S0WS PF3 - OFF I2S0CKO PF1 - OFF EA27 PC6 - EA26 PC5 ON I2S1CKO PF4 I2S1DO PF5 I2S1WS PF7 SDCLK PG2 MX PG3 MY PJ0 SDRAS PJ1 SDCAS PJ2 SDWE ON OFF , SRLLB , SRLUB , SRWR PJ3 ON ON OFF SDLLDQM PJ4 ON SDLUDQM PJ5 NDALE PJ6 NDCLE PJ7 SDCKE PK0 ON LCP0 PK1 OFF ON OFF LLOAD PK2 LFR PK3 LVSYNC PK4 LHSYNC PK5 LGOE0 PK6 LGOE1 PK7 LGOE2 PL0-PL7 ON LD0-LD7 92CF26A-41 92CF26A-41 2007-11-21 TMP92CF26A TMP92CF26A Table 3.3.9 Output buffer state table (2/2) Output Buffer State Port Name Output Function Name During Reset In HALT mode (IDLE2/1/STOP) When the CPU is operating =1 PM2 When Used as function Pin PM1 When Used as Output port =0 When Used as When Used as When Used as When Used as function Pin Output port function Pin Output port MLDALM,TA1OUT MLDALM , ALARM PM7 PN0-PN7 KO0-KO7 PP1 TA3OUT PP2 TA5OUT PP3 ON PWE TA7OUT PP4-PP5 TB0OUT0 PP7 TB1OUT0 PR0 OFF - - - ON ON OFF - ON - PR1 ON - - ON ON OFF - PP6 ON SPDO PR2 SPCS PR3 SPCLK PT0-PT7 LD8-LD15 LD8-LD15 PU0-PU6 LD16-LD22 LD16-LD22 PU7 OFF OFF ON ON OFF LD23 EO_TRGOUT ON PV0 SCLK0 OFF PV1 - PV2 - PV6 SDA PV7 SCL - - PV3-PV4 PW0-PW7 CLKOUT, LDIV PX5 OFF - PX4 - - ON ON OFF ON - PX7 - PZ6-PZ7 D+, D- - X2 OFF - - ON ON - XT2 - ON ON EO_MCUDATA, EO_MCUREQ - ON - - PZ0-PZ5 - ON - OFF OFF ON/OF depend on USBC operation Always ON ON: The buffer is always turned on. When the bus is released, however, output buffers for some pins are turned off. IDLE2/1:ON, STOP: output "H" IDLE2/1:ON, STOP: output "HZ" *1: Port having a pull-up/pull-down resistor. OFF: The buffer is always turned off. - : Not applicable 92CF26A-42 92CF26A-42 2007-11-21 TMP92CF26A TMP92CF26A 3.4 Boot ROM The TMP92CF26A TMP92CF26A contains boot ROM for downloading a user program, and supports two kinds of downloading methods. 3.4.1 Operation Modes The TMP92CF26A TMP92CF26A has two operation modes: MULTI mode and BOOT mode. The operation mode is selected according to the AM1 and AM0 pin levels when RESET is asserted. (1) MULTI mode: After reset, the CPU fetches instructions from external memory and executes them. (2) BOOT mode: After reset, the CPU fetches instructions from internal boot ROM and executes them. The boot ROM loads a user program into internal RAM from USB, or via UART, and then branches to the internal RAM. In this way the user program starts boot operation. Table 3.4.2 shows an outline of boot operation. Table 3.4.1 Operation Modes Mode Setting Pins Operation Mode AM1 AM0 0 1 MULTI 1 0 TEST (Setting prohibited) 1 1 BOOT (Start from internal boot ROM) 0 RESET 0 TEST (Setting prohibited) Start from external 16-bit bus memory Table 3.4.2 Outline of Boot Operation Name Loading Priority Source I/F (a) 1 PC (UART) UART (b) 2 PC (USB_HOST) USB 92CF26A-43 92CF26A-43 Destination Internal RAM Operation after Loading Branch to internal RAM 2007-11-21 TMP92CF26A TMP92CF26A 3.4.2 Hardware Specifications of Internal Boot ROM (1) Memory map Figure 3.4.1 shows a memory map of BOOT mode. The boot ROM incorporated in the TMP92CF26A TMP92CF26A is an 8-Kbyte ROM area mapped to addresses 3FE000H 3FE000H to 3FFFFFH. In MULTI mode, the boot ROM is not mapped and the above area is mapped as an external area. 000000H 000000H Internal I/O 001FF0H 001FF0H 002000H 002000H 010000H 010000H Internal RAM (128 Kbytes) 021FFFH 021FFFH 046000H 046000H 04A000H 04A000H (Internal Backup RAM 16 Kbytes) 3FE000H 3FE000H Internal Boot ROM (8 Kbytes) 3FFF00H 3FFF00H 400000H 400000H FFFF00H FFFF00H (B) Reset/Interrupt (Note) Vector Area (256 bytes) (A) Reset/Interrupt (Note) Vector Area (256 bytes) FFFFFFH Note: BROMCR = "1" : (B) when booting BROMCR = "0" : (A) when multi mode Figure 3.4.1 Memory Map of BOOT Mode (2) Switching the boot ROM area to an external area After the boot sequence is executed in BOOT mode, an application system program may start running without a reset being asserted. In this case, it is possible to switch the boot ROM area to an external area. 92CF26A-44 92CF26A-44 2007-11-21 TMP92CF26A TMP92CF26A 3.4.3 Outline of Boot Operation The method for downloading a user program can be selected from two types: from UART, or via USB. After reset, the boot program on the internal boot ROM executes as shown in Figure 3.4.2. Regardless of the downloading method used, the boot program downloads a user program into the internal RAM and then branches to the internal RAM. Figure 3.4.3 shows how the boot program uses the internal RAM (common to all the downloading methods). Start Yes RESUME check PMCCTL=1 No Clock setting · fSYS = fOSCH · fUSB = fOSCH × 24/5 (a) (b) UART check No No Yes Download via UART USB check Yes Download via USB Branch to internal RAM 46000h Branch to internal RAM 3000h Note 1: To download a user program via USB, a USB device driver and special application software are needed on the PC. Note 2: To download a user program via UART, special application software is needed on the PC. Note 3: The (a), (b) in the above flowchart indicate points where the settings of external port pins are changed. For details, see Table 3.4.3. Figure 3.4.2 Flowchart for Internal Boot ROM Operation 92CF26A-45 92CF26A-45 2007-11-21 TMP92CF26A TMP92CF26A 002000H 002000H Work Area for Boot Program (4 Kbytes) 003000H 003000H Download Area for User Program (124 Kbytes) 021FFFH 021FFFH 046000H 046000H Work Area for User Program (14 Kbytes) 049800H 049800H Stack Area for Boot program (2K bytes) 049FFFH 049FFFH Figure 3.4.3 How the Boot Program Uses Internal RAM 92CF26A-46 92CF26A-46 2007-11-21 TMP92CF26A TMP92CF26A (1) Port settings Table 3.4.3 shows the port settings by the boot program. When designing your application system, please also refer to Table 3.4.4 for recommended pin connections for using the boot program. The boot program only sets the ports shown in the table below; other ports are left as they are after reset or at startup of the boot program. Table 3.4.3 Port Settings by the Boot Program Port Name UART Function Name (a) P90 TXD0 Output P91 USB Description I/O RXD0 Input - D+ D- PUCTL Output No change from (a) I/O PU6 No change from after reset state (input port) I/O - (b) Set as RXD0 input pin (c) Set as TXD0 output pin No change from (b) No change No change from after reset state (input port) 92CF26A-47 92CF26A-47 Set as output port No change from (b) 2007-11-21 TMP92CF26A TMP92CF26A Table 3.4.4 Recommended Pin Connections Port Name UART Function Name I/O UART P90 TXD0 Output P91 RXD0 Input - D+ I/O - USB Recommended Pin Connections for Each Download Method D- Connect to the level shifter. I/O USB No special setting is needed for booting via USB. Add a pull-up resistor (100 krecommended) to prevent transition to UART processing. No special setting is needed for booting via UART. Connect to the USB connector by adding a dumping resistor (27recommended) and a programmable pull-up resistor (1.5 krecommended). When USB is not accessed, the pin level should be fixed with a resistor to prevent flow-through current. If USB is not used, add a pull-up or pull-down resistor to prevent flow-through current on the D+/D- pins. - PU6 PUCTL Connect to the USB connector by adding a dumping resistor (27 recommended). When USB is not accessed, the pin level should be fixed with a resistor to prevent flow-through current. This pin is used to control ON/OFF of the D+ pin's pull-up resistor. Add a switch externally so that the pull-up is turned on when "1". Reset sets this pin as an input port, so add a pull-down resistor (100k recommended). Output Note 1: When a user program is downloaded from UART and USB is used in the system, the pull-up resistor for USB's D+ pin should not be turned on in BOOT mode. Note 2: When a user program is downloaded via USB, do not start the UART application software on the PC. Note 3: When a user program is downloaded via UART, do not connect a USB connector. Note 4: When USB is not used, the D+ and D- pins must be pulled up or down to prevent flow-through current. 92CF26A-48 92CF26A-48 2007-11-21 TMP92CF26A TMP92CF26A (2) I/O register settings Table 3.4.5 shows the I/O registers that are set by the boot program. After the boot sequence, if execution moves to an application system program without a reset being asserted, the settings of these I/O registers must be taken into account. Also note that the registers in the CPU and the internal RAM remain in the state after execution of the boot program. Table 3.4.5 I/O Register Settings by Boot Program Register Name Set Value Description WDMOD 00H Watchdog timer not active WDCR B1H Watchdog timer disabled SYSCR0 70H High-frequency and low-frequency oscillators operating SYSCR1 00H Clock gear = 1/1 SYSCR2 2CH Initial value PLLCR0 00H PLL clock not used PLLCR1 00H Normally PLL is disabled. or 60H However, only in the case of booting via USB, PLL is activated for USB. INTEUSB 04H USB interrupt level setting INTETC01 INTETC01 44H INTTC interrupt level setting Note: The values to be set in the I/O registers for UART and USB are not described here. If these functions are needed in a user program, set each I/O register as necessary. 92CF26A-49 92CF26A-49 2007-11-21 TMP92CF26A TMP92CF26A 3.4.4 Downloading a User Program via UART (1) Connection example Figure 3.4.4 shows an example of connections for downloading a user program via UART (using a 16-bit NOR Flash memory device as program memory). UART 3 pins TXD Level RXD Shifter PC TXD0 P90 (OUT) RXD0, P91 (IN) RTS AM0 D+ DP82, CS2 P70, RD PJ2, SRWR TMP92CF26A TMP92CF26A D0 to D15 CE OE WE NOR Flash Memory D0 toD15 AM1 A1 to 20 A0 toA19 Note: When USB is not used, add a pull-up or pull-down resistor to the D+ and D- pins to prevent flow-through current. Figure 3.4.4 UART Connection Example (2) UART interface specifications SIO channel 0 is used for downloading a user program. The UART communication format in BOOT mode is shown below. Before booting, the PC must also be set up with the same conditions. Although the default baud rate is 9600 bps, this can be changed as shown in Table 3.4.8. Serial transfer mode: : UART (asynchronous) mode, full-duplex Data length : 8 bits Parity bit : None STOP bit : 1 bit Handshake : None Baud rate (default) : 9600 bps 92CF26A-50 92CF26A-50 2007-11-21 TMP92CF26A TMP92CF26A (3) UART data transfer format Table 3.4.6 to Table 3.4.11 show the supported frequencies, data transfer format, baud rate modification command, operation command, and version management information, respectively. Please also refer to the description of boot program operation later in this section. Table 3.4.6 Supported Frequencies (X1) 6.00 MHz 8.00 MHz 9.00 MHz 10.00 MHz Note: The built-in PLL (clock multiplier) is not used regardless of the oscillation frequency. Table 3.4.7 Transfer Format Byte Number to Transfer data from PC to TMP92CF26A TMP92CF26A Transfer Boot Baud Rate Transfer data from TMP92CF26A TMP92CF26A to PC - (Frequency measurement and baud rate auto setting) 1st byte Matching data (5AH) 2nd byte - OK: Echo back data (5AH) 3rd byte to - Version management information 9600 bps ROM Error: No transfer (See Table 3.4.10) 6th byte 7th byte - Frequency information 8th byte Baud rate modification command (See Table 3.4.8.) - 9th byte OK: Echo back data - 10th byte Error: Error code x 3 New baud rate NG: Operation stop by checksum error User program to Intel Hex format (binary) (n - 4)th byte (n - 3)th byte - OK: SUM (High) (n - 2)th byte - OK: SUM (Low) (n - 1)th byte User program start command (C0H) (See Table 3.4.9.) - (See (4)-c).) OK: Echo back data (C0H) Error: Error code x 3 n'th byte - RAM - Branch to user program start address "Error code x 3" means that the error code is transmitted three times. For example, if the error code is 62H, the TMP92CF26A TMP92CF26A transmits 62H three times. For error codes, see (4)-b). 92CF26A-51 92CF26A-51 2007-11-21 TMP92CF26A TMP92CF26A Table 3.4.8 Baud Rate Modification Command Baud Rate (bps) 9600 19200 38400 57600 115200 Modification Command 28H 18H 07H 06H 03H Note 1: If fOSCH (oscillation frequency) is 10.0 MHz, 57600 and 115200 bps are not supported. Note 2: If fOSCH (oscillation frequency) is 6.00, 8.00, or 9.00 MHz, 38400, 57600, and 115200 bps are not supported. Table 3.4.9 Operation Command Operation Command Operation C0H User program start Table 3.4.10 Version Management Information Version Information ASCII Code FRM1 46H, 52H, 4DH, 31H Table 3.4.11 data of measuring frequency X1-X2 oscillator 6.000 8.000 9.000 frequency (MHz) 09H 0AH 08H 10.000 0BH (4) Description of the UART boot program operation The boot program receives a user program sent from the PC via UART and transfers it to the internal RAM. If the transfer ends normally, the boot program calculates SUM and sends the result to the PC before executing the user program. The execution start address is the first address received. The boot program enables users to perform customized on-board programming. When UART is used to download a user program, the maximum allowed program size is 124 Kbytes (3000H 3000H ­ 21FFFH 21FFFH). (The extended Intel Hex format is supported.) a) Operation procedure 1. Connect the serial cable. This must be done before the microcontroller is reset. 2. Set the AM1 and AM0 pins to "1" and reset the microcontroller. 3. The receive data in the 1st byte is matching data (5AH). Upon starting in BOOT mode, the boot program goes to a state in which it waits for matching data. When matching data is received, the initial baud rate of the serial channel is automatically set to 9600 bps. 4. The 2nd byte is used to echo back 5AH to the PC upon completion of the automatic baud rate setting in the 1st byte. If automatic baud rate setting fails, the boot program stops operation. 5. The 3rd through 6th bytes are used to send the version management information of the boot program in ASCII code. The PC should check that the correct version of the boot program is used. 6. The 7th byte is used to send information on the measured frequency. The PC should check that the frequency of the resonator is measured correctly. 92CF26A-52 92CF26A-52 2007-11-21 TMP92CF26A TMP92CF26A 7. The receive data in the 8th byte is baud rate modification data. The five kinds of baud rate modification data shown in Table 3.4.8 are available. Even when the baud rate is not changed, the initial baud rate data (28H: 9600 bps) must be sent. Baud rate modification becomes effective after the echo back transmission is completed. 8. The 9th byte is used to echo back the received data to the PC when the data received in the 8th byte is one of the baud rate modification data corresponding to the operating frequency of the microcontroller. Then, the baud rate is changed. If the received baud rate data does not correspond to the operating frequency, the boot program stops operation after sending the baud rate modification error code (62H). 9. The receive data in the 10th to (n-4)th bytes is received as binary data in Intel Hex format. No echo back data is returned to the PC. The boot program ignores received data and does not send error code to the PC until it receives the start mark (3AH for ":") of Intel Hex format. After receiving the start mark, the boot program receives a range of data from record length to checksum and writes the received data to the specified RAM addresses successively. If a receive error or checksum error occurs, the boot program stops operation without sending error code to the PC. The boot program executes the SUM calculation routine upon detecting the end record. Thus, after sending the end record, the PC should be placed in a state in which it waits for SUM data. 10. The (n-3)th and (n-2)th bytes are used to send the SUM value to the PC in the order of upper byte and lower byte. For details on how to calculate SUM, see "SUM calculation" to be described later. SUM calculation is performed after detecting the end record only when no receives error or checksum error has occurred. Immediately after SUM calculation is completed, the boot program sends the SUM value to the PC. After sending the end record, the PC should determine whether or not writing to RAM has completed successfully based on whether or not the SUM value is received from the boot program. 11. After sending the SUM value, the boot program waits for the user program start command (C0H). If the SUM value is correct, the PC should send the user program start command in the (n-1)th byte. 12. The n'th byte is used to echo back the user program start command to the PC. After sending the echo back data, the boot program sets the stack pointer to 4A000H 4A000H and jumps to the address that is received first as Intel Hex format data. 13. If the user program start command is not correct or a receive error has occurred, the boot program stops operation after sending the error code to the PC three times. 92CF26A-53 92CF26A-53 2007-11-21 TMP92CF26A TMP92CF26A b) Error codes The boot program uses the error codes shown in Table 3.4.12 to notify the PC of its processing status. Table 3.4.12 Error Codes Error Code 62H Meaning Unsupported baud rate 64H Invalid operation command A1H Framing error in received data A3H Overrun error in received data Note 1: If a receive error occurs while a user program is being received, no error code will be sent to the PC. Note 2: After sending an error code, the boot program stops operation. c) SUM calculation 1. Calculation method SUM is calculated by adding data in bytes and is returned in words, as explained below. Example: A1H If the data to be calculated consists of the 4 bytes shown to the left, SUM is calculated as follows: B2H A1H + B2H + C3H + D4H = 02EAH 02EAH C3H SUM (HIGH) = 02H SUM (LOW) = EAH D4H 2. Data to be calculated SUM is calculated from the data at the first received address through the last received address. Even if received addresses are not continuous, unwritten addresses are also included in SUM calculation. The user program should not contain unwritten gaps. 92CF26A-54 92CF26A-54 2007-11-21 TMP92CF26A TMP92CF26A d) Notes on Intel Hex format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (3AH for ":") of the next record. If data other than 3AH is received between records, it is ignored. 2. Once the PC program has finished sending the checksum of an end record, it must wait for 2 bytes of data (upper and lower bytes of SUM) before sending any other data. This is because after receiving the checksum of an end record, the boot program calculates SUM and returns the result to the PC in 2 bytes. 3. Writing to areas other than internal RAM may cause incorrect operation. To transfer a record, set the paragraph address to 0000H 0000H. 4. Since the address pointer is initially set to 00H, the record type to be transferred first does not have to be an address record. 5. Addresses 3000H 3000H to 21FFFH 21FFFH are allocated as the user program download area. 6. A user program in Intel Hex format (ASCII codes) must be converted into binary data in advance, as explained in the example below. Example: How to convert an Intel Hex file into binary format The following shows how an Intel Hex format file is displayed on a text editor. : 103000000607F100030000F201030000B1F16010B7 : 00000001FF 00000001FF However, the actual data consists of ASCII codes, as shown below. Thus, the ASCII codes must be converted into binary data based on the conversion rules shown in the table below. ASCII Code Binary Data 3A 3A (Only 3A remains the same.) 30 to 39 0 to 9 41 or 61 A 42 or 62 B 43 or 63 C 44 or 64 D 45 or 65 E 46 or 66 F 0D0A Delete Intel Hex format Data record 3A 10 3000 00 0607F100030000F201030000B1F16010 0607F100030000F201030000B1F16010 B7 Data Checksum Record type Address Record length End record : (Start mark) 3A 00 0000 01 FF Data Record type Address Record length : (Start mark) 92CF26A-55 92CF26A-55 2007-11-21 TMP92CF26A TMP92CF26A e) User program receive error If either of the following error conditions occurs while a user program is being received, the boot program stops operation. If the record type is other than 00H, 01H, or 02H If a checksum error occurs f) Measured frequency/baud rate error When the boot program receives matching data, it measures the oscillation frequency. If an error is within plus or minus 3%, the boot program decides on that frequency. Each baud rate includes a setting error as shown in Table 3.4.13. For example, in the case of 10.00 MHz /9600 bps, the baud rate is actually set at 9615.38 bps. To establish communication, the sum of the baud rate setting error and the measured frequency error must be within plus or minus 3 %. Table 3.4.13 Baud Rate Setting Errors (%) 9600 bps 19200 bps 38400 bps 57600 bps 115200 bps 6.000 MHz 0.2 0.2 - - - 8.000 MHz 0.2 0.2 - - - 9.000 MHz 0.2 -0.7 - - - 10.000 MHz 0.2 0.2 -1.4 - - -: Not supported 92CF26A-56 92CF26A-56 2007-11-21 TMP92CF26A TMP92CF26A (5) Others a) Handshake function Although the CTS pin is available in the TMP92CF26A TMP92CF26A, the boot program does not use it for transfer control. b) RS-232C RS-232C connector The RS-232C RS-232C connector must not be connected or disconnected while the boot program is running. c) Software on the PC When downloading a user program via UART, special application software is needed on the PC. 92CF26A-57 92CF26A-57 2007-11-21 TMP92CF26A TMP92CF26A 3.4.5 Downloading a User Program via USB (1) Connection example Figure 3.4.5 shows an example of connections for downloading a user program via USB (using a 16-bit NOR Flash memory device as program memory). PUCTL R1 = 1.5 k R4 = 100 k R2 = 27 PC R3 = 27 PU6, LD22 RXD,P91 P82, CS2 P70, RD PJ2, SRWR D+ D- TMP92CF26A TMP92CF26A AM0 D0 to D15 CE OE WE NOR Flash D0 to D15 AM1 A0 to A19 A1 to A20 Note 1: The value of pull-up and pull-down resistors are recommended values. Note 2: The PU6 and LD22 pins are assigned as PUCTL (pull-up control) output for USB. Be careful about this if the system uses the 24-bit TFT display function. Note 3: Since the input gates of the D+ and D- pins are always open even at unused (unaccessed) times, these pins must be set to a fixed level to prevent flow-through current. Although the level setting is not specified in the above diagram, be sure to fix the level of the D+ and D- pins by referring to the chapter on USB. Figure 3.4.5 USB Connection Example (2) USB interface specifications When a user program is downloaded via USB, the oscillation frequency should be set to 10.00 MHz. The transfer speed should be fixed to full speed (12 Mbps). The boot program uses the following two transfer types. Table 3.4.14 Transfer Types Used by the Boot Program Transfer Type Control Transfer Bulk Transfer Description Used for transmitting standard requests and vendor requests. Used for responding to vendor requests and transmitting a user program. 92CF26A-58 92CF26A-58 2007-11-21 TMP92CF26A TMP92CF26A The following shows an overview of the USB communication flow. (Legends) Control Transfer Bulk Transfer Host (PC) Connection Recognition TMP92CF26A TMP92CF26A Send GET_DISCRIPTOR Send DESCRIPTOR information Send the microcontroller information command Send microcontroller information data Prepare microcontroller information data Check data Data Transfer Convert Intel Hex format data into binary data Send the microcontroller information command Send microcontroller information data Prepare microcontroller information data Check data Send the user program transfer start command Send data Send a user program Load the received data into the specified RAM address area & prepare microcontroller information data (If the received data cannot be loaded into RAM for some reason, it is discarded.) Transfer End Processing Transmit the transfer result command 2 seconds after completion of user program transfer Send the transfer result command Send transfer result data Prepare transfer result data Check data Branch to internal RAM Figure 3.4.6 Overall Flowchart 92CF26A-59 92CF26A-59 2007-11-21 TMP92CF26A TMP92CF26A Table 3.4.15 Vendor Request Commands Command Name Value of bRequest Operation Notes Microcontroller information command 00H Send microcontroller Microcontroller information data is information sent by bulk IN transfer after the setup stage is completed. User program transfer start command 02H Receive a user program Set the size of a user program in wIndex. The user program is received by bulk OUT transfer after the setup stage is completed. User program transfer result command 04H Send the transfer result Transfer result data is sent by bulk IN transfer after the setup stage is completed. Table 3.4.16 Setup Command Data Structure Field Name bmRequestType Value 40H Meaning D7 0: Host to Device D6-D5 bRequest 00H, 02H, 04H 2: Vendor D4-D0 0: Device 00H: Microcontroller information 02H: User program transfer start 04H: User program transfer result wValue 00H~FFFFH Own data number (Not used by boot program) wIndex 00H~FFFFH User program size (Used when starting a user program transfer) wLength 0000H 0000H 92CF26A-60 92CF26A-60 Fixed 2007-11-21 TMP92CF26A TMP92CF26A Table 3.4.17 Standard Request Commands Standard Request Response Method GET_STATUS Automatic response by hardware CLEAR_FEATURE Automatic response by hardware SET_FEATURE Automatic response by hardware SET_ADDRESS Automatic response by hardware GET_DISCRIPTOR Automatic response by hardware SET_DISCRIPTOR Not supported GET_CONFIGRATION Automatic response by hardware SET_CONFIGRATION Automatic response by hardware GET_INTERFACE Automatic response by hardware SET_INTERFACE Automatic response by hardware SYNCH_FRAME Ignored Table 3.4.18 Information Returned by GET_DISCRIPTOR DeviceDescriptor Field Name Value Meaning Blength 12H 18 bytes BdescriptorType 01H Device descriptor BcdUSB 0110H 0110H USB Version 1.1 BdeviceClass 00H Device class (Not in use) BdeviceSubClass 00H Sub command (Not in use) BdeviceProtocol 00H Protocol (Not in use) BmaxPacketSize0 40H EP0 maximum packet size (64 bytes) IdVendor 0930H 0930H Vendor ID IdProduct 6504H 6504H Product ID (0) BcdDevice 0001H 0001H Device version (v0.1) Imanufacturer 00H Index value of string descriptor indicating manufacturer name Iproduct 00H Index value of string descriptor indicating product name IserialNumber 00H Index value of string descriptor indicating product serial number BnumConfigurations 01H There is one configuration. 92CF26A-61 92CF26A-61 2007-11-21 TMP92CF26A TMP92CF26A ConfigrationDescriptor Field Name Value Meaning bLength 09H 9 bytes bDescriptorType 02H Configuration descriptor wTotalLength 0020H 0020H Total length (32 bytes) which each descriptor of both configuration descriptor, interface bNumInterfaces 01H There is one interface. bConfigurationValue 01H Configuration number 1 iConfiguration 00H Index value of string descriptor indicating configuration name (Not in use) and endpoint is added. bmAttributes 80H Bus power MaxPower 31H Maximum power consumption (49 mA) InterfaceDescriptor Field Name Value Meaning bLength 09H 9 bytes bDescriptorType