TLCS-900/H1 TMP92CA25FG TMP92CA25 TMP92CA25FG/JTMP92CA25 900/H1 JTMP92CA25 - Datasheet Archive

 

TLCS-900/H1 Series TMP92CA25FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs.

 

TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 TLCS-900/H1 Series TMP92CA25FG TMP92CA25FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". TMP92CA25 TMP92CA25 CMOS 32-bit Microcontroller TMP92CA25FG/JTMP92CA25 TMP92CA25FG/JTMP92CA25 1. Outline and Device Characteristics The TMP92CA25 TMP92CA25 is a high-speed advanced 32-bit Microcontroller developed for controlling equipment which processes mass data. The TMP92CA25 TMP92CA25 has a high-performance CPU (900/H1 900/H1 CPU) and various built-in I/Os. The TMP92CA25FG TMP92CA25FG is housed in a 144-pin flat package. The JTMP92CA25 JTMP92CA25 is a chip form product. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 900/H1 CPU) · Compatible with TLCS-900/L1 TLCS-900/L1 instruction code · 16 Mbytes of linear address space · General-purpose register and register banks · Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case) (2) Minimum instruction execution time: 50 ns (at fSYS = 20 MHz) RESTRICTIONS ON PRODUCT USE 070208EBP 070208EBP · The information contained herein is subject to change without notice. 021023_D · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B · The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C · The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E · For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S 92CA25-1 92CA25-1 2007-02-28 TMP92CA25 TMP92CA25 (3) Internal memory · Internal RAM: 10 Kbytes (can be used for program, data and display memory) · Internal ROM: 0 Kbytes (used as boot program) (4) External memory expansion · Expandable up to 512 Mbytes (shared program/data area) · Can simultaneously support 8,- 16- or 32-bit width external data bus . dynamic data bus sizing (5) Memory controller · Chip select output: 4 channels (6) 8-bit timers: 4 channels (7) 16-bit timer/event counter: 1 channel (8) General-purpose serial interface: 1 channels · UART/synchronous mode · IrDA ver.1.0 (115 kbps) mode selectable (9) Serial bus interface: 1 channel: 1 channel · I2C bus mode only (10) I2S (Inter-IC sound) interface: 1 channel · I2S bus mode/SIO mode selectable (Master, transmission only) · 32-byte FIFO buffer (11) LCD controller · Supports monochrome for STN · Built-in RAM LCD driver (12) SPI controller · Supported only SPI mode for SD card (13) SDRAM controller: 1 channel · Supports 16 M, 64 M, 128 M, 256 M, and up to 512-Mbit SDR (Single Data Rate)-SDRAM · Supported not only operate as RAM and Data for LCD display but also programming directly from SDRAM (14) Timer for real-time clock (RTC) · Based on TC8521A TC8521A (15) Key-on wakeup (Interrupt key input) (16) 10-bit AD converter (Built-in Sample Hold circuit): 4 channels (17) Touch screen interface · Available to reduce external components (18) Watchdog timer (19) Melody/alarm generator · Melody: Output of clock 4 to 5461 Hz · Alarm: Output of 8 kinds of alarm pattern and 5 kinds of interval interrupt 92CA25-2 92CA25-2 2007-02-28 TMP92CA25 TMP92CA25 (20) MMU · Expandable up to 512 Mbytes (3 local area/8 bank method) · Independent bank for each program, read data, write data and LCD display data (21) Interrupts: 49 interrupt · 9 CPU interrupts: · 34 internal interrupts: Seven selectable priority levels · 7 external interrupts: Seven selectable priority levels (6-edge selectable) Software interrupt instruction and illegal instruction (21) Input/output ports: 84 pins (Except Data bus (16bit), Address bus (24bit) and RD pin) (22) NAND flash interface: 2 channels · Direct NAND flash connection capability · ECC (error detection) calculation (for SLC- type) (23) Stand-by function · Three HALT modes: IDLE2 (programmable), IDLE1, STOP · Each pin status programmable for stand-by mode (24) Triple-clock controller · Clock doubler (PLL) supplies 40 system-clock from external 10MHz oscillator to CPU · Clock gear function: Select high-frequency clock fc to fc/16 · RTC (fs = 32.768 kHz) (25) Operating voltage: · VCC = 3.0 V to 3.6 V (fc max = 40 MHz) · VCC = 2.7 V to 3.6 V (fc max = 27 MHz) (26) Package: · 144-pin QFP (P-LQFP144 P-LQFP144 -1616-0.40C) · 144-pin chip form is also available. For details, contact your local Toshiba sales representative. 92CA25-3 92CA25-3 2007-02-28 TMP92CA25 TMP92CA25 PG0 to PG1 (AN0 to AN1) AN2/MX (PG2) AN3/MY/ ADTRG (PG3) AVCC, AVSS VREFH, VREFL 10-bit 4-channel AD converter (PX, INT4) P96 (PY, INT5) P97 Touch screen I/F (TSI) (TXD0) PF0 (RXD0) PF1 (SCLK0) PF2 Serial I/O SIO0 (I2SCKO, TXD0) P90 (I2SDO, RXD0) P91 (I2SWS, SCLK0) P92 (SDA) P93 (SCL) P94 (CLK32KO CLK32KO) P95 2 IS XWA XBC XDE XHL XIX XIY XIZ XSP PLL W A B C D E H L IX IY IZ SP 32 bits SR H-OSC Clock gear L-OSC RESET Interrupt controller F D0 to D7 Port 1 2 SBI (I Cbus) Watchdog timer MMU 8-bit timer (TIMERA1) (TA3OUT, INT1) PC1 (TB0OUT0, INT2) PC2 (INT3) PC3 Port 7 16-bit timer (TIMERB0) (LCP0) PK0 (LLP) PK1 (LFR) PK2 (LBCD) PK3 PL0 to PL5 (LD0 to LD5) (LD6, BUSRQ ) PL6 (LD7, BUSAK ) PL7 ( SDRAS , SRLLB ) PJ0 ( SDCAS , SRLUB ) PJ1 ( SDWE , SRWR ) PJ2 (SDLLDQM) PJ3 (SDLUDQM) PJ4 (NDALE) PJ5 (NDCLE) PJ6 (SDCKE) PJ7 (SDCLK) PF7 P10 to P17 (D8 to D15) A0 to A7 A8 to A15 Port 6 8-bit timer (TIMERA3) PC4 PC5 PF3 PF4 PF5 PF6 BE XT1 XT2 AM0 AM1 8-bit timer (TIMERA2) (SPDI) PK4 (SPDO) PK5 ( SPCS ) PK6 (SPCLK) PK7 RTCVCC DVCC [3] DVSS [3] X1 X2 PC 8-bit timer (TIMERA0) (TA1OUT, INT0) PC0 900/H1 900/H1 CPU P60 to P67 (A16 to A23) P70 ( RD ) P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) P73 (EA24) P74 (EA25) P75 (R/ W , NDR/ B ) P76 ( WAIT ) NAND flash I/F (2 channel) SPI controller Port C Port 8 Port F LCD controller Port L Keyboard I/F 10-KB 10-KB RAM Port N RTC SDRAM controller Melody/ Alarm out P80 ( CS0 ) P81 ( CS1 , SDCS ) P82 ( CS2 , CSZA ) P83 ( CS3 ) P84 ( CSZB , ND0CE ) P85 ( CSZC , ND1CE ) P86 ( CSZD ) P87 ( CSZE ) PC7 ( CSZF , EA25) PA0 to PA7 (KI0 to KI7) PC6 (KO8,EA24) PN0 to PN7 (KO0 to KO7) PM2 ( ALARM , MLDALM ) PM1 (MLDALM) Figure 1.1 TMP92CA25 TMP92CA25 Block Diagram 92CA25-4 92CA25-4 2007-02-28 TMP92CA25 TMP92CA25 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CA25FG TMP92CA25FG, their names and functions are as follows: 2.1 Pin Assignment 110 115 120 125 130 135 1 105 5 100 10 95 TMP92CA25FG TMP92CA25FG 15 QFP144 QFP144 90 20 Top View 85 25 80 30 75 70 65 60 55 50 P67, A23 P66, A22 P65, A21 P64, A20 DVCC3 P63, A19 P62, A18 P61, A17 P60, A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PF6 PF5 DVSS3 PF4 PF3 PK7, SPCLK PK6, SPCS PK5, SPDO PK4, SPDI PN7, KO7 PN6, KO6 PC3, INT3 DVSS2 DVCC2 D0 D1 D2 D3 D4 D5 D6 D7 P10, D8 P11, D9 P12, D10 P13, D11 P14, D12 P15, D13 P16, D14 P17, D15 PN0, KO0 PN1, KO1 PN2, KO2 PN3, KO3 PN4, KO4 PN5, KO5 RESET 45 PC4 PC5 DVCC1 X1 DVSS1 X2 AM0 AM1 BE 40 35 RTCVCC VREFL VREFH PG0, AN0 PG1, AN1 PG2, AN2, MX PG3, AN3, ADTRG , MY P96, PX, INT4 P97, PY, INT5 PA3, KI3 PA4, KI4 PA5, KI5 PA6, KI6 PA7, KI7 P90, TXD0, I2SCKO P91, RXD0, I2SDO P92, SCLK0, CTS0 , I2SWS P93, SDA P94, SCL P95, CLK32KO CLK32KO PC2, TB0OUT0, INT2 PL0, LD0 PL1, LD1 PL2, LD2 PL3, LD3 PL4, LD4 PL5, LD5 PL6, LD6 PL7, LD7 PK0, LCP0 PK1, LLP PK2, LFR PK3, LBCD PM2, ALARM , MLDALM PM1, MLDALM XT1 XT2 140 AVCC AVSS PA2, KI2 PA1, KI1 PA0, KI0 PJ7, SDCKE PJ6, NDCLE PJ5, NDALE PJ4, SDLUDQM PJ3, SDLLDQM PJ2, SDWE, SRWR PJ1, SDCAS, SRLUB PJ0, SDRAS, SRLLB PF7, SDCLK PC1, TA3OUT, INT1 PC0, TA1OUT, INT0 PF2, SCLK0, CTS0 PF1, RXD0 PF0, TXD0 PC7, CSZF, EA25 P87, CSZE P86, CSZD P85, CSZC, ND1CE P84, CSZB, ND0CE P83, CS3 P82, CS2, CSZA P81, CS1, SDCS PC6, KO8, EA24 P80, CS0 P76, WAIT P75, RW, NDR/B P74, EA25 P73, EA24 P72, WRLU, NDWE P71, WRLL, NDRE P70, RD Figure 2.1.1 shows the pin assignment of the TMP92CA25FG TMP92CA25FG. Figure 2.1.1 Pin Assignment Diagram (144-pin QFP) 92CA25-5 92CA25-5 2007-02-28 TMP92CA25 TMP92CA25 2.2 PAD Assignment (Chip size 4.98 mm × 5.61 mm) Table 2.2.1 Pad Assignment Diagram (144-pin chip) Unit: m Pin No. Name X point Y point Pin No. Name X point Y point Pin No. Name X point Y point 1 VREFL -2363 2309 49 DVSS2 -447 -2678 97 A13 2359 822 2 VREFH -2363 2189 50 DVCC2 -297 -2678 98 A14 2359 939 3 PG0 -2363 1934 51 D0 -172 -2678 99 A15 2359 1055 4 PG1 -2363 1593 52 D1 -72 -2678 100 P60 2359 1171 5 PG2 -2363 1493 53 D2 28 -2678 101 P61 2359 1288 6 PG3 -2363 1393 54 D3 128 -2678 102 P62 2359 1400 7 P96 -2363 1293 55 D4 228 -2678 103 P63 2359 1514 8 P97 -2363 1192 56 D5 328 -2678 104 DVCC3 2359 1643 9 PA3 -2363 1088 57 D6 429 -2678 105 P64 2359 1779 10 PA4 -2363 988 58 D7 529 -2678 106 P65 2359 1902 11 PA5 -2363 888 59 P10 629 -2678 107 P66 2359 2027 12 PA6 -2363 788 60 P11 729 -2678 108 P67 2359 2309 13 PA7 -2363 688 61 P12 829 -2678 109 P70 1994 2675 14 P90 -2363 587 62 P13 929 -2678 110 P71 1874 2675 15 P91 -2363 487 63 P14 1029 -2678 111 P72 1753 2675 16 P92 -2363 387 64 P15 1129 -2678 112 P73 1633 2675 17 P93 -2363 287 65 P16 1229 -2678 113 P74 1527 2675 18 P94 -2363 187 66 P17 1329 -2678 114 P75 1420 2675 19 P95 -2363 87 67 PN0 1429 -2678 115 P76 1316 2675 20 PC2 -2363 -13 68 PN1 1529 -2678 116 P80 1211 2675 21 PL0 -2363 -113 69 PN2 1630 -2678 117 PC6 1104 2675 22 PL1 -2363 -213 70 PN3 1753 -2678 118 P81 999 2675 23 PL2 -2363 -313 71 PN4 1873 -2678 119 P82 893 2675 24 PL3 -2363 -413 72 PN5 1994 -2678 120 P83 787 2675 25 PL4 -2363 -514 73 PN6 2359 -2313 121 P84 682 2675 26 PL5 -2363 -614 74 PN7 2359 -2049 122 P85 574 2675 27 PL6 -2363 -714 75 PK4 2359 -1708 123 P86 468 2675 28 PL7 -2363 -814 76 PK5 2359 -1587 124 P87 363 2675 29 PK0 -2363 -914 77 PK6 2359 -1472 125 PC7 259 2675 30 PK1 -2363 -1014 78 PK7 2359 -1359 126 PF0 154 2675 31 PK2 -2363 -1114 79 PF3 2359 -1243 127 PF1 50 2675 32 PK3 -2363 -1215 80 PF4 2359 -1131 128 PF2 -55 2675 33 PM2 -2363 -1473 81 DVSS3 2359 -1012 129 PC0 -158 2675 34 PM1 -2363 -1594 82 PF5 2359 -885 130 PC1 -261 2675 35 XT1 -2363 -1935 83 PF6 2359 -749 131 PF7 -364 2675 36 XT2 -2363 -2313 84 A0 2359 -639 132 PJ0 -467 2675 37 RTCVCC -1986 -2678 85 A1 2359 -530 133 PJ1 -568 2675 38 BE -1853 -2678 86 A2 2359 -420 134 PJ2 -669 2675 39 PC4 -1732 -2678 87 A3 2359 -311 135 PJ3 -771 2675 40 PC5 -1612 -2678 88 A4 2359 -199 136 PJ4 -872 2675 41 DVCC1 -1499 -2678 89 A5 2359 -88 137 PJ5 -972 2675 42 X1 -1386 -2678 90 A6 2359 23 138 PJ6 -1074 2675 43 DVSS1 -1261 -2678 91 A7 2359 134 139 PJ7 -1175 2675 44 X2 -972 -2678 92 A8 2359 245 140 PA0 -1278 2675 45 AM0 -872 -2678 93 A9 2359 356 141 PA1 -1379 2675 46 AM1 -772 -2678 94 A10 2359 473 142 PA2 -1499 2675 47 RESET -672 -2678 95 A11 2359 589 143 AVSS -1860 2675 48 PC3 -572 -2678 96 A12 2359 705 144 AVCC -1985 2675 92CA25-6 92CA25-6 2007-02-28 TMP92CA25 TMP92CA25 2.3 Pin Names and Functions The following table shows the names and functions of the input/output pins Table 2.3.1 Pin Names and Functions (1/5) Pin Name D0 to D7 P10 to P17 D8 to D15 Number of Pins 8 8 I/O I/O Data: Data bus 0 to 7 I/O Port 1: I/O port input or output specifiable in units of bits I/O Data: Data bus 8 to 15 A0 to A7 8 Output A8 to A15 8 Output P60 to P67 A16 to A23 P70 RD 8 1 WRLL I/O 1 Address: Address bus 0 to 7 Address: Address bus 8 to 15 Port 6: I/O port input or output specifiable in units of bits Output Address: Address bus 16 to 23 Output Port70: Output port Output I/O P71 Function Read: Outputs strobe signal to read external memory Port 71: I/O port Output Write: Output strobe signal for writing data on pins D0 to D7 Output NDRE NAND flash read: Outputs strobe signal to read external NAND flash I/O P72 Write: Output strobe signal for writing data on pins D8 to D15 NDWE Output Write Enable for NAND flash P73 Output Port 73: Output port Output Extended Address 24 Output Port 74: Output port Output Extended Address 25 EA24 P74 EA25 1 Port 72: I/O port Output WRLU 1 1 I/O P75 R/ W 1 Input NDR/ B P76 WAIT Output 1 I/O Input Port 75: I/O port Read/Write: 1 represents read or dummy cycle; 0 represents write cycle NAND flash ready (1)/Busy (0) input Port 76: I/O port Wait: Signal used to request CPU bus wait 92CA25-7 92CA25-7 2007-02-28 TMP92CA25 TMP92CA25 Table 2.3.2 Pin Names and Functions (2/5) Pin Name P80 CS0 Number of Pins Output Output Port80: Output port Chip select 0: Outputs "low" when address is within specified address area 1 Output Output Output Port81: Output port Chip select 1: Outputs "low" when address is within specified address area Chip select for SDRAM: Outputs "0" when address is within SDRAM address area 1 Output Output Output Port82: Output port Chip select 2: Outputs "Low" when address is within specified address area Expand chip select: ZA: Outputs "0" when address is within specified address area 1 Output Output Port83: Output port Chip select 3: Outputs "low" when address is within specified address area 1 Output Output Output Port84: Output port Expand chip select: ZB: Outputs "0" when address is within specified address area Chip select for NAND flash 0: Outputs "0" when NAND flash 0 is enabled 1 Output Output Output Port85: Output port Expand chip select: ZC: Outputs "0" when address is within specified address area Chip select for NAND flash 1: Outputs "0" when NAND flash 1 is enabled 1 Output Output Port86: Output port Expand chip select: ZD: outputs "0" when address is within specified address area 1 Output Output Port87: Output port Expand chip select: ZE: Outputs "0" when address is within specified address area I/O Output Output I/O Input Output I/O I/O Input Output Port90: I/O port Serial 0 send data: Open-drain output programmable 2 I S clock output Port91: I/O port (Schmitt-input) Serial 0 receive data 2 I S data output Port92: I/O port (Schmitt-input) Serial 0 clock I/O Serial 0 data send enable (Clear to send) 2 I S word select output SDCS P82 CS2 CSZA P83 CS3 P84 CSZB ND0CE P85 CSZC ND1CE P86 CSZD P87 CSZE P90 TXD0 I2SCKO P91 RXD0 I2SDO P92 SCLK0 CTS0 I2SWS P93 SDA P94 SCL P95 CLK32KO CLK32KO P96 INT4 PX P97 INT5 PY PA0 to PA7 KI0 to KI7 Function 1 P81 CS1 I/O 1 1 1 1 1 1 1 1 8 I/O Port 93: I/O port I/O I C data I/O I/O Port 94: I/O port I/O I C clock I/O Output Output Input Input Output Input Input Output Input Input 2 2 Port95: Output port Output fs (32.768 kHz) clock Port 96: Input port (Schmitt-input) Interrupt request pin4: Interrupt request with programmable rising/falling edge X-Plus: Pin connectted to X+ for touch screen panel Port 97: Input port (Schmitt-input) Interrupt request pin5: Interrupt request with programmable rising/falling edge Y-Plus: Pin connectted to Y+ for touch screen panel Port: A0 to A7 port: Pin used to input ports (Schmitt input, with pull-up resistor) Key input 0 to 7: Pin used for key-on wakeup 0 to 7 92CA25-8 92CA25-8 2007-02-28 TMP92CA25 TMP92CA25 Table 2.3.3 Pin Names and Functions (3/5) Pin Name Number of Pins I/O 1 Input PC0 INT0 I/O TA1OUT Output PC1 INT1 I/O 1 TA3OUT Output PC2 INT2 I/O 1 TB0OUT0 PC3 INT3 PC4 to PC5 Input Input Output 1 I/O Input Function Port C0: I/O port (Schmitt-input) Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge 8-bit timer 1 output: Timer 1 output Port C1: I/O port (Schmitt-input) Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge 8-bit timer 3 output: Timer 3 output Port C2: I/O port (Schmitt-input) Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge Timer B0 output Port C3: I/O port (Schmitt-input) Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge 2 I/O Port C4 to C5: U/O port I/O Port C6: I/O port 1 Output Key Output 8: Pin used of key-scan strobe (Open-drain output programmable) EA24 Output Extended Address 24 PC7 I/O PC6 KO8 CSZF 1 EA25 PF0 TXD0 PF1 RXD0 Output 1 1 1 SDCLK PG0 to PG1 AN0 to AN1 1 I/O Input Expand chip select: ZF: Outputs "0" when address is within specified address area Extended Address 25 Port F0: I/O port (Schmitt-input) Serial 0 send data: Open-drain output programmable Port F1: I/O port (Schmitt-input) Serial 0 receive data Port F2: I/O port (Schmitt-input) I/O Serial 0 clock I/O Output Output Serial 0 data send enable (Clear to send) Port F7: Output port Clock for SDRAM (When SDRAM is not used, SDCLK can be used as system clock) 1 Input Port G0 to G1 port: Pin used to input ports Input Analog input 0 to 1: Pin used to Input to AD conveter Input 2 PG2 AN2 Output Input CTS0 PF7 I/O Port C7: I/O port I/O PF2 SCLK0 Output Port G2 port: Pin used to input ports Input Analog input 2: Pin used to Input to AD conveter MX Output PG3 Input Port G3 port: Pin used to input ports Input Analog input 3: Pin used to input to AD conveter AN3 MY ADTRG 1 X-Minus: Pin connectted to X- for touch screen panel Output Y-Minus: Pin connectted to Y- for touch screen panel Intput AD trigger: Signal used to request AD start 92CA25-9 92CA25-9 2007-02-28 TMP92CA25 TMP92CA25 Table 2.3.4 Pin Names and Functions (4/5) Pin Name Number of Pins Function Output PJ0 SDRAS I/O 1 Port J0: Output port Output Row address strobe for SDRAM SRLLB Output Data enable for SRAM on pins D0 to D7 PJ1 Output Port J1: Output port Output Column address strobe for SDRAM SRLUB Output Data enable for SRAM on pins D8 to D15 PJ2 Output Port J2: Output port Output Write enable for SDRAM SRWR Output Write for SRAM: Strobe signal for writing data PJ3 Output Port J3: Output port Output Data enable for SDRAM on pins D0 to D7 Output Port J4: Output port Output Data enable for SDRAM on pins D8 to D15 SDCAS SDWE SDLLDQM PJ4 SDLUDQM PJ5 NDALE PJ6 NDCLE PJ7 SDCKE PK0 LCP0 PK1 LLP PK2 LFR PK3 LBCD PK4 SPDI PK5 SPDO PK6 SPCS PK7 SPCLK PL0 to PL3 LD0 to LD3 PL4 to PL5 LD4 to LD5 PL6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 2 1 LD6 I/O Address latch enable for NAND flash Port J6: I/O port Command latch enable for NAND flash Output Port J7: Output port Output Clock enable for SDRAM Output Port K0: Output port Output LCD driver output pin Output Port K1: Output port Output LCD driver output pin Output Port K2: Output port Output LCD driver output pin Output Port K3: Output port Output I/O Input I/O Output I/O Output I/O LCD driver output pin Port K4: I/O port Data input pin for SD card Port K5: I/O port Data output pin for SD card Port K6: I/O port Chip select pin for SD card Port K7: I/O port Output Clock output pin for SD card Output Port L0 to L3: Output port Output I/O Output I/O Input 1 Port J5: I/O port Output Output BUSRQ PL7 I/O Output I/O Data bus for LCD driver Port L4 to L5: I/O port Data bus for LCD driver Port L6: I/O port Data bus for LCD driver Bus request: request pin that set external memory bus to high-impedance (for External DMAC) Port L7: I/O port LD7 Output Data bus for LCD driver BUSAK Output Bus acknowledge: this pin show that external memory bus pin is set to high-impedance by receiving BUSRQ (for External DMAC) 92CA25-10 92CA25-10 2007-02-28 TMP92CA25 TMP92CA25 Table 2.3.5 Pin Names and Functions (5/5) Pin Name PM1 MLDALM Number of Pins 1 Port M1: Output port 8 KO0 to KO7 Output Melody/alarm output pin Port M2: Output port Output RTC alarm output pin Output 1 MLDALM PN0 to PN7 Output Function Output PM2 ALARM I/O Melody/alarm output pin (inverted) I/O Output Port N0 to N7: I/O port Key out pin (Open-drain setting ) Operation mode: Fix to AM1 = "0", AM0 = "1" for 16-bit external bus starting AM0, AM1 2 Input Fix to AM1 = "1", AM0 = "0" for 32-bit external bus starting Fix to AM1 = "1", AM0 = "1" Prohibit setting Fix to AM1 = "0", AM0 = "0" Prohibit setting X1/X2 2 I/O High-frequency oscillator connection pins XT1/XT2 2 I/O RESET 1 Input Reset: Initializes TMP92CA25 TMP92CA25 (with pull-up resistor, Schmitt input) VREFH 1 Input Pin for reference voltage input to AD converter (H) VREFL 1 Input RTCVCC 1 - 1 Input AVCC 1 - Power supply pin for AD converter AVSS 1 - GND pin for AD converter (0 V) DVCC 3 - Power supply pins (All DVCC pins should be connected to the power supply pin) DVSS 3 - GND pins (0 V) (All DVSS pins should be connected to GND (0 V) BE Low-frequency oscillator connection pins Pin for reference voltage input to AD converter (L) Power supply pin for RTC Back up enable pin: When power off DVCC and AVSS during RTC is operating, set to "L" level beforehand. Usually, this pin used to "H" level. (Schmitt input) 92CA25-11 92CA25-11 2007-02-28 TMP92CA25 TMP92CA25 3. Operation This section describes the basic components, functions and operation of the TMP92CA25 TMP92CA25. 3.1 CPU The TMP92CA25 TMP92CA25 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the TLCS-900/L1 TLCS-900/L1 CPU. The TLCS-900/H1 TLCS-900/H1 CPU has an expanded 32-bit internal data bus to process instructions more quickly. The following is an outline of the CPU: Table 3.1.1 TMP92CA25 TMP92CA25 Outline Parameter TMP92CA25 TMP92CA25 Width of CPU address bus 24 bits Width of CPU data bus 32 bits Internal operating frequency Max 20 MHz Minimum bus cycle 1-clock access (50 ns at fSYS = 20MHz) Internal RAM 32-bit 1-clock access INTC, SDRAMC, 8-bit 2-clock access 16-bit 2-clock Internal I/O access 8-bit 56-clock access External SRAM, Masked ROM External SDRAM MEMC, NDFC, TSI, PORT I2S, SPIC, LCDC TMRA, TMRB, SIO, RTC, MLD/ALM, SBI, CGEAR, ADC 8- or 16-bit 2-clock access (waits can be inserted) 16-bit 1-clock access 8-bit 4-clock access External NAND flash (waits can be inserted) Minimum instruction 1-clock (50 ns at fSYS = 20MHz) execution cycle 2-clock (100 ns at fSYS = 20MHz) Conditional jump Instruction queue buffer 12 bytes Compatible with TLCS-900/L1 TLCS-900/L1 Instruction set (LDX instruction is deleted) CPU mode Maximum mode only Micro DMA 8 channels 92CA25-12 92CA25-12 2007-02-28 TMP92CA25 TMP92CA25 3.1.2 Reset Operation When resetting the TMP92CA25 TMP92CA25, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input low for at least 20 system clocks (16 µs at fc = 40 MHz). At reset, since the clock doubler (PLL) is bypassed and the clock-gear is set to 1/16, the system clock operates at 1.25 MHz (fc = 40 MHz). When the reset has been accepted, the CPU performs the following: · Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H FFFF00H to FFFF02H FFFF02H: PC PC PC data in location FFFF00H FFFF00H data in location FFFF01H FFFF01H data in location FFFF02H FFFF02H · Sets the stack pointer (XSP) to 00000000H 00000000H. · Sets bits of the status register (SR) to 111 (thereby setting the interrupt level mask register to level 7). · Clears bits of the status register to 00 (there by selecting register bank 0). When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. · Initializes the internal I/O registers as shown in the "Special Function Register" table in section 5. · Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Internal reset is released as soon as external reset is released. Memory controller operation cannot be ensured until the power supply becomes stable after power-on reset. External RAM data provided before turning on the TMP92CA25 TMP92CA25 may be corrupted because the control signals are unstable until the power supply becomes stable after power on reset. VCC (3.3 V) RESET High-frequency oscillation stabilized time +20 system clock 0 s (Min) Figure 3.1.1 Power on Reset Timing Example 92CA25-13 92CA25-13 2007-02-28 92CA25-14 92CA25-14 P71~P72, P75~P76, P90~P94, P96~P97, PC0~PC3, PC6~PC7, PF0~PF1, PG0~PG3, PJ5~PJ6, PL4~PL7, PA0~PA7 P40~P47,P50~P57 P74~P72, PK0~PK3, PL0~PL3 PF7 PJ3~PJ4, PJ7 PM1~PM2 SRxxB SRWR (Input mode) (Input mode) (Output mode) (Output mode) Note: This chart shows timing for a reset using a 32-bit external bus (AM1:0=10). DATA-OUT DATA-IN Sampling Figure 3.1.2 TMP92CA25 TMP92CA25 Reset Timing Chart 2007-02-28 High-Z Pull up (Internal) fsys×(13.5~14.5) clock (After reset released, starting 1 wait read cycle) DATA-IN 0FFFF00H 0FFFF00H Read WRxx D0D31 D0D31 SRxxB RD D0D31 D0D31 CS2 CS0,1, 3 A23A0 A23A0 RESET fsys TMP92CA25 TMP92CA25 Write TMP92CA25 TMP92CA25 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup Input Pin Operation Mode AM1 AM0 16-bit external bus starting (MULTI 16 mode) 0 1 8-bit external bus starting (MULTI 8 mode) 1 0 Prohibit setting 1 1 Reserve (Toshiba test mode) 0 0 RESET 92CA25-15 92CA25-15 2007-02-28 TMP92CA25 TMP92CA25 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92CA25 TMP92CA25. 000000H 000000H Internal I/O (8 Kbytes) Direct area (n) 000100H 000100H 001D00H 001D00H 002000H 002000H 004800H 004800H 64-Kbyte area (nn) Internal RAM (10 Kbytes) 010000H 010000H External memory F00000H F00000H Provisional emulator control (64 Kbytes) (Note 1) 16-Mbyte area (R) (-R) (R+) (R + R8/16 R8/16) (R + d8/16) (nnn) F10000H F10000H External memory FFFF00H FFFF00H Vector table (256 bytes) (Note 2) FFFFFFH ( = Internal area) Figure 3.2.1 Memory Map Note 1: The Provisional emulator control area, mapped F00000H F00000H to F0FFFFH after reset, is for emulator use and so is not available. When emulator WR signal and RD signal are asserted, this area is accessed. Ensure external memory is used. Note 2: Do not use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved for an emulator. 92CA25-16 92CA25-16 2007-02-28 TMP92CA25 TMP92CA25 3.3 Clock Function and Stand-by Function The TMP92CA25 TMP92CA25 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and (4) noise reduction circuits. They are used for low power, low noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFR 3.3.3 System clock controller 3.3.4 Clock doubler (PLL) 3.3.5 Noise reduction circuits 3.3.6 Stand-by controller 92CA25-17 92CA25-17 2007-02-28 TMP92CA25 TMP92CA25 The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual clock mode (X1, X2, XT1 and XT2 pins) and (c) triple clock mode (X1, X2, XT1 and XT2 pins and PLL). Figure 3.3.1 shows a transition figure. IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt IDLE1 mode (Operate only oscillator) Reset (fOSCH/32) Release reset Instruction NORMAL mode Interrupt Instruction Instruction Interrupt STOP mode (Stops all circuits) Dual clock mode transition figure Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) Interrupt STOP mode (Stops all circuits) Note Instruction Instruction Instruction NORMAL mode (4 × fOSCH/gear value/2) Note Instruction Interrupt Instruction SLOW mode (fs/2) Interrupt Instruction Interrupt Using PLL (c) Note 1: Interrupt SLOW mode (fs/2) Instruction IDLE1 mode Instruction (Operate oscillator and PLL) Interrupt STOP mode (Stops all circuits) (fOSCH/gear value/2) Instruction Interrupt Instruction Interrupt Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Instruction IDLE2 mode (I/O operate) Instruction Interrupt NORMAL mode (fOSCH/gear value/2) Instruction Interrupt Instruction Interrupt (b) IDLE2 mode (I/O operate) Reset (fOSCH/32) Release reset IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Triple clock mode transition figure It is not possible to control PLL in SLOW mode when shifting from SLOW mode to NORMAL mode with use of PLL. (PLL start up/stop/change write to PLLCR0, PLLCR1 register) Note 2: When shifting from NORMAL mode with use of PLL to NORMAL mode, execute the following setting in the same order. 1) Change CPU clock (PLLCR0 "0") 2) Stop PLL circuit (PLLCR1 "0") Note 3: It is not possible to shift from NORMAL mode with use of PLL to STOP mode directly. NORMAL mode should be set once before shifting to STOP mode. (Sstop the high-frequency oscillator after stopping PLL.) Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 is called the clock fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is defined as one state. 92CA25-18 92CA25-18 2007-02-28 TMP92CA25 TMP92CA25 3.3.1 Block Diagram of System Clock SYSCR0 SYSCR2 Warm-up timer (High/low-frequency oscillator) T T0 fFPH Lock up timer (PLL) ÷4 ÷8 SYSCR0 XT1 XT2 fs Low-frequency oscillator PLLCR1, PLLCR0 fs fPLL = fOSCH × 4 X2 Clock doubler (PLL) ÷2 fc/4 Selector fIO SYSCR1 fc/16 ÷2 High-frequency oscillator fOSCH fSYS fc/2 fc/8 SYSCR0 X1 ÷2 fc ÷4 ÷8 ÷16 SYSCR1 Clock-gear PLLCR0 fSYS T0 CPU TMRA0 to 3, TMRB0 LCDC RAM, ROM Memory controller Interrupt controller fIO NAND flash controller Prescaler SIO0 to SIO1 2 IS Prescaler I/O ports SDRAMC I2C bus TSI SPIC Prescaler RTC fs MLD/ALM ADC WDT Figure 3.3.2 Block Diagram of System Clock 92CA25-19 92CA25-19 2007-02-28 TMP92CA25 TMP92CA25 3.3.2 SFR 7 SYSCR0 (10E0H 10E0H) Bit symbol 6 XEN XTEN Read/Write After reset 4 3 2 1 0 1 0 GEAR1 GEAR0 0 0 WUEF R/W R/W 1 1 Highfrequency oscillator (fc) Lowfrequency oscillator (fs) 0: Stop 1: Oscillation Function 5 0 0: Stop 1: Oscillation Warm-up timer 0: Write don't care 1: Write start timer 0: Read end warm-up 1: Read do not end warm-up 7 SYSCR1 (10E1H 10E1H) 6 5 4 3 SYSCK Bit symbol 2 GEAR2 Read/Write R/W After reset 0 Function 1 Select Select gear value of high-frequency (fc) system clock 000: fc 0: fc 001: fc/2 1: fs 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (10E2H 10E2H) Bit symbol - Read/Write 0 5 4 3 2 WUPTM1 WUPTM0 HALTM1 HALTM0 1 0 1 1 R/W After reset 6 Function Always write "0" 1 0 R/W Warm-up timer HALT mode 00: Reserved 00: Reserved 8 01: STOP mode 14 10: IDLE1 mode 16 11: IDLE2 mode 01: 2 /input frequency 10: 2 /input frequency 11: 2 /input frequency Note 1: The unassigned registers, SYSCR0, SYSCR0, SYSCR1, and SYSCR2 are read as undefined value. Note 2: Low-frequency oscillator is enabled on reset. Figure 3.3.3 SFR for System Clock 92CA25-20 92CA25-20 2007-02-28 TMP92CA25 TMP92CA25 7 6 5 4 3 2 1 0 EXTIN DRVOSCH DRVOSCL Bit symbol PROTECT Read/Write R After reset 0 0 1 1 Protect flag 1: External clock fc oscillator driver ability fs oscillator driver ability 1: Normal 1: Normal 0: Weak EMCCR0 (10E3H 10E3H) 0: Weak Function R/W 0: OFF 1: ON EMCCR1 (10E4H 10E4H) Bit symbol Read/Write After reset Function EMCCR2 (10E5H 10E5H) Switch the protect ON/OFF by writing the following to 1st-KEY, 2nd-KEY 1st-KEY: write in sequence EMCCR1 = 5AH, EMCCR2 = A5H Bit symbol 2nd-KEY: write in sequence EMCCR1 = A5H, EMCCR2 = 5AH Read/Write After reset Function Note: When restarting the oscillator from the stop oscillation state (e.g. restarting the oscillator in STOP mode), set EMCCR0, = "1". Figure 3.3.4 SFR for System Clock 92CA25-21 92CA25-21 2007-02-28 TMP92CA25 TMP92CA25 7 5 Bit symbol FCSEL LUPFG Read/Write R/W R After reset PLLCR0 (10E8H 10E8H) 6 0 0 Function Select fc clock 0: fOSCH 3 2 1 0 3 2 1 0 Lock up timer status flag 1: fPLL 4 0: Not end 1: End Note: Ensure that the logic of PLLCR0 is different from 900/L1 900/L1's DFM. 7 PLLCR1 (10E9H 10E9H) 6 Bit symbol 4 PLLON Read/Write 5 R/W After reset Function 0 Control on/off 0: OFF 1: ON Figure 3.3.5 SFR for PLL 7 PxDR (xxxxH) Bit symbol 6 5 4 3 2 1 0 Px7D Px6D Px5D Px4D Px3D Px2D Px1D Px0D 1 1 1 1 1 1 1 1 Read/Write After reset R/W Function Output/input buffer drive-register for stand-by mode (Purpose and use) This register is used to set each pin status at stand-by mode. All ports have registers of the format shown above. ("x" indicates the port name.) For each register, refer to "3.5 Function of ports". Before "Halt" instruction is executed, set each register according to the expected pin-status. They will be effective after the CPU has executed the "Halt" instruction. This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP). The output/input buffer control table is shown below. OE PxnD Output Buffer Input Buffer 0 0 OFF OFF 0 1 OFF ON 1 0 OFF OFF 1 1 ON OFF Note 1: OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note 2: "n" in PxnD denotes the bit number of PORTx. Figure 3.3.6 SFR for Drive Register 92CA25-22 92CA25-22 2007-02-28 TMP92CA25 TMP92CA25 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 changes the system clock to either fc or fs, SYSCR0 and SYSCR0 control enabling and disabling of each oscillator, and SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The combination of settings = 1, = 0 and = 100 will cause the system clock (fSYS) to be set to fc/32 (fc/16 × 1/2) after reset. For example, fSYS is set to 1.25 MHz when the 40 MHz oscillator is connected to the X1 and X2 pins. (1) Switching from normal mode to slow mode When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. The warm-up time can be selected using SYSCR2. This warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2. Table 3.3.1 shows the warm-up time. Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.1 Warm-up Times at fOSCH = 40 MHz, fs = 32.768 kHz Warm-up Time SYSCR2 Change to Normal Mode 8 6.4 (s) 14 409.6 (s) 01 (2 /frequency) 10 (2 /frequency) 16 11 (2 /frequency) 1.638 (ms) 92CA25-23 92CA25-23 Change to Slow Mode 7.8 (ms) 500 (ms) 2000 (ms) 2007-02-28 TMP92CA25 TMP92CA25 Example 1: Setting the clock Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 EQU 10E0H 10E0H SYSCR1 EQU 10E1H 10E1H SYSCR2 EQU 10E2H 10E2H (SYSCR2), 0 X 1 1 - - X X B ; LD 16 Sets warm-up time to 2 /fs. SET ; Enables low-frequency oscillation. 2, (SYSCR0) ; Clears and starts warm-up timer. BIT 2, (SYSCR0) ; JR NZ, WUP ; SET 3, (SYSCR1) ; Changes fSYS from fc to fs. RES WUP: 6, (SYSCR0) SET 7, (SYSCR0) ; Disables high-frequency oscillation. Detects stopping of warm-up timer. X: Don't care, -: No change X1, X2 pins XT1, XT2 pins Warm-up timer Counts up by fSYS Counts up by fs End of warm-up timer fc fs System clock fSYS Clears and starts Enables low-frequency warm-up timer Chages fSYS from fc to fs Disabiles high-frequency End of warm-up timer 92CA25-24 92CA25-24 2007-02-28 TMP92CA25 TMP92CA25 Example 2: Setting the clock Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 EQU 10E0H 10E0H SYSCR1 EQU 10E1H 10E1H SYSCR2 EQU 10E2H 10E2H (SYSCR2), 0 X 1 0 - - X X B ; LD 14 Sets warm-up time to 2 /fc. SET ; Enables high-frequency oscillation. 2, (SYSCR0) ; Clears and starts warm-up timer. BIT 2, (SYSCR0) ; JR NZ, WUP ; RES 3, (SYSCR1) ; Changes fSYS from fs to fc. RES WUP: 7, (SYSCR0) SET 6, (SYSCR0) ; Disables low-frequency oscillation. Detects stopping of warm-up timer. X: Don't care, -: No change X1, X2 pins XT1, XT2 pins Warm-up timer Counts up by fc Counts up by fSYS End of warm-up timer fs fc System Clock fSYS Enables Clears and starts high-frequency warm-up timer Changes fSYS from fs to fc End of warm-up timer 92CA25-25 92CA25-25 Disables low-frequency 2007-02-28 TMP92CA25 TMP92CA25 (2) Clock gear controller fFPH is set according to the contents of the clock gear select register SYSCR1 to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. Example 3: Changing to a high-frequency gear SYSCR1 EQU 10E1H 10E1H LD (SYSCR1), XXXX0000B XXXX0000B ; Changes fSYS to fc/2. LD (DUMMY), 00H ; Dummy instruction X: Don't care (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 register.It is necessary for the warm-up time to elapse before the change occurs after writing the register value. There is the possibility that the instruction following the clock gear changing instruction is executed by the clock gear before changing.To execute the instruction following the clock gear switching instruction by the clock gear after changing, input the dummy instruction as follows (instruction to execute the write cycle). Example: SYSCR1 EQU 10E1H 10E1H LD (SYSCR1), XXXX0001B XXXX0001B ; Changes fSYS to fc/4. LD (DUMMY), 00H ; Dummy instruction Instruction to be executed after clock gear has changed 92CA25-26 92CA25-26 2007-02-28 TMP92CA25 TMP92CA25 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. A low-speed-frequency oscillator can be used, even though the internal clock is high-frequency. A reset initializes PLL to stop status, so setting to PLLCR0, PLLCR1 register is needed before use. As with an oscillator, this circuit requires time to stabilize. This is called the lock up time and it is measured by a 16-stage binary counter. Lock up time is about 1.6 ms at fOSCH = 10 MHz. Note 1: Input frequency range for PLL The input frequency range (High-frequency oscillation) for PLL is as follows: fOSCH = 6 to 10 MHz (VCC = 3.0 to 3.6 V) Note 2: PLLCR0 The logic of PLLCR0 is different from 900/L1 900/L1's DFM. Exercise care in determining the end of lock up time. The following is an example of settings for PLL starting and PLL stopping. Example 1: PLL starting PLLCR0 EQU PLLCR1 EQU LD LUP: 10E8H 10E8H 10E9H 10E9H (PLLCR1), 1 X X X X X X X B ; BIT 5, (PLLCR0) ; JR Z, LUP ; LD (PLLCR0), X 1 X X X X X X B ; Enables PLL operation and starts lock up. Detects end of lock up. Changes fc from 10 MHz to 40 MHz. X: Don't care PLL output: fPLL Lock up timer Counts up by fOSCH During lock up After lock up System clock fSYS Starts PLL operation and starts lock up 92CA25-27 92CA25-27 Changes from 10 MHz to 40 MHz Lock up ends 2007-02-28 TMP92CA25 TMP92CA25 Example 2: PLL stopping PLLCR0 EQU 10E8H 10E8H PLLCR1 EQU 10E9H 10E9H LD (PLLCR0), X0XXXXXXB ; Changes fc from 40 MHz to10 MHz. LD (PLLCR1), 0XXXXXXXB ; Stop PLL. X: Don't care PLL output: fPLL System clock fSYS Changes from 40 MHz to 10 MHz Stops PLL operation 92CA25-28 92CA25-28 2007-02-28 TMP92CA25 TMP92CA25 Limitations on the use of PLL 1. It is not possible to execute PLL enable/disable control in the SLOW mode (fs) (writing to PLLCR0 and PLLCR1). PLL should be controlled in the NORMAL mode. 2. When stopping PLL operation during PLL use, execute the following settings in the same order. LD 3. (PLLCR0), 00H ; Change the clock fPLL to fOSCH LD (PLLCR1), 00H ; PLL stop When stopping the high-frequency oscillator during PLL use, stop PLL before stopping the high-frequency oscillator. Examples of settings are shown below: (1) Start up/change control (OK) Low-frequency oscillator operation mode (fs) (high-frequency oscillator STOP) High-frequency oscillator start up High-frequency oscillator operation mode (fOSCH) PLL start up PLL use mode (fPLL) 1 1 - - - 1 - - B ; LD 2, (SYSCR0) ; NZ, WUP ; LD (SYSCR1), - - - - 0 - - - B ; Change the system clock fs to fOSCH LD (PLLCR1), 1 - - - - - - - B ; PLL start-up/lock up start BIT 5, (PLLCR0) ; JR Z, LUP ; LD LUP: (SYSCR0), BIT JR WUP: (PLLCR0), (OK) High-frequency oscillator start/warm-up start Check for warm-up end flag Check for lock up end flag - 1 - - - - - - B ; Change the system clock fOSCH to fPLL Low-frequency oscillator operation mode (fs) (high-frequency oscillator Operate) High-frequency oscillator operation mode (fOSCH) PLL start up PLL use mode (fPLL) LD - - - - 0 - - - B ; Change the system clock fs to fOSCH (PLLCR1), 1 - - - - - - - B ; PLL start-up/lock up start BIT 5, (PLLCR0) ; JR Z, LUP ; LD LUP: (SYSCR1), LD (PLLCR0), Check for lock up end flag - 1 - - - - - - B ; Change the system clock fOSCH to fPLL (Error) Low-frequency oscillator operation mode (fs) (high-frequency oscillator STOP) High-frequency oscillator start up PLL start up PLL use mode (fPLL) 1 1 - - - 1 - - B ; LD (SYSCR0), BIT 2, (SYSCR0) ; JR WUP: NZ, WUP ; 1 - - - - - - - B ; High-frequency oscillator start/warm-up start Check for warm-up end flag PLL start-up/lock up start LD LUP: (PLLCR1), BIT 5, (PLLCR0) ; JR Z, LUP ; LD (PLLCR0), - 1 - - - - - - B ; Change the internal clock fOSCH to fPLL LD (SYSCR1), - - - - 0 - - - B ; Change the system clock fs to fPLL 92CA25-29 92CA25-29 Check for lock up end flag 2007-02-28 TMP92CA25 TMP92CA25 (2) Change/stop control (OK) PLL use mode (fPLL) High-frequency oscillator operation mode (fOSCH) PLL Stop Low-frequency oscillator operation mode (fs) High-frequency oscillator stop LD (PLLCR0), - 0 - - - - - - B ; LD (PLLCR1), 0 - - - - - - - B ; PLL stop LD (SYSCR1), - - - - 1 - - - B ; Change the system clock fOSCH to fs LD (SYSCR0), 0 - - - - - - - B ; High-frequency oscillator stop Change the system clock fPLL to fOSCH (Error) PLL use mode (fPLL) Low-frequency oscillator operation mode (fs) PLL stop High-frequency oscillator stop LD (SYSCR1), - - - - 1 - - - B ; Change the system clock fPLL to fs LD (PLLCR0), - 0 - - - - - - B ; Change the internal clock (fC) fPLL to fOSCH LD (PLLCR1), 0 - - - - - - - B ; PLL stop LD (SYSCR0), 0 - - - - - - - B ; High-frequency oscillator stop (OK) PLL use mode (fPLL) Set the STOP mode High-frequency oscillator operation mode (fOSCH) PLL stop Halt (High-frequency oscillator stop) LD (SYSCR2), - - - - 0 1 - - B ; Set the STOP mode (This command can be executed before use of PLL) LD (PLLCR0), - 0 - - - - - - B ; Change the system clock fPLL to fOSCH LD (PLLCR1), 0 - - - - - - - B ; ; HALT PLL stop Shift to STOP mode (Error) PLL use mode (fPLL) Set the STOP mode Halt (High-frequency oscillator stop) LD (SYSCR2), - - - - 0 1 - - B ; HALT ; 92CA25-30 92CA25-30 Set the STOP mode (This command can execute before use of PLL) Shift to STOP mode 2007-02-28 TMP92CA25 TMP92CA25 3.3.5 Noise Reduction Circuits Noise reduction circuits are built-in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents When above function is used, set EMCCR0 and EMCCR2 registers (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 X1 pin Enable oscillation Resonator EMCCR0 C2 X2 pin (Setting method) The drive ability of the oscillator is reduced by writing "0" to EMCCR0 register. At reset, is initialized to "1" and the oscillator starts oscillation by normal drivability when the power-supply is on. Note: This function (EMCCR0 = "0") is available when fOSCH = 6 to 10 MHz. 92CA25-31 92CA25-31 2007-02-28 TMP92CA25 TMP92CA25 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Enable oscillation Resonator EMCCR0 C2 fS XT2 pin (Setting method) The drive ability of the oscillator is reduced by writing 0 to the EMCCR0 register. At reset, is initialized to "1". (3) Single drive for high-frequency oscillator (Purpose) Remove the need for twin drives and prevent operational errors caused by noise input to X2 pin when an external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 register. X2 pin's output is always "1". At reset, is initialized to "0". 92CA25-32 92CA25-32 2007-02-28 TMP92CA25 TMP92CA25 (4) Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or by changes to the memory control register (memory controller, MMU) which prevent fetch operations. Runaway error handling is also facilitated by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR, MEMCR0 2. MMU LOCALPX/PY/PZ, LOCALLX/LY/LZ, LOCALRX/RY/RZ, LOCALWX/WY/WZ, 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 4. PLL PLLCR0, PLLCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 registers. (Double key) 1st KEY: writes in sequence, 5AH at EMCCR1 and A5H at EMCCR2 2nd KEY: writes in sequence, A5H at EMCCR1 and 5AH at EMCCR2 Protection state can be confirmed by reading EMCCR0. At reset, protection becomes OFF. INTP0 interruption also occurs when a write operation to the specified SFR is executed with protection in the ON state. 92CA25-33 92CA25-33 2007-02-28 TMP92CA25 TMP92CA25 3.3.6 Stand-by Controller (1) HALT modes and port drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 register and each pin-status is set according to the PxDR register, as shown below: 7 PxDR (xxxxH) 5 4 3 2 1 0 Px7D Px6D Px5D Px4D Px3D Px2D Px1D Px0D 1 Bit symbol 6 1 1 1 1 1 1 1 Read/Write R/W After reset Function Output/input buffer drive register for stand-by mode (Purpose and use) · This register is used to set each pin status at stand-by mode. · All ports have this registers of the format shown above. ("x" indicates the port name.) · For each register, refer to 3.5 function of ports. · Before "Halt" instruction is executed, set each register according to the expected pin status. They will be effective after the CPU has executed the "Halt" instruction. · This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP). · The Output/Input buffer control table is shown below. OE Output Buffer Input Buffer 0 0 OFF OFF 0 1 OFF ON 1 0 OFF OFF 1 Note 1: PxnD 1 ON OFF OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note 2: "n" in PxnD denotes the bit number of PORTx The subsequent actions performed in each mode are as follows: 1. IDLE2: only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. Table 3.3.2 shows the register setting operation during IDLE2 mode. Table 3.3.2 SFR Setting Operation during IDLE2 Mode Internal I/O SFR TMRA01 TMRA01 TA01RUN TA01RUN TMRA23 TMRA23 TA23RUN TA23RUN TMRB0 TB0RUN SIO0 2 SC0MOD1 I C bus SBI0BR0 AD converter ADMOD1 WDT WDMOD 2. IDLE1: Only the oscillator, RTC (real-time clock) and MLD continue to operate. 3. STOP: All internal circuits stop operating. 92CA25-34 92CA25-34 2007-02-28 TMP92CA25 TMP92CA25 The operation of each of the different HALT modes is described in Table 3.3.3. Table 3.3.3 I/O Operation during HALT Modes HALT Mode IDLE2 IDLE1 STOP SYSCR2 11 10 01 CPU Stop I/O ports Depend on PxDR register setting TMRA, TMRB SIO, SBI Block AD converter Available to select operation block Stop WDT I2S, LCDC, SDRAMC, Interrupt controller, USBC, Operate RTC, MLD Operate (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination of the states of the interrupt mask register and the HALT modes. The details for releasing the halt status are shown in Table 3.3.4. · Release by interrupt requesting The HALT mode release method depends on the status of the enabled interrupt .When the interrupt request level set before executing the HALT instruction exceeds the value of the interrupt mask register, the interrupt is processed depending on its status after the HALT mode is released, and the CPU status executing the instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, HALT mode release is not executed. (in non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 to INT4, INTKEY, INTRTC, INTALM and interrupts, even if the interrupt request level set before executing the halt instruction is less than the value of the interrupt mask register, HALT mode release is executed. In this case, the interrupt is processed, and the CPU starts executing the instruction following the HALT instruction, but the interrupt request flag is held at "1". · Release by resetting Release of all halt statuses is executed by resetting. When the STOP mode is released by RESET, it is necessary to allow enough resetting time (see Table 3.3.5) for operation of the oscillator to stabilize. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the HALT instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the HALT instruction is executed.) 92CA25-35 92CA25-35 2007-02-28 TMP92CA25 TMP92CA25 Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Interrupt Enabled HALT Mode Interrupt Disabled (Interrupt level) (Interrupt mask) Status of Received Interrupt (Interrupt level) < (Interrupt mask) IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP × × - - - INT0 to INT4 (Note 1) *1 × *1 INTALM0 to INTALM4 INTTA0 to INTTA3, × × × × × INTRX0 to INTTX0, INTSBI × × × × × INTTBO0, INTI2S × × × × × INTAD, INT5, INTSPI × × × × × INTKEY *1 INTRTC *1 *1 *1 INTLCD Interrupt Source of Halt State Clearance INTWD × × × × × INTTB0 to INTTB1 RESET × Initialize LSI : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from the instruction following the HALT instruction. ×: Cannot be used to release the HALT mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. This combination is not available. *1: Release of the HALT mode is executed after warm-up time has elapsed. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. Example: Releasing IDLE1 mode An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8200H LD (PCFC), 01H ; Sets PC0 to INT0. 8203H 8203H LD (IIMC), 00H ; Selects INT0 interrupt rising edge. 8206H 8206H LD (INTE0AD), 06H ; Sets INT0 interrupt level to 6. 8209H 8209H EI 5 ; Sets interrupt level to 5 for CPU. 820BH 820BH LD (SYSCR2), 28H 820EH 820EH HALT ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 INT0 interrupt routine RETI 820FH 820FH LD XX, XX 92CA25-36 92CA25-36 2007-02-28 TMP92CA25 TMP92CA25 (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release IDLE2 mode Figure 3.3.7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC and MLD continue to operate. The system clock stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.8 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release IDLE1 mode Figure 3.3.8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 92CA25-37 92CA25-37 2007-02-28 TMP92CA25 TMP92CA25 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.9 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release STOP mode Figure 3.3.9 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.5 Example of Warm-up Time after Releasing STOP Mode at fOSCH = 40 MHz, fs = 32.768 kHz SYSCR2 SYSCR1 01 (2 ) 10 (214) 0 (fc) 6.4 s 409.6 s 1.638 ms 1 (fs) 7.8 ms 500 ms 2000 ms 8 92CA25-38 92CA25-38 11 (216) 2007-02-28 TMP92CA25 TMP92CA25 Table 3.3.6 Input Buffer State Table Input Buffer State In HALT mode (IDLE1/2/STOP) Input Function Port Name Name D0~D7 When the CPU is operating During Reset D0~D7 OFF When used as Function pin When used as Input pin ON upon external read = 1 - = 0 When used When used When When used as as used as as Function pin Input pin Function pin Input pin - - OFF OFF P10~P17 D8~D15 P60~P67 - - - - P71~P72 - - - - P75 NDR / B P76 ON ON OFF WAIT - - - P90 - P91 RXD0 P92 CTS0 , SCLK0 P93~P94 1 SDA, SCL P96 * INT4 P97 INT5 1 PA0~PA7* KI0-KI7 PC0 INT2 PC3 OFF INT1 PC2 ON ON ON INT0 PC1 ON ON INT3 PC4~PC7 - PF0 - PF1 OFF RXD0 - - ON CTS0 PF2 ON OFF SCLK0 2 PG0~PG2* PG3 - *2 - OFF ADTRG - ON ON upon port read - ON OFF - ON PJ5~PJ6 - - - - PK4 SPDI ON ON OFF PK5~PK5 - PL4~PL5, PL7 - PL6 BUSRQ PN0~PN7 BE RESET AM0, AM1 X1, XT1 - ON - - - - - ON - ON - ON ON OFF - - - ON - ON - - ON IDLE2/IDLE1:ON, STOP:OFF ON: The buffer is always turned on. A current flows the input buffer if the *1: Port having a pull-up/pull-down resistor. input pin is not driven. *2: AIN input does not cause a current to flow through the buffer. OFF: The buffer is always turned off. -: No applicable 92CA25-39 92CA25-39 2007-02-28 TMP92CA25 TMP92CA25 Table 3.3.7 Output Buffer State Table (1/2) Output Buffer State In HALT mode (IDLE1/2/STOP) When the CPU is operating Port Name Output Function Name D0~D7 During Reset D0~D7 OFF P10~P17 D8~D15 A0~A15 A16~A23 P70 WRLL , NDRE P72 EA24 P74 - - ON OFF - OFF - EA25 P75 - When used as Output pin = 0 When used When used as as Function Output pin pin WRLU , NDWE P73 ON upon external write When used as Function pin RD P71 When used as Output pin A16~A15, P60~P67 When used as Function pin = 1 R/W P76 CS3 P84 - - OFF - CSZC , ND1CE P86 ON CSZB , ND0CE P85 ON CS2 , CSZA P83 OFF CS1 , SDCS P82 ON CS0 P81 - - P80 ON CSZD P87 CSZE P90 ON ON OFF ON TXD0, I2SCKO P91 I2SWS P93 SCL P95 CLK32KO CLK32KO P96 PX P97 PY OFF SDA P94 ON I2SDO P92 ON ON: The buffer is always turned on. OFF ON OFF - - - *1: Port having a pull-up/pull-down resistor. OFF: The buffer is always turned off. -: Not applicable 92CA25-40 92CA25-40 2007-02-28 TMP92CA25 TMP92CA25 Table 3.3.8 Output Buffer State Table (2/2) Output Buffer State In HALT mode (IDLE1/2/STOP) When the CPU is operating Port Name Output Function Name PC0 TA3OUT PC2 When used as Function pin When used as Output pin = 1 When used as Function pin When used as Output pin = 0 When used When used as as Function Output pin pin TA1OUT PC1 During Reset TB0OUT0 PC3 KO8, EA24 PC7 CSZF , EA25 PF0 ON OFF - - PC6 ON - - TXD0 PF1 ON - PF2 OFF ON ON PF7 SDCLK MX PG3 OFF SDWE , SRWR PJ3 SDLLDQM PJ4 NDALE PJ6 NDCLE PJ7 SDCKE PK0 - SDLUDQM PJ5 - SDCAS , SRLUB PJ2 - OFF SDRAS SRLLB PJ1 - ON MY PJ0 - OFF SCLK0 PG2 - ON LCP PK1 LLP PK2 ON ON OFF OFF ON LFR PK3 ON LBCD PK4 - PK5 SPDO PK6 SPCS PK7 LD0~LD3 PL4~PL6 LD4~LD6 PL7 MLDALM PM2 MLDALM , ALARM PN0~PN7 KO0~KO7 X2 - XT2 - - - OFF LD7, BUSAK PM1 ON SPCLK PL0~PL3 ON - OFF ON OFF ON OFF IDLE2/1:ON, ON ON: The buffer is always turned on. - - STOP: output "H" IDLE2/1:ON, STOP: output "HZ" *1: Port having a pull-up/pull-down resistor. OFF: The buffer is always turned off. -: Not applicable 92CA25-41 92CA25-41 2007-02-28 TMP92CA25 TMP92CA25 3.4 Interrupts Interrupts are controlled by the CPU Interrupt mask register (bits12 to 14 of the status register) and by the built-in interrupt controller. The TMP92CA25 TMP92CA25 has a total of 49 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources Software interrupts: 8 sources Illegal instruction interrupt: 1 source Internal interrupts: 33 sources Internal I/O interrupts: 25 sources Micro DMA transfer end interrupts: 8 sources External interrupts: 7 sources Interrupts on external pins (INT0 to INT5, INTKEY) A fixed individual interrupt vector number is assigned to each interrupt source. Any one of six levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU interrupt mask register . If the priority level of the interrupt is greater than or equal to the value in the interrupt mask register, the CPU accepts the interrupt. However, software interrupts and illegal instruction interrupts generated by the CPU are processed irrespective of the value in . The value in the interrupt mask register can be changed using the EI instruction (EI num sets to num). For example, the command EI 3 enables the acceptance of all non-maskable interrupts and of maskable interrupts whose priority level, as set in the interrupt controller, is 3 or higher. The commands EI and EI 0 enable the acceptance of all non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence both are equivalent to the command EI 1). The DI instruction (sets to 7) is exactly equivalent to the EI 7 instruction. The DI instruction is used to disable all maskable interrupts (since the priority level for maskable interrupts ranges from 1 to 6). The EI instruction takes effect as soon as it is executed. In addition to the general purpose interrupt processing mode described above, there is also a micro DMA processing mode. In micro DMA mode the CPU automatically transfers data in one-byte, two-byte or four-byte blocks; this mode allows high-speed data transfer to and from internal and external memory and internal I/O ports. In addition, the TMP92CA25 TMP92CA25 also has a software start function in which micro DMA processing is requested in software rather than by an interrupt. Figure 3.4.1 is a flowchart showing overall interrupt processing. 92CA25-42 92CA25-42 2007-02-28 TMP92CA25 TMP92CA25 Micro DMA soft start request Interrupt processing Interrupt specified by micro DMA start vector ? YES Clear interrupt request flag NO Interrupt vector calue "V" read interrupt request F/F clear Data transfer by micro DMA Micro DMA processing General-purpose interrupt processing PUSH PC PUSH SR SR Level of accepted interrupt + 1 INTNEST INTNEST + 1 COUNT COUNT - 1 COUNT = 0 YES NO Clear vector register generating micro DMA transfer end interrupt (INTTC0 to 7) PC (FFFF00H FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 92CA25-43 92CA25-43 2007-02-28 TMP92CA25 TMP92CA25 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4) and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level has been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: the smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (pointed to by XSP). (3) The CPU sets the value of the CPU's interrupt mask register to the priority level for the accepted interrupt plus 1. However, if the priority level for the accepted interrupt is 7, the register's value is set to 7. (4) The CPU increments the interrupt nesting counter INTNEST by 1. (5) The CPU jumps to the address given by adding the contents of address FFFF00H FFFF00H + the interrupt vector, then starts the interrupt processing routine. On completion of interrupt processing, the RETI instruction is used to return control to the main routine. RETI restores the contents of the program counter and the status register from the stack and decrements the interrupt nesting counter INTNEST by 1. Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request is received for an interrupt with a priority level equal to or greater than the value set in the CPU interrupt mask register , the CPU will accept the interrupt. The CPU interrupt mask register is then set to the value of the priority level for the accepted interrupt plus 1. If during interrupt processing, an interrupt is generated with a higher priority than the interrupt currently being processed, or if, during the processing of a non-maskable interrupt processing, a non-maskable interrupt request is generated from another source, the CPU will suspend the routine which it is currently executing and accept the new interrupt. When processing of the new interrupt has been completed, the CPU will resume processing of the suspended interrupt. If the CPU receives another interrupt request while performing processing steps (1) to (5), the new interrupt will be sampled immediately after execution of the first instruction of its interrupt processing routine. Specifying DI as the start instruction disables nesting of maskable interrupts. A reset initializes the interrupt mask register to 111, disabling all maskable interrupts. Table 3.4.1 shows the TMP92CA25 TMP92CA25 interrupt vectors and micro DMA start vectors. FFFF00H FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area. 92CA25-44 92CA25-44 2007-02-28 TMP92CA25 TMP92CA25 Table 3.4.1 TMP92CA25 TMP92CA25 Interrupt Vectors and Micro DMA Start Vectors Default Priority Type Interrupt Source and Source of Micro DMA Request Vector Value Micro Address Refer DMA Start to Vector Vector 1 Reset or [SWI0] instruction 0000H 0000H FFFF00H FFFF00H 2 [SWI1] instruction 0004H 0004H FFFF04H FFFF04H 3 Illegal instruction or [SWI2] instruction 0008H 0008H FFFF08H FFFF08H 4 [SWI3] instruction 000CH 000CH FFFF0CH 5 Non- [SWI4] instruction 0010H 0010H FFFF10H FFFF10H 6 maskable [SWI5] instruction 0014H 0014H FFFF14H FFFF14H 7 [SWI6] instruction 0018H 0018H FFFF18H FFFF18H 8 [SWI7] instruction 001CH 001CH FFFF1CH 9 (Reserved) 0020H 0020H FFFF20H FFFF20H 10 INTWD: Watchdog Timer 0024H 0024H FFFF24H FFFF24H - Micro DMA - - - (Note1) 11 INT0: INT0 pin input 0028H 0028H FFFF28H FFFF28H 0AH (Note 2) 12 INT1: INT1 pin input 002CH 002CH FFFF2CH 0BH 13 INT2: INT2 pin input 0030H 0030H FFFF30H FFFF30H 0CH 14 INT3: INT3 pin input 0034H 0034H FFFF34H FFFF34H 0DH 15 INT4: INT4 pin input (TSI) 0038H 0038H FFFF38H FFFF38H 0EH 16 INTALM0: ALM0 (8192 Hz) 003CH 003CH FFFF3CH 0FH 17 INTALM1: ALM1 (512 Hz) 0040H 0040H FFFF40H FFFF40H 10H 18 INTALM2: ALM2 (64 Hz) 0044H 0044H FFFF44H FFFF44H 11H 19 INTALM3: ALM3 (2 Hz) 0048H 0048H FFFF48H FFFF48H 12H 20 INTALM4: ALM4 (1 Hz) 004CH 004CH FFFF4CH 13H 21 INTP0: Protect0 (Write to special SFR) 0050H 0050H FFFF50H FFFF50H 14H 22 (Reserved) 0054H 0054H FFFF54H FFFF54H 15H 23 INTTA0: 8-bit timer 0 0058H 0058H FFFF58H FFFF58H 16H 24 INTTA1: 8-bit timer 1 005CH 005CH FFFF5CH 17H 25 INTTA2: 8-bit timer 2 0060H 0060H FFFF60H FFFF60H 18H 26 INTTA3: 8-bit timer 3 0064H 0064H FFFF64H FFFF64H 19H 27 INTTB0: 16-bit timer 0 0068H 0068H FFFF68H FFFF68H 1AH 28 INTTB1: 16-bit timer 0 006CH 006CH FFFF6CH 1BH INTKEY: Key-on wakeup 0070H 0070H FFFF70H FFFF70H 1CH INTRTC: RTC (Alarm interrupt) 0074H 0074H FFFF74H FFFF74H 1DH 1EH 29 30 Maskable 31 INTTBO0: 16-bit timer 0 (Overflow) 0078H 0078H FFFF78H FFFF78H 32 INTLCD: LCDC/LP pin 007CH 007CH FFFF7CH 1FH 33 INTRX0: Serial receive (Channel 0) 0080H 0080H FFFF80H FFFF80H 20H (Note 2) 34 INTTX0: Serial transmission (Channel 0) 0084H 0084H FFFF84H FFFF84H 21H 35 (Reserved) 0088H 0088H FFFF88H FFFF88H 22H (Note 2) 36 (Reserved) 008CH 008CH FFFF8CH 23H 37 (Reserved) 0090H 0090H FFFF90H FFFF90H 24H 38 (Reserved) 0094H 0094H FFFF94H FFFF94H 25H 39 INT5: INT5 pin input 0098H 0098H FFFF98H FFFF98H 26H 2 40 INTI2S: I S (Channel 0) 009CH 009CH FFFF9CH 27H 41 INTNDF0 (NAND flash controller channel 0) 00A0H 00A0H FFFFA0H 28H 42 INTNDF1 (NAND flash controller channel 1) 00A4H 00A4H FFFFA4H 29H 43 INTSPI: SPIC 00A8H 00A8H FFFFA8H 2AH 44 INTSBI: SBI 00ACH 00ACH FFFFACH 2BH 45 (Reserved) 00B0H 00B0H FFFFB0H 2CH 46 (Reserved) 00B4H 00B4H FFFFB4H 2DH 47 (Reserved) 00B8H 00B8H FFFFB8H 2EH 48 (Reserved) 00BCH 00BCH FFFFBCH 2FH 49 (Reserved) 00C0H 00C0H FFFFC0H 30H 50 (Reserved) 00C4H 00C4H FFFFC4H 31H 92CA25-45 92CA25-45 2007-02-28 TMP92CA25 TMP92CA25 Default Priority Type Interrupt Source and Source of Micro DMA Request Vector Value Micro Address Refer DMA Start to Vector Vector 51 (Reserved) 00C8H 00C8H FFFFC8H 32H 52 INTAD: AD conversion end 00CCH 00CCH FFFFCCH 33H 53 INTTC0: Micro DMA end (Channel 0) 00D0H 00D0H FFFFD0H 34H 54 INTTC1: Micro DMA end (Channel 1) 00D4H 00D4H FFFFD4H 35H 55 INTTC2: Micro DMA end (Channel 2) 00D8H 00D8H FFFFD8H 36H INTTC3: Micro DMA end (Channel 3) 00DCH 00DCH FFFFDCH 37H INTTC4: Micro DMA end (Channel 4) 00E0H 00E0H FFFFE0H 38H 58 INTTC5: Micro DMA end (Channel 5) 00E4H 00E4H FFFFE4H 39H 59 INTTC6: Micro DMA end (Channel 6) 00E8H 00E8H FFFFE8H 3AH 60 INTTC7: Micro DMA end (Channel 7) 00ECH 00ECH FFFFECH 3BH 00F0H 00F0H FFFFF0H - : : to 00FCH 00FCH FFFFFCH - 56 57 Maskable - to (Reserved) - Note 1: Micro DMA default priority. Micro DMA initiation takes priority over other maskable interrupts. Note 2: When initiating micro DMA, set at edge detect mode. 92CA25-46 92CA25-46 2007-02-28 TMP92CA25 TMP92CA25 3.4.2 Micro DMA Processing In addition to general purpose interrupt processing, the TMP92CA25 TMP92CA25 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source. Because the micro DMA function is implemented through the CPU, when the CPU is placed in a stand-by state by a Halt instruction, the requirements of the micro DMA will be ignored (pending). Micro DMA supports 8 channels and can be transferred continuously by specifying the micro DMA burst function as below. Note: When using the micro DMA transfer end interrupt, always write "1" to bit 7 of SIMC register. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to eight types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte, two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: the lower the channel number, the higher the priority (channel 0 thus has the highest priority and channel 7 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (i.e., interrupt requests should be disabled). If micro DMA and general purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. (Note) In this case, edge triggered interrupts are the only kinds of general interrupts which can be accepted. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 92CA25-47 92CA25-47 2007-02-28 TMP92CA25 TMP92CA25 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from memory to memory, from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (1), detailed description of the transfer mode register. Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (provided that the transfer counter for the source is initially set to 0000H 0000H). Micro DMA processing can be initiated by any one of 34 different interrupts ­ the 33 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode (micro DMA transfers are the same in every mode except counter mode). (The conditions for this cycle are as follows: Both source and destination memory are internal RAM and multiples by 4 numbered source and destination addresses.) 1 state (1) (2) (3) (4) src (5) dst fSYS A23 to A0 Note: In fact, src and dst address are not output to A23 to A0 pins because they are internal RAM address. Figure 3.4.2 Timing for Micro DMA Cycle State (1), (2): Instruction fetch cycle (Prefetches the next instruction code) State (3): Micro DMA read cycle State (4): Micro DMA write cycle State (5): (The same as in state (1), (2) 92CA25-48 92CA25-48 2007-02-28 TMP92CA25 TMP92CA25 (2) Soft start function The TMP92CA25 TMP92CA25 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. (If write "0" to each bit, micro DMA doesn't operate). On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. Only one channel can be set for DMA request at once. (Do not write "1" to plural bits.) When writing again 1 to the DMAR register, check whether the bit is "0" before writing "1". If read "1", micro DMA transfer isn't started yet. When a burst is specified by the DMAB register, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is 0. If execatee soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writign to other bits by mistake. Symbol DMAR Name Address 109H DMA Request (Prohibit RMW) 7 6 5 4 3 DREQ7 DREQ6 DREQ5 DREQ4 2 1 0 DREQ3 DREQ2 DREQ1 DREQ0 0 0 0 R/W 0 0 0 0 0 1: DMA request in software (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr, r can be used to set these registers. Channel 0 DMAS0 DMA source address register 0 DMAD0 DMA destination address register 0 DMAC0 DMAM0 DMA counter register 0 DMA mode register 0 Channel 7 DMAS7 DMA source address register 7 DMAD7 DMA destination address register 7 DMAC7 DMAM7 DMA counter register 7 DMA mode register 7 8 bits 16 bits 32 bits 92CA25-49 92CA25-49 2007-02-28 TMP92CA25 TMP92CA25 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAMn[4:0] 000zz 001zz 010zz 011zz 100zz 101zz 110zz 11100 ZZ: DMAM0 to DMAM7 Mode Description Destination INC mode (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn Destination DEC mode (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source INC mode (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source DEC mode (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source and destination INC mode (DMADn+) (DMASn+) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source and destination DEC mode (DMADn-) (DMASn-) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source and destination Fixed mode (DMADn) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTCn Counter mode DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INTTCn Execution State Number 5 states 5 states 5 states 5 states 6 states 6 states 5 states 5 states 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (Reserved) Note1: N stands for the micro DMA channel number (0 to 7) DMADn+/DMASn+: Post-increment (register value is incremented after transfer) DMADn-/DMASn-: Post-decrement (register value is decremented after transfer) "I/O" signifies fixed memory addresses; "memory" signifies incremented or decremented memory addresses. Note2: The transfer mode register should not be set to any value other than those listed above. Note3: The execution state number shows number of best case (1-state memory access). 92CA25-50 92CA25-50 2007-02-28 TMP92CA25 TMP92CA25 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left hand side of the diagram shows the interrupt controller circuit. The right hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 52 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing a micro DMA start vector to the INTCLR register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12 INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupt (watchdog timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bit of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt's vector address to the CPU. The CPU compares the mask value set in of the status register (SR) with the priority level of the requested interrupt; if the latter is higher, the interrupt is accepted. Then the CPU sets SR to the priority level of the accepted interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests with a priority value equal to or higher than the value set in SR (e.g., interrupts with a priority higher than the interrupt being processed) will be accepted. When interrupt processing has been completed (e.g., after execution of a RETI instruction), the CPU restores to SR the priority value which was saved on the stack before the interrupt was generated. The interrupt controller also includes eight registers which are used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (see Table 3.4.1), enables the corresponding interrupts to be processed by micro DMA processing. The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD) prior to micro DMA processing. 92CA25-51 92CA25-51 2007-02-28 92CA25-52 92CA25-52 Micro DMA counter 0 interrupt INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 INT1 INT2 INT3 INT4 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INT0 INTWD RESET D5 D4 D3 D2 D1 D0 Dn + 3 Interrupt request F/F C B A Y1 Y2 Y3 Y4 Y5 Y6 Decoder INTTC0 D Q CLR 6 51 Selector S V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH 6 V = 20H V = 24H DMA0V DMA1V : DMA7V Soft start Interrupt vector read Micro DMA acknowledge S Q R Interrupt request F/F D Q CLR Micro DMA start vector setting register Reset Dn + 2 Dn + 1 Dn Q Priority setting register RESET interrupt vector read S R Interrupt request F/F Interrupt controller 8 1 7 0 1 2 3 4 5 6 7 A B C D2 D3 D4 D5 D6 D7 D0 D1 3 INTRQ2 to 0 3 Interrupt vector read Interrupt vector generator 8 input OR 45 1 A 2 Highest priority B 3 interrupt 4 level select C 5 6 7 Micro DMA channel priority decoder 6 1 Interrupt request Priority encoder signal to CPU Interrupt level detect 3 if IFF = 7 then 0 Micro DMA channel specification Micro DMA request INT01 INT01 to INT4, INTKEY,INTRTC, INTALM RESET Halt release During IDLE1 During STOP Interrupt request signal EI 1 to 7 DI RESET If INTRQ2 to 0 IFF 2 to 0 then 1. 3 3 IFF2 to 0 Interrupt mask F/F CPU TMP92CA25 TMP92CA25 Figure 3.4.3 Block Diagram of Interrupt Controller 2007-02-28 TMP92CA25 TMP92CA25 (1) Interrupt level setting registers Symbol INTE0AD Name INT0 & INTAD Address 7 6 5 IADC IADM2 F0H & 0 & D0H I2C & D1H I4C II2SC & D4H ITA1C INTTA3 0 0 INTTB1 D5H 0 0 II2SM1 0 0 0 II2SM0 I5C 0 0 ITA1M1 ITA3M2 0 ITA3M1 R 0 0 0 ITB1M2 ITA1M0 ITA0C 0 ITB1M1 R 0 - R/W 0 0 0 R/W enable 0 ITA0M2 0 0 0 ITA3M0 ITA2C ITA2M2 INTSPI enable E0H ITX1C - 0 0 0 0 ITB1M0 ITB0C ITB0M2 0 E5H enable 0 0 enable E6H IA1C IA1M2 - ITBO0C 0 ITX0M0 IRX0C 0 0 0 0 0 ITBO0M1 ITBO0M2 ITBO0M0 R/W 0 0 0 IRX0M1 IRX0M2 R ITX1M0 0 R - 0 IA1M1 IA1M0 IRX0M0 R/W 0 0 0 - - - Note: Always write 0 INTALM0 R/W 0 IA3C IA3M2 R 0 ITB0M0 R/W IA0C IA0M2 R 0 0 0 0 IA3M1 IA3M0 IA2C IA2M2 IA0M0 0 0 IA2M1 IA2M0 INTALM2 R/W 0 IA0M1 R/W INTALM3 INTEALM23 INTEALM23 ITB0M1 R - ITX1M1 0 0 INTALM2 & INTALM3 0 INTTB0 (TMRB0) INTALM1 INTEALM01 INTEALM01 ITA2M0 R/W R/W 0 INTALM0 & INTALM1 ITA2M1 R R/W ITX1M2 0 INTRX0 ITX0M1 0 R ITA0M0 INTTA2 (TMRA2) INTTX1 INTESPI ITA0M1 INTTBO0 - R 0 0 R/W 0 R/W ITX0M2 I5M0 0 R ITX0C 0 I5M1 I5M2 INTTX0 DBH I3M0 0 - DAH I3M1 I3M2 R INTTB1 (TMRB1) D8H 0 INTTA0 (TMRA0) R/W ITB1C I1M0 R/W R R/W ITA3C I1M1 I1M2 R Note: Always write 0 & 0 I3C R/W ITA1M2 0 INT5 0 INTRX0 INTTX0 I1C I4M0 enable INTES0 0 R R/W 0 0 INTTBO0 (Overflow) I2M0 INTTA3 (TMRA3) enable INTETBO0 I4M1 0 INTTB0 INTETB01 INTETB01 0 INT3 I4M2 0 enable & I2M1 R INTTA2 INTETA23 INTETA23 0 INTTA1 (TMRA1) enable & 0 R/W R 0 I0M0 R/W INT1 I2M2 II2SM2 I0M1 R INTI2S EBH 0 INT0 0 R 0 INTTA0 INTTA1 I0M2 INT4 enable INTETA01 INTETA01 I0C 0 INT5 INTI2S IADM0 R 0 enable INTE5I2S IADM1 R/W INT3 INT4 1 INT2 enable INTE34 INTE34 2 R INT1 INT2 3 INTAD enable INTE12 INTE12 4 0 92CA25-53 92CA25-53 R 0 0 R/W 0 0 0 2007-02-28 TMP92CA25 TMP92CA25 Symbol Name Address 7 6 - 5 - 4 3 2 - - IA4C IA4M2 - INTEALM4 INTALM4 enable E7H enable E8H 0 0 - IRC - IRM2 enable E9H - 0 0 - - - IKC enable EAH - INTEND01 INTEND01 INTNDF1 R/W - - IN1M2 - ILCD1C 0 IN1M0 R/W 0 0 INTP0 - - ILCDM2 EEH ILCDM1 ILCDM0 R/W 0 IN0C 0 0 IN0M2 IN0M1 IN0M0 R R/W 0 0 0 0 - - IP0C IP0M2 - enable 0 INTNDF0 IN1M1 R enable INTEP0 0 INTLCD R IN1C IKM0 0 INTNDF1 ECH 0 IKM1 R 0 Note: Always write 0 INTNDF0 & 0 IKM2 - INTLCD IRM0 R/W INTKEY Note: Always write 0 INTELCD 0 IRM1 R - INTKEY 0 INTRTC - Note: Always write 0 INTEKEY IA4M0 R/W - INTERTC IA4M1 R - 0 INTALM4 Note: Always write 0 INTRTC 1 0 0 IP0M1 IP0M0 INTP0 R Note: Always write 0 0 R/W 0 0 0 lxxM2 lxxM0 0 0 0 1 Disables interrupt requests Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 Interrupt request flag lxxM1 0 0 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests 92CA25-54 92CA25-54 Function (Write) 2007-02-28 TMP92CA25 TMP92CA25 Symbol Name INTETC01 INTETC01 INTTC0 & INTTC1 enable INTETC23 INTETC23 INTETC45 INTETC45 INTTC2 & INTTC3 enable INTTC4 & INTTC5 enable Address 7 6 5 ITC1C ITC1M2 4 3 2 ITC1M0 ITC0C ITC0M2 INTTC1 (DMA1) F1H 0 R/W 0 ITC3C 0 ITC3M2 0 0 0 ITC3M0 0 ITC2C R/W 0 ITC5C 0 ITC5M2 0 0 INTTC6 & INTTC7 F4H enable ITC7C ITC5M0 ITC4C 0 ITC4M2 0 ITC7M0 ITC6C INTWD enable F7H - 0 0 0 ITC6M1 R 0 - ITC4M0 0 ITC6M2 ITC6M0 R/W 0 0 0 - - - - - - - INTWDT ITC4M1 R/W 0 R/W 0 0 INTTC6 (DMA6) ITC7M1 R 0 ITC2M0 0 R 0 ITC7M2 ITC2M1 0 INTTC7 (DMA7) INTETC67 INTETC67 ITC2M2 R/W 0 R/W 0 0 INTTC4 (DMA4) ITC5M1 R 0 R INTTC5 (DMA5) F3H ITC0M0 R/W INTTC2 (DMA2) ITC3M1 R ITC0M1 R INTTC3 (DMA3) F2H 0 INTTC0 (DMA0) ITC1M1 R 1 INTWD - - ITCWD R Note: Always write 0 0 lxxM2 lxxM0 0 0 0 0 0 1 Disables interrupt requests Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 Interrupt request flag lxxM1 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests 92CA25-55 92CA25-55 Function (Write) 2007-02-28 TMP92CA25 TMP92CA25 (2) External interrupt control Symbol Name Address 7 6 5 I5EDGE I4EDGE 4 I3EDGE 3 2 1 I2EDGE I1EDGE I0EDGE I0LE W IIMC Interrupt input mode control 0 0 0 0 - R/W 0 0 0 0 0 F6H INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0: INT0 (Prohibit edge 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising RMW) mode 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: INT0 level mode Always write "0" *INT0 level enable 0 Edge detect INT 1 "H" level INT Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense. Setting example: DI LD LD NOP NOP NOP EI (IIMC), XXXXXX00B XXXXXX00B ; Switches from level to edge. (INTCLR), 0AH ; Clears interrupt request flag. ; Wait EI execution X: Don't care, -: No change. Note 2: See electrical characteristics in section 4 for external interrupt input pulse width. Settings of External Interrupt Pin Function Interrupt Pin Name Mode Setting Method Rising edge = 0 = 1 Rising edge = 0 Falling edge = 1 Rising edge = 0 Falling edge = 1 Rising edge INT5 = 1 Falling edge INT4 = 0 Rising edge INT3 = 1 Falling edge INT2 = 0, = 1 Rising edge INT1 PC0 Falling edge High level INT0 = 0, = 0 = 0 Falling edge