TLCS-900/L1 TMP91PW10 TMP91PW10F TMP91CU10 000000H 000080H 001080H FE0000H - Datasheet Archive

 

TLCS-900/L1 TMP91PW10 16 TLCS-900/L1 TMP91PW10 LSI IDLE1 STOP (IDLE2 ) CPU fFPH 5 ( NMI , INT0) () TMP91PW10 / CMOS 16

 

CMOS 16 TLCS-900/L1 TLCS-900/L1 TMP91PW10 TMP91PW10 16 TLCS-900/L1 TLCS-900/L1 TMP91PW10 TMP91PW10 LSI IDLE1 STOP (IDLE2 ) CPU fFPH 5 ( NMI , INT0) () TMP91PW10 TMP91PW10 / CMOS 16 TMP91PW10F TMP91PW10F 1. TMP91PW10 TMP91PW10 128 K PROM TMP91CU10 TMP91CU10 LSI EPROM / TMP91PW10 TMP91PW10 ROM TMP91CU10 TMP91CU10 PROM TMP91CU10 TMP91CU10 TMP91PW10 TMP91PW10 000000H 000000H I/O 000080H 000080H RAM (4 K ) 001080H 001080H FE0000H FE0000H ROM 128 K FFFF00H FFFF00H (256 ) = ) FFFFFFH TMP91PW10 TMP91PW10 ROM RAM TMP91PW10F TMP91PW10F OTP 128 K 4 K 100-LQFP 100-LQFP BM11129 BM11129 000629TBP1 000629TBP1 · / 1.3 · · ( ) ( ) ( "" ) · · · 91PW10-1 91PW10-1 2003-03-31 TMP91PW10 TMP91PW10 AN0~AN7 (P50~P57) AVcc AVss VREFL VREFH CPU (TLCS-900/L1 TLCS-900/L1) 10 BIT 8CH AD CONVERTER TXD0 (P90) RXD0 (P91) SCLK0/ CTS0 (P92) SERIAL I/O (CH.0) TXD1 (P93) RXD1 (P94) SCLK1 (P95) XWA XBC XDE XHL XIX XIY XIZ XSP W A B C D E H L IX IY IZ SP 32 bit SR F PC OSC1 Clock Gear OSC2 SERIAL I/O (CH.1) TXD2 (P60) RXD2 (P61) SCLK2/ CTS2 (P62) WATCH-DOG TIMER SERIAL I/O (CH.2) 8 BIT TIMER (TIMER 0) TO1 (P71) PORT 0 8 BIT TIMER (TIMER 2) PORT 1 (P10~P17) AD8/A8~AD15/A15 AD15/A15 (P20~P27) A0/A16 A0/A16~A7/A23 A7/A23 PORT A 4 KB RAM (P00~P07) AD0~AD7 PORT 2 8 BIT TIMER (TIMER 1) PA0~PA7 P63P65 P63P65~P67 8BIT TIMER (TIMER 3) TI4/INT3 (P73) TO5 (P74) 8 BIT TIMER (TIMER 5) CS/WAIT CONTROLLER (3-BLOCK) 8 BIT TIMER (TIMER 4) 128 KB ROM INTERRUPT CONTROLLER 8 BIT TIMER (TIMER 6) TO7/INT4 (P75) XT1 (P96) XT2 (P97) CLK ALE EA RESET RD (P30) WR (P31) HWR (P32) BUSRQ (P34) BUSAK (P35) R/ W (P36) AM8/ 16 P37 PORT 6 TI0/INT1 (P70) TO3/INT2 (P72) DVcc [3] DVss [3] X1 X2 16 BIT TIMER (TIMER 8) 8 BIT TIMER (TIMER 7) 16 BIT TIMER (TIMER 9) ( (P40) CS0 (P41) CS1 (P42) CS2 WAIT (P33) NMI INT0 (P64) TI8/INT5 (P80) TI9/INT6 (P81) TO8 (P82) TO9 (P83) TIA/INT7 (P84) TIB/INT8 (P85) TOA/TOB (P86) ): 1.1 TMPU91PW10F TMPU91PW10F 91PW10-2 91PW10-2 2003-03-31 TMP91PW10 TMP91PW10 2. TMP91PW10 TMP91PW10 2.1 TMP91PW10F TMP91PW10F 2.1.1 88 P65 P66 89 87 P64/INT0 P64/INT0 P67 90 86 P63 DVSS 91 85 P62/SCLK2/ P62/SCLK2/ CTS2 P50/AN0 P50/AN0 92 84 P61/RXD2 P61/RXD2 P51/AN1 P51/AN1 93 83 P60/TXD2 P60/TXD2 P52/AN2 P52/AN2 94 82 P42/ CS2 P53/AN3 P53/AN3 95 81 P41/ CS1 P54/AN4 P54/AN4 96 80 P40/ CS0 P55/AN5 P55/AN5 97 79 P37 P56/AN6 P56/AN6 98 78 P57/AN7 P57/AN7 99 77 P36/ R / W P35/ BUSAK VREFH 100 76 P34/ BUSRQ VREFL 1 75 P33/ WAIT AVSS 2 74 P32/ HWR AVCC 3 73 P31/ WR P70/TI0/INT1 P70/TI0/INT1 4 72 P30/ RD P71/TO1 P71/TO1 5 71 P27/A7/A23 P27/A7/A23 P72/TO3/INT2 P72/TO3/INT2 6 70 P26/A6/A22 P26/A6/A22 P73/TI4/INT3 P73/TI4/INT3 7 69 P25/A5/A21 P25/A5/A21 P74/TO5 P74/TO5 8 68 P24/A4/A20 P24/A4/A20 P75/TO7/INT4 P75/TO7/INT4 9 67 P23/A3/A19 P23/A3/A19 P80/TI8/INT5 P80/TI8/INT5 10 66 P22/A2/A18 P22/A2/A18 P81/TI9/INT6 P81/TI9/INT6 11 65 P21/A1/A17 P21/A1/A17 P82/TO8 P82/TO8 12 64 P20/A0/A16 P20/A0/A16 P83/TO9 P83/TO9 13 63 DVCC P84/TIA/INT7 P84/TIA/INT7 14 62 DVSS P85/TIB/INT8 P85/TIB/INT8 15 61 P86/TOA/TOB P86/TOA/TOB 16 60 NMI P17/AD15/A15 P17/AD15/A15 P90/TXD0 P90/TXD0 17 59 P16/AD14/A14 P16/AD14/A14 P91/RXD0 P91/RXD0 18 58 P15/AD13/A13 P15/AD13/A13 P92/SCLK0/ P92/SCLK0/ CTS0 19 57 P14/AD12/A12 P14/AD12/A12 P93/TDX1 P93/TDX1 20 56 P13/AD11/A11 P13/AD11/A11 P94/RDX1 P94/RDX1 21 55 P12/AD10/A10 P12/AD10/A10 P95/SCLK1 P95/SCLK1 22 54 P11/AD9/A9 P11/AD9/A9 AM8/ 16 23 53 P10/AD8/A8 P10/AD8/A8 CLK 24 52 P07/AD7 P07/AD7 DVCC 25 51 P06/AD6 P06/AD6 DVSS 26 50 P05/AD5 P05/AD5 X1 27 49 P04/AD4 P04/AD4 X2 28 48 P03/AD3 P03/AD3 EA 29 47 P02/AD2 P02/AD2 RESET 30 46 P01/AD1 P01/AD1 P96/XT1 P96/XT1 31 45 P00/AD0 P00/AD0 P97/XT2 P97/XT2 32 44 DVCC TEST1 33 43 ALE TEST2 34 42 PA7 PA0 35 41 PA6 PA1 36 40 PA5 PA2 37 39 PA4 38 PA3 2.1.1 91PW10-3 91PW10-3 2003-03-31 TMP91PW10 TMP91PW10 2.2 2.2.1 2.2.1 (1/3) P00~P07 AD0~AD7 8 0: (): / 0~7 P10~P17 AD8~AD15 A8~A15 8 1: (): / 8~15 : 8~15 P20~P27 A0~A7 A16~A23 8 2: ( ) : 0~7 : 16~23 P30 1 30: : (P3 = 0 P3FC = 1 1 1 32: () : D8~15 1 33: () : CPU 1 : D0~15A0~23 RD WR HWR CS0 CS1 CS2 RD RD P31 WR P32 HWR P33 WAIT P34 BUSRQ 31: : D0~7 34: () ( DMAC ) 1 P35 BUSAK 35: () : BUSRQ D0~15A0~23 RD WR HWR CS0 CS1 CS2 ( DMAC ) 1 P36 R/W 36: () /: "1" "0" 1 37: 40: () 0: "0" 1 41: () 1: "0" 1 P40 1 P37 42: () 2: "0" 8 CS0 P41 CS1 P42 CS2 P50~P57 AN0~AN7 () 5: : AD BUSRQ BUSAK DMA I/O 91PW10-4 91PW10-4 2003-03-31 TMP91PW10 TMP91PW10 2.2.1 (2/3) P60 TXD2 1 60: 2 P61 RXD2 1 61: 2 P62 SCLK2 1 62: 2 2 (Clear To Send) CTS2 P63 1 63: P64 INT0 1 64: 0: / P65~P67 3 65~67: P70 TI0 INT1 1 70: 0: 0 1: P71 TO1 1 71: 1: 0 1 P72 TO3 INT2 1 72: 3: 2 3 2: P73 TI4 INT3 1 74: 4: 4 3: P74 TO5 1 75: 5: 4 5 P75 TO7 INT4 1 76: 7: 6 7 4: P80 TI8 INT5 1 80: 8: 8 / 5: P81 TI9 INT6 1 81: 9: 8 / 6: P82 TO8 1 82: 8: 8 P83 TO9 1 83: 9: 9 P84 TIA INT7 1 84: A: 9 / 7: P85 TIB INT8 1 85: B: 9 / 8: P86 TOA TOB 1 86: A: A B: B 91PW10-5 91PW10-5 2003-03-31 TMP91PW10 TMP91PW10 2.2.1 (3/3) P90 TXD0 1 90: 0 P91 RXD0 1 91: 0 P92 SCLK0 1 92: 0 0 (Clear To Send) P93 TXD1 1 93: 1 P94 RXD1 1 94: 1 P95 SCLK1 1 95: 1 P96 XT1 1 96: () P97 XT2 1 97: () PA0~PA7 3 A0~A7: () ALE 1 () NMI 1 : CLK 1 : X 1 ÷ 4 CTS0 EA 1 TMP91PW10 TMP91PW10 Vcc AM8/ 16 1 : Vcc / 1 RESET 1 : LSI () VREFH 1 AD () VREFL 1 AD () AVCC 1 AVSS 1 X1/X2 2 TEST1/TEST2 2 / DVCC 3 DVSS 3 GND (0 V) () AD AD GND (0 V) TEST1 TEST2 RESET / 91PW10-6 91PW10-6 2003-03-31 TMP91PW10 TMP91PW10 PROM A7~A0 8 A15~A8 8 A16 1 8 CE 1 (MCU P27~P20 P17~P10 / P07~P00 P32 D7~D0 P33 OE 1 P30 PGM 1 P31 VPP 1 12.75 V/5 V () EA VCC 4 6.25 V/5 V VCCAVCC VSS 4 0V VSSAVSS P34 1 RESET 1 CLK 1 ALE 1 X1 1 X2 1 7 2 / 48 () (PROM ) P42~P40 P37~P35 AM8/ 16 TEST1TEST2 P57~P50 P67~P60 P75~P70 P86~P80 P97~P90 PA7~PA0 VREFH VREFL 91PW10-7 91PW10-7 2003-03-31 TMP91PW10 TMP91PW10 3. TMP91PW10 TMP91PW10 TMP91PW10 TMP91PW10 TMP91CU10 TMP91CU10 ROM PROM TMP91CU10 TMP91CU10 TMP91CU10 TMP91CU10 MCU PROM 3.1 MCU (1) CLK () MCU MCU TMP91CU10 TMP91CU10 3.2 TMP91PW10 TMP91PW10 000000H 000000H 00000H 00000H I/O 000080H 000080H RAM 001080H 001080H PROM (128 K ) FE0000H FE0000H PROM (128 K ) 1FFFFH FFFF00H FFFF00H FFFFFFH 3.2.1 MCU 91PW10-8 91PW10-8 3.2.2 PROM 2003-03-31 TMP91PW10 TMP91PW10 4. 4.1 "X" SYSCR1 (TMP91PW10F TMP91PW10F) fFPH "X" fc = 1/fc (SYSCR1 = "0000") Vcc -0.5~6.5 V VIN -0.5~Vcc + 0.5 V () IOL 120 mA () IOH -80 mA (Ta = 85°C) PD 600 mW (10 s) TSOLDER 260 °C TSTG -65~150 °C TOPR -40~85 °C 1 () 4.2 DC (1/2) Min Vcc fc = 4~13.5 MHz fs = 30~34 kHz (Ta = -40~85°C) AD0~15 VIL Vcc 2.7 V Port2~A (exceptP87P5) VIL1 Input Low Voltage VIL2 EA AM8/ 16 VIL3 X1Port5 Input High Voltage RESET NMI INT0 AD0~15 Port2~A (exceptP87) V 0.8 0.3 Vcc -0.3 VIL4 VIH Typ. ( 1) Max 3.6 2.7 Power Supply Voltage AVcc = DVcc AVss = DVss = 0 V Vcc = 2.7~3.6 V 0.25 Vcc 0.3 0.2 Vcc Vcc 2.7 V 2.2 VIH1 0.7 Vcc RESET NMI INT0 VIH2 0.75 Vcc EA AM8/ 16 VIH3 X1 VIH4 V Output Low Voltage VOL VOH2 Darlington Drive Current (8 Output Pins max) IDAR ( 2) Vcc = 2.7~3.6 V Vcc + 0.3 Vcc - 0.3 0.8 Vcc IOL = 1.6 mA 0.45 (Vcc = 2.7~3.6 V) IOH = -400 µA (Vcc = 3 V ± 10%) VEXT = 1.5 V REXT = 1.1 k (Vcc = 3 V ± 10%) V 2.4 -1.0 -3.5 Input Leakage Current ILI 0.0 VIN Vcc 0.02 ±5 Output Leakage Current ILO 0.2 VIN Vcc - 0.2 0.05 ±10 mA µA ( 1) Typ. Ta = 25°CVcc = 3 V ( 2) IDAR 8 IDAR 91PW10-13 91PW10-13 2003-03-31 TMP91PW10 TMP91PW10 4.2 DC (2/2) Power Down Voltage (@STOPRAM Back up) VSTOP RESET Pull Up Resister RRST Pin Capacitance Schmitt Width RESET NMI INT0 CIO Min VIL2 = 0.2 Vcc Typ. ( 1) Max VIH2 = 0.8 Vcc 2.0 3.6 V Vcc = 3 V ± 10% 30 250 k 10 pF fc = 1 MHz VTH 0.4 1.0 V Programmable PKL Vcc = 3 V ± 10% 30 200 Programmable PKH Vcc = 3 V ± 10% 80 300 NORMAL ( 2) 14 23 10 17 6 11 IDLE1 1.1 2.8 SLOW ( 2) 40 55 32 45 18 35 k Vcc = 3 V ± 10% fc = 13.5 MHz (Typ. Vcc = 3.0 V) RUN IDLE2 RUM IDLE2 Icc Vcc = 3 V ± 10% fs = 32.768 kHz (Typ. Vcc = 3.0 V) 6 IDLE1 STOP Ta 50°C Ta 70°C Ta 85°C Vcc = 2.7~3.6 V mA µA 20 10 0.2 20 µA 50 ( 1) Typ. Ta = 25°CVcc = 3 V ( 2) Icc NORMAL : 91PW10-14 91PW10-14 2003-03-31 TMP91PW10 TMP91PW10 4.3 AC (1) Vcc = 3.0 V ± 10% V No. 13.5 MHz Min Max 31250 Min Max 1 (= x) tOSC 74 74 ns 2 CLK tCLK 2x - 40 108 ns 3 A0-23 A0-23 CLK tAK 0.5x - 30 7 ns 4 CLK A0-23 A0-23 tKA 1.5x - 85 26 ns 5 A0-15 A0-15 ALE tAL 0.5x - 34 30 ns 6 ALE A0-15 A0-15 tLA 0.5x - 30 7 ns 7 ALE High tLL x - 50 24 ns 8 ALE RD / WR tLC 0.5x - 27 10 ns 9 RD / WR ALE tCL 0.5x - 30 7 ns 10 A0-15 A0-15 RD / WR tACL x - 40 34 ns 11 A0-23 A0-23 RD / WR tACH 1.5x - 50 61 ns 12 RD / WR A0-23 A0-23 tCA 0.5x - 37 13 A0-15 A0-15 D0-15 D0-15 tADL 3.0x - 55 182 ns 14 A0-23 A0-23 D0-15 D0-15 tADH 3.5x - 65 194 ns 15 RD D0-15 D0-15 tRD 103 ns 16 RD Low tRR 2.0x - 40 108 ns 17 RD D0-15 D0-15 tHR 0 0 ns 18 RD A0-15 A0-15 tRAE x - 20 54 ns 19 WR Low tWW 2.0x - 40 108 ns 20 D0-15 D0-15 WR tDW 2.0x - 80 68 ns 21 WR D0-15 D0-15 tWD 0.5x - 32 5 ns 22 A0-23 A0-23 WAIT [1WAIT + n ] tAWH 23 A0-15 A0-15 WAIT [1WAIT + n ] tAWL 24 RD / WR WAIT [1WAIT + n ] tCW 25 A0-23 A0-23 PORT tAPH 26 A0-23 A0-23 PORT tAPH2 27 A0-23 A0-23 PORT tAP 0 2.0x - 45 3.5x - 60 199 ns 162 3.0x - 60 2.0x + 0 ns ns 148 2.5x - 120 2.5x + 50 ns 65 ns 359 ns 235 3.5x + 100 ns AC · : High 0.7 × Vcc /Low 0.3 × Vcc · : High 0.9 × Vcc /Low 0.1 × Vcc 91PW10-15 91PW10-15 , CL = 50 pF 2003-03-31 TMP91PW10 TMP91PW10 (1) tOSC X1 tCLK CLK tKA tAK A0~23 CS0 ~ 2 R/ W tAWH tAWL tCW WAIT tAPH tAPH2 Port Input tADH RD tCA tRR tACH tRAE tACL tLC tRD tHR tADL AD0~15 A0~15 tAL ALE D0~15 tLA tCL tLL 91PW10-16 91PW10-16 2003-03-31 TMP91PW10 TMP91PW10 (2) X1 CLK A0~23 CS0 ~ 2 R/W WAIT Port Output tWW WR HWR tDW AD0~15 A0~15 tWD D0~15 ALE 91PW10-17 91PW10-17 2003-03-31 TMP91PW10 TMP91PW10 4.4 AD AVcc = VccAVss = Vss Min Typ. Max (+) VREFH Vcc - 0.2 V Vcc Vcc (-) VREFL Vss Vss Vss + 0.2 V VAIN Vcc = 3 V ± 10% = 1 Vcc = 3 V ± 10% = 0 () VREFL IREF (VREFL = 0 V) - V VREFH 0.5 1.5 mA 0.02 5.0 µA ±1 ±3 LSB ( 1) 1LSB = (VREFH - VREFL)/1024 [V] ( 2) AD fc () (fs ) fc 4 MHz ( 3) AVcc : Icc 91PW10-18 91PW10-18 2003-03-31 TMP91PW10 TMP91PW10 4.5 (1) I/O SCLK Min SCLK Min Max 1.18 µs 91.5 µs 172 ns 152 µs 270 ns 0 0 0 ns tHSR SCLK / * Data Max 5x - 100 tOHS SCLK / * Input Data Min 16x tOSS SCLK / * Output Data Max 13.5 MHz 488 µs tSCY Output Data SCLK / * 32.768 kHz ) tSRD tSCY/2 - 5x - 50 tSCY - 5x - 100 336 µs 714 ns ) fs fs *) SCLK /.SCLK SCLK SCLK SCLK SCLK 32.768 kHz ) 13.5 MHz Min Max Min Max Min 8192x 488 µs 250 ms 1.18 606.2 Max SCLK () tSCY 16x Output Data SCLK tOSS tSCY - 2x - 150 427 µs 886 ns SCLK Output Data tOHS 2x - 80 60 µs 68 ns SCLK Input Data tHSR 0 0 0 ns SCLK Data tSRD ) tSCY - 2x - 150 428 µs 886 µs ns fs fs SCLK tSCY / SCLK () OUTPUT DATA TxD tOSS tOHS 0 1 2 tSRD INPUT DATA RxD 3 tHSR 0 1 2 3 VALID VALID VALID VALID 91PW10-19 91PW10-19 2003-03-31 TMP91PW10 TMP91PW10 4.6 (TI0, TI4, TI8, TI9, TIA, TIB) Variable Min 13.5 MHz Max Min Max tVCK 8X + 100 692 ns tVCKL 4X + 40 336 ns tVCKH 4X + 40 336 ns 4.7 (1) NMI INT0 Variable Min 13.5 MHz Max Min Max NMI INT0~4 tINTAL 4X 296 ns NMI INT0~4 tINTAH 4X 296 ns (2) INT5~8 INT4~7 CPU (9 ) tINTBL tINTBH (INT5~8 ) (INT5~8 ) Variable 13.5 MHz Variable 13.5 MHz Min Min Min Min 00 (fFPH) 1 (fs) ( 2) 8X + 100 692 8X + 100 692 01 (fs) 8XT + 0.1 244.3 8XT + 0.1 244.3 10 (fc/16) 0 (fc) 128X + 0.1 9.572 128X + 0.1 9.572 8XT + 0.1 244.3 8XT + 0.1 244.3 00 (fFPH) 01 (fs) ns µs ( 1) XT fs fs = 32.768 [kHz] ( 2) fs fc/16 tSCH SCOUT tSCL 91PW10-20 91PW10-20 2003-03-31 TMP91PW10 TMP91PW10 4.8 / ( 1) CLK tBRC tBRC tCBAL BUSRQ tCBAH BUSAK tABA tBAA ( 2) AD0~AD15, A0~A23, CS0 ~ CS2 , R / W ( 2) RD, WR , HWR ALE Variable Min 13.5 MHz Max Min Max CLK BUSRQ tBRC CLK BUSAK tCBAL 1.5x + 120 231 ns CLK BUSAK tCBAH 0.5x + 40 77 ns BUSAK BUSAK ( 1) 120 120 ns tABA 0 80 0 80 ns tBAA 0 80 0 80 ns BUSRQ "0" ( 2) OFF (CR ) / 91PW10-21 91PW10-21 2003-03-31 TMP91PW10 TMP91PW10 4.9 PROM DC AC Ta = 25 ± 5°C Vcc = 5 V ± 10% Min Max VPP 4.5 5.5 V Input High Voltage (A0~A16 CE OE PGM ) VIH1 2.2 VCC + 0.3 V Input Low Voltage (A0~A16 CE OE PGM ) VIL1 -0.3 0.8 V Address to Output Delay tACC CL = 50 pF 2.25TCYC 25TCYC + ns VPP Read Voltage TCYC = 400 ns (10 MHz Clock) = 200 ns 4.10 PROM DC AC Ta = 25 ± 5°C Vcc = 6.25 V ± 0.25 V Min Typ Max 12.75 13.00 VCC + V V Programing Supply Voltage Input High Voltage (D0~D7 A0~A16 CE OE PGM ) R5 VIH 12.50 2.6 Input Low Voltage (D0~D7A0~A16 CE OE PGM ) VIL -0.3 0.8 V 0.3 VCC Supply Current ICC fc = 10 MHz 50 mA VPP Supply Current IPP VPP = 13.00 50 mA 0.105 ms V PGM Program Pulse Width tPW CL = 50 pF 91PW10-22 91PW10-22 0.095 0.1 2003-03-31 TMP91PW10 TMP91PW10 4.11 PROM A0-A16 A0-A16 CE OE PGM tACC D0~D7 91PW10-23 91PW10-23 2003-03-31 TMP91PW10 TMP91PW10 4.12 PROM A0-A16 A0-A16 CE OE D0~D7 UNKNOWN tPW PGM VPP ) 1. VPP (12.75 V) Vcc 2. VPP = 12.75 V 3. VPP 14 V 14 V 91PW10-24 91PW10-24 2003-03-31