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TLCS-870/C TMP86FS49BUG 86CH49 86CM49 86PM49 86CS49 86FS49 86FS49B 86FS49A - Datasheet Archive
TLCS-870/C Series TMP86FS49BUG The information contained herein is subject to change without notice. 021023_D TOSHIBA is
8 Bit Microcontroller TLCS-870/C TLCS-870/C Series TMP86FS49BUG TMP86FS49BUG The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S © 2007 TOSHIBA CORPORATION All Rights Reserved TMP86FS49BUG TMP86FS49BUG Differences among Products Differences in Functions 86CH49 86CH49 86CM49 86CM49 86PM49 86PM49 86CS49 86CS49 86FS49 86FS49 ROM 16 Kbytes (Mask) 32 Kbytes (Mask) 32 Kbytes (OTP) 60 Kbytes (Mask) RAM 512 bytes 1 Kbyte 1 Kbyte 2 Kbytes 86FS49B 86FS49B 60 Kbytes (Flash) 2 Kbytes 128 bytes (Flash control register not contained) DBR(note1) 86FS49A 86FS49A 128 bytes (Flash control register contained) I/O 56 pins High-current port 13 pins (sink open drain) Interrupt External: 5 interrupts, Internal: 19 interrupts Timer/counter 16-bit: 2 channels 8-bit: 4 channels UART 2 channels SIO 2 channels I2C 1 channel Key-on wake-up 4 channels 10-bit AD converter (note2) 16 channels Flash Security N.A. VDD Structurer of TEST pin R RIN without protect diode on the VDD side R without pull down resister Absolute Maximum Rating of Power supply(VDD) VDD R RIN without protect diode on the VDD side R VDD R without pull down resister without pull down resister 6.5V Emulation chip Package Read/Write protect Read protect without protect diode on the VDD side R without pull down resister 6.0V TMP86C949XB TMP86C949XB QFP64P-14140 QFP64P-14140.80A QFP64-P-1414-0 QFP64-P-1414-0.80A LQFP64-P-1010-0 LQFP64-P-1010-0.50D SDIP64-P-750-1 SDIP64-P-750-1.78 QFP64-P-1414-0 QFP64-P-1414-0.80A LQFP64-P-1010-0 LQFP64-P-1010-0.50D Note 1: The products with Flash memory (86FS49 86FS49, 86FS49A 86FS49A, 86FS49B 86FS49B) contain the Flash control register (FLSCR) at 0FFFH in the DBR area. The products with mask ROM or OTP and the emulation chip do not have the FLSCR register. In these devices, therefore, a program that accesses the FLSCR register cannot function properly (executes differently as in the case of a Flash product). Note 2: In this data sheet,the following pin names and register names have been changed from the data sheet of the old edition. Although the names have been changed, their functions remain the same. TMP86FS49BUG TMP86FS49BUG OLD name NEW name AD Converter analog input pin name P60(AIN00 AIN00) P61(AIN01 AIN01) P62(AIN02 AIN02) P63(AIN03 AIN03) P64(AIN04 AIN04) P65(AIN05 AIN05) P66(AIN06 AIN06) P67(AIN07 AIN07) P70(AIN10 AIN10) P71(AIN11 AIN11) P72(AIN12 AIN12) P73(AIN13 AIN13) P74(AIN14 AIN14) P75(AIN15 AIN15) P76(AIN16 AIN16) P77(AIN17 AIN17) P60(AIN0) P61(AIN1) P62(AIN2) P63(AIN3) P64(AIN4) P65(AIN5) P66(AIN6) P67(AIN7) P70(AIN8) P71(AIN9) P72(AIN10 AIN10) P73(AIN11 AIN11) P74(AIN12 AIN12) P75(AIN13 AIN13) P76(AIN14 AIN14) P77(AIN15 AIN15) ADCCR1 register function name 0000:AIN00 AIN00 0001:AIN01 AIN01 0010:AIN02 AIN02 0011:AIN03 AIN03 0100:AIN04 AIN04 0101:AIN05 AIN05 0110:AIN06 AIN06 0111:AIN07 AIN07 1000:AIN10 AIN10 1001:AIN11 AIN11 1010:AIN12 AIN12 1011:AIN13 AIN13 1100:AIN14 AIN14 1101:AIN15 AIN15 1110:AIN16 AIN16 1111:AIN17 AIN17 0000:AIN0 0001:AIN1 0010:AIN2 0011:AIN3 0100:AIN4 0101:AIN5 0110:AIN6 0111:AIN7 1000:AIN8 1001:AIN9 1010:AIN10 AIN10 1011:AIN11 AIN11 1100:AIN12 AIN12 1101:AIN13 AIN13 1110:AIN14 AIN14 1111:AIN15 AIN15 TMP86FS49BUG TMP86FS49BUG Differences in Electrical Characteristics 86CH49 86CH49 86CM49 86CM49 86PM49 86PM49 86CS49 86CS49 86FS49 86FS49 [V] [V] [V] 5.5 5.5 86FS49A 86FS49A 5.5 86FS49B 86FS49B [V] [V] 5.5 5.5 (a) 3.6 4.5 16 [MHz] (a) 1.8V to 5.5V (-40 to 85°C) (a) 3.6 3.0 2.7 1.8 4.5 1.8 (b) 3.0 2.7 (Note 1) 1 4.2 8 16 [MHz] (a) 2.0V to 5.5V (-40 to 85°C) (b) 1.8V to 2.0V (-20 to 85°C) 1 4.2 8 16 [MHz] 1.8 (a) 4.5V to 5.5V (-40 to 85°C) (b) 3.0V to 3.6V (-40 to 85°C) 1 4.2 8 0.030 0.034 8 (a) 3.6 0.030 0.034 4.2 4.5 (Note 3) (b) 0.030 0.034 1 (b) 3.0 2.7 3.0 2.7 2.0 1.8 1.8 (Note 2) 3.6 (a) 0.030 0.034 (a) 3.0 2.7 0.030 0.034 Read / Fetch 4.5 3.6 16 [MHz] (a) 3.0V to 5.5V (-40 to 85°C) (b) 2.7V to 3.0V (-20 to 85°C) 1 4.2 8 16 [MHz] (a) 2.7V to 5.5V (-40 to 85°C) [V] 5.5 (a) 4.5 3.6 - - 3.0 2.7 1.8 0.030 0.034 Erase / Program Operating condition (MCU mode) 4.5 - - 1 4.2 8 16 [MHz] (a) 4.5V to 5.5V (-10 to 40°C) [V] 5.5 (a) 3.6 - - 1.8 Operating Current 3.0 2.7 0.030 0.034 Operating condition (Serial PROM mode) 4.5 - 2 4.2 8 16 [MHz] (a) 4.5V to 5.5V (-10 to 40°C) Operating current varies with each product. For details, refer to the datasheet (electrical characteristics) of each product. (Note 5) (Note 4) Note 1: With the 86CS49 86CS49, the operating temperature (Topr) is -20 °C to 85 °C when the supply voltage VDD is less than 2.0 V. Note 2: With the 86FS49 86FS49, the supply voltage VDD is specified as two separate ranges. While the MCU is operating, do not change the supply voltage from range (a) to range (b) or from range (b) to range (a). Note 3: With the 86FS49A 86FS49A, the operating temperature (Topr) is -20 °C to 85 °C when the supply voltage VDD is less than 3.0 V. Note 4: With the 86FS49A/B 86FS49A/B, when a program is executing in the Flash memory or when data is being read from the Flash memory, the Flash memory operates in an intermittent manner causing peak currents in the Flash memory momentarily, as shown in Figure. In this case, the supply current IDD (in NORMAL1, NORMAL2 and SLOW1 modes) is defined as the sum of the average peak current and MCU current. Note 5: About the measurement condition of supply current, VIL level of TEST pin is deffrent between 86FS49B 86FS49B and the other 86xx49 series MCUs. The supply current is defined as follows; VIL of TEST pin : VIL 0.1V (86FS49B 86FS49B), VIL 0.2V (others) It is described in the section "Electrical characteristics" of TMP86FS49B TMP86FS49B in detail. 1 machine cycle (4/fc or 4/fs) n Program counter (PC) n+1 n+2 n+3 Momentary Flash current I DDP-P [mA] Max. current Sum of average momentary Typ. current Flash current and MCU current MCU current Intermittent Operation of Flash Memory TMP86FS49BUG TMP86FS49BUG Revision History Date Revision 2007/8/28 1 First Release 2008/8/29 2 Contents Revised Caution in Setting the UART Noise Rejection Time When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The combination "O" is available but please do not select the combination "". The transfer clock generated by timer/counter interrupt is calculated by the following equation : Transfer clock [Hz] = Timer/counter source clock [Hz] ÷ TTREG set value RXDNC setting BRG setting Transfer clock [Hz] 000 110 (When the transfer clock generated by timer/counter interrupt is the same as the right side column) 11 (Reject pulses shorter than 127/fc[s] as noise) 00 (No noise rejection) 01 (Reject pulses shorter than 31/fc[s] as noise) 10 (Reject pulses shorter than 63/fc[s] as noise) fc/13 O O O fc/8 O fc/16 O O fc/32 O O O O O O O The setting except the above Table of Contents Differences among Products TMP86FS49BUG TMP86FS49BUG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 2.1.2 2.1.3 Memory Address Map. 9 Program Memory (Flash) . 9 Data Memory (RAM) . 9 2.2.1 2.2.2 Clock Generator. 10 Timing Generator . 12 2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2.1 2.2.2.2 Configuration of timing generator Machine cycle 2.2.3.1 2.2.3.2 2.2.3.3 Single-clock mode Dual-clock mode STOP mode 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.2.3 2.2.4 2.3 Operation Mode Control Circuit . 13 Operating Mode Control . 18 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.1 2.3.2 2.3.3 2.3.4 External Reset Input . 31 Address trap reset . 32 Watchdog timer reset. 32 System clock reset. 32 3. Interrupt Control Circuit 3.1 3.2 Interrupt latches (IL23 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.1 3.2.2 Interrupt master enable flag (IMF) . 36 Individual interrupt enable flags (EF23 to EF4) . 37 3.3.1 3.3.2 Interrupt acceptance processing is packaged as follows. 39 Saving/restoring general-purpose registers . 40 Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2.1 Using PUSH and POP instructions i 3.3.2.2 Using data transfer instructions 3.3.3 Interrupt return . 41 3.4.1 3.4.2 Address error detection . 42 Debugging . 42 3.4 3.5 3.6 3.7 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. Special Function Register (SFR) 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Port P0 (P07 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P37 to P30) (Large Current Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P54 to P50) (Large Current Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 52 54 55 56 58 59 62 6. Watchdog Timer (WDT) 6.1 6.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Malfunction Detection Methods Using the Watchdog Timer . Watchdog Timer Enable . Watchdog Timer Disable . Watchdog Timer Interrupt (INTWDT). Watchdog Timer Reset . 66 67 68 68 69 6.3.1 6.3.2 6.3.3 6.3.4 Selection of Address Trap in Internal RAM (ATAS) . Selection of Operation at Address Trap (ATOUT) . Address Trap Interrupt (INTATRAP). Address Trap Reset . 70 70 70 71 6.3 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7. Time Base Timer (TBT) 7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.1.1 7.1.2 7.1.3 Configuration . 73 Control . 73 Function . 74 7.2.1 7.2.2 Configuration . 75 Control . 75 7.2 ii Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8. 16-Bit TimerCounter 1 (TC1) 8.1 8.2 8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 Timer mode. 80 External Trigger Timer Mode . 82 Event Counter Mode . 84 Window Mode . 85 Pulse Width Measurement Mode. 86 Programmable Pulse Generate (PPG) Output Mode . 89 9. 16-Bit Timer/Counter2 (TC2) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.3.1 9.3.2 9.3.3 Timer mode. 95 Event counter mode. 97 Window mode . 97 10. 8-Bit TimerCounter (TC3, TC4) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 8-Bit Timer Mode (TC3 and 4) . 8-Bit Event Counter Mode (TC3, 4) . 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4). 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4). 16-Bit Timer Mode (TC3 and 4) . 16-Bit Event Counter Mode (TC3 and 4) . 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4). 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) . Warm-Up Counter Mode. 10.3.9.1 10.3.9.2 105 106 106 109 111 112 112 115 117 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 11. 8-Bit TimerCounter (TC5, TC6) 11.1 11.2 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.3.9 8-Bit Timer Mode (TC5 and 6) . 8-Bit Event Counter Mode (TC5, 6) . 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6). 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6). 16-Bit Timer Mode (TC5 and 6) . 16-Bit Event Counter Mode (TC5 and 6) . 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6). 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) . Warm-Up Counter Mode. 11.3.9.1 125 126 126 129 131 132 132 135 137 Low-Frequency Warm-up Counter Mode iii 11.3.9.2 (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 12. Asynchronous Serial interface (UART1 ) 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8.1 12.8.2 Data Transmit Operation . 144 Data Receive Operation . 144 12.9.1 12.9.2 12.9.3 12.9.4 12.9.5 12.9.6 Parity Error. Framing Error. Overrun Error . Receive Data Buffer Full. Transmit Data Buffer Empty . Transmit End Flag . 139 140 142 143 143 144 144 144 12.9 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 145 145 145 146 146 147 13. Asynchronous Serial interface (UART2 ) 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.1 13.8.2 Data Transmit Operation . 154 Data Receive Operation . 154 13.9.1 13.9.2 13.9.3 13.9.4 13.9.5 13.9.6 Parity Error. Framing Error. Overrun Error . Receive Data Buffer Full. Transmit Data Buffer Empty . Transmit End Flag . 149 150 152 153 153 154 154 154 13.9 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 155 155 155 156 156 157 14. Synchronous Serial Interface (SIO1) 14.1 14.2 14.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.3.1 Serial clock . 162 14.3.1.1 14.3.1.2 Clock source Shift edge 14.3.2.1 Transmit mode 14.3.2 iv Transfer bit direction . 164 14.3.2.2 14.3.2.3 Receive mode Transmit/receive mode 14.3.3.1 14.3.3.2 14.3.3.3 Transmit mode Receive mode Transmit/receive mode 14.3.3 Transfer modes. 165 15. Synchronous Serial Interface (SIO2) 15.1 15.2 15.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.3.1 Serial clock . 180 15.3.1.1 15.3.1.2 Clock source Shift edge 15.3.2.1 15.3.2.2 15.3.2.3 Transmit mode Receive mode Transmit/receive mode 15.3.3.1 15.3.3.2 15.3.3.3 Transmit mode Receive mode Transmit/receive mode 15.3.2 15.3.3 Transfer bit direction . 182 Transfer modes. 183 16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.1 16.2 16.3 16.4 16.5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Data Format in the I2C Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5.1 195 195 195 196 197 Acknowledgement mode specification. 199 16.5.1.1 16.5.1.2 Acknowledgment mode (ACK = "1") Non-acknowledgment mode (ACK = "0") 16.5.3.1 16.5.3.2 Clock source Clock synchronization 16.5.2 16.5.3 Number of transfer bits . 200 Serial clock . 200 16.5.4 16.5.5 16.5.6 16.5.7 16.5.8 16.5.9 16.5.10 16.5.11 16.5.12 16.5.13 Slave address and address recognition mode specification . Master/slave selection . Transmitter/receiver selection. Start/stop condition generation . Interrupt service request and cancel. Setting of I2C bus mode . Arbitration lost detection monitor . Slave address match detection monitor. GENERAL CALL detection monitor . Last received bit monitor. 16.6.1 16.6.2 16.6.3 Device initialization . 205 Start condition and slave address generation. 205 1-word data transfer. 205 16.6 201 201 201 202 202 203 203 204 204 204 Data Transfer of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6.3.1 16.6.3.2 16.6.4 16.6.5 When the MST is "1" (Master mode) When the MST is "0" (Slave mode) Stop condition generation . 208 Restart . 209 17. 10-bit AD Converter (ADC) 17.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 v 17.2 17.3 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 17.3.1 17.3.2 17.3.3 Software Start Mode . 215 Repeat Mode . 215 Register Setting . 216 17.6.1 17.6.2 17.6.3 17.6.4 Restrictions for AD Conversion interrupt (INTADC) usage . Analog input pin voltage range . Analog input shared pins . Noise Countermeasure . 17.4 17.5 17.6 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 218 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 219 219 219 219 18. Key-on Wakeup (KWU) 18.1 18.2 18.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19. Flash Memory 19.1 Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 19.1.1 19.1.2 Flash Memory Command Sequence Execution Control (FLSCR) . 224 Flash Memory Bank Select Control (FLSCR) . 224 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 Byte Program . Sector Erase (4-kbyte Erase) . Chip Erase (All Erase) . Product ID Entry . Product ID Exit . Security Program . 19.4.1 Flash Memory Control in the Serial PROM Mode. 228 19.2 19.3 19.4 Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 225 225 226 226 226 226 Toggle Bit (D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Access to the Flash Memory Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 19.4.1.1 19.4.2 How to write to the flash memory by executing the control program in the RAM area (in the RAM loader mode within the serial PROM mode) Flash Memory Control in the MCU mode. 230 19.4.2.1 How to write to the flash memory by executing a user write control program in the RAM area (in the MCU mode) 20. Serial PROM Mode 20.1 20.2 20.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Serial PROM Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.3.1 20.3.2 20.3.3 20.3.4 Serial PROM Mode Control Pins . Pin Function. Example Connection for On-Board Writing. Activating the Serial PROM Mode . 20.6.1 20.6.2 20.6.3 Flash Memory Erasing Mode (Operating command: F0H) . 241 Flash Memory Writing Mode (Operation command: 30H) . 243 RAM Loader Mode (Operation Command: 60H) . 246 20.4 20.5 20.6 vi 234 234 235 236 Interface Specifications for UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Operation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 20.6.4 20.6.5 20.6.6 20.6.7 Flash Memory SUM Output Mode (Operation Command: 90H) . Product ID Code Output Mode (Operation Command: C0H). Flash Memory Status Output Mode (Operation Command: C3H) . Flash Memory security program Setting Mode (Operation Command: FAH) . 20.8.1 20.8.2 Calculation Method . 254 Calculation data . 255 20.10.1 20.10.2 20.10.3 Password String. 257 Handling of Password Error . 257 Password Management during Program Development . 257 20.7 20.8 248 249 251 252 Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Checksum (SUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 20.9 Intel Hex Format (Binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.10 Passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.11 20.12 20.13 20.14 20.15 Product ID Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Status Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Erasure Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 258 260 261 262 21. Input/Output Circuit 21.1 21.2 Control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 22. Electrical Characteristics 22.1 22.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 22.2.1 22.2.2 22.2.3 22.3 22.4 22.5 22.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.6.1 22.7 22.8 MCU mode (Flash Programming or erasing) . 268 MCU mode (Except Flash Programming or erasing) . 268 Serial PROM mode . 269 270 272 273 273 Write/Retention Characteristics . 273 Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 23. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C TLCS-870/C (LSI). vii viii TMP86FS49BUG TMP86FS49BUG CMOS 8-Bit Microcontroller TMP86FS49BUG TMP86FS49BUG The TMP86FS49BUG TMP86FS49BUG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 61440 bytes of Flash Memory. It is pin-compatible with the TMP86CM49UG/CS49UG TMP86CM49UG/CS49UG (Mask ROM version). The TMP86FS49BUG TMP86FS49BUG can realize operations equivalent to those of the TMP86CM49UG/CS49UG TMP86CM49UG/CS49UG by programming the on-chip Flash Memory. Product No. ROM (FLASH) RAM Package MaskROM MCU Emulation Chip TMP86FS49BUG TMP86FS49BUG 61440 bytes 2048 bytes LQFP64-P-1010-0 LQFP64-P-1010-0.50D TMP86CM49UG/ TMP86CM49UG/ CS49UG CS49UG TMP86C949XB TMP86C949XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C TLCS-870/C series - Instruction execution time : 0.25 µs (at 16 MHz) 122 µs (at 32.768 kHz) - 132 types & 731 basic instructions 2. 24interrupt sources (External : 5 Internal : 19) 3. Input / Output ports (56 pins) Large current output: 13pins (Typ. 20mA), LED direct drive 4. Watchdog Timer 5. Prescaler - Time base timer - Divider output function 6. 16-bit timer counter: 1 ch - Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 7. 16-bit timer counter: 1 ch - Timer, Event counter, Window modes This product uses the Super Flash technology under the licence of Silicon Storage Technology, Inc. Super Flash is registered trademark of Silicon Storage Technology, Inc. · The information contained herein is subject to change without notice. 021023_D · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B · The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C · The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E · For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86FS49BUG TMP86FS49BUG 8. 8-bit timer counter : 4 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 9. 8-bit UART : 2 ch 10. High-Speed SIO: 2ch 11. Serial Bus Interface(I2C Bus): 1ch 12. 10-bit successive approximation type AD converter - Analog input: 16 ch 13. Key-on wakeup : 4 ch 14. Clock operation Single clock mode Dual clock mode 15. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR. IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interruputs(CPU restarts). IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts). SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock.Release by falling edge of the source clock which is set by TBTCR. SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts). SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. interruput. 16. Wide operation voltage: 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz Page 2 Release by TMP86FS49BUG TMP86FS49BUG 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RESET (STOP/INT5) P20 (INT0) P00 (BOOT/RXD1) P01 (TXD1) P02 (INT1) P03 (SI1) P04 (SO1) P05 (SCK1) P06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 (INT3/TC2) P15 (PDO5/PWM5/TC5) P16 (PDO6/PWM6/PPG6/TC6) P17 (SCL) P50 (SDA) P51 P52 P53 P54 P30 P31 P32 P33 P34 P35 P36 P37 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P14 (TC4/PDO4/PWM4/PPG4) P13 (TC3/PDO3/PWM3) P12 (PPG) P11 (DVO) P10 (TC1) P47 P46 (SCK2) P45 (SO2) P44 (SI2) P43 P42 (TXD2) P41 (RXD2) P40 P77 (AIN15 AIN15) P76 (AIN14 AIN14) P75 (AIN13 AIN13) 1.2 Pin Assignment Figure 1-1 Pin Assignment Page 3 P74(AIN12 AIN12) P73(AIN11 AIN11) P72(AIN10 AIN10) P71(AIN9) P70(AIN8) P67(AIN7/STOP3) P66(AIN6/STOP2) P65(AIN5/STOP1) P64(AIN4/STOP0) P63(AIN3) P62(AIN2) P61(AIN1) P60(AIN0) AVDD VAREF P07(INT2) 1.3 Block Diagram TMP86FS49BUG TMP86FS49BUG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86FS49BUG TMP86FS49BUG 1.4 Pin Names and Functions The TMP86FS49BUG TMP86FS49BUG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/3) Pin Name Pin Number Input/Output Functions 17 IO I PORT07 PORT07 External interrupt 2 input 16 IO IO PORT06 PORT06 Serial clock input/output 1 P05 SO1 15 IO O PORT05 PORT05 Serial data output 1 P04 SI1 14 IO I PORT04 PORT04 Serial data input 1 P03 INT1 13 IO I PORT03 PORT03 External interrupt 1 input P02 TXD1 12 IO O PORT02 PORT02 UART data output 1 P01 RXD1 BOOT 11 IO I I PORT01 PORT01 UART data input 1 Serial PROM mode control input 10 IO I PORT00 PORT00 External interrupt 0 input 51 IO I O PORT17 PORT17 TC6 input PDO6/PWM6/PPG6 output 50 IO I O PORT16 PORT16 TC5 input PDO5/PWM5 output 49 IO I I PORT15 PORT15 TC2 input External interrupt 3 input 48 IO I O PORT14 PORT14 TC4 input PDO4/PWM4/PPG4 output 47 IO I O PORT13 PORT13 TC3 input PDO3/PWM3 output 46 IO O PORT12 PORT12 PPG output 45 IO O PORT11 PORT11 Divider Output P10 TC1 44 IO I PORT10 PORT10 TC1 input P22 XTOUT 7 IO O PORT22 PORT22 Resonator connecting pins(32.768kHz) for inputting external clock P21 XTIN 6 IO I PORT21 PORT21 Resonator connecting pins(32.768kHz) for inputting external clock P07 INT2 P06 SCK1 P00 INT0 P17 TC6 PDO6/PWM6/PPG6 P16 TC5 PDO5/PWM5 P15 TC2 INT3 P14 TC4 PDO4/PWM4/PPG4 P13 TC3 PDO3/PWM3 P12 PPG P11 DVO Page 5 1.4 Pin Names and Functions TMP86FS49BUG TMP86FS49BUG Table 1-1 Pin Names and Functions(2/3) Pin Name Pin Number Input/Output Functions 9 IO I I PORT20 PORT20 External interrupt 5 input STOP mode release signal input P37 64 IO PORT37 PORT37 P36 63 IO PORT36 PORT36 P35 62 IO PORT35 PORT35 P34 61 IO PORT34 PORT34 P33 60 IO PORT33 PORT33 P32 59 IO PORT32 PORT32 P31 58 IO PORT31 PORT31 P30 57 IO PORT30 PORT30 P47 43 IO PORT47 PORT47 42 IO IO PORT46 PORT46 Serial clock input/output 2 P45 SO2 41 IO O PORT45 PORT45 Serial data output 2 P44 SI2 40 IO I PORT44 PORT44 Serial data input 2 P43 39 IO PORT43 PORT43 P42 TXD2 38 IO O PORT42 PORT42 UART data output 2 P41 RXD2 37 IO I PORT41 PORT41 UART data input 2 P40 36 IO PORT40 PORT40 P54 56 IO PORT54 PORT54 P53 55 IO PORT53 PORT53 P52 54 IO PORT52 PORT52 P51 SDA 53 IO IO PORT51 PORT51 I2C bus data P50 SCL 52 IO IO PORT50 PORT50 I2C bus clock P67 AIN7 STOP3 27 IO I I PORT67 PORT67 Analog Input7 STOP3 input P66 AIN6 STOP2 26 IO I I PORT66 PORT66 Analog Input6 STOP2 input P65 AIN5 STOP1 25 IO I I PORT65 PORT65 Analog Input5 STOP1 input P64 AIN4 STOP0 24 IO I I PORT64 PORT64 Analog Input4 STOP0 input P20 INT5 STOP P46 SCK2 Page 6 TMP86FS49BUG TMP86FS49BUG Table 1-1 Pin Names and Functions(3/3) Pin Name Pin Number Input/Output Functions P63 AIN3 23 IO I PORT63 PORT63 Analog Input3 P62 AIN2 22 IO I PORT62 PORT62 Analog Input2 P61 AIN1 21 IO I PORT61 PORT61 Analog Input1 P60 AIN0 20 IO I PORT60 PORT60 Analog Input0 P77 AIN15 AIN15 35 IO I PORT77 PORT77 Analog Input15 P76 AIN14 AIN14 34 IO I PORT76 PORT76 Analog Input14 P75 AIN13 AIN13 33 IO I PORT75 PORT75 Analog Input13 P74 AIN12 AIN12 32 IO I PORT74 PORT74 Analog Input12 P73 AIN11 AIN11 31 IO I PORT73 PORT73 Analog Input11 P72 AIN10 AIN10 30 IO I PORT72 PORT72 Analog Input10 P71 AIN9 29 IO I PORT71 PORT71 Analog Input9 P70 AIN8 28 IO I PORT70 PORT70 Analog Input8 XIN 2 I Resonator connecting pins for high-frequency clock XOUT 3 O Resonator connecting pins for high-frequency clock RESET 8 I Reset signal TEST 4 I Test pin for out-going test. Normally, be fixed to low. VAREF 18 I Analog Base Voltage Input Pin for A/D Conversion AVDD 19 I Analog Power Supply VDD 5 I +5V VSS 1 I 0(GND) Page 7 1.4 Pin Names and Functions TMP86FS49BUG TMP86FS49BUG Page 8 TMP86FS49BUG TMP86FS49BUG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86FS49BUG TMP86FS49BUG memory is composed Flash, RAM, DBR(Data buffer register) and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86FS49BUG TMP86FS49BUG memory address map. 0000H 0000H SFR SFR: 64 bytes 003FH 003FH 0040H 0040H 2048 bytes RAM RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack 083FH 083FH 0F80H 0F80H DBR: 128 bytes DBR Data buffer register includes: Peripheral control registers Peripheral status registers 0FFFH 1000H 1000H Flash: Program memory 61440 bytes Flash FFB0H Vector table for interrupts (16 bytes) FFBFH FFC0H Vector table for vector call instructions (32 bytes) FFDFH FFE0H Vector table for interrupts FFFFH (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (Flash) The TMP86FS49BUG TMP86FS49BUG has a 61440 bytes (Address 1000H 1000H to FFFFH) of program memory (Flash ). 2.1.3 Data Memory (RAM) The TMP86FS49BUG TMP86FS49BUG has 2048 bytes (Address 0040H 0040H to 083FH 083FH) of internal RAM. The first 192 bytes (0040H 0040H to 00FFH 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. Page 9 2. Operational Description 2.2 System Clock Controller TMP86FS49BUG TMP86FS49BUG The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to "00H". (TMP86FS49BUG TMP86FS49BUG) LD ; Start address setup A, H ; Initial value (00H) setup LD SRAMCLR: HL, 0040H 0040H LD BC, 07FFH 07FFH LD (HL), A INC HL DEC BC JRS F, SRAMCLR 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register TBTCR 0036H 0036H Clock generator XIN fc High-frequency clock oscillator Timing generator XOUT Standby controller 0038H 0038H XTIN Low-frequency clock oscillator SYSCR1 fs System clocks 0039H 0039H SYSCR2 System control registers XTOUT Clock generator control Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 10 TMP86FS49BUG TMP86FS49BUG Low-frequency clock High-frequency clock XIN XOUT XIN XOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator XTIN XTOUT (Open) (c) Crystal (b) External oscillator (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 11 2. Operational Description 2.2 System Clock Controller 2.2.2 TMP86FS49BUG TMP86FS49BUG Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 and TBTCR, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler and the divider are cleared to "0". fc or fs Main system clock generator Machine cycle counters SYSCK DV7CK High-frequency clock fc Low-frequency clock fs 1 2 fc/4 S A Divider Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 B Multiplexer S B0 B1 A0 Y0 A1 Y1 Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 12 TMP86FS49BUG TMP86FS49BUG Timing Generator Control Register TBTCR (0036H 0036H) 7 6 (DVOEN) 5 4 DV7CK (DVOCK) DV7CK 3 (TBTEN) Selection of input to the 7th stage of the divider 2 1 0 (TBTCK) (Initial value: 0000 0000) 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86FS49BUG TMP86FS49BUG is placed in this mode after reset. Page 13 2. Operational Description 2.2 System Clock Controller TMP86FS49BUG TMP86FS49BUG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 = "1", and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF (Interrupt master enable flag) is "1" (Interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When the IMF is "0" (Interrupt disable), the execution will resume with the instruction which follows the IDLE1 mode start instruction. (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 = "1". When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR, the timing generator starts feeding the clock to all peripheral circuits. When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back again. IDLE0 mode is entered and returned regardless of how TBTCR is set. When IMF = "1", EF7 (TBT interrupt individual enable flag) = "1", and TBTCR = "1", interrupt processing is performed. When IDLE0 mode is entered while TBTCR = "1", the INTTBT interrupt latch is set after returning to NORMAL1 mode. 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 becomes "1", the hardware changes into SLOW2 mode. As the SYSCR2 becomes "0", the hardware changes into NORMAL2 mode. As the SYSCR2 becomes "0", the hardware changes into SLOW1 mode. Do not clear SYSCR2 to "0" during SLOW2 mode. (3) SLOW1 mode This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock. Page 14 TMP86FS49BUG TMP86FS49BUG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (4) IDLE2 mode In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode. (5) SLEEP1 mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode. In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (6) SLEEP2 mode The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock. (7) SLEEP0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by setting "1" on bit SYSCR2. When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR, the timing generator starts feeding the clock to all peripheral circuits. When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back again. SLEEP0 mode is entered and returned regardless of how TBTCR is set. When IMF = "1", EF7 (TBT interrupt individual enable flag) = "1", and TBTCR = "1", interrupt processing is performed. When SLEEP0 mode is entered while TBTCR = "1", the INTTBT interrupt latch is set after returning to SLOW1 mode. 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 15 2. Operational Description 2.2 System Clock Controller TMP86FS49BUG TMP86FS49BUG IDLE0 mode RESET Reset release Note 2 SYSCR2 = "1" SYSCR1 = "1" SYSCR2 = "1" NORMAL1 mode Interrupt STOP pin input IDLE1 mode (a) Single-clock mode SYSCR2 = "0" SYSCR2 = "1" SYSCR2 = "1" IDLE2 mode NORMAL2 mode Interrupt SYSCR1 = "1" STOP pin input SYSCR2 = "0" SYSCR2 = "1" STOP SYSCR2 = "1" SLEEP2 mode SLOW2 mode Interrupt SYSCR2 = "0" SYSCR2 = "1" SYSCR2 = "1" SLEEP1 mode Interrupt (b) Dual-clock mode SYSCR1 = "1" SLOW1 mode STOP pin input SYSCR2 = "1" Note 2 SLEEP0 mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR setting. Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode Low Frequency RESET NORMAL1 Single clock IDLE1 Oscillation Operate Halt Operate Halt Operate with high frequency Machine Cycle Time 4/fc [s] 4/fc [s] Halt Oscillation Operate with low frequency Oscillation Halt Operate Operate Operate with low frequency SLOW1 4/fs [s] Stop SLEEP0 STOP Reset Stop SLEEP2 SLEEP1 Reset Halt SLOW2 Dual clock Other Peripherals Stop NORMAL2 IDLE2 TBT Operate IDLE0 STOP CPU Core Reset High Frequency Halt Stop Halt Page 16 Halt TMP86FS49BUG TMP86FS49BUG System Control Register 1 SYSCR1 7 6 5 4 (0038H 0038H) STOP RELM RETM 3 OUTEN 2 1 0 WUT (Initial value: 0000 00*) STOP STOP mode start 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) R/W RELM Release method for STOP mode 0: Edge-sensitive release 1: Level-sensitive release R/W RETM Operating mode after STOP mode 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode R/W Port output during STOP mode 0: High impedance 1: Output kept R/W OUTEN Return to NORMAL mode 00 3 x 213/fs 216/fc 213/fs 3 x 214/fc 3 x 26/fs 11 Warm-up time at releasing STOP mode 3 x 216/fc 01 10 WUT Return to SLOW mode 214/fc 26/fs R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H 0039H) 7 6 5 4 XEN XTEN SYSCK IDLE 3 2 1 TGHALT 0 (Initial value: 1000 *0*) XEN High-frequency oscillator control 0: Turn off oscillation 1: Turn on oscillation XTEN Low-frequency oscillator control 0: Turn off oscillation 1: Turn on oscillation SYSCK Main system clock select (Write)/main system clock monitor (Read) 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) IDLE CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) TGHALT TG control (IDLE0 and SLEEP0 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W R/W Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator, *; Don't care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR. Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to "0". Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to "0". Note 8: Before setting TGHALT to "1", be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals may be set after IDLE0 or SLEEP0 mode is released. Page 17 2. Operational Description 2.2 System Clock Controller 2.2.4 TMP86FS49BUG TMP86FS49BUG Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP3 to STOP0) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 to "1". During STOP mode, the following status is maintained. 1. Oscillations are turned off, and all internal operations are halted. 2. The data memory, registers, the program status word and port output latches are all held in the status in effect before STOP mode was entered. 3. The prescaler and the divider of the timing generator are cleared to "0". 4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7]) which started STOP mode. STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the SYSCR1. Do not use any key-on wakeup input (STOP3 to STOP0) for releasing STOP mode in edge-sensitive mode. Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP3 to STOP0). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOP3 to STOP0 pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP3 to STOP0 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP3 to STOP0 input is high. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: (SYSCR1), 01010000B 01010000B ; Sets up the level-sensitive release mode TEST (P2PRD). 0 ; Wait until the STOP pin input goes low level JRS F, SSTOPH ; IMF 0 DI SET (SYSCR1). 7 ; Starts STOP mode Page 18 TMP86FS49BUG TMP86FS49BUG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if JRS F, SINT5 LD (SYSCR1), 01010000B 01010000B port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 DI SET SINT5: (SYSCR1). 7 ; Starts STOP mode RETI VIH STOP pin XOUT pin NORMAL operation STOP operation Warm up Confirm by program that the STOP pin input is low and start STOP mode. NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP3 to STOP0 pin input for releasing STOP mode in edge-sensitive release mode. Example :Starting STOP mode from NORMAL mode ; IMF 0 DI LD (SYSCR1), 10010000B 10010000B ; Starts after specified to the edge-sensitive release mode VIH STOP pin XOUT pin NORMAL operation STOP operation Warm up NORMAL operation STOP mode started by the program. STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode Page 19 2. Operational Description 2.2 System Clock Controller TMP86FS49BUG TMP86FS49BUG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 in accordance with the resonator characteristics. 3. When the warm-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction. Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 Return to SLOW Mode 12.288 4.096 3.072 1.024 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 20 Page 21 Figure 2-9 STOP Mode Start/Release Divider Instruction execution Program counter Main system clock Oscillator circuit STOP pin input Divider Instruction execution Program counter Main system clock Oscillator circuit 0 Halt Turn off Turn on Turn on n Count up a+3 Warm up a+2 n+2 n+3 n+4 0 (b) STOP mode release 1 Instruction address a + 2 a+4 2 Instruction address a + 3 a+5 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+1 SET (SYSCR1). 7 a+3 3 Instruction address a + 4 a+6 0 Halt Turn off TMP86FS49BUG TMP86FS49BUG 2. Operational Description 2.2 System Clock Controller 2.2.4.2 TMP86FS49BUG TMP86FS49BUG IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input Reset No No Interrupt request Yes "0" IMF "1" (Interrupt release mode) Normal release mode Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 22 TMP86FS49BUG TMP86FS49BUG · Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 to "1". · Release the IDLE1/2 and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode. These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and SLEEP1/2 modes, the SYSCR2 is automatically cleared to "0" and the operation mode is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes. IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. (1) Normal release mode (IMF = "0") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to "0" by load instructions. (2) Interrupt release mode (IMF = "1") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 23 Page 24 Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Watchdog timer Instruction execution Program counter Interrupt request Main system clock Watchdog timer Instruction execution Program counter Interrupt request Main system clock Watchdog timer Instruction execution Program counter Interrupt request Main system clock Halt Halt Halt Halt Operate Operate Operate Acceptance of interrupt Instruction address a + 2 a+4 (b) IDLE1/2 and SLEEP1/2 modes release Interrupt release mode a+3 Normal release mode a+3 (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Operate SET (SYSCR2). 4 a+2 Halt a+3 2.2 System Clock Controller 2. Operational Description TMP86FS49BUG TMP86FS49BUG TMP86FS49BUG TMP86FS49BUG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input Yes Reset No No TBT source clock falling edge Yes No TBTCR = "1" Yes No TBT interrupt enable Yes (Normal release mode) No IMF = "1" Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 25 2. Operational Description 2.2 System Clock Controller TMP86FS49BUG TMP86FS49BUG · Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 to "1". · Release the IDLE0 and SLEEP0 modes IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode. These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag of TBT and TBTCR. After releasing IDLE0 and SLEEP0 modes, the SYSCR2 is automatically cleared to "0" and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR is set to "1", INTTBT interrupt latch is set to "1". IDLE0 and SLEEP0 modes can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR setting. (1) Normal release mode (IMF·EF7·TBTCR = "0") IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR. After the falling edge is detected, the program operation is resumed from the instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR is set to "1", INTTBT interrupt latch is set to "1". (2) Interrupt release mode (IMF·EF7·TBTCR = "1") IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR and INTTBT interrupt processing is started. Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR. Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started. Page 26 Halt Page 27 Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Watchdog timer Instruction execution Program counter TBT clock Halt Halt Watchdog timer Main system clock Halt Instruction execution Program counter TBT clock Main system clock Watchdog timer Instruction execution Program counter Interrupt request Main system clock a+3 Halt Operate Operate (b) IDLE and SLEEP0 modes release Interrupt release mode a+3 Normal release mode a+3 Acceptance of interrupt Instruction address a + 2 a+4 (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Operate SET (SYSCR2). 2 a+2 TMP86FS49BUG TMP86FS49BUG 2. Operational Description 2.2 System Clock Controller 2.2.4.4 TMP86FS49BUG TMP86FS49BUG SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 to switch the main system clock to the low-frequency clock for SLOW2 mode. Next, clear SYSCR2 to turn off high-frequency oscillation. Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 1 (Switches the main system clock to the low-frequency clock for SLOW2) CLR (SYSCR2). 7 ; SYSCR2 0 (Turns off high-frequency oscillation) Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET (SYSCR2). 6 ; SYSCR2 1 LD (TC5CR), 43H ; Sets mode for TC6, 5 (16-bit mode, fs for source) LD (TC6CR), 05H ; Sets warming-up counter mode LDW (TTREG5), 8000H 8000H ; Sets warm-up time (Depend on oscillator accompanied) ; IMF 0 DI SET (EIRE). 2 ; IMF 1 EI SET ; Enables INTTC6 (TC6CR). 3 ; Starts TC6, 5 CLR (TC6CR). 3 ; Stops TC6, 5 SET (SYSCR2). 5 ; SYSCR2 1 : PINTTC6: (Switches the main system clock to the low-frequency clock) CLR (SYSCR2). 7 ; SYSCR2 0 (Turns off high-frequency oscillation) RETI : VINTTC6: DW PINTTC6 ; INTTC6 vector table Page 28 TMP86FS49BUG TMP86FS49BUG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC6,TC5), clear SYSCR2 to switch the main system clock to the high-frequency clock. SLOW mode can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET (SYSCR2). 7 ; SYSCR2 1 (Starts high-frequency oscillation) LD (TC5CR), 63H ; Sets mode for TC6, 5 (16-bit mode, fc for source) LD (TC6CR), 05H ; Sets warming-up counter mode LD (TTREG6), 0F8H ; Sets warm-up time ; IMF 0 DI SET (EIRE). 2 ; IMF 1 EI SET ; Enables INTTC6 (TC6CR). 3 ; Starts TC6, 5 CLR (TC6CR). 3 ; Stops TC6, 5 CLR (SYSCR2). 5 ; SYSCR2 0 : PINTTC6: (Switches the main system clock to the high-frequency clock) RETI : VINTTC6: DW PINTTC6 ; INTTC6 vector table Page 29 Page 30 Figure 2-14 Switching between the NORMAL2 and SLOW Modes SET (SYSCR2). 7 SET (SYSCR2). 5 SLOW1 mode Instruction execution XEN SYSCK Highfrequency clock Lowfrequency clock Main system clock NORMAL2 mode Instruction execution XEN SYSCK Highfrequency clock Lowfrequency clock Main system clock (b) Switching to the NORMAL2 mode Warm up during SLOW2 mode CLR (SYSCR2). 5 (a) Switching to the SLOW mode SLOW2 mode CLR (SYSCR2). 7 NORMAL2 mode SLOW1 mode Turn off 2.2 System Clock Controller 2. Operational Description TMP86FS49BUG TMP86FS49BUG TMP86FS49BUG TMP86FS49BUG 2.3 Reset Circuit The TMP86FS49BUG TMP86FS49BUG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when power is turned on. Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Initial Value Program counter (PC) (SP) Not initialized Initial Value (FFFEH) Stack pointer On-chip Hardware General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Prescaler and divider of timing generator 0 Not initialized Jump status flag (JF) Not initialized Zero flag (ZF) Not initialized Carry flag (CF) Not initialized Half carry flag (HF) Not initialized Sign flag (SF) Not initialized Overflow flag (VF) Not initialized (IMF) 0 (EF) 0 (IL) Watchdog timer 0 Enable Output latches of I/O ports Control registers Interrupt individual enable flags Interrupt latches 2.3.1 Refer to each of control register RAM Interrupt master enable flag Refer to I/O port circuitry Not initialized External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 31 2. Operational Description 2.3 Reset Circuit TMP86FS49BUG TMP86FS49BUG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 is set to "1"), DBR or the SFR area, address trap reset will be generated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz). Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution Reset release JP a Instruction at address r Address trap is occurred Internal reset maximum 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR, DBR or on-chip RAM (WDTCR1 = "1") space. Note 2: During reset release, reset vector "r" is read out, and an instruction at address "r" is fetched and decoded. Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 Sys