TLCS-870/C TMP86CS25ADFG P-LQFP100-1414-0 TMP86C925XB 060116EBP SCK0/SEG59 - Datasheet Archive

 

TLCS-870/C Series TMP86CS25ADFG TMP86CS25ADFG The information contained herein is subject to change without notice. 021023 _ D

 

8 Bit Microcontroller TLCS-870/C TLCS-870/C Series TMP86CS25ADFG TMP86CS25ADFG TMP86CS25ADFG TMP86CS25ADFG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S © 2006 TOSHIBA CORPORATION All Rights Reserved Page 2 Revision History Date Revision 2006/2/11 1 First Release 2006/7/10 2 Periodical updating.No change in contents. 2006/7/27 3 Periodical updating.No change in contents. 2006/9/5 4 Contents Revised 2006/11/15 5 Contents Revised Table of Contents TMP86CS25ADFG TMP86CS25ADFG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 2.1.2 2.1.3 Memory Address Map. 9 Program Memory (MaskROM). 9 Data Memory (RAM) . 9 2.2.1 2.2.2 Clock Generator. 10 Timing Generator . 12 2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2.1 2.2.2.2 Configuration of timing generator Machine cycle 2.2.3.1 2.2.3.2 2.2.3.3 Single-clock mode Dual-clock mode STOP mode 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.2.3 2.2.4 2.3 Operation Mode Control Circuit . 13 Operating Mode Control . 18 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.1 2.3.2 2.3.3 2.3.4 External Reset Input . 31 Address trap reset . 32 Watchdog timer reset. 32 System clock reset. 32 3. Interrupt Control Circuit 3.1 3.2 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.1 3.2.2 Interrupt master enable flag (IMF) . 36 Individual interrupt enable flags (EF15 to EF4) . 36 3.4.1 3.4.2 Interrupt acceptance processing is packaged as follows. 39 Saving/restoring general-purpose registers . 40 3.3 3.4 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4.2.1 3.4.2.2 Using PUSH and POP instructions Using data transfer instructions 3.4.3 Interrupt return . 42 3.5.1 3.5.2 Address error detection . 43 Debugging . 43 3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 i 3.6 3.7 3.8 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. Special Function Register (SFR) 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P36 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 55 56 57 58 59 60 6. Watchdog Timer (WDT) 6.1 6.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Malfunction Detection Methods Using the Watchdog Timer . Watchdog Timer Enable . Watchdog Timer Disable . Watchdog Timer Interrupt (INTWDT). Watchdog Timer Reset . 62 63 64 64 65 6.3.1 6.3.2 6.3.3 6.3.4 Selection of Address Trap in Internal RAM (ATAS) . Selection of Operation at Address Trap (ATOUT) . Address Trap Interrupt (INTATRAP). Address Trap Reset . 66 66 66 67 6.3 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7. Time Base Timer (TBT) 7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.1.1 7.1.2 7.1.3 Configuration . 69 Control . 69 Function . 70 7.2.1 7.2.2 Configuration . 71 Control . 71 7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8. 18-Bit Timer/Counter (TC1) 8.1 8.2 8.3 ii Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.1 8.3.2 8.3.3 8.3.4 Timer mode. 77 Event Counter mode . 78 Pulse Width Measurement mode. 79 Frequency Measurement mode . 80 9. 8-Bit TimerCounter (TC3, TC4) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 8-Bit Timer Mode (TC3 and 4) . 89 8-Bit Event Counter Mode (TC3, 4) . 90 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4). 90 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4). 93 16-Bit Timer Mode (TC3 and 4) . 95 16-Bit Event Counter Mode (TC3 and 4) . 96 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4). 96 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) . 99 Warm-Up Counter Mode. 101 9.3.9.1 9.3.9.2 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 10. 8-Bit TimerCounter (TC5, TC6) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 8-Bit Timer Mode (TC5 and 6) . 8-Bit Event Counter Mode (TC6) . 8-Bit Programmable Divider Output (PDO) Mode (TC6). 8-Bit Pulse Width Modulation (PWM) Output Mode (TC6). 16-Bit Timer Mode (TC5 and 6) . 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6). 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) . Warm-Up Counter Mode. 10.3.8.1 10.3.8.2 108 109 109 112 114 115 118 120 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 11. Asynchronous Serial interface (UART ) 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.1 11.8.2 Data Transmit Operation . 128 Data Receive Operation . 128 11.9.1 123 124 126 127 127 128 128 128 Parity Error. 129 11.9 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 iii 11.9.2 11.9.3 11.9.4 11.9.5 11.9.6 Framing Error. Overrun Error . Receive Data Buffer Full. Transmit Data Buffer Empty . Transmit End Flag . 129 129 130 130 131 12. Synchronous Serial Interface (SIO0) 12.1 12.2 12.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.3.1 Clock source . 135 12.3.1.1 12.3.1.2 Internal clock External clock 12.3.2.1 12.3.2.2 Leading edge Trailing edge 12.3.2 12.4 12.5 12.6 Shift edge. 137 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.6.1 12.6.2 12.6.3 4-bit and 8-bit transfer modes . 138 4-bit and 8-bit receive modes . 140 8-bit transfer / receive mode . 141 13. Synchronous Serial Interface (SIO1) 13.1 13.2 13.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.3.1 Clock source . 145 13.3.1.1 13.3.1.2 Internal clock External clock 13.3.2.1 13.3.2.2 Leading edge Trailing edge 13.3.2 13.4 13.5 13.6 Shift edge. 147 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.6.1 13.6.2 13.6.3 4-bit and 8-bit transfer modes . 148 4-bit and 8-bit receive modes . 150 8-bit transfer / receive mode . 151 14. 8-Bit AD Converter (ADC) 14.1 14.2 14.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.3.1 14.3.2 14.3.3 14.3.4 AD Conveter Operation . AD Converter Operation . STOP and SLOW Mode during AD Conversion . Analog Input Voltage and AD Conversion Result . 14.4.1 14.4.2 14.4.3 Analog input pin voltage range . 159 Analog input shared pins . 159 Noise countermeasure. 159 14.4 iv 156 156 157 158 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15. Key-on Wakeup (KWU) 15.1 15.2 15.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16. LCD Driver 16.1 16.2 Configuration of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Controlling LCD Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 16.2.1 Frame frequency. 165 16.4.1 16.4.2 Method of connecting booster circuit by using a regulator . 166 Method of connecting booster circuit without using a regulator . 166 16.5.1 16.5.2 Setting display data . 167 Blanking . 168 16.6.1 16.6.2 Initial setting . 168 Storing display data . 168 16.3 16.4 16.5 16.6 LCD Booster Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Methods of Connecting LCD Booster Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Method of Controlling LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 17. Input/Output Circuitry 17.1 17.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 18. Electrical Characteristics 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter 1 input (ECIN) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 176 177 178 179 179 180 180 19. Package Dimension This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C TLCS-870/C (LSI). v vi TMP86CS25ADFG TMP86CS25ADFG CMOS 8-Bit Microcontroller TMP86CS25ADFG TMP86CS25ADFG Product No. ROM (MaskROM) RAM Package Emulation Chip TMP86CS25ADFG TMP86CS25ADFG 61440 bytes 2048 bytes P-LQFP100-1414-0 P-LQFP100-1414-0.50F TMP86C925XB TMP86C925XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C TLCS-870/C series - Instruction execution time : 0.25 µs (at 16 MHz) 122 µs (at 32.768 kHz) - 132 types & 731 basic instructions 2. 20interrupt sources (External : 5 Internal : 15) 3. Input / Output ports (42 pins) Large current output: 4pins (Typ. 20mA), LED direct drive 4. Watchdog Timer 5. Prescaler - Time base timer - Divider output function 6. 18-bit Timer/Counter : 1ch - Timer Mode - Event Counter Mode - Pulse Width Measurement Mode - Frequency Measurement Mode 7. 8-bit timer counter : 4 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, 060116EBP 060116EBP · The information contained herein is subject to change without notice. 021023_D · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B · The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C · The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E · For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86CS25ADFG TMP86CS25ADFG Programmable pulse generation (PPG) modes 8. 8-bit UART/SIO : 1 ch 9. 8-bit SIO: 1 ch 10. 8-bit successive approximation type AD converter (with sample hold) Analog inputs: 8ch 11. Key-on wakeup : 4 ch 12. LCD driver/controller Built-in voltage booster for LCD driver With displaymemory LCD direct drive capability (60 seg × 16 com, 60 seg × 8 com, 60 seg × 4 com) 1/16,1/8,1/4 duties or static drive are programmably selectable 13. Clock operation Single clock mode Dual clock mode 14. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR. IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interruputs(CPU restarts). IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts). SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock.Release by falling edge of the source clock which is set by TBTCR. SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts). SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. interruput. 15. Wide operation voltage: 4.5 V to 5.5 V at 16.0MHz /32.768 kHz 2.7 V to 5.5 V at 8.0 MHz /32.768 kHz 1.8 V to 5.5 V at 4.2MHz /32.768 kHz Page 2 Release by TMP86CS25ADFG TMP86CS25ADFG 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 RESET (INT5/STOP) P20 (AIN0) P60 (ECIN/AIN1) P61 (ECNT/AIN2) P62 (INT0/AIN3) P63 (STOP2/AIN4) P64 (STOP3/AIN5) P65 (STOP4/AIN6) P66 (STOP5/AIN7) P67 VAREF (SCK0/SEG59 SCK0/SEG59) P17 (SO0/TXD/SEG58 SO0/TXD/SEG58) P16 (SI0/RXD/SEG57 SI0/RXD/SEG57) P15 (MUL6/SEG56 MUL6/SEG56) P14 (MUL5/SEG55 MUL5/SEG55) P13 (MUL4/SEG54 MUL4/SEG54) P12 (SEG53 SEG53) P11 (SEG52 SEG52) P10 (MUL3/SEG51 MUL3/SEG51) P33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 XOUT TEST VDD (XTIN) P21 (XTOUT) P22 SEG0 COM0 COM1 COM2 COM3 COM4 (COM5/MUL4) P34 (COM6/MUL5) P35 (COM7/MUL6) P36 (COM8) P70 (COM9/MUL0) P71 (COM10/MUL1 COM10/MUL1) P72 (COM11/MUL2 COM11/MUL2) P73 (COM12/MUL3 COM12/MUL3) P74 (COM13/SI1 COM13/SI1) P75 (COM14/SO1 COM14/SO1) P76 (COM15/SCK1 COM15/SCK1) P77 V4 V3 V2 V1 C1 C0 VSS XIN 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 SEG24 SEG24 SEG25 SEG25 1.2 Pin Assignment Figure 1-1 Pin Assignment Page 3 SEG26 SEG26 SEG27 SEG27 SEG28 SEG28 SEG29 SEG29 SEG30 SEG30 SEG31 SEG31 SEG32 SEG32 SEG33 SEG33 SEG34 SEG34 SEG35 SEG35 SEG36 SEG36 SEG37 SEG37 SEG38 SEG38 SEG39 SEG39 P50 (SEG40 SEG40) P51 (SEG41 SEG41) P52 (SEG42 SEG42) P53 (SEG43 SEG43) P54 (SEG44 SEG44) P55 (SEG45 SEG45) P56 (SEG46 SEG46) P57 (SEG47 SEG47) P30 (SEG48/MUL0 SEG48/MUL0) P31 (SEG49/MUL1 SEG49/MUL1) P32 (SEG50/MUL2 SEG50/MUL2) 1.3 Block Diagram TMP86CS25ADFG TMP86CS25ADFG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86CS25ADFG TMP86CS25ADFG 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/4) Pin Name Pin Number Input/Output Functions 17 IO O I PORT17 PORT17 LCD segment output 59 Serial Clock I/O 0 18 I O O O PORT16 PORT16 LCD segment output 58 UART data output Serial Data Output 0 P15 SEG57 SEG57 RXD SI0 19 IO O I I PORT15 PORT15 LCD segment output 57 UART data input Serial Data Input 0 P14 SEG56 SEG56 MUL6 20 IO O I PORT14 PORT14 LCD segment output 56 Multi Function 6 pin P13 SEG55 SEG55 MUL5 21 IO O I PORT13 PORT13 LCD segment output 55 Multi Function 5 pin P12 SEG54 SEG54 MUL4 22 IO O I PORT12 PORT12 LCD segment output 54 Multi Function 4 pin P11 SEG53 SEG53 23 IO O PORT11 PORT11 LCD segment output 53 P10 SEG52 SEG52 24 IO I PORT10 PORT10 LCD segment output 52 P22 XTOUT 5 IO O PORT22 PORT22 Resonator connecting pins(32.768kHz) for inputting external clock P21 XTIN 4 IO I PORT21 PORT21 Resonator connecting pins(32.768kHz) for inputting external clock 7 IO I I PORT20 PORT20 STOP mode release signal input External interrupt 5 input P36 MUL6 COM7 84 IO I O PORT36 PORT36 Multi Function 6 pin LCD common output 7 P35 MUL5 COM6 83 IO I I PORT35 PORT35 Multi Function 5 pin LCD common output 6 P34 MUL4 COM5 82 IO I I PORT34 PORT34 Multi Function 4 pin LCD common output 5 P33 SEG51 SEG51 MUL3 25 IO I I PORT33 PORT33 LCD segment output 51 Multi Function 3 pin P32 SEG50 SEG50 MUL2 26 IO O I PORT32 PORT32 LCD segment output 50 Multi Function 2 pin P17 SEG59 SEG59 SCK0 P16 SEG58 SEG58 TXD SO0 P20 STOP INT5 Page 5 1.4 Pin Names and Functions TMP86CS25ADFG TMP86CS25ADFG Table 1-1 Pin Names and Functions(2/4) Pin Name Pin Number Input/Output Functions P31 SEG49 SEG49 MUL1 27 IO O I PORT31 PORT31 LCD segment output 49 Multi Function 1 pin P30 SEG48 SEG48 MUL0 28 IO O I PORT30 PORT30 LCD segment output 48 Multi Function 0 pin P57 SEG47 SEG47 29 IO I PORT57 PORT57 LCD segment output 47 P56 SEG46 SEG46 30 IO O PORT56 PORT56 LCD segment output 46 P55 SEG45 SEG45 31 IO O PORT55 PORT55 LCD segment output 45 P54 SEG44 SEG44 32 IO O PORT54 PORT54 LCD segment output 44 P53 SEG43 SEG43 33 IO O PORT53 PORT53 LCD segment output 43 P52 SEG42 SEG42 34 IO O PORT52 PORT52 LCD segment output 42 P51 SEG41 SEG41 35 IO O PORT51 PORT51 LCD segment output 41 P50 SEG40 SEG40 36 IO O PORT50 PORT50 LCD segment output 40 P67 AIN7 STOP5 15 IO I I PORT67 PORT67 AD converter analog input 7 STOP5 input P66 AIN6 STOP4 14 IO I I PORT66 PORT66 AD converter analog input 6 STOP4 input P65 AIN5 STOP3 13 IO I I PORT65 PORT65 AD converter analog input 5 STOP3 input P64 AIN4 STOP2 12 IO I I PORT64 PORT64 AD converter analog input 4 STOP2 input 11 IO I I PORT63 PORT63 AD converter analog input 3 External interrupt 0 input P62 AIN2 ECNT 10 IO I I PORT62 PORT62 AD converter analog input 2 ECNT input P61 AIN1 ECIN 9 IO I I PORT61 PORT61 AD converter analog input 1 ECIN input P60 AIN0 8 IO I PORT60 PORT60 AD converter analog input 0 92 IO IO O PORT77 PORT77 Serial Clock I/O 1 LCD common output 15 P63 AIN3 INT0 P77 SCK1 COM15 COM15 Page 6 TMP86CS25ADFG TMP86CS25ADFG Table 1-1 Pin Names and Functions(3/4) Pin Name Pin Number Input/Output Functions P76 SO1 COM14 COM14 91 IO O O PORT76 PORT76 Serial Data Output 1 LCD common output 14 P75 SI1 COM13 COM13 90 IO I O PORT75 PORT75 Serial Data Input 1 LCD common output 13 P74 MUL3 COM12 COM12 89 IO IO O PORT74 PORT74 Multi Function 3 pin LCD common output 12 P73 MUL2 COM11 COM11 88 IO O O PORT73 PORT73 Multi Function 2 pin LCD common output 11 P72 MUL1 COM10 COM10 87 IO IO O PORT72 PORT72 Multi Function 1 pin LCD common output 10 P71 MUL0 COM9 86 IO O O PORT71 PORT71 Multi Function 0 pin LCD common output 9 P70 COM8 85 IO O PORT70 PORT70 LCD common output 8 SEG39 SEG39 37 O LCD segment output 39 SEG38 SEG38 38 O LCD segment output 38 SEG37 SEG37 39 O LCD segment output 37 SEG36 SEG36 40 O LCD segment output 36 SEG35 SEG35 41 O LCD segment output 35 SEG34 SEG34 42 O LCD segment output 34 SEG33 SEG33 43 O LCD segment output 33 SEG32 SEG32 44 O LCD segment output 32 SEG31 SEG31 45 O LCD segment output 31 SEG30 SEG30 46 O LCD segment output 30 SEG29 SEG29 47 O LCD segment output 29 SEG28 SEG28 48 O LCD segment output 28 SEG27 SEG27 49 O LCD segment output 27 SEG26 SEG26 50 O LCD segment output 26 SEG25 SEG25 51 O LCD segment output 25 SEG24 SEG24 52 O LCD segment output 24 SEG23 SEG23 53 O LCD segment output 23 SEG22 SEG22 54 O LCD segment output 22 SEG21 SEG21 55 O LCD segment output 21 SEG20 SEG20 56 O LCD segment output 20 SEG19 SEG19 57 O LCD segment output 19 SEG18 SEG18 58 O LCD segment output 18 Page 7 1.4 Pin Names and Functions TMP86CS25ADFG TMP86CS25ADFG Table 1-1 Pin Names and Functions(4/4) Pin Name Pin Number Input/Output Functions SEG17 SEG17 59 O LCD segment output 17 SEG16 SEG16 60 O LCD segment output 16 SEG15 SEG15 61 O LCD segment output 15 SEG14 SEG14 62 O LCD segment output 14 SEG13 SEG13 63 O LCD segment output 13 SEG12 SEG12 64 O LCD segment output 12 SEG11 SEG11 65 O LCD segment output 11 SEG10 SEG10 66 O LCD segment output 10 SEG9 67 O LCD segment output 9 SEG8 68 O LCD segment output 8 SEG7 69 O LCD segment output 7 SEG6 70 O LCD segment output 6 SEG5 71 O LCD segment output 5 SEG4 72 O LCD segment output 4 SEG3 73 O LCD segment output 3 SEG2 74 O LCD segment output 2 SEG1 75 O LCD segment output 1 SEG0 76 O LCD segment output 0 COM4 81 O LCD common output 4 COM3 80 O LCD common output 3 COM2 79 O LCD common output 2 COM1 78 O LCD common output 1 COM0 77 O LCD common output 0 V4 93 I LCD voltage booster pin V3 94 I LCD voltage booster pin V2 95 I LCD voltage booster pin V1 96 I LCD voltage booster pin C1 97 I LCD voltage booster pin C0 98 I LCD voltage booster pin XIN 100 I Resonator connecting pins for high-frequency clock XOUT 1 O Resonator connecting pins for high-frequency clock RESET 6 I Reset signal TEST 2 I Test pin for out-going test. Normally, be fixed to low. VAREF 16 I Analog reference voltage input (High) VDD 3 I Power Supply VSS 99 I 0(GND) Page 8 TMP86CS25ADFG TMP86CS25ADFG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86CS25ADFG TMP86CS25ADFG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86CS25ADFG TMP86CS25ADFG memory address map. 0000H 0000H SFR SFR: 64 bytes 003FH 003FH 0040H 0040H 2048 bytes RAM RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack 083FH 083FH 0F00H 0F00H DBR: 256 bytes DBR 0FFFH 1000H 1000H MaskROM: Data buffer register includes: Peripheral control registers Peripheral status registers LCD display memory Program memory 61440 bytes MaskROM FFC0H Vector table for vector call instructions (32 bytes) FFDFH FFE0H Vector table for interrupts FFFFH (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (MaskROM) The TMP86CS25ADFG TMP86CS25ADFG has a 61440 bytes (Address 1000H 1000H to FFFFH) of program memory (MaskROM ). 2.1.3 Data Memory (RAM) The TMP86CS25ADFG TMP86CS25ADFG has 2048 bytes (Address 0040H 0040H to 083FH 083FH) of internal RAM. The first 192 bytes (0040H 0040H to 00FFH 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Page 9 2. Operational Description 2.2 System Clock Controller TMP86CS25ADFG TMP86CS25ADFG Example :Clears RAM to "00H". (TMP86CS25ADFG TMP86CS25ADFG) LD ; Start address setup LD A, H ; Initial value (00H) setup LD BC, 07FFH 07FFH LD (HL), A INC HL DEC BC JRS SRAMCLR: HL, 0040H 0040H F, SRAMCLR 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register TBTCR 0036H 0036H Clock generator XIN fc High-frequency clock oscillator Timing generator XOUT Standby controller 0038H 0038H XTIN Low-frequency clock oscillator SYSCR1 fs System clocks 0039H 0039H SYSCR2 System control registers XTOUT Clock generator control Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 10 TMP86CS25ADFG TMP86CS25ADFG Low-frequency clock High-frequency clock XIN XOUT XIN XOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator XTIN XTOUT (Open) (c) Crystal (b) External oscillator (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 11 2. Operational Description 2.2 System Clock Controller 2.2.2 TMP86CS25ADFG TMP86CS25ADFG Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 7. LCD 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 and TBTCR, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler and the divider are cleared to "0". fc or fs Main system clock generator Machine cycle counters SYSCK DV7CK High-frequency clock fc Low-frequency clock fs 1 2 fc/4 S A Divider Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 B Multiplexer S B0 B1 A0 Y0 A1 Y1 Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 12 TMP86CS25ADFG TMP86CS25ADFG Timing Generator Control Register TBTCR (0036H 0036H) 7 6 (DVOEN) 5 4 DV7CK (DVOCK) DV7CK 3 (TBTEN) Selection of input to the 7th stage of the divider 2 1 0 (TBTCK) (Initial value: 0000 0000) 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86CS25ADFG TMP86CS25ADFG is placed in this mode after reset. Page 13 2. Operational Description 2.2 System Clock Controller TMP86CS25ADFG TMP86CS25ADFG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 = "1", and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF (Interrupt master enable flag) is "1" (Interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When the IMF is "0" (Interrupt disable), the execution will resume with the instruction which follows the IDLE1 mode start instruction. (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 = "1". When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR, the timing generator starts feeding the clock to all peripheral circuits. When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back again. IDLE0 mode is entered and returned regardless of how TBTCR is set. When IMF = "1", EF6 (TBT interrupt individual enable flag) = "1", and TBTCR = "1", interrupt processing is performed. When IDLE0 mode is entered while TBTCR = "1", the INTTBT interrupt latch is set after returning to NORMAL1 mode. 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 becomes "1", the hardware changes into SLOW2 mode. As the SYSCR2 becomes "0", the hardware changes into NORMAL2 mode. As the SYSCR2 becomes "0", the hardware changes into SLOW1 mode. Do not clear SYSCR2 to "0" during SLOW2 mode. (3) SLOW1 mode This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock. Page 14 TMP86CS25ADFG TMP86CS25ADFG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (4) IDLE2 mode In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode. (5) SLEEP1 mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode. In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (6) SLEEP2 mode The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock. (7) SLEEP0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by setting "1" on bit SYSCR2. When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR, the timing generator starts feeding the clock to all peripheral circuits. When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back again. SLEEP0 mode is entered and returned regardless of how TBTCR is set. When IMF = "1", EF6 (TBT interrupt individual enable flag) = "1", and TBTCR = "1", interrupt processing is performed. When SLEEP0 mode is entered while TBTCR = "1", the INTTBT interrupt latch is set after returning to SLOW1 mode. 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 15 2. Operational Description 2.2 System Clock Controller TMP86CS25ADFG TMP86CS25ADFG IDLE0 mode RESET Reset release Note 2 SYSCR2 = "1" SYSCR1 = "1" SYSCR2 = "1" NORMAL1 mode Interrupt STOP pin input IDLE1 mode (a) Single-clock mode SYSCR2 = "0" SYSCR2 = "1" SYSCR2 = "1" IDLE2 mode NORMAL2 mode Interrupt SYSCR1 = "1" STOP pin input SYSCR2 = "0" SYSCR2 = "1" STOP SYSCR2 = "1" SLEEP2 mode SLOW2 mode Interrupt SYSCR2 = "0" SYSCR2 = "1" SYSCR2 = "1" SLEEP1 mode Interrupt (b) Dual-clock mode SYSCR1 = "1" SLOW1 mode STOP pin input SYSCR2 = "1" Note 2 SLEEP0 mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR setting. Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode Low Frequency RESET NORMAL1 Single clock IDLE1 Oscillation Operate Halt Operate Halt Operate with high frequency Machine Cycle Time 4/fc [s] ­ 4/fc [s] Halt Oscillation Operate with low frequency Oscillation Halt Operate Operate Operate with low frequency SLOW1 4/fs [s] Stop SLEEP0 STOP Reset Stop SLEEP2 SLEEP1 Reset Halt SLOW2 Dual clock Other Peripherals Stop NORMAL2 IDLE2 TBT Operate IDLE0 STOP CPU Core Reset High Frequency Halt Stop Halt Page 16 Halt ­ TMP86CS25ADFG TMP86CS25ADFG System Control Register 1 SYSCR1 7 6 5 4 (0038H 0038H) STOP RELM RETM 3 OUTEN 2 1 0 WUT (Initial value: 0000 00*) STOP STOP mode start 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) R/W RELM Release method for STOP mode 0: Edge-sensitive release 1: Level-sensitive release R/W RETM Operating mode after STOP mode 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode R/W Port output during STOP mode 0: High impedance 1: Output kept R/W OUTEN Return to NORMAL mode 00 3 x 213/fs 216/fc 213/fs 3 x 214/fc 3 x 26/fs 11 Warm-up time at releasing STOP mode 3 x 216/fc 01 10 WUT Return to SLOW mode 214/fc 26/fs R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H 0039H) 7 6 5 4 XEN XTEN SYSCK IDLE 3 2 1 TGHALT 0 (Initial value: 1000 *0*) XEN High-frequency oscillator control 0: Turn off oscillation 1: Turn on oscillation XTEN Low-frequency oscillator control 0: Turn off oscillation 1: Turn on oscillation SYSCK Main system clock select (Write)/main system clock monitor (Read) 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) IDLE CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) TGHALT TG control (IDLE0 and SLEEP0 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W R/W Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator, *; Don't care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR. Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to "0". Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to "0". Note 8: Before setting TGHALT to "1", be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals may be set after IDLE0 or SLEEP0 mode is released. Page 17 2. Operational Description 2.2 System Clock Controller 2.2.4 TMP86CS25ADFG TMP86CS25ADFG Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 to "1". During STOP mode, the following status is maintained. 1. Oscillations are turned off, and all internal operations are halted. 2. The data memory, registers, the program status word and port output latches are all held in the status in effect before STOP mode was entered. 3. The prescaler and the divider of the timing generator are cleared to "0". 4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7]) which started STOP mode. STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the SYSCR1. Do not use any key-on wakeup input (STOP5 to STOP2) for releasing STOP mode in edge-sensitive mode. Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2 pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5 to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: (SYSCR1), 01010000B 01010000B ; Sets up the level-sensitive release mode TEST (P2PRD). 0 ; Wait until the STOP pin input goes low level JRS F, SSTOPH ; IMF 0 DI SET (SYSCR1). 7 ; Starts STOP mode Page 18 TMP86CS25ADFG TMP86CS25ADFG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if JRS F, SINT5 LD (SYSCR1), 01010000B 01010000B port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 DI SET SINT5: (SYSCR1). 7 ; Starts STOP mode RETI VIH STOP pin XOUT pin NORMAL operation STOP operation Warm up Confirm by program that the STOP pin input is low and start STOP mode. NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode. Example :Starting STOP mode from NORMAL mode ; IMF 0 DI LD (SYSCR1), 10010000B 10010000B ; Starts after specified to the edge-sensitive release mode VIH STOP pin XOUT pin NORMAL operation STOP operation Warm up NORMAL operation STOP mode started by the program. STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode Page 19 2. Operational Description 2.2 System Clock Controller TMP86CS25ADFG TMP86CS25ADFG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 in accordance with the resonator characteristics. 3. When the warm-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction. Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 Return to SLOW Mode 12.288 4.096 3.072 1.024 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 20 Page 21 Figure 2-9 STOP Mode Start/Release Divider Instruction execution Program counter Main system clock Oscillator circuit STOP pin input Divider Instruction execution Program counter Main system clock Oscillator circuit 0 Halt Turn off Turn on Turn on n Count up a+3 Warm up a+2 n+2 n+3 n+4 0 (b) STOP mode release 1 Instruction address a + 2 a+4 2 Instruction address a + 3 a+5 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+1 SET (SYSCR1). 7 a+3 3 Instruction address a + 4 a+6 0 Halt Turn off TMP86CS25ADFG TMP86CS25ADFG 2. Operational Description 2.2 System Clock Controller 2.2.4.2 TMP86CS25ADFG TMP86CS25ADFG IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input Reset No No Interrupt request Yes "0" IMF "1" (Interrupt release mode) Normal release mode Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 22 TMP86CS25ADFG TMP86CS25ADFG · Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 to "1". · Release the IDLE1/2 and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode. These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and SLEEP1/2 modes, the SYSCR2 is automatically cleared to "0" and the operation mode is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes. IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. (1) Normal release mode (IMF = "0") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to "0" by load instructions. (2) Interrupt release mode (IMF = "1") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 23 Page 24 Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Watchdog timer Instruction execution Program counter Interrupt request Main system clock Watchdog timer Instruction execution Program counter Interrupt request Main system clock Watchdog timer Instruction execution Program counter Interrupt request Main system clock Halt Halt Halt Halt Operate Operate Operate Acceptance of interrupt Instruction address a + 2 a+4 (b) IDLE1/2 and SLEEP1/2 modes release Interrupt release mode a+3 Normal release mode a+3 (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Operate SET (SYSCR2). 4 a+2 Halt a+3 2.2 System Clock Controller 2. Operational Description TMP86CS25ADFG TMP86CS25ADFG TMP86CS25ADFG TMP86CS25ADFG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input Yes Reset No No TBT source clock falling edge Yes No TBTCR = "1" Yes No TBT interrupt enable Yes (Normal release mode) No IMF = "1" Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 25 2. Operational Description 2.2 System Clock Controller TMP86CS25ADFG TMP86CS25ADFG · Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 to "1". · Release the IDLE0 and SLEEP0 modes IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode. These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag of TBT and TBTCR. After releasing IDLE0 and SLEEP0 modes, the SYSCR2 is automatically cleared to "0" and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR is set to "1", INTTBT interrupt latch is set to "1". IDLE0 and SLEEP0 modes can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR setting. (1) Normal release mode (IMF·EF6·TBTCR = "0") IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR. After the falling edge is detected, the program operation is resumed from the instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR is set to "1", INTTBT interrupt latch is set to "1". (2) Interrupt release mode (IMF·EF6·TBTCR = "1") IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR and INTTBT interrupt processing is started. Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR. Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started. Page 26 Halt Page 27 Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Watchdog timer Instruction execution Program counter TBT clock Halt Halt Watchdog timer Main system clock Halt Instruction execution Program counter TBT clock Main system clock Watchdog timer Instruction execution Program counter Interrupt request Main system clock a+3 Halt Operate Operate (b) IDLE and SLEEP0 modes release Interrupt release mode a+3 Normal release mode a+3 Acceptance of interrupt Instruction address a + 2 a+4 (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Operate SET (SYSCR2). 2 a+2 TMP86CS25ADFG TMP86CS25ADFG 2. Operational Description 2.2 System Clock Controller 2.2.4.4 TMP86CS25ADFG TMP86CS25ADFG SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 to switch the main system clock to the low-frequency clock for SLOW2 mode. Next, clear SYSCR2 to turn off high-frequency oscillation. Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 1 (Switches the main system clock to the low-frequency clock for SLOW2) CLR (SYSCR2). 7 ; SYSCR2 0 (Turns off high-frequency oscillation) Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET (SYSCR2). 6 ; SYSCR2 1 LD (TC3CR), 43H ; Sets mode for TC4, 3 (16-bit mode, fs for source) LD (TC4CR), 05H ; Sets warming-up counter mode LDW (TTREG3), 8000H 8000H ; Sets warm-up time (Depend on oscillator accompanied) ; IMF 0 DI SET (EIRH). 3 ; IMF 1 EI SET ; Enables INTTC4 (TC4CR). 3 ; Starts TC4, 3 CLR (TC4CR). 3 ; Stops TC4, 3 SET (SYSCR2). 5 ; SYSCR2 1 : PINTTC4: (Switches the main system clock to the low-frequency clock) CLR (SYSCR2). 7 ; SYSCR2 0 (Turns off high-frequency oscillation) RETI : VINTTC4: DW PINTTC4 ; INTTC4 vector table Page 28 TMP86CS25ADFG TMP86CS25ADFG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2 to switch the main system clock to the high-frequency clock. SLOW mode can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET (SYSCR2). 7 ; SYSCR2 1 (Starts high-frequency oscillation) LD (TC3CR), 63H ; Sets mode for TC4, 3 (16-bit mode, fc for source) LD (TC4CR), 05H ; Sets warming-up counter mode LD (TTREG4), 0F8H ; Sets warm-up time ; IMF 0 DI SET (EIRH). 3 ; IMF 1 EI SET ; Enables INTTC4 (TC4CR). 3 ; Starts TC4, 3 CLR (TC4CR). 3 ; Stops TC4, 3 CLR (SYSCR2). 5 ; SYSCR2 0 : PINTTC4: (Switches the main system clock to the high-frequency clock) RETI : VINTTC4: DW PINTTC4 ; INTTC4 vector table Page 29 Page 30 Figure 2-14 Switching between the NORMAL2 and SLOW Modes SET (SYSCR2). 7 SET (SYSCR2). 5 SLOW1 mode Instruction execution XEN SYSCK Highfrequency clock Lowfrequency clock Main system clock NORMAL2 mode Instruction execution XEN SYSCK Highfrequency clock Lowfrequency clock Main system clock (b) Switching to the NORMAL2 mode Warm up during SLOW2 mode CLR (SYSCR2). 5 (a) Switching to the SLOW mode SLOW2 mode CLR (SYSCR2). 7 NORMAL2 mode SLOW1 mode Turn off 2.2 System Clock Controller 2. Operational Description TMP86CS25ADFG TMP86CS25ADFG TMP86CS25ADFG TMP86CS25ADFG 2.3 Reset Circuit The TMP86CS25ADFG TMP86CS25ADFG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when power is turned on. Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Initial Value Program counter (PC) (SP) Not initialized Initial Value (FFFEH) Stack pointer On-chip Hardware General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Prescaler and divider of timing generator 0 Not initialized Jump status flag (JF) Not initialized Zero flag (ZF) Not initialized Carry flag (CF) Not initialized Half carry flag (HF) Not initialized Sign flag (SF) Not initialized Overflow flag (VF) Not initialized (IMF) 0 (EF) 0 (IL) Watchdog timer 0 Enable Output latches of I/O ports Control registers Interrupt latches 2.3.1 Not initialized RAM Interrupt individual enable flags Refer to each of control register LCD data buffer Interrupt master enable flag Refer to I/O port circuitry Not initialized External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 31 2. Operational Description 2.3 Reset Circuit TMP86CS25ADFG TMP86CS25ADFG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 is set to "1"), DBR or the SFR area, address trap reset will be generated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz). Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution Reset release JP a Instruction at address r Address trap is occurred Internal reset maximum 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR, DBR or on-chip RAM (WDTCR1 = "1") space. Note 2: During reset release, reset vector "r" is read out, and an instruction at address "r" is fetched and decoded. Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 System clock reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 and SYSCR2 simultaneously to "0". - In case of clearing SYSCR2 to "0", when the SYSCR2 is "0". - In case of clearing SYSCR2 to "0", when the SYSCR2 is "1". The reset time is maximum 24/fc (1.5 µs at 16.0 MHz). Page 32 TMP86CS25ADFG TMP86CS25ADFG Page 33 2. Operational Description 2.3 Reset Circuit TMP86CS25ADFG TMP86CS25ADFG Page 34 TMP86CS25ADFG TMP86CS25ADFG 3. Interrupt Control Circuit The TMP86CS25ADFG TMP86CS25ADFG has a total of 20 interrupt sources excluding reset, of which 4 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Factors Internal/External Enable Condition Interrupt Latch Vector Address Priority (Reset) Non-maskable ­ FFFE 1 Internal INTSWI (Software interrupt) Non-maskable ­ FFFC 2 Internal INTUNDEF (Executed the undefined instruction interrupt) Non-maskable ­ FFFC 2 Internal INTATRAP (Address trap interrupt) Non-maskable IL2 FFFA 2 Internal INTWDT (Watchdog timer interrupt) Non-maskable IL3 FFF8 2 External INT0 IMF· EF4 = 1, INT0EN = 1 IL4 FFF6 5 External INT1 IMF· EF5 = 1 IL5 FFF4 6 Internal INTTBT IMF· EF6 = 1 IL6 FFF2 7 External INT2 IMF· EF7 = 1 IL7 FFF0 8 Internal INTTC1 IMF· EF8 = 1 IL8 FFEE 9 Internal INTRXD IMF· EF9 = 1, IL9ER = 0 IL9 FFEC 10 Internal INTSIO0 IMF· EF9 = 1, IL9ER = 1 Internal INTTXD IMF· EF10 = 1, IL10ER IL10ER = 0 IL10 FFEA 11 Internal INTSIO1 IMF· EF10 = 1, IL10ER IL10ER = 1 Internal INTTC4 IMF· EF11 = 1 IL11 FFE8 12 Internal INTTC6 IMF· EF12 = 1 IL12 FFE6 13 Internal INTADC IMF· EF13 = 1 IL13 FFE4 14 IL14 FFE2 15 IL15 FFE0 16 External INT3 IMF· EF14 = 1, IL14ER IL14ER = 0 Internal INTTC3 IMF· EF14 = 1, IL14ER IL14ER = 1 External INT5 IMF· EF15 = 1, IL15ER IL15ER = 0 Internal INTTC5 IMF· EF15 = 1, IL15ER IL15ER = 1 Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 to "0" (It is set for the "reset request" after reset is cancelled). For details, see "Address Trap". Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1 to "0" (It is set for the "Reset request" after reset is released). For details, see "Watchdog Timer". 3.1 Interrupt latches (IL15 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 003CH 003CH and 003DH 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Page 35 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CS25ADFG TMP86CS25ADFG Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches ; IMF 0 DI LDW (ILL), 1110100000111111B 1110100000111111B ; IL12, IL10 to IL6 0 ; IMF 1 EI Example 2 :Reads interrupt latchess WA, (ILL) ; W ILH, A ILL TEST (ILL). 7 ; if IL7 = 1 then jump JR F, SSET LD Example 3 :Tests interrupt latches 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH 003AH and 003BH 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". 3.2.2 Individual interrupt enable flags (EF15 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor- Page 36 TMP86CS25ADFG TMP86CS25ADFG mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF ; IMF 0 DI LDW : (EIRL), 1110100010100000B 1110100010100000B ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. : ; IMF 1 EI Example 2 :C compiler description example unsigned int _io (3AH) EIRL; /* 3AH shows EIRL address */ _DI(); EIRL = 10100000B 10100000B; : _EI(); Page 37 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CS25ADFG TMP86CS25ADFG Interrupt Latches (Initial value: 00000000 000000*) ILH,ILL (003DH 003DH, 003CH 003CH) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 IL15 IL14 IL13 IL12 IL11 IL10 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 ILH (003DH 003DH) IL15 to IL2 1 0 ILL (003CH 003CH) at RD 0: No interrupt request Interrupt latches at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) 1: Interrupt request R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000*0) EIRH,EIRL (003BH 003BH, 003AH 003AH) 15 14 13 12 11 10 9 8 7 6 5 4 EF15 EF14 EF13 EF12 EF11 EF10 EF9 EF8 EF7 EF6 EF5 EF4 EIRH (003BH 003BH) EF15 to EF4 IMF 3 2 1 0 IMF EIRL (003AH 003AH) Individual-interrupt enable flag (Specified for each bit) 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Interrupt master enable flag 0: 1: Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 38 TMP86CS25ADFG TMP86CS25ADFG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated. The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL. 1. INTRXD and INTSIO0 share the interrupt source level whose priority is 10. 2. INTTXD and INTSIO1 share the interrupt source level whose priority is 11. 3. INT3 and INTTC3 share the interrupt source level whose priority is 15. 4. INT5 and INTTC5 share the interrupt source level whose priority is 16. Interrupt source selector INTSEL (003EH 003EH) 7 6 5 4 3 2 1 0 - IL9ER IL10ER IL10ER - - - IL14ER IL14ER IL15ER IL15ER (Initial value: *00* *00) IL9ER Selects INTRXD or INTSIO0 0: INTRXD 1: INTSIO0 R/W IL10ER IL10ER Selects INTTXD or INTSIO1 0: INTTXD 1: INTSIO1 R/W IL14ER IL14ER Selects INT3 or INTTC3 0: INT3 1: INTTC3 R/W IL15ER IL15ER Selects INT5 or INTTC5 0: INT5 1: INTTC5 R/W 3.4 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Page 39 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86CS25ADFG TMP86CS25ADFG Interrupt service task 1-machine cycle Interrupt request Interrupt latch (IL) IMF Execute instruction Execute instruction a-1 PC SP a Execute instruction Interrupt acceptance a+1 b a b+1 b+2 b + 3 n-1 n-2 n Execute RETI instruction c+2 c+1 a n-2 n-1 n-3 a+1 a+2 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address FFF2H 03H FFF3H Entry address D2H D203H D203H 0FH D204H D204H Vector 06H Interrupt service program Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved