TMP04CH00FXXX JTMP04CH00XXXS SEG60 COM10 QFP100 S59/COM10 S60/COM9 0001H 0002H - Datasheet Archive

 

TOSHIBA CMOS Digital Linear Integrated Circuit Silicon Monolithic TMP04CH00FXXX (JTMP04CH00XXXS) CMOS 4 bit LL Microcontroller

 

TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) TOSHIBA CMOS Digital Linear Integrated Circuit Silicon Monolithic TMP04CH00FXXX TMP04CH00FXXX (JTMP04CH00XXXS JTMP04CH00XXXS) CMOS 4 bit LL Microcontroller (LL: Low power consumption & Low voltage operation) The TMP04CH00FXXX TMP04CH00FXXX is a high-performance microcontroller designed to be in a variety of low-voltage products. It is a 4 bit CMOS LL microcontroller with integrated a 4 bit high-performance CPU, memory (static work RAM, data RAM and program ROM). LCD display LL controller driver, and a multi-function timer into a single chip. The basic features are as follows. Features Weight: 1.65 g (typ.) · Number of instructions: 56 · Minimum instruction execution time: 61 µs (at 32.768 kHz) 1 µs (at 2 MHz/3.0 V) · Oscillating circuit : low speed-crystal oscillator (32.768 kHz)/internal CR (33 kHz at 1.5 V) high speed-crystal oscillator (2 MHz at 3.0 V)/external CR (200 kHz at 1.5 V) · Built-in ROM size : 16 K words (1 word = 16 bits) · Built-in RAM size Work RAM Data RAM : : 512 × 4 bits : 6 K bits · Input pins : 8 pins (with interrupts) · I/O pins : 8 pins · Output pins : 1 pin (Buzzer) · Interruption : 2 external system (input pins, general purpose I/O pin) 2 internal system (timer/counter, timings) · Timer : 8 bits × 2 ch or 16 bits × 1 ch (software-selectable) · LCD display driver controller: 60 seg × 8 com Mask option 58 seg × 10 com Mask option · Built-in LCD driver power circuit · Watchdog timer : Timer/Counter can be used as Watch Dog Timer · Supply voltage : 1.5/3.0 V (typ.) Mask option 1 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) TEST XHIN XHOUT XLIN XLOUT BRESET Test circuit Oscillator control Reset T4X CORE Work RAM (2 K bits) ROM (16 K words) Display RAM Data RAM (6 K bits) LCD control SEG1 to SEG60 SEG60 COM1 to COM10 COM10 V4 Quadrupler Interrupt control V3 V2 V1 V1 C1 C2 VXT Timer (8 bit/16 bit) Voltage reglater VSS VDD IN1 to IN4 IO01 to IO04 IO11 to IO14 IO21 to IO24 I/O port (IN × 8, I/O × 8) BZ control Figure 1 BZ Block diagram 2 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Pin Configuration 1. Pin Assignment 80 51 81 50 QFP100 QFP100 100 31 1 30 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 V1 26 IO21 51 S22 76 S47 2 C1 27 IO22 52 S23 77 S48 3 C2 28 IO23 53 S24 78 S49 4 VSS 29 IO24 54 S25 79 S50 5 VXT 30 S1 55 S26 80 S51 6 BRESET 31 S2 56 S27 81 S52 7 XLIN 32 S3 57 S28 82 S53 8 XLOUT 33 S4 58 S29 83 S54 9 VDD 34 S5 59 S30 84 S55 10 XHIN 35 S6 60 S31 85 S56 11 XHOUT 36 S7 61 S32 86 S57 12 TEST 37 S8 62 S33 87 S58 13 BZ 38 S9 63 S34 88 S59/COM10 S59/COM10 14 IN1 39 S10 64 S35 89 S60/COM9 S60/COM9 15 IN2 40 S11 65 S36 90 COM8 16 IN3 41 S12 66 S37 91 COM7 17 IN4 42 S13 67 S38 92 COM6 18 IO01 43 S14 68 S39 93 COM5 19 IO02 44 S15 69 S40 94 COM4 20 IO03 45 S16 70 S41 95 COM3 21 IO04 46 S17 71 S42 96 COM2 22 IO11 47 S18 72 S43 97 COM1 23 IO12 48 S19 73 S44 98 V4 24 IO13 49 S20 74 S45 99 V3 25 IO14 50 S21 75 S46 100 V2 3 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 2. Pin Description Pin Name Function VDD Power supply (+) VSS Power supply (-) VXT Voltage regulator1 output (output for only the mask option 3.0 V type) V1 Voltage regulator2 output V2 to V4 Boosted voltage output C1, C2 Capacitor pin for LCD booster XHIN, XHOUT Crystal/resister connection pin for high speed oscillator XLIN, XLOUT Crystal connection pin for low speed oscillator IN1 to IN4 Input port (with interruption) IO01 to IO04 Input port (with interruption) IO11 to IO14 I/O port IO21 to IO24 I/O port SEG1 to SEG60 SEG60 LCD segment output COM1 to COM10 COM10 LCD common output BZ Buzzer output BRESET Reset input (low active) TEST Test input 4 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Memory Map 1. Program ROM Program ROM consists of 16 bits 1 word. Op-code and operand are executed in one word units. Program ROM consists of 4 K words per page. The internal program ROM area is 4 pages (16 K words). This program ROM area can be used for constant data ROM. In this case, it can be used in byte units (1 byte = 8 bits). 1 word Upper 8 bit Lower 8 bit 000H 0001H 0001H INT0 0002H 0002H INT1 0003H 0003H Page 0 RESET START INT2 INT. 0004H 0004H INT3 Entry Address 0005H 0005H INT4 0006H 0006H 0007H 0007H 0FFFH 1000H 1000H Page 1 to 3 3FFFH 15 Figure 2 Note: 8 7 0 Program memory map Use the CALL instruction to write the interrupt entry address. Write NOP for unused interrupts. Example: CALL A NOP CALL B NOP NOP NOP NOP ; INT0 ; INT1 ; INT2 ; INT3 ; INT4 ; INT5 ; INT6 5 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 2. Work RAM Address Bank 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Page F E D C B A 9 8 7 6 5 4 3 2 1 0 63 55 47 39 31 23 15 7 62 54 46 38 30 22 14 6 61 53 45 37 29 21 13 5 60 52 44 36 28 20 12 4 59 51 43 35 27 19 11 3 58 50 42 34 26 18 10 2 57 49 41 33 25 17 9 1 56 48 40 32 24 16 8 0 Bank 1 No. Figure 3 Stack area Work RAM 6 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Work RAM consists of 512 × 4 bits. R/W is performed at the address specified by bellows. (1) Indirectly addressing mode (Figure 4 (a) DMB in F-reg, H, L-reg specify the Work RAM address. (DMB: bank, H-reg : page, L-reg: address) LD A, M: A RAM (HL) DMB Directly addressing mode (Figure 4 (b) Immediate data (8 bits) in instruction specify the Work RAM page and address. Bank is specified by DMB in F-reg. LDI 2CH, 0AH: RAM (2CH) AH Indirectly addressing Instruction field xxxx xxxx or xxxx DMB RAM address (b) (3) LR RAM address (a) (2) HR xxxx xxxx xxxx Directly addressing Instruction field Index addressing mode (Figure 4 (c) ) Address (L-reg) is specified by the immediate data (4 bits) in instruction, and the other immediate data specify page. LDRI 4H, 3H: RAM (HL + 4H) RAM (3H, L) L L + 1, A A - 1 yyyy + LR zzzz RAM address (c) Index addressing Figure 4 Addressing mode BANK0, PAGE8 to F area can be used as Stack area. When using the "CALL/CALLS" instruction or start the interruption routine, the data of program counter and Program memory bank are stored in Stack area. Then, using "RET" instruction, program return according to those data. And, using "PUSH" instruction, 8 bits data in a pair register can be stored in Stack area. Then, using "POP" instruction, those data are returned to the register. Maximum Stack area is 64 (0 to 63), and each Stack area consist of 8 bits. 7 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 3. Data RAM TMP04CH00FXXX TMP04CH00FXXX has 6 K bits Data RAM (256AD 256AD × 3 bank × 8 bit), and addressing and data read/write is done by Register file, as follows. When the data is read from Data RAM/written in Data RAM, CE1 (PB0) is needed to set 1. (PB0: Register file Page 3, AD0) PB0 3 2 1 0 MSB LSB CE1 Addressing is decided by RAB1 to RAB2 (PB3), RAC1 to RAC4 (PB5), RAR1 to RAR4 (PB4) 3 2 1 0 RAB2 RAB1 : PB4 RAR4 RAR3 RAR2 RAR1 : PB5 RAC4 RAC3 RAC2 RAC1 MSB BANK : PB3 ROW COLMN LSB Data is read/written by 8 bits which is set in RAD1 to RAD8 (PB6, PB7). To read from/written into Data RAM, only 8 bits transference instruction can be used. MSB 2 1 0 PB7 RAD8 RAD7 RAD6 RAD5 PB6 CAUTION: 3 RAD4 RAD3 RAD2 LSB RAD1 When "HALT" instruction is excuted for the next instruction of transference the data to Data RAM, the data of Data RAM is broken. Also, data may be destroyed if the HALT instruction is executed while CE1 is set to 1. Therefore, be sure to set CE1 to CE0 before executing the HALT instruction. RAD1 to RAD8 (PB6, PB7) are valid for only 8-bit transfer instructions. Do not use the 4-bit transfer instructions. 4. Display RAM TMP04CH00FXXX TMP04CH00FXXX has 600 bits Display RAM (60 seg × 8 com/58 seg × 10 com), and addressing and data read/write is decided by Register file, as follows. When the data is read from/written into Display RAM, DRCE (PC6-bit2) is needed to be 1. MSB 2 1 0 PC6 3 DRCE DON DSTA LSB Addressing is decided by DRR1 to DRR4 (PD4), DRC1 to DRC3 (PD5) (LSB is DRR1, and MSB is DRC3) MSB 3 2 1 0 PD5 DRC3 DRC2 DRC1 PD4 DRR4 DRR3 DRR2 DRR1 8 LSB 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Data is read/written by 8 bits which is set in DRD1 to DRD 8 (PD6, PD7). To read from/written into DISPLAY, only 8 bits transference instruction can be used. MSB 3 2 1 0 LSB PD7 DRD8 DRD7 DRD6 DRD5 PD6 DRD4 DRD3 DRD2 DRD1 When the display duty is selected 1/8, S1 to S60 are used as segment output and display data is read from/written into Display RAM which address is 00H to 03BH. Also, when using with a 1/10 duty cycle, segments are used from S1 up to S58 and the data COM9 and COM10 COM10 are written to and read from addresses beginning with 40H via DRD1 and DRD2. CAUTION: 1. 2. When "HALT" instruction is executed for the next instruction of the transference the data to Display RAM, the data of Display RAM is broken. When "HALT" instruction is executed during DRCE is 1, the data of Display RAM is broken. Therefore, be sure to set DRCE to 0 before executing the HALT instruction. DRD1 to DRD8 (PD6, PD7) are valid for only 8-bit transfer instructions. Do not use the 4-bit transfer instructions. DRD 8 00H 01H 02H 3AH 3BH 3CH 3DH 3EH 3FH DRD 7 DRD 6 DRD 5 DRD 4 DRD 2 DRD 1 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 S1 S2 S3 S59 S60 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 COM10 COM10 COM9 40H 41H 7AH 7BH 7CH 7DH 7EH 7FH DRD 3 Do not use. This area does not exist actually. S59 S60 1 1 1 1 Figure 5 S1 S2 1 1 1 1 Display RAM 9 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) DSTA PC6 DON DRCE LATCH LATCH LATCH Read data from PD6/PD7 (8-bit transfer) CE Write data to PD6/PD7 (8-bit transfer). READ WRITE PD5 PD4 DRC3 DRC2 DRC1 DRR4 DRR3 DRR2 DRR1 PD7 PD6 DRD8 DRD7 DRD6 DRD5 DRD4 DRD3 DRD2 DRD1 LATCH LATCH LATCH LATCH LATCH LATCH LATCH A6 A5 A4 A3 A2 ADDRESS A1 A0 D7 D6 D5 D4 D3 DATA D2 D1 D0 Display RAM COMMON SELECT S60 OUT SEGMENT DRIVER60 DRIVER60 COMMON DRIVER1 S59 OUT SEGMENT DRIVER59 DRIVER59 ON COMMON DRIVER2 S58 OUT SEGMENT DRIVER58 DRIVER58 Booster clock V3 COMMON DRIVER8 S3 OUT SEGMENT DRIVER3 SEG/COM = VSS COMMON DRIVER9 S2 OUT SEGMENT DRIVER2 COMMON/SEGMENT Driver timing generator circuit COMMON DRIVER10 DRIVER10 S1 OUT DUTY 4 kHz V4 SEGMENT DRIVER1 Mask option fL (Low-speed clock) Output gate V2 C1 C2 Booster circuit for LCD bias (Quadrupler) Mask option V1 VDD VSS Voltage regulator S1 S2 S58 S3 Figure 6 S59 S60 /COM10 /COM10 /COM9 COM8 COM2 COM1 LCD driver 10 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Register File Register files consist of (1) general-purpose registers, (2) system registers, and (3) peripheral I/O registers. Figure 6 shows the overall configuration of register files. 1. General Register 1. Flag Register: MSB R00 3 DMB F-Register (PAGE/AD = 0/0) F-Register 2 1 (0) ZF 0 LSB CF CF : Carry Flag ZF : Zero Flag (0) : Not use DMB : Work RAM Bank 2. Accumulater Register: A-Register (PAGE/AD = 0/1) Accumulator for arithmetic operations. When consecutive instructions are executed, used as a counter register. 3. H.L Register (PAGE/AD = 0/3 to 2) H.L Register are used for Work RAM address setting with DMB. MSB R03 3 HR3 H-Register 2 1 HR2 HR1 0 LSB HR0 Work RAM page MSB R02 3 LR3 L-Register 2 1 LR2 LR1 0 LSB LR0 Work RAM address 4. Bank Register (PAGE/AD = 0/7): B-Register B-Register is used for ROM page. MSB R07 3 2 1 0 3 2 1 LSB 0 0000 = Page 0 0001 = Page 1 0010 = Page 2 0011 = Page 3 5. E-Register, D-Register, P-Register (B-Register) (PAGE/AD = 0/4, 0/5, 0/6, 0/7) General purpose register. When using ROM as Data Table Function, B, P, D, E-Register are used for ROM address setting. (Data table function: user can use ROM area for store the constant, and can access those constant by LDBL and LDBH instruction.) 11 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 2. System Registers 1. Stack pointer (PAGE/AD = 1/0, 1/1) The stack pointer shows the location (63 to 0) in the stack area in work RAM. MSB R11 2. 0 SP2 SP1 3 2 1 0 SP32 SP16 SP8 Interrupt Enable/Disable Registers (PAGE/AD = 1/2, 1/3) Enable/disable interrupts. There are five interrupt vectors (INT0 to INT4). Writing data in the bit corresponding to an interrupt enables/disables the interrupt. The details are described in the section on peripheral circuits. MSB R13 2 1 0 INT1 INT0 (0) 3 2 1 0 MSB 3 INT2 R12 3. 1 MSB 2 SP4 R10 3 INT4 INT3 Input/Output Registers (PAGE/AD = 1/4, 1/5) Used for the input/output pins (IO11 to IO14, IO21 to IO24). Using the bit that corresponds to a pin, output data can be set or input data can be read. The details are described in the section on peripheral circuits. MSB MSB R15 2 1 0 IO14 R14 3 IO13 IO12 IO11 3 2 1 0 IO24 IO23 IO22 IO21 12 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 3. Peripheral I/O Registers Registers used to control peripheral circuits specific to the product are allocated to pages 2 to 7. The details are described in the section on peripheral circuits. Note: A precaution relating to Writes to System Registers/Peripheral I/O Registers. Writing to System Register and I/O Registers is performed in synchronization with W. Because rising edges of W coincides with the timing at which Write data is output on the data bus, it is possible that incorrect data is output to the peripheral circuits for a very short period of time. Please take this into account when programming. Data bus D Q LATCH C D Q LATCH Peripheral circuits C D Q LATCH C D W Q LATCH C CLK F0 F1 F2 F3 Register write timing (W) Write data Outputs incorrect data. 13 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Address 0 1 2 3 0 4 5 2 6 7 4 6 8 bit Address Page (RFB) LOWER4BIT R/W MSB Read UPPER4BIT Write Read Write L4BIT Read Write H4BIT Read Write L4BIT Read Write H4BIT Read Write L4BIT Read Write H4BIT Read Write BIT 3 BIT 2 F A L H E D P B BIT 1 0 REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER 0 LSB BIT 0 MSB BIT 3 INT2 IOD14 IOD14 IOO14 IOO14 IOD24 IOD24 1 BIT 2 STACK INT1 IOD13 IOD13 IOO13 IOO13 IOD23 IOD23 IOO24 IOO24 IOO23 IOO23 (R1x) BIT 1 POINTER (SP) INT0 INT4 IOD12 IOD12 IOO12 IOO12 IOD22 IOD22 IOO22 IOO22 0 INT3 IOD11 IOD11 IOO11 IOO11 IOD21 IOD21 IOO21 IOO21 LSB BIT 0 MSB BIT 3 IND4 IOD04 IOD04 BIT 2 IND3 IOD03 IOD03 LOWCP RST3 2 (PAx) 0 RST4 BIT 1 IND2 IOD02 IOD02 CPMODE2 RST2 LSB BIT 0 IND1 IOD01 IOD01 CPMODE1 RST1 MSB BIT 3 RAR4 RAC4 RAD4 RAD8 3 BIT 2 RAR3 RAC3 RAD3 RAD7 (PBx) BIT 1 RAB2 RAR2 RAC2 RAD2 RAD6 RAB1 RAR1 RAC1 RAD1 RAD5 LSB BIT 0 MSB BIT 3 CE1 IIN4 IIE4 4 BIT 2 ESELT IIN3 IIE3 (PCx) BIT 1 ESELIO IIN2 IIE2 LSB BIT 0 ESELI IIN1 IIE1 MSB BIT 3 TI4 5 BIT 2 TI3 4/8 TIR3 TIE3 DRR3 DRC3 DRD3 DRD7 (PDx) BIT 1 TI2 16/32 TIR2 TIE2 DRR2 DRC2 DRD2 DRD6 128/256 TIR1 TIE1 DRR1 DRC1 DRD1 DRD5 1/2 DRCE DON IOIE0 TIR4 LSB BIT 0 TI1 MSB BIT 3 TCR14 TCR14 SET14 SET14 TCR18 TCR18 SET18 SET18 BIT 2 TCR13 TCR13 SET13 SET13 TCR17 TCR17 SET17 SET17 CKS13 CKS13 6 (PEx) TIE4 DSTA DRR4 TC1EN BIT 1 TCR12 TCR12 SET12 SET12 TCR16 TCR16 SET16 SET16 CKS12 CKS12 CMPEN1 BIT 0 TCR11 TCR11 SET11 SET11 TCR15 TCR15 SET15 SET15 CKS11 CKS11 BIT 3 TCR24 TCR24 SET24 SET24 TCR28 TCR28 SET28 SET28 TCPS TC2EN 7 BIT 2 TCR23 TCR23 SET23 SET23 TCR27 TCR27 SET27 SET27 CKS23 CKS23 (PFx) BIT 1 TCR22 TCR22 SET22 SET22 TCR26 TCR26 SET26 SET26 CKS22 CKS22 BIT 0 TCR21 TCR21 SET21 SET21 TCR25 TCR25 SET25 SET25 BZ3 WDT1 MSB P1 DRD8 2/4 K TC1R LSB DRD4 P2 CKS21 CKS21 LSB Figure 7 Note: TCI1E TCI1R BZ2 BZ1 TC2R CMPEN2 TCI2E TCI2R Register file Blank columns are indeterminate. 14 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Peripheral Circuit Each peripheral circuits can be accessed (Read/Write/Circuit setting) by Register files. 1. Oscillator Block MSB 2 PA6 3 LOWCP 1 0 LSB CPMODE2 CPMODE1 The CPU clock is generated by the asynchronous oscillator switching circuit which has low-speed and high-speed clock oscillator circuit. This block also provides the clock for the timer circuit, LCD driver, Quadrupler. Oscillation mode is controlled by Register files "CPMODE1" and "CPMODE2" (PAGE/AD = 2/6), as follows. Low- Highspeed speed OSC OSC System CP Mode Name CPMODE 1 CPMODE 2 0 0 OFF OFF OFF (CPM0) 1 0 ON OFF Low-speed (CPM1) 0 1 OFF ON High-speed (CPM2) 1 1 ON ON High-speed (CPM3) CPMODE 1, 2 are initially 1 (CPM3). "LOWCP" is the display clock control bit. When "LOWCP" is set to 1, Low OSC clock is supplied to LCD circuit. "LOWCP" is initially "0". Even if LOWCP is set to 1, clock cannot be occupied to display circuit during Low-speed OSC stopped, and display cannot be shown. Low-speed OSC circuit can select X'tal or internal CR oscillation by Mask option. High-speed OSC circuit can select X'tal or external CR oscillation by Mask option. Setting a register to CPM1 and executing a HALT instruction sets the mode to Halt (system CP off, high-speed oscillator off, low-speed oscillator on). Setting a register to CPM0 and executing a HALT instruction sets the mode to Stop (system CP off, high-speed oscillator and low-speed oscillators off). Even if, mode is changed to MODE 0 from MODE 1/2/3, there are no changing until use "HALT" instruction. The High/Low-speed OSC circuit has WARM UP function. The warm-up function disables the crystal oscillator as the system clock from when the crystal oscillator starts oscillation to when the frequency stabilizes. The warm-up circuit in the high-speed crystal oscillator circuit consists of a 15-stage binary counter. The warm-up time is 16,384 pulses of the high-speed clock. The warm-up circuit in the low-speed crystal oscillator circuit consists of a 9-stage binary counter. The warm-up time is 256 pulses of the high-speed clock. The low-speed oscillation does not have enough warm-up time, therefore, when the oscillation is started, software need to make warming up time enoughly. Set the warm-up time by software to approx. 500 ms as standard. When the System CP is changed between Low and High (CPM1CPM2/3 or CPM2CPM1), changing System CP waits to finish the warming up time. Also that until the system CP is changed, instructions are executed with the previous system CP. If the CR oscillator is selected as the high- or low-speed oscillator circuit, the warm-up function is disabled. 15 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Reset START Mode High-Speed Clock: ON Low-Speed Clock: ON System Clock: STOP Interrupt CPM0 (STOP Mode) High-Speed Clock: OFF Low-Speed Clock: OFF System Clock: STOP Automatically shifts to CPM3 mode. (Note 2) High-Speed Clock warm-up Set the oscillation mode to CPM3. (Note 2) High-Speed Clock warm-up CPM3 Mode High-Speed Clock: ON Low-Speed Clock: ON System Clock: High-Speed Set the oscillation mode to CPM2. Set the oscillation mode to CPM1 Set the oscillation mode (Note 1) Low-Speed Clock to CPM3. warm-up Set the oscillation mode to CPM2. Set the oscillation (Note 2) High-Speed Clock warm-up mode to CPM0, then execute CPM1 CPM2 HALT instruction. High-Speed Clock: OFF High-Speed Clock: ON Low-Speed Clock: ON System Clock: Low-Speed Low-Speed Clock: OFF System Clock: High-Speed Set the oscillation mode to CPM1. (Note1) Low-Speed Clock warm-up Interrupt Executes HALT instruction. HALT Mode High-Speed Clock: OFF Low-Speed Clock: ON System Clock: STOP Note 1: Low-Speed Clock warm-up If X'tal oscillation circuit is selected for low-speed oscillation, it takes some time before low-speed oscillation is used for system clock. Note 2: High-Speed Clock warm-up If X'tal oscillation circuit is selected for high-speed oscillation, it takes some time before high-speed oscillation is used for system clock. Figure 8 Mode transition High-speed clock fH (2 MHz) 1 2 3 4 5 6 16 kHz 8 kHz 4 kHz 2 kHz 1 kHz 512 Hz 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 MHz 512 kHz 256 kHz 128 kHz 16 kHz TMP04CH00FXXX TMP04CH00FXXX has 21 bits Divider. The divider circuit of bits 1 to 6 generates a clock from 1 MHz to 32 kHz by dividing the high-speed clock (2 MHz). The divider circuit of bits 7 to 21 generates a clock from 16 kHz to 1 Hz by dividing the 32 kHz clock. When the low-speed oscillator circuit is on (CPM1/CPM3), a low-speed clock (32 MHz) is supplied to the divider circuit of bits 7 to 21. When the low-speed oscillator circuit is off (CPM2), output from bit 6 is supplied. 32 kHz Binary counter 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Low-speed clock fL (32 kHz) 1 Hz Binary counter System CP generator circuit Figure 9 Divider circuit 16 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) The reset for this Divider circuit is done by Register file RST1 to RST4 (PA7W). MSB PA7W 3 2 1 0 RST4 RST3 RST2 RST1 RST1: Binary counter RST2: Binary counter RST3: Binary counter RST4: Binary counter 1 to 6 7 to 12 13 to 17 18 to 21 LSB (2 M to 32 kHz) reset (16 k to 512 Hz) reset (256Hz to 16 Hz) reset (8Hz to 1 Hz) reset (when using 2 MHz, 32 kHz crystal) CAUTION: 1. Do not set System CP to low speed when the Low-speed OSC is not in operation or before stable. 2. Do not set System CP to high speed when the High-speed OSC is not in operation or before stable. 3. And, when Low-speed OSC is on, low-speed frequency is supplied from 7th bit Divider circuit (when use 2 MHz crystal for High-speed OSC and 32 kHz crystal for Low-speed OSC and the mode is CPM3, 1 MHz to 32 kHz are made by 2 MHz crystal, 16 kHz to 1 Hz are made by 32 kHz crystal. And when the mode is CPM2, all frequency are made by 2 MHz crystal. Therefore if the mode change between CPM1 and CPM2 or CPM2 and CPM3, the frequency which is supplied by Binary counter 7 to 21 shift the timing). 4. When operated with a 1.5 V power supply, the oscillation frequency on the high-speed side is 200 kHz (max), so that the output of binary counter 6 is 3.125 kHz (max). Consequently, if the mode is changed from CPM1 or CPM3 to CPM2 or from CPM2 to CPM1 or CPM3, the generated timing changes greatly. 5. When the crystal oscillator circuit is used for low-speed oscillation, a long time is required from oscillation stop to oscillation start. The LCD circuit operates using a low-speed clock. LCD cannot be performed until oscillation starts. After power on, operate the low-speed oscillator circuit at all times and do not change to STOP mode. Example 1 START mode (After warming up, program start at address 0000.) CPM3 (High/Low speed ON, SYSCP = High, LOWCP OFF) LD 26O, 7H CPM3 (High/Low speed ON, SYSCP = High, LOWCP ON) LD 26O, 4H CPM0 (High/Low speed ON, SYSCP = High, LOWCP ON) HALT STOP mode (High/Low-speed OSC, STOP, SYSCP OFF, LOWCP OFF) When an interruption occurs, the mode is changed to START mode and program start at the address which is decided by each interruption (refer to Figure 2). Example 2 START mode (After warming up, program start at address 0000.) CPM3 (High/Low speed ON, SYSCP = High, LOWCP OFF) LD 26O, 5H CPM1 (Low speed ON, SYSCP = low, LOWCP ON) HALT HALT mode (High speed OSC OFF, Low-speed OSC ON, SYSCP OFF, LOWCP ON) When an interruption occurs, the mode is changed to slow mode (CPM1) and program start at the address which is decided by each interruption. 17 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Example 3 START mode (After warming up, program start at address 0000.) CPM3 (High/Low speed ON, SYSCP = High, LOWCP OFF) LD 26O, 7H CPM3 (High/Low speed ON, SYSCP = High, LOWCP ON) LD 26O, 4H CPM0 (High/Low speed ON, SYSCP = High, LOWCP ON) (There are no change after shift to CPM0.) LD 26O, 7H CPM3 (High/Low speed ON, SYSCP = High, LOWCP ON) Example 4 (After reset) BRESET fH fL System CP Stop mode Unstable OSC Warming up for high-speed OSC (16384 clock, 7.8 ms/2 MHz) 2.86 µs/2 MHz CPU ON (CPM3) Unstable OSC Warming up for low-speed OSC (256 clock, 7.8 ms/32 kHz) 18 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Example 5 (CPM3 1) fH fL System CP Command CPM3 1 CPM3 max 64 µs/32 kHz CPM1 Example 6 (CPM1 2) fH fL System CP Command CPM1 2 Unstable Warming up for high-speed OSC OSC max max 15 µs/ 1.43 µs/2 MHz 32 kHz 16384 CLOCK (7.8 ms/2 MHz) CPM1 Note: CPM2 No warm-up is provided for high-speed and low-speed RC oscillations by mask options. 19 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Low-speed (CR) oscillator circuit Q TFF C Q R Q TFF C Q R 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz 256 Hz 512 Hz 1 kHz 2 kHz 4 kHz 8 kHz 16 kHz 32 kHz 64 kHz 128 kHz 256 kHz Q TFF C Q R High-speed (CR) oscillator circuit XHIN 512 kHz 1 MHz R Q TFF C Q R XHOUT R PA6 CP CP LOWCP MODE1 MODE2 RST1 RST2 RST3 PA7W RST4 LATCH LATCH LATCH To LCD driver OSCHSTOP LOCPEN OSCLSTOP BRESET HICPEN TIMING CONTROL TIMING GENERATOR F0 F1 F2 F3 Basic timing "H" SET CPM3 System reset by watchdog timer CPSTOP SET CPM1/CPM3 SYSCP Release from HALT/STOP mode Figure 10 Oscillator circuit/Divider circuit 20 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 2. Interruption Block Interruption is supplied by IN1to IN4, IO01 to IO04, Timer/Counter1 to Counter2, Timing. (Interruption priority) Interruption priority can be selected by Register file P1 and P2. Interrupt priority is valid only when multiple interrupts occur simultaneously. P1 and P2 are initially 0. MSB 3 1 0 PC7 2 P2 P1 LSB P1 P2 INT0 INT1 INT2 INT3 INT4 0 0 IIN IOIN TIN TCIN1 TCIN2 1 0 IOIN IIN TIN TCIN1 TCIN2 0 1 TIN IIN IOIN TCIN1 TCIN2 1 1 TCIN1 IIN IOIN TIN TCIN2 (Higher) (Lower) Priority IIN: IN1 to IN4, IOIN: IO01 to IO04, TIN: TIMING, TCIN1/2: TIMER/COUNTER1/2 (Interruption enable/disable) Each interruption (IIN, IOIN, TIN, TCIN1, TCIN2) is decided enable/disable as follows. IIN : IIE1 to IIE4 IOIN : IOIE0 TIN : TIE1 to TIE4 TCIN1 : TCI1E TCIN2 : TCI2E (R42-BIT R42-BIT 0 to 3) (R43-BIT R43-BIT 0) (R53-BIT R53-BIT 0 to 3) (R64-BIT R64-BIT 1) (R74-BIT R74-BIT 1) After deciding priority by P1, P2 each interruption is decided enable/disable by INT0 to INT4. Disable the unnecessary interrupts in your application by initial settings of IIE1-4, IOIE, TIE1-4, and TCI1E/2E. INT0 to INT4 are initially 0 (disable) MSB 3 2 1 0 R12 INT2 INT1 INT0 (0) R13 INT4 INT3 INT0 to INT4 = 0 =1 LSB INT0 to INT4 disable INT0 to INT4 enable (Interrupt reset) After an interrupt occurs, reset the interrupt following the procedures described below. First, reset IN1 to IN4 interrupt/IO01 to IO04 Interrupt/Timing Interrupt/Timer Counter 1 Interrupt/Timer Counter 2 Interrupt. Then reset the signal "Release from HALT/STOP Mode" by executing a transfer instruction to R12 or R13. (Re-enable interrupts by executing a transfer instruction to R12 or R13, as you need.) How to deactivate respective interrupts will be explained in the sections which describe each of the interrupts. 21 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) PC7 P1 P2 LATCH LATCH P1 IN1 to IN4 Interrupt R12 INT0 INT1 INT2 LATCH LATCH LATCH INT3 R13 INT4 LATCH LATCH Executes transfer S Q RSFF instructions R to R12/R13 R12/R13 P2 IIN INT0 Release from HALT/STOP Mode. IINT0 Priority selector IO01 to IO04 IOIN Interrupt Input P2 P1 INT4 INT3 INT1 INT2 INT1 0 TCIN2 TCIN1 TIN IOIN IIN 0 1 TCIN2 TCIN1 TIN IIN IOIN 1 0 TCIN2 TCIN1 IOIN IIN TIN 1 TIN Interrupt Generation Circuit IINT2 INT0 0 Timing Interrupt Interrupt request IINT1 Output 1 TCIN2 IOIN IIN TCIN1 TIN INT2 Timer Counter 1 Interrupt TCIN1 INT3 Timer Counter 2 Interrupt TCIN2 INT4 Interrupt vector IINT3 IINT4 R Executes RET instruction. Figure 11 Interruption circuit block 22 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 2-1. Input or I/O Interruption (Interruption enable/disable) MSB IIE1 = 0 1 IIE2 = 0 1 IIE3 = 0 1 IIE4 = 0 1 2 1 0 IIE4 PC2 3 IIE3 IIE2 LSB IIE1 IN1 Interruption disable IN1 Interruption enable IN2 Interruption disable IN2 Interruption enable IN3 Interruption disable IN3 Interruption enable IN4 Interruption disable IN4 Interruption enable IIE1 to IIE4 are initially 0 (IN1 to IN4 interruption disable). 3 2 1 0 IOIE0 MSB PC3 IOIE0 = 0 1 LSB IO01 to IO04 Interruption disable IO01 to IO04 Interruption enable IOIE0 is initially 0 (disable). Interruption enable/disable bit can use as interruption reset. When the interruption occurs and after recognizing the interruption, it can be resetted by setting IIE1 to IIE4 or IOIE0. (Interruption data read) Interruption Data of IN1 to IN4 can be read by Register file IIN1 to IIN4. MSB PC1R 3 2 1 0 IIN4 IIN3 IIN2 IIN1 Example LD 42O, 0FH (set enable to IN1 to IN4) IN1 interruption occurs. Program goes to the address which is decided by each interruption. LD M, 41O LSB (read IN1 to IN4 interruption) recognize which interruption is occurred. (recognize IN1 interruption is occurred.) LD 42O, 0EH LD 12O, 0FH LD 13O, 0FH LD 42O, 0FH (reset IN1 interruption) (set enable to INT0 to INT2) (set enable to INT3 to INT4) (set enable to IN1 to IN4 interruption) 23 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) IIE1 PC2 IIE2 IIE3 IIE4 LATCH LATCH LATCH LATCH PC0 ESELI ESELO ESELT IIN1 PC1R IIN2 IIN3 IIN4 LATCH LATCH LATCH To timing interrupt circuit To IO01 to IO04 ports "H" D Q DFF C R R IN1 to IN4 interrupt (IIN) "H" D IN2 Q DFF C R R "H" D IN3 Q DFF C R R "H" D IN4 Q DFF C R R Mask option IN1 IND1 IND2 IND3 PA0R IND4 Figure 12 IN1 to IN4 interrupts 24 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) PC3 IOIE PC0 ESELI ESELO ESELT LATCH LATCH LATCH LATCH To timing interrupt circuit To IN1 to IN4 ports "H" D IO01 Q DFF IO01 to IO04 interrupt (IOIN) C R R "H" D IO02 Q DFF C R R "H" D IO03 Q DFF C R R "H" D IO04 Q DFF C R R IOD01 IOD01 IOD02 IOD02 IOD03 IOD03 IOD04 IOD04 PA1R Figure 13 IO01 to IO04 interrupts Note: Disabling input or input/output interrupts using PC2 or PC3 is valid only when a rising edge interrupt (see 4, Input/Output ports) is selected. If a level interrupt is selected, disabling interrupts using PC2 or PC3 is invalid. 25 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 2-2. Timing Interruption (Timing Interruption selecting) Timing Interruptions are selectable by Register file (PD1) 128/256, 16/32, 4/8, 1/2. 128/256, 16/32, 4/8 and 1/2 are initially 0 (1 Hz, 4 Hz, 16 Hz, 128 Hz is selected). MSB 128/256 = 0 1 16/32 = 0 1 4/8 =0 1 1/2 =0 1 2 1 0 1/2 PD1 3 LSB 4/8 16/32 128/256 128 Hz 256 Hz 16 Hz 32 Hz 4 Hz 8 Hz 1 Hz 2 Hz INT. select INT. select INT. select INT. select INT. select INT. select INT. select INT. select (Timing Interruption enable/disable) Selected Timing Interruption can be controlled enable/disable by Register file TIE1 to TIE4 (PD3). TIE1 to TIE4 are initially 0 (disable). MSB PD3 TIE1 = 0 1 TIE2 = 0 1 TIE3 = 0 1 TIE4 = 0 1 3 2 1 0 TIE4 TIE3 TIE2 TIE1 1 Hz or 2 Hz 1 Hz or 2 Hz 4 Hz or 8 Hz 4 Hz or 8 Hz 16 Hz or 32 Hz 16 Hz or 32 Hz 128 Hz or 256 Hz 128 Hz or 256 Hz LSB INT. disable INT. enable INT. disable INT. enable INT. disable INT. enable INT. disable INT. enable 26 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) (Timing Interruption Reset) The timing interruption for the selected timing interruption is reset by register files TIR1 to TIR4 (PD2W). TIR1 to TIR4 are initially 0 (disable). MSB TIR1 = 1 TIR2 = 1 TIR3 = 1 TIR4 = 1 2 1 0 TIR4 PD2W 3 TIR3 TIR2 TIR1 1 Hz or 2 Hz 4 Hz or 8 Hz 16 Hz or 32 Hz 128 Hz or 256 Hz LSB Interruption reset Interruption reset Interruption reset Interruption reset (Timing Interruption Read) Selected Timing Interruption can be read by Register file TI1 to TI4 (PD0R). MSB PD0R 3 2 1 0 TI4 TI3 TI2 TI1 TI1: Interruption data of TI2: Interruption data of TI3: Interruption data of TI4: Interruption data of LSB 1 Hz or 2 Hz 4 Hz or 8 Hz 16 Hz or 32 Hz 128 Hz or 256 Hz (Interruption Edge Selection) TIN Interruption can be selected the reading point ( ESTLT is initially 0 (rising edge). MSB PC0 3 2 1 0 ESELT (ESLIO) or ) by Register file ESELT. LSB (ESELI) ESELT = 0: Interruption at rising Edge of Timing INT. 1: Interruption at down Edge of Timing INT. Example LD 51O, 01H (256 Hz, 16 Hz, 4 Hz, 1 Hz select) LD 53O, 07H (256 Hz disable, 16 Hz, 4 Hz, 1 Hz enable) When the 1Hz interruption occurs. LD M, 50O (read timing interruption) Recognize 1Hz interruption. LD 52O, 01H (reset 1Hz interruption) Note: Since a mode transition from CPM1 or CPM3 to CPM2 or from CPM2 to CPM1 or CPM3 causes the timing of the binary counters 7-21 to change, timing interrupts also have their timings changed. 27 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 1/2 4/8 PD1 16/32 128/256 LATCH LATCH LATCH LATCH TIE1 PD3 TIE2 TIE3 PC0 ESELI ESELO ESELT TIE4 LATCH LATCH LATCH LATCH TI1 PD0R TI2 TI3 TI4 LATCH LATCH LATCH To IN1 to IN4 ports To IO01 to IO04 ports "H" 2 Hz D TIM1 Q DFF C R 1 Hz Timing interrupt (TIN) "H" D Q DFF C R "H" 8 Hz D TIM2 Q DFF C R 4 Hz "H" D Q DFF C R "H" 32 Hz D TIM3 Q DFF C R 16 Hz "H" D Q DFF C R "H" 256 Hz D TIM4 Q DFF C R 128 Hz "H" D Q DFF C R TIR1 TIR2 TIR3 PD2W TIR4 Figure 14 Timing interrupt circuit 28 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 2-3. 8 bits/16 bits Timer Counter Interruption When Timer/Counter1, 2 overflow or coincide with setting Time/Count, each Interruption occurs. 2 1 0 TCI1E TCI1R R/W PE4 3 MSB LSB W PF4 3 2 1 0 TCI2E TCI2R R/W MSB W TCI1E/TCI2E = 1 =0 TCI1R/TCI2R = 1 LSB Timer/Counter1, 2 Interruption enable Timer/Counter1, 2 Interruption disable Timer/Counter1, 2 Interruption reset TCI1E, TCI2E and TCI2R are initially 0 (DISABLE). 29 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 3. Timer/Counter The Timer/Counter circuit can use as 8 bit × 2ch or 16 bit × 1ch Timer/Counter. And there Time/Counter can be use as general Timer/Counter, Watch Dog Timer, or Multi Interruption Timer. 8 bits/16 bits can be switched by Register file TCPS. And input frequency also can be changed by Register CKS11 CKS11 to CKS13 CKS13 and CKS21 CKS21 to CKS23 CKS23, as follows. 3 2 1 0 CKS13 CKS13 CKS12 CKS12 CKS11 CKS11 3 2 1 0 PF2 TCPS CKS23 CKS23 CKS22 CKS22 CKS21 CKS21 CKS 11 CKS 12 CKS 13 0 0 0 fH/2 1 0 0 fH/2 0 1 0 fH/2 MSB PE2 MSB LSB LSB Input Frequency for Timer Counter1 (fH = 2 MHzfL = 32 kHz) 21 12 8 15 (fL/2 ) 6 (fL/2 ) 2 1 0 fH/2 1 CKS 22 CKS 23 0 0 0 13 Hz (122 µs) Hz (3.81 µs) 2 OFF CKS 21 (1.0 s) 18 (fL/2 ) 3 1 1 Hz 512 Hz (19.5 ms) 1 0 0 2 Input Frequency for Timer Counter2 (fH = 2 MHzfL = 32 kHz) 15 fH/2 9 fH/2 9 (fL/2 ) 3 (fL/2 ) 5 0 1 0 1 0 1 2 (15.6 ms) Hz (244 µs) Hz (15.2 µs) 19 fH/2 12 16 fH/2 1 64 Hz Hz (1.90 µs) OFF TCPS = 0 8 bit × 2 ch = 1 16 bit × 1 ch 2 2 2 Timer/Counter Timer/Counter When Timer/Counter is used as 16 bits timer, TIMER2 is used as lower bits. And CKS11 CKS11 to CKS13 CKS13 are ignored. Input Frequency is decided by CKS21 CKS21 to CKS23 CKS23. CKS11 CKS11 to CKS13 CKS13, CKS21 CKS21 to CKS23 CKS23, TCPS are initially 0. (Timer/Counter1 : 1Hz, Timer/Counter2: 64 Hz, 8 bit × 2 ch) CAUTION: 256 kHz of Timer/Counter1, 512 kHz, 64 kHz of Timer/Counter2 can be used when High-speed OSC is on. 30 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Timer function can be selected by Register file/WDT1 and CMPEN1, 2. Timer/Counter1 can be used as Watch Dog Timer. And Input Frequency can be controlled by Register file TC1EN and TC2EN. Timer/Counter is resetted by Register file TC1R, TC2R. MSB 2 1 0 TC1EN TC1R CMPEN1 WDT1 R/W W R/W R/W 3 2 1 0 TC2EN TC2R CMPEN2 (Note) R/W PE3 3 W R/W MSB PF3 LSB LSB Note: Writing 1 invalidates TC2 interrupts. Timer/Counter1 setting is made in PE3. Timer/Counter2 setting is made in PF3. All the bits of PE3 and PF3 are initially 0. PE3 WDT1 = 0: Used as 8-bit Timer/Counter. = 1: Used as Watchdog Timer. CMPEN1 = 0: An interrupt is generated if Timer/Counter1 overflows. (The entire system is reset if WDT1 = 1.) = 1: An interrupt is generated if Timer/Counter1 values match Time/Count set values (The entire system is reset if WDT1 = 1.) TC1R = 1: Timer/Counter1 is reset (cleared). Timer/Counter1 resumes counting up after reset. (Refer to the timing chart below.) TC1EN = 0: Reference clock input on Timer/Counter1 is stopped. = 1: Reference clock input on Timer/Counter1 is started. PF3 BIT 0 = 1: Timer/Counter2 cannot be used as 8-bit Timer/Counter. = 0: Timer/Counter2 is used as 8-bit Timer/Counter. CMPEN2 = 0: An interrupt occurs if Timer/Counter2 overflows. = 1: An interrupt occurs if Timer/Counter2 values match Time/Count set values. TC2R = 1: Timer/Counter2 is reset (cleared). Timer/Counter2 resumes counting up after reset. (Refer to the timing chart below.) TC2EN = 0: Reference clock input on Timer/Counter2 is stopped. = 1: Reference clock input on Timer/Counter2 is started. Timing chart for timer/counter 1/2 reset SYSCP F0 F2 TC1R/TC2R WRITE RESET Count up starts Count up Count up Timer/counter reset 31 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Timer/Counter1,2 data can read from Register file TCR11 TCR11 to TCR18 TCR18 and TCR21 TCR21 to TCR28 TCR28. MSB 3 2 1 0 LSB PE0R TCR14 TCR14 TCR13 TCR13 TCR12 TCR12 TCR11 TCR11 PE1R TCR18 TCR18 TCR17 TCR17 TCR16 TCR16 TCR15 TCR15 PF0R TCR24 TCR24 TCR23 TCR23 TCR22 TCR22 TCR21 TCR21 PF1R TCR28 TCR28 TCR27 TCR27 TCR26 TCR26 TCR25 TCR25 Timer/Counter1, 2 Comparison data is set by Register file SET11 SET11 to SET18 SET18 and SET21 SET21 to SET28 SET28. MSB 3 2 1 0 LSB PE0W SET14 SET14 SET13 SET13 SET12 SET12 SET11 SET11 PE1W SET18 SET18 SET17 SET17 SET16 SET16 SET15 SET15 PF0W SET24 SET24 SET23 SET23 SET22 SET22 SET21 SET21 PF1W SET28 SET28 SET27 SET27 SET26 SET26 SET25 SET25 SET11 SET11 to SET18 SET18 and SET21 SET21 to SET28 SET28 are initially 0. CAUTION: 1. When generating an interrupt for the timer/counter by comparing it with the setup value (SET11 SET11 to SET18 SET18, SET21 SET21 to SET28 SET28) or resetting the system, set the setup values in register files SET11 SET11 to SET18 SET18 and SET21 SET21 to SET28 SET28 before enabling CMPEN1 and CMPEN2. 2. When generating an interrupt by a 16-bit timer by comparing it with the setup value, enable all of CMPEN1, CMPEN2, TC1EN, and TC2EN using instructions. 3. Since the setup values and timer/counter values both are 0 after initialization, an interrupt is generated or the system is reset immediately when CMPEN1 is enabled. 4. Since a mode transition from CPM1 or CPM3 to CPM2 or from CPM2 to CPM1 or CPM3 causes the timing of the binary counters 7-21 to change, the timer/counters also have their timings changed. 5. Do not change the timer/counter from 8 bits to 16 bits in the middle of operation after the timer/counter has started counting, because such a change could cause the data to be destroyed. 32 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) PE2 CKS11 CKS11 CKS12 CKS12 CKS13 CKS13 LATCH LATCH LATCH PE0W SET11 SET11 SET12 SET12 SET13 SET13 SET14 SET14 PE1W SET15 SET15 SET16 SET16 SET17 SET17 SET18 SET18 LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH A1 1 Hz Multiplexer 512 Hz A2 A3 A4 A5 A6 A < B IN A7 A8 A < B OUT (1) 8-bit magnitude comparator (1) A = B IN 8 kHz 256 kHz B1 PE3 CMP WDT1 TC1R TC1EN EN1 LATCH B2 B3 B4 B5 B6 B7 B8 Q1 LATCH LATCH System reset by watchdog timer A = B OUT (1) CLOCK OUT Q2 Q3 Q4 Q5 Q6 Q7 Q8 D Q CLOCK LATCH C R RESET Q1 "H" D Q3 Q4 Q5 TCR11 TCR11 TCR12 TCR12 TCR13 TCR13 TCR14 TCR14 PE0R S Q RSFF C 8-bit counter (1) Q2 Q DFF TCIN1 R R Q6 Q7 Q8 TCR15 TCR15 TCR16 TCR16 TCR17 TCR17 TCR18 TCR18 PE1R LATCH PE2 CKS21 CKS21 CKS22 CKS22 CKS23 CKS23 TCPS PE0W SET21 SET21 SET22 SET22 SET23 SET23 SET24 SET24 LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH A1 64 Hz A2 A3 A4 A5 A6 Multiplexer 4 kHz A7 A8 A < B OUT (2) 8-bit magnitude comparator (2) A = B OUT (2) 64 kHz 512 kHz CLOCK OUT B1 PF3 CMP TC2R TC2EN EN2 LATCH LATCH LATCH B2 B3 B4 B5 B6 B7 B8 Q1 TCI1R TCI1E PE4 PE1W SET25 SET25 SET26 SET26 SET27 SET27 SET28 SET28 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q1 "H" D D Q CLOCK LATCH C R RESET Q3 Q4 Q5 TCR21 TCR21 TCR22 TCR22 TCR23 TCR23 TCR24 TCR24 PF0R S Q RSFF C 8-bit counter (2) Q2 Q DFF TCIN2 R R Q6 Q7 Q8 TCR25 TCR25 TCR26 TCR26 TCR27 TCR27 TCR28 TCR28 PF1R LATCH TCI2R TCI2E PF4 Figure 15 Timer/Counter 33 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 4. Input/IO Ports (Refer to Figure 18) TMP04CH00FXXX TMP04CH00FXXX has 8 inputs and 8 I/O ports. 8 input ports have Interruption. 4-1. Input (IN1 to IN4, IO01 to IO04) Each input data can be read by Register file IND1 to IND4. MSB 2 1 0 IND4 PA0R 3 IND3 IND2 LSB IND1 Each input Interruption function can be set enable/disable by Register file IIE1 to IIE4. MSB 2 1 0 IIE4 PC2 3 IIE3 IIE2 LSB IIE1 IIE1 to IIE 4 = 0 IN1 to IN4 each Interruption disable = 1 IN1 to IN4 each Interruption enable Note 1: IIE1 to IIE4 interrupt disable/enables are register files that are effective when rising-edge interrupts are selected. When level interrupts are selected, interrupts are disabled/enabled by the data input from ports. In this case, therefore, interrupts cannot be disabled/enabled by the register files. After the level-triggered interrupt is selected, do not apply 61-µs or less pulse (low speed, two cycles) to the IN pin. Malfunction may occur. 4 inputs (IN1 to IN4) Interruption data can be read by Register file IIN1 to IIN4. MSB 2 1 0 IIN4 PC1R 3 IIN3 IIN2 IIN1 LSB Note 2: Interrupt data IO01 to IO04 cannot be read out. Only the data input from ports can be read out. (Refer to Figure 13.) Interrupt timings (rising edge/evel) can be selected using register file ESELI. Each input Interruption recognized timing (rising edge/High level) can be selected by Register file ESELI (R40 bit1). MSB PC0 3 2 1 (ESELT) (ESELIO) 0 LSB ESELI ESELI = 0 IN1 to IN4: Interruption at rising edge of input INT. 1 IN1 to IN4: High level of input INT. Input level-triggered interrupts are possible when ESELI = 1. In this case, if interrupts have been enabled by register files INT0-4, the interrupt remain asserted while the input level is high. IN INT0 to INT4 enable/disable INT Figure 16 Interruption by high level-read 34 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Input ports (IO01 to IO04) The input data can be read out via register files IOD01 IOD01 to IOD04 IOD04. MSB PA1R 3 2 1 0 IOD04 IOD04 IOD03 IOD03 IOD02 IOD02 IOD01 IOD01 LSB IOD01 IOD01 to IOD04 IOD04 have an interrupt facility, so that interrupts can be disabled/enabled by register file IOIE0. (Four interrupt sources are collectively disabled/enabled by IOIE0.) PC3 3 2 1 0 MSB LSB IOIE0 IOIE0 = 0 IO01 to IO04 are disabled. 1 IO01 to IO04 are enabled. Note: The IO01 to IO04 interrupt disable/enables are the register files that are effective when rising-edge interrupts are selected. When level interrupts are selected, interrupts are disabled/enabled by the data input from ports. In this case, therefore, interrupts cannot be disabled/enabled by the register files. After the level-triggered interrupt is selected, do not apply 61-µs or less pulse (low speed, two cycles) to the IO0 pin. Malfunction may occur. Interrupt timings of IO01 to IO04 (rising edge/level) can be selected using register file ESELIO. MSB PC0 3 2 1 0 LSB (ESELT) ESELIO (ESELI) ESELIO = 0 Interrupts IO01 to IO04 are rising edge-triggered. 1 Interrupts IO01 to IO04 level-triggered. Input level-triggered interrupts are possible when ESELIO = 1. In this case, if interrupts have been enabled by register files INT0 to INT4, the interrupt remain asserted while the input level is high. IN INT0 to INT4 Enable/disable INT Figure 17 Level-triggered interrupts 35 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) I/O ports (IO11 to IO14, IO21 to IO24) Each input data can be read by following Register file, when using input port. MSB 3 2 1 0 R14R IOD14 IOD14 IOD13 IOD13 IOD12 IOD12 IOD11 IOD11 R15R IOD24 IOD24 IOD23 IOD23 IOD22 IOD22 IOD21 IOD21 LSB When using each input/output port for output, the output data can be set using the register file shown below. MSB 3 2 1 0 R14W IOO14 IOO14 IOO13 IOO13 IOO12 IOO12 IOO11 IOO11 R15W IOO24 IOO24 IOO23 IOO23 IOO22 IOO22 IOO21 IOO21 LSB Input/Output Circuit R RIN IN1 to IN4 IO01 to IO04 IO11 to IO14 RIN IO21 to IO24 After reset, these ports are low (pulled down). R 4-2. Figure 18 Structure of input/output port RIN : Internal pull-down resistor, 400 k (typ.) R : Input protective resistor, 100 (typ.) 36 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) R15R IOD24 IOD24 IOD23 IOD23 IOD22 IOD22 IOD21 IOD21 R14W IOO14 IOO14 IOO13 IOO13 IOO12 IOO12 IOO11 IOO11 R14R IOD14 IOD14 IOD13 IOD13 IOD12 IOD12 IOD11 IOD11 "H" D Q LATCH "H" D Q LATCH R IO11 R IO21 "H" "H" D Q LATCH D Q LATCH R IO12 R IO22 "H" "H" D Q LATCH D Q LATCH R IO13 R IO23 "H" "H" D Q LATCH Figure 19 D Q LATCH IO14 R IO24 R R15W IOO24 IOO24 IOO23 IOO23 IOO22 IOO22 IOO21 IOO21 IO11 to IO14, IO21 to IO24 37 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 5. Buzzer Circuit Buzzer sound can be selected by Register file BZ1, BZ2, BZ3 and 2k/4k. MSB PE7 2 k/4 k LSB BZ3 BZ2 BZ1 2 k/4 k = 0 Basic frequency 2 kHz = 1 Basic frequency 4 kHz 8 Hz 4 Hz 2 Hz 1 Hz BZ BZ BZ 3 2 1 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 OFF (000) 0 0 OFF ON (000) (001) 0 (BZ OFF) 1 (BZ ON) 2 k/4 kHz 0 ON (001) 1 Figure 20 Buzzer sound BZ sound can be made by software using (000), (001) setting, as above. When the Register file R67 is set the above (BZ3, BZ2, BZ1) = (010) to (111), each BZ sound is continuously released setting (BZ3, BZ2, BZ1) to (000). Note: The above buzzer sounds are shown with respect to timings in the CPM2 mode where the high-speed oscillation frequency is 2 MHz, the CPM1/3 mode where the low-speed oscillation frequency is 32 kHz, and in the HALT mode. 38 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) BZ1 PE7 BZ2 BZ3 2 K/4 K LATCH LATCH LATCH LATCH 4 kHz 2 kHz "H" Input BZ1 Output OUT BZ3 BZ2 BZ1 8 Hz 4 Hz 2 Hz 1 Hz OUT 0 0 1 * * * * 1 0 1 0 * * * 0 1 0 1 1 * * 0 * 1 1 0 0 * 1 0 * 1 1 0 1 * 1 * 0 1 1 1 0 1 * * * 1 1 1 1 1 * 0 * BZ 1 BZ2 BZ3 1 Hz 1 Hz 2 Hz 2 Hz 4 Hz 4 Hz 8 Hz 8 Hz Other than above 0 *: D'ont care Figure 21 Buzzer circuit 39 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 6. LCD Circuit The LCD driver circuit has common signals and segment signals to drive 4.5 V, 1/8 or 1/10 duty, 1/4 bias LCD. Duty can be selected by Mask option either 1/8 or 1/10. Duty Frame Frequency Common Segment 1/8 97.5 Hz COM1 to COM8 S1 to S60 1/10 117.0 Hz COM1 to COM10 COM10 S1 to S58 The LCD driver circuit is controlled by Register file both DSTA and DON, and Display RAM is enable on DRCE = 1 MSB PC6W DSTA = 0 =1 DON = 0 =1 DRCE = 0 =1 3 2 1 0 DRCE DON DSTA LSB com/seg = VSS enable normal Display Booster circuit (Quadrupler) OFF Booster circuit (Quadrupler) ON disable Display RAM enable Display RAM CAUTION: 1. Display signals from segment and common are made by the clock which come from low- speed oscillation. Even though the high-speed oscillator may be operating no display is output unless the low-speed oscillator is operating. 2. Register file DON and DSTA are read to Display Driver circuit by the clock which is made by LOWCP. When the LOWCP is needed OFF it is needs max. 103 ms after changing the data of DON and DSTA. 40 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) LCD drive waveform (1) 1/8 duty 21/16,384 s 21/2,048 s COM1 V4 V3 V2 V1 VSS COM2 V4 V3 V2 V1 VSS COM3 V4 V3 V2 V1 VSS COM4 V4 V3 V2 V1 VSS COM5 V4 V3 V2 V1 VSS COM6 V4 V3 V2 V1 VSS COM7 V4 V3 V2 V1 VSS COM8 V4 V3 V2 V1 VSS SEGMENTCOM1 to COM8: OFF V4 V3 V2 V1 VSS SEGMENTCOM1: ON, COM2 to COM8: OFF V4 V3 V2 V1 VSS SEGMENTCOM1: OFF, COM2: ON, COM3 to COM8: OFF V4 V3 V2 V1 VSS SEGMENTCOM1, COM2: ON, COM3 to COM8: OFF V4 V3 V2 V1 VSS SEGMENTCOM1, COM2: OFF, COM3: ON, COM4 to COM8: OFF V4 V3 V2 V1 VSS SEGMENTCOM1 to COM7: ON COM8: OFF V4 V3 V2 V1 VSS SEGMENTCOM1 to COM8: ON V4 V3 V2 V1 VSS *: fL: 32,768 Hz Figure 22 LCD drive waveform (1/8 duty) 41 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) (2) 1/10 duty 7/8,192 s 35/4,096 s COM1 V4 V3 V2 V1 VSS COM2 V4 V3 V2 V1 VSS COM3 V4 V3 V2 V1 VSS COM4 V4 V3 V2 V1 VSS COM5 V4 V3 V2 V1 VSS COM6 V4 V3 V2 V1 VSS COM7 V4 V3 V2 V1 VSS COM8 V4 V3 V2 V1 VSS COM9 V4 V3 V2 V1 VSS COM10 COM10 V4 V3 V2 V1 VSS SEGMENTCOM1 to COM10 COM10: OFF V4 V3 V2 V1 VSS SEGMENTCOM1: ON, COM2 to COM10 COM10: OFF V4 V3 V2 V1 VSS SEGMENTCOM1: OFF, COM2: ON, COM2 to COM10 COM10: OFF V4 V3 V2 V1 VSS SEGMENTCOM1, COM2: ON, COM3 to COM10 COM10: OFF V4 V3 V2 V1 VSS SEGMENTCOM1, COM2: OFF, COM3: ON, COM4 to COM10 COM10: OFF V4 V3 V2 V1 VSS SEGMENTCOM1 to COM9: ON, COM10 COM10: OFF V4 V3 V2 V1 VSS SEGMENTCOM1 to COM10 COM10: ON V4 V3 V2 V1 VSS *: fL: 32,768 Hz Figure 23 LCD drive waveform (1/10 duty) 42 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 7. Mask option TMP04CH00FXXX TMP04CH00FXXX has 12 Mask option. Mask code Battery Duty Segment High-speed OSC Low-speed OSC IN1 to IN4 Pull-down Resister A1081 A1081 1.5 V 1/8 60 CR X'tal Incorporated A1083 A1083 1.5 V 1/8 60 CR CR Incorporated A10A1 A10A1 1.5 V 1/10 58 CR X'tal Incorporated A10A3 A10A3 1.5 V 1/10 58 CR CR Incorporated A3080 A3080 3.0 V 1/8 60 X'tal X'tal Incorporated A3081 A3081 3.0 V 1/8 60 CR X'tal Incorporated A3083 A3083 3.0 V 1/8 60 CR CR Incorporated A30A0 A30A0 3.0 V 1/10 58 X'tal X'tal Incorporated A30A1 A30A1 3.0 V 1/10 58 CR X'tal Incorporated A30A3 A30A3 3.0 V 1/10 58 CR CR Incorporated A3480 A3480 3.0 V 1/8 60 X'tal X'tal Not Incorporated A34A0 A34A0 3.0 V 1/10 58 X'tal X'tal Not Incorporated Supply voltage Either 1.5 V or 3.0 V can be selected as the supply voltage. When 3.0 V is used, the low-speed oscillator circuit is driven by output from the internal constant voltage circuit (VREG2) thus reducing current dissipation. 1.5 V VDD 1.5 V 0V Low-speed (crystal) oscillator circuit Rfb VSS XLIN 32 kHz Rout XLOUT When 1.5 V selected VXT VDD 3.0 V Constant voltage circuit 0V VREG2 1.8 V VSS Low-speed (crystal) XLIN oscillator circuit Rfb 3.0 V (1) Rout 32 kHz XLOUT When 3.0 V selected 43 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) (2) LCD duties/number of segments Either 1/8 or 1/10 can be selected as the LCD duty. When 1/8 is selected, the number of segment pins is 60. When 1/10 is selected, the number of segment pins is 58. Among LCD drive pins, the functions (segment/common) of S59/COM10 S59/COM10 and S60/COM9 S60/COM9 are switched depending on the duty selected. (3) High-speed oscillator circuit Either the crystal or the CR oscillator circuit can be selected as the high-speed oscillator circuit. After a reset, the CPU starts operating using the high-speed clock as the system clock. Therefore, even if only a low-speed clock is used for the following processes, the high-speed oscillator circuit must operate normally at startup. Select either the crystal or the CR oscillator circuit and correctly connect the external component (crystal oscillator or resistor) to the XHIN/XHOUT pin. Rfb XHIN Crystal oscillator Rout fH XHOUT When crystal oscillator circuit is selected XHIN fH External resistor Rf Note: Internal capacitor XHOUT When CR oscillator circuit is selected 44 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) (4) Note: Low-speed oscillator circuit Either the crystal or the CR oscillator circuit can be selected as the low-speed oscillator circuit. A low-speed clock is used in the LCD driver circuit. To display the LCD, the low-speed oscillator circuit must be operated. When the CR oscillator circuit is selected, because both resistor and capacitor are built in, an external component is not required. Connect the XLIN pin to VSS. If the pin is left open, the internal circuit gates become unstable, possibly allowing surge current to flow. Rfb XLIN Crystal oscillator fL Rout XLOUT When crystal oscillator circuit is selected XLIN fL Internal capacitor R XLOUT Internal resistor When CR oscillator circuit is selected IN1 to IN4 pull-down resistor Pull-down resistor for IN1 to IN4 pins can be chosen to be incorporated or not incorporated. R IN1 to IN4 pins VSS (0 V) Pull-down resistor incorparated IN1 to IN4 pins R (5) VSS (0 V) Pull-down resistor not incorporated 45 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Electrical Characteristics Absolute Maximam Ratings (VSS = 0 V) Characteristics Symbol Rating Unit Power supply voltage VDD -0.3 to 6.0 V Input voltage VIN -0.3 to VDD + 0.3 V Power dissipation (Topr = 80°C) PD 350 mW Solder temperature Tsol 260 (10 s) °C Storage temperature Tstg -55 to 125 °C Operating temperature Topr 0 to 40 °C Recommended operating condition 1.5V version (unless otherwise specified, VSS = 0 V, Topr = 0°C to 40°C) Characteristics Symbol Test Condition Min Typ. Max Unit 1.2 1.5 1.8 V VDD (Note 1) 32.768 VDD = 1.5 V (Note 2) 20 33 55 fXTH1 VDD = 1.5 V (Note 3) 200 VDD = 1.3 V VDD × 0.8 VDD VDD = 1.7 V VDD × 0.7 VDD VDD = 1.3 V 0 VDD × 0.2 VDD = 1.7 V "H" level VDD = 1.2 V to 1.8 V fXTL2 Oscillation frequency fXTH = 200 kHz fXTL1 Power supply voltage 0 VDD × 0.3 VIH Input voltage "L" level V VIL 0.1 0.1 V2 0.1 V3 0.1 V4 Voltage capacitance C1, C2 V1 Quadrupler capacitance kHz 0.1 µF µF Note 1: Crystal oscillation circuit is used for low-speed oscillator. Note 2: Internal CR oscillator is used for low-speed oscillator. Note 3: An CR oscillating circuit configured with an external R is used for the high-speed oscillator. Oscillation Characteristics Symbol Test Condition Typ. Max Unit (Note 4) 1.4 V (Note 4) TSTA = 10 s, Topr = 25°C Min 1.2 V OSC starting voltage VSTA OSC holding voltage VHOLD Frequency of internal CR OSC fOSC1 VDD = 1.5 V (Note 5) 20 33 55 kHz fOSC2 VDD = 1.5 V Rf = 150 k (Note 6) 200 kHz Frequency of High-speed OSC Note 4: Crystal oscillation circuit for low-speed oscillator. Input 1.4 V or more at power-on. Note 5: Internal CR oscillator for low-speed oscillator. Note 6: An CR oscillating circuit configured with an external R is used for the high-speed oscillator. 46 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) DC Characteristics Characteristics Symbol Test Condition Min Typ. Max Unit IIH1 VDD = 1.8 V, VIN = 0 V -500 500 nA IIL1 VDD = 1.8 V, VIN = 1.8 V 3.21 4.5 7.5 µA VDD = 1.8 V, VIN = 0 V, (Note) Low Resistor side -60 -36 -25.7 IIH2H VDD = 1.8 V, VIN = 0 V, High Resistor side -6 -3.6 -2.57 IIL3 VDD = 1.8 V, VIN = 1.8 V 6.43 9.0 15.0 Output current (1) (IO11 to IO14, IO21 to IO24) IOH1 VDD = 1.2 V, VOH = 0.7 V -150 IOL1 VDD = 1.2 V, VOL = 0.5 V 0.89 1.25 2.08 Output current (2) (BZ) IOH2 VDD = 1.2 V, VOH = 0.7 V -500 IOL2 VDD = 1.2 V, VOL = 0.5 V 500 IOH3 V1 = 1.125 V, V2 = 2.25 V, V3 = 3.375 V, V4 = 4.5 V -100 100 VOM = V2 - 0.5 V -50 VOH = V4 - 0.5 V -100 100 VOM = V3 - 0.5 V -50 VOM = V1 + 0.5 V 50 V1 1.075 1.125 1.175 V2 2.05 2.25 2.45 3.175 3.375 3.575 Input current (1) (IN1 to IN4, IO01 to IO04, IO11 to IO14, IO21 to IO24) IIH2L Input current (2) (BRESET) Input current (3) (TEST) Output current (3) (SEGMENT) IOL3 IOM3 IOH4 Output current (4) (COMMON) IOL4 IOM4 IOM4 Quadrupler output voltage V3 V1 = 1.125 V, V2 = 2.25 V, V3 = 3.375 V, V4 = 4.5 V µA VOH = V4 - 0.5 V VOL = 0.5 V VOL = 0.5 V V1 = 1.125 V, Ta = 25°C V4 IDDOP Power supply voltage (1) (Low-speed crystel oscillation circuit) IDDSLOW IDDHOLD IDDSTOP IDDOP Power supply current (2) (Low-speed CR oscillation circuit) IDDSLOW IDDHOLD IDDSTOP Note: 4.3 VDD = 1.5 V, fH = 200 kHz fL = 32 kHz At High-speed operation VDD = 1.5 V, fL = 32 kHz At Low-speed operation VDD = 1.5 V, fL = 32 kHz In HOLD mode 4.5 48 9.5 11 Display ON 4 6 VDD = 1.5 V, In STOP mode VDD = 1.5 V, f = 200 kHz fL = Internal At High-speed operation VDD = 1.5 V, fL = Internal At Low-speed operation VDD = 1.5 V,fL = Internal In HOLD mode V 7 Display OFF µA 12 Display OFF µA 73 Display ON µA 77 Display OFF µA 4.7 Display ON µA 0.4 1 Display ON 50 77 Display OFF 73 Display ON 12 17 Display OFF 16 Display ON 5 7.5 Display OFF 6.5 0.4 µA 1 VDD = 1.5 V, In STOP mode µA The BRESET pin is connected to VDD (High level) via two resistors as shown below. To minimize the current that flows at reset, the low resistance consists of a P-channel FET. When the input level is VSS (Low level), the FET is off. The resistance is . The specified input current (2), IIH2L, is the current that flows when the low resistance = P-channel FET is on. However, the low-resistance is off when VIN = 0 V, so actual measurement is impossible. 47 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) BRESET RESET R High resistance Low resistance VDD = "High" level Recommended operating condition 3.0 V version (unless otherwise specified, VSS = 0 V, Topr = 0 to 40°C) Characteristics Symbol Test Condition Min Typ. Max Unit 2.4 3.0 3.6 V VDD (Note 1) 32.768 VDD = 3.0 V (Note 2) 20 35 60 fXTH1 VDD = 2.4 V to 3.6 V (Note 3) 2.0 fXTH2 VDD = 3.0 V (Note 4) 2.0 VDD = 2.4 V VDD × 0.8 VDD VDD = 3.6 V VDD × 0.7 VDD VDD = 2.4 V 0 VDD × 0.2 VDD = 3.6 V "H" level VDD = 2.4 V to 3.6 V fXTL2 Oscillation frequency fXTH = 2 MHz fXTL1 Power supply voltage 0 VDD × 0.3 VIH Input voltage "L" level VIL C1, C2 0.1 0.1 V2 0.1 V3 0.1 V4 0.1 VXT Voltage capacitance MHz V V1 Quadrupler capacitance kHz 0.1 µF µF Note 1: Crystal oscillation circuit is used for low-speed oscillator. Note 2: Internal CR oscillator is used for low-speed oscillator. Note 3: Crystal oscillation circuit is used for high-speed oscillator. Note 4: An CR oscillating circuit configured with an external R is used for the high-speed oscillator. Oscillation Characteristics Symbol Test Condition Min Typ. Max Unit OSC starting voltage (Low-speed) VSTA1 TSTA = 10 s, Topr = 25°C 1.85 V OSC starting voltage (High-speed) VSTA2 TSTA = 8 ms 2.10 V OSC holding voltage (Low-speed) VHOLD1 1.65 V OSC holding voltage (High-speed) VHOLD2 1.90 V 20 35 60 kHz 2.0 MHz Frequency of internal CR OSC fOSC1 Frequency of High-speed OSC fOSC2 VDD = 3.0 V (Note 5) VDD = 3.0 V, Rf = 13.0 k (Note 6) Note 5: Internal CR oscillator for low-speed oscillator. Note 6: An CR oscillating circuit configured with an external R is used for the high-speed oscillator. 48 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) DC Characteristics Characteristics Symbol Test Condition Min Typ. Max Unit IIH1 VDD = 3.6 V, VIN = 0 V -500 500 nA IIL1 VDD = 3.6 V, VIN = 3.6 V 6.43 9.0 15.0 µA IIH2L VDD = 3.6 V, VIN = 0 V, Low Resistor side -120 -72 -51.4 IIH2H VDD = 3.6 V, VIN = 0 V, High Resistor side -12 -7.2 -5.14 IIL3 VDD = 3.6 V, VIN = 3.6 V 12.9 18.0 30.0 µA Output current (1) (IO11 to IO14, IO21 to IO24) IOH1 VDD = 2.4 V, VOH = 1.9 V -1.5 mA IOL1 VDD = 2.4 V, VOL = 0.5 V 0.89 1.25 2.08 µA Output current (2) (BZ) IOH2 VDD = 2.4 V, VOH = 1.9 V -2.0 IOL2 VDD = 2.4 V, VOL = 0.5 V 2.0 IOH3 VDD = 3.0 V, VREG = 1.125 V, V2 = 2.25 V, V3 = 3.375 V, V4 = 4.5 V -100 100 VOM = V2 - 0.5 V -50 VOH = V4 - 0.5 V -100 100 VOM = V3 - 0.5 V -50 VOM = V1 + 0.5 V 50 Input current (1) (IN1 to IN4, IO01 to IO04, IO11 to IO14, IO21 to IO24) Input current (2) (BRESET) Input current (3) (TEST) Output current (3) (SEGMENT) IOL3 IOM3 IOH4 Output current (4) (COMMON) IOL4 IOM4 VDD = 3.0 V, VREG = 1.125 V, V2 = 2.25 V, V3 = 3.375 V, V4 = 4.5 V IOM4 Voltage regulater output VOH = V4 - 0.5 V VOL = 0.5 V VOL = 0.5 V VREG1 VDD = 3.0 V (Note 1) 1.075 1.125 1.175 VREG2 VDD = 3.0 V (Note 2) 1.8 V2 Quadrupler output µA V3 V4 2.05 2.25 3.375 3.575 4.5 µA µA V 2.45 3.175 4.3 VDD = 3.0 V VREG = 1.125 V, Ta = 25°C mA 4.7 V Note 1: Voltage regulator for quadrupler Note 2: Voltage output regulator for low-speed oscillator 49 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Characteristics Symbol IDDOP Power supply current (1) (High-speed crystal oscillation circuit) (Low-speed crystal oscillation circuit) IDDSLOW IDDHOLD IDDSTOP IDDOP Power supply current (2) (High-speed CR oscillation circuit) (Low-speed CR oscillation circuit) IDDSLOW IDDHOLD IDDSTOP Test Condition Min Typ. Max Display VDD = 3.0 V, ON fH = 2 MHz, fL = 32 kHz At High-speed operation Display OFF 0.85 1.2 1.2 Display ON 17.0 24.0 Display OFF 23.0 Display ON 5.5 11.0 Display OFF 10.0 0.8 1.2 Display VDD = 3.0 V, ON fH = 2 MHz, fL = Internal At High-speed operation Display OFF 0.85 1.5 1.5 Display ON 23.0 40.0 Display OFF 39.0 Display ON 6.5 14.0 Display OFF 12.0 0.8 1.4 VDD = 3.0 V, fL = 32 kHz At Low-speed operation VDD = 3.0 V, fL = 32 kHz In HOLD mode VDD = 3.0 V In STOP mode VDD = 3.0 V fL = Internal At Low-speed operation VDD = 3.0 V, fL = Internal In HOLD mode VDD = 3.0 V In STOP mode 50 Unit mA µA mA µA 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Example of Application Circuit LCD SEG1 to SEG60/COM1 SEG60/COM1 to COM8 (SEG1 to SEG58/COM1 SEG58/COM1 to COM10 COM10) BZ TEST (Note 7) V4 XHIN (Note 5) (Note 7) (Note 2) V3 XHOUT (Note 7) V2 XLIN TMP04CH00FXXX TMP04CH00FXXX (Note 6) (Note 7) (Note 3) V1 XLOUT (Note 7) VXT BRESET (Note 4) C1 VSS (Note 1) (Note 7) C2 IN IN IN IN IO IO IO IO IO IO IO IO IO IO IO IO 1 2 3 4 01 02 03 04 11 12 13 14 21 22 23 24 VDD Note 1: Either 1.5 V or 3 V can be selected as the supply voltage. Note 2: Recommended high-speed oscillator circuit capacitor: 22 pF Note 3: Recommended low-speed oscillator circuit capacitor: 15 pF Note 4: Insert a 0.1 µF capacitor between BRESET and VSS. Note 5: High-speed CR oscillator circuit (optional) Note 6: Low-speed CR oscillator circuit (optional) XHIN XHOUT XLIN 150 k (200 kHz@1.5 V) 13 k (2 MHz@3.0 V) XLOUT C and R are built in. Connect XLIN to VSS. Note 7: Adjust between 0.1 to 1.0 µF depending on the size of the LCD panel used. 51 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) Package Dimensions Weight: 1.65 g (typ.) 52 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 Bare chip 1. Pad assignment S51 S22 S52 S53 S54 S55 S56 S57 S58 COM10/S59 COM10/S59 COM9/S60 COM9/S60 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 V4 V3 V2 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 JTMP04CH00XXXS JTMP04CH00XXXS (top view) S1 C1 C2 VSS VXT BRESET XLIN XLOUT VDD XHIN XHOUT TEST BZ IN1 IN2 IN3 IN4 IO01 IO02 IO03 IO04 IO11 IO12 IO13 IO14 IO21 IO22 IO23 IO24 V1 Chip size Chip thickness 5.87 × 5.39 (mm) 450 ± 30 (µm) Substrate voltage VSS 53 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) 2. Pad location table (×10-3mm) No. PAD Name X Point Y Point No. PAD Name X Point Y Point 1 V1 -2695 -2031 65 S36 92 2427 100 V2 -2695 -1694 64 S35 272 2427 99 V3 -2695 -1514 63 S34 452 2427 98 V4 -2695 -1330 62 S33 632 2427 97 COM1 -2695 -1148 61 S32 812 2427 96 COM2 -2695 -968 60 S31 992 2427 95 COM3 -2695 -788 59 S30 1172 2427 94 COM4 -2695 -608 58 S30 1352 2427 93 COM5 -2695 -428 57 S28 1532 2427 92 COM6 -2695 -248 56 S27 1712 2427 91 COM7 -2695 -68 55 S26 1892 2427 90 COM8 -2695 112 54 S25 2072 2427 89 S60/COM9 S60/COM9 -2695 292 53 S24 2252 2427 88 S59/COM10 S59/COM10 -2695 472 52 S23 2432 2427 87 S58 -2695 652 51 S22 2695 2150 86 S57 -2695 832 50 S21 2695 1733 85 S56 -2695 1012 49 S20 2695 1553 84 S55 -2695 1192 48 S19 2695 1373 83 S54 -2695 1372 47 S18 2695 1193 82 S53 -2695 1552 46 S17 2695 1013 81 S52 -2695 1732 45 S16 2695 833 80 S51 -2695 2150 44 S15 2695 653 79 S50 -2428 2427 43 S14 2695 473 78 S49 -2248 2427 42 S13 2695 293 77 S48 -2068 2427 41 S12 2695 113 76 S47 -1888 2427 40 S11 2695 -67 75 S46 -1708 2427 39 S10 2695 -252 74 S45 -1528 2427 38 S9 2695 -432 73 S44 -1348 2427 37 S8 2695 -612 72 S43 -1168 2427 36 S7 2695 -792 71 S42 -988 2427 35 S6 2695 -972 70 S41 -808 2427 34 S5 2695 -1152 69 S40 -628 2427 33 S4 2695 -1332 68 S39 -448 2427 32 S3 2695 -1512 67 S38 -268 2427 31 S2 2695 -1692 66 S37 -88 2427 30 S1 2695 -2031 54 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) No. PAD Name X Point Y Point 29 IO24 2444 -2427 28 IO23 2264 -2427 27 IO22 2084 -2427 26 IO21 1904 -2427 25 IO14 1724 -2427 24 IO13 1544 -2427 23 IO12 1364 -2427 22 IO11 1184 -2427 21 IO04 1004 -2427 20 IO03 824 -2427 19 IO02 644 -2427 18 IO01 464 -2427 17 IN4 272 -2427 16 IN3 92 -2427 15 IN2 -88 -2427 14 IN1 -268 -2427 13 BZ -452 -2427 12 TEST -633 -2427 11 XHOUT -813 -2427 10 XHIN -933 -2427 9 VDD -1202 -2427 8 XLOUT -1408 -2427 7 XLIN -1588 -2427 6 BRESET -1768 -2427 5 VXT -1948 -2427 4 VSS -2116 -2427 3 C2 -2281 -2427 2 C1 -2461 -2427 55 2002-12-11 TMP04CH00FXXX TMP04CH00FXXX(JTMP04CH00XXXS JTMP04CH00XXXS) RESTRICTIONS ON PRODUCT USE 000707EBA 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 56 2002-12-11