TMC2360 SMPTE-170M CCIR-656 PAL800 27MHZ PAL640 VGA640-NTSC/PAL 27011D 27014D - Datasheet Archive

 

TMC2360 Video Output Processor VGA to NTSC/PAL Features Description · Single-package graphics to video conversion ·

 

www.fairchildsemi.com TMC2360 TMC2360 Video Output Processor VGA to NTSC/PAL Features Description · Single-package graphics to video conversion · Multiple input formats ­ 640x480 50/60 Hz, 800x600 50 Hz · Multiple output standards ­ NTSC, NTSC-EIA, PAL-B/G/H/I, PAL-M · Composite and S-video output formats · No external memory required · Horizontal and vertical positioning inputs · Configuration set by 11 switches ­ Microcontroller port optional · Auto sync polarity detection · Internal color bars · 3-channel 8-bit input digitizer · 2x oversampling 9-bit D/A converters · Accepts programming through H and V timing ­ VESA DPMS, filter modes, video standard · Single +5V power supply The TMC2360 TMC2360 converts RGB video and sync from a standard VGA source into NTSC or PAL video. Composite and S-Video outputs are compliant with SMPTE-170M SMPTE-170M and CCIR-656 CCIR-656 specifications. A fully-integrated 3-line flicker filter provides three selectable operating modes. Reference designs are available from the factory. System implementation requires an absolute minimum of external components. Critical timing is derived from a single 27 MHz crystal or an external clock reference. All functions are directly controlled via package pins. Video and filtering modes may be programmed through either a microcontroller port or Vertical Sync Communications (VSCOM). VESA Display Power Management Signaling (DPMS) is supported. Power is derived from a single +5V supply. Package is an 80-lead Metric Quad Flat Pack (MQFP), available in 2.0mm (KM) or 2.7mm (KL) package thickness. Applications · · · · VGA to video converter modules Computer video outputs Video games TV VGA in VTOUT VREF RREF CBYPR Block Diagram VTIN VRT R G B 8-bit A/D 8-bit A/D 8-bit A/D Interlacer & Flicker Filter 9-bit D/A 9-bit D/A 9-bit D/A Digital Video Encoder COMPOSITE LUMA CHROMA PXCK 27MHz ADCLK Control SVIDEN CVIDEN BLUE BLANK POSR POSD PAL800 PAL800 MPEN A0 A1 CE R/W D7-0 Microprocessor Interface Output TVSTD1-0 FIL RESET Process PHASE DPMS VSCOM Input PWRDN Clock Processor LPFA LPFP XTAL1 XTAL2 ADIVN PDIVM VGAHS HSOUT VGAVS VSOUT S-VIDEO REF 24452A Rev. 1.2.1 TMC2360 TMC2360 PRODUCT SPECIFICATION Functional Description The TMC2360 TMC2360 is a VGA to Video converter capable of producing video signals conforming to NTSC and PAL standards using a single low-cost application circuit. Within the TMC2360 TMC2360 is all of the active circuitry required to generate a television signal with outstanding image quality in a standalone application. Vertical Sync Communications may be enabled with the VSCOM pin to detect the number of VGAHS pulses during the VGAVS period. With VSCOM, the Flicker Filter mode and the Video Standard may be selected by commands communicated via the VGA sync signals. Flicker Filter Incoming VGA source signals must be 2X the frame and 2X the line rate of the outgoing TV standard within a ±2% tolerance. Supported VGA formats are 640x480 at 60 Hz for NTSC and PAL-M, and 640x480 and 800x600 at 50 Hz for PAL B/G/H/I. The TMC2360 TMC2360 is ideal for portable converter applications, as well as integration into notebook and palmtop computers and video games. Input Section Analog VGA signals are digitized by three 8-bit A/D converters, operating at rates of up to 36 Ms/s. The signal range is 0 to 700 mV established by the reference voltage, VRT. By connecting VTOUT to VRT, the A/D converter reference voltage may be supplied by an on-chip voltage follower with an input, VTIN, that may be varied from 0 to 2 volts to accommodate different input levels. Clock Processor Flicker may be traded-off against vertical resolution with a three-line adaptive flicker filter. A single toggle pin (FIL) selects either High Filter, Medium Filter, or No Filter modes. A fourth mode, Color Bars, is useful for video setup and as a reference point for filter selection. Video Encoder Unless VSCOM is enabled, TVSTD1-0 pins select the TV standard to be either NTSC, PAL or PAL-M. Relative to the bezel framed by horizontal and vertical sync, the image may be moved right/left, and down/up by pulsing the POSR and POSD pins. BLANK suppreses the image, setting the screen either black or blue according to the state of the BLUE pin. NTSC (SMPTE 170M) and PAL (CCIR 624) video signals are produced by three 9-bit D/A converters that can drive the 37.5W load of a double-terminated 75W line. Digital 2X oversampling minimizes sinX/X distortion, facilitating use of low-cost output filters. Two phase-locked loops synthesize clocks from the VGA Horizontal Sync signal. One loop generates ADCLK, which is used internally as the A/D sample clock. A second PLL generates PXCK, which is used internally as the digital encoder clock. Control Processor Either internal or external phase-locked loops may be selected by programming pins A1 and A0. For internal loops, loop filters must be connected to LPFA and LPFP. TMC2360 TMC2360 setup and control is derived from external switches and push buttons. Schmitt trigger inputs reject external noise. Unused controls may be preset by hardwiring inputs to ground or VCC. With external phase-locked loops, the internal divide by N and divide by M counters are still used. Only the phase detector, charge pump and VCO need be located in the external controller. A stable timebase reference for subcarrier generation is derived from a 27 MHz crystal, or a TTL clock applied to pin XTAL1. To synchronize the video encoder, vertical timing is derived from VGAVS, the VGA vertical sync signal. VGAHS and VGAVS signals of either polarity are accepted. Composite and S-Video D/As are independently enabled via CVIDEN and SVIDEN pins to minimize power dissipation. Encoder Output Current Output current is established by VREF and an external resistor connected between RREF and ground. An internal 1.235 volt reference is buffered from VREF by a resistor, so VREF may be overridden by an external voltage. Output current may be calibrated by resistor selection or setting a potentiometer attached to RREF. To minimize DAC noise, a bypass capacitor must be connected from CBYPR to an adjacent VDDA pin. Microprocessor Port VESA Display Power Management Signaling functions may be enabled with the DPMS pin. Using the DPMS protocol, operational commands may be communicated to the TMC2360 TMC2360 via VGAHS and VGAVS signals. DPMS STAND-BY or DPMS SUSPEND modes set the processor to sleep and blanks the screen. DPMS OFF sets the processor, A/Ds and D/As to sleep with a blanked screen. 2 Instead of utilizing control pin inputs, two operational modes, TV Standard and Flicker Filter, may be selected by writing to the VGA control register. Five registers may be read: address, VGA0, VGA1, Revision ID and Part ID. PRODUCT SPECIFICATION TMC2360 TMC2360 Pin Assignments ­ 80-Lead MQFP Package (KL or KM) 80 65 1 64 24 41 25 40 65-3687-06 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name AGND COMPOSITE RREF VREF DGND PHASE VDD DGND VDD DGND 27MHZ 27MHZ PXCK ADCLK VDD DGND ADIVN PDIVM D7 D6 D5 Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name D4 D3 D2 D1 D0 VSOUT HSOUT DGND VDD MPEN A1 A0 R/W CE VDD DGND BLUE BLANK TVSTD1 TVSTD0 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name PAL800 PAL800 FIL DPMS VSCOM VGAVS VGAHS POSR POSD AGND B VDDA VDDA G AGND VRT VTOUT VTIN AGND R VDDA Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name DGND VDD AGND LPFA VDDPLLA AGND LPFP VDDPLLP XTAL2 XTAL1 RESET PWRDN SVIDEN CVIDEN VDDA VDDA CBYPR CHROMA AGND LUMA Pin Descriptions Pin Number Type/ Value ADCLK 13 TTL A/D Converter Clock Output. Generated by an internal phaselocked loop slaved to VGAHS. ADIVN 16 TTL Internal ADCLK divided by N Output. Enabled by A0 and A1 pins according to Table 1 or by VGA Control Register 1. LPFA 64 - PXCK 12 TTL Encoder Clock Output. Generated by an internal phase-locked loop slaved to VGAHS. PDIVM 17 TTL Internal PXCK divided by M Output. Enabled by A0 and A1 pins according to Table 1 or by VGA Control Register 1. LPFP 67 - Encoder PLL Loop Filter Connection. An external RC network is connected here. XTAL1-2 70, 69 - Subcarrier Reference Crystal/Clock. Connection terminals for an external 27 MHz crystal. Alternatively, the XTAL1 pin may be used as an input from an external oscillator or clock. Subcarrier frequency accuracy is based on this clock. 27MHZ 27MHZ 11 TTL VGAHS 46 CMOSS Pin Name Pin Function Description Clocks A/D PLL Loop Filter Connection. An external RC network is connected here. Subcarrier Reference Clock Output. Buffered TTL output from 27MHz crystal oscillator/reference clock. VGA Horizontal Sync. Incoming VGA sync may be of either polarity (active LOW or active HIGH). VGAHS frequency must be within 2% of the nominal specified value. The VGAHS pin has a light pull-up and a Schmitt trigger. 3 TMC2360 TMC2360 PRODUCT SPECIFICATION Pin Descriptions (continued) Pin Number Type/ Value VGAVS 45 CMOSS HSOUT 27 TTL Buffered Horizontal Sync Output. Follows VGAHS. VSOUT 26 TTL Buffered Vertical Sync Output. Follows VGAVS. 39, 40 CMOSP Video Output Standard Select. Preprogrammed into the TMC2360 TMC2360 are timing, subcarrier frequency and phase parameters corresponding to worldwide NTSC and PAL standards. TVSTD1-0 select one of four sets of parameters to set up the encoder. Frame rate of the graphics source must be twice the frame rate of the selected video standard. PAL800 PAL800 41 CMOSP Resolution Select for PAL. Sets number of samples per VGA line. DPMS 43 CMOSP Display Power Management Signaling Enable. When HIGH, the operational state of the TMC2360 TMC2360 is controlled by the pulse activity on VGAHS and VGAVS. When LOW, the state of the TMC2360 TMC2360 is controlled only by input pins. FIL 42 CMOSS Flicker Filter Mode Select. The adaptive flicker reduction filter may be configured for HIGH filtering, MEDIUM filtering, or NO filtering by pulsing this input HIGH. FIL defaults to HIGH-filter mode upon powerup. If VSCOM is HIGH, the filter mode will be selected by the pulsewidth of VGAVS, and FIL will be ignored. The FIL input is a Schmitt trigger. VSCOM 44 CMOSP Vertical Sync Communications Enable. When HIGH, vertical sync pulse width (VGAVS) will control the filter mode, and FIL will be ignored. PWRDN 72 CMOSP Power-Down Control. When HIGH, the TMC2360 TMC2360 is fully operational and enabled. When LOW, the TMC2360 TMC2360 is configured for minimum power consumption. D/A converters and clocks are disabled. Previously established set-up conditions are retained and remain in effect when PWRDN goes HIGH. RESET 71 CMOSP Reset. Initializes internal registers. PHASE 6 CMOSP Sampling Phase Control. Shifts the A/D sampling phase by 180°. Set Phase = LOW. CVIDEN 74 CMOSP Composite Video D/A Power Enable. When HIGH, the COMPOSITE D/A converter is enabled. When LOW it is disabled to save power. SVIDEN 73 CMOSP S-Video D/A Power Enable. When HIGH, the CHROMA and LUMA D/A converters are enabled. When LOW, they are disabled to save power. BLANK 38 CMOSP Blank Screen Generator. When HIGH, the color selected by BLUE is displayed on the screen. When LOW, incoming video from the internal FIFO is encoded. BLUE 37 CMOSP Blank Screen Color Selector. When HIGH, the screen will be blanked to blue when BLANK is HIGH. When LOW, the screen will be blanked to black when BLANK is HIGH. Pin Name Pin Function Description VGA Vertical Sync. Incoming VGA sync may be of either polarity (active LOW or active HIGH). The VGAVS pin has a light pull-up and a Schmitt trigger. Global Controls TVSTD1-0 Encoder Controls 4 PRODUCT SPECIFICATION TMC2360 TMC2360 Pin Descriptions (continued) Pin Number Type/ Value 47, 48 CMOSS TV Image Position Controls. Position controls shift the VGA image horizontally or vertically, revealing portions that are found near the edges or in the overscan areas. Default power-up position is the midpoint of the adjustment range. POSD,R inputs are Schmitt triggers. 59, 53, 50 700 mV Analog RGB Inputs. Analog red, blue and green inputs to the A/D converters from incoming VGA signals. Nominal voltage range is 0.0 to +700 mV. VTIN 57 750 mV A/D Converter Reference Buffered Input. Buffer is a voltage follower that may be connected to VRT. VTOUT 56 750 mV A/D Converter Reference Buffered Output. May be connected to VRT to supply current to A/D converter reference resistors. In power down mode, VTOUT drops to zero. VRT 55 750 mV A/D Converter Reference Input, Unbuffered. Supplies current to A/D converter reference resistors. May be driven from VTOUT. Voltage range is 0.5 to 2.0 volts. COMPOSITE 2 1 V p-p NTSC/PAL Video Output, Composite Video. NTSC/PAL baseband composite output can drive 1 Volt p-p video into a 37.5 W load. Contains sync, subcarrier and active video information to drive monitors, projectors, VCRs, and other video devices. LUMA 80 1 V p-p Luminance-only Video. This analog monochrome video output can drive 1 Volt p-p video into a 37.5 W load. Contains all sync and active video information necessary to drive black-and-white video devices. CHROMA 78 1 V p-p Chrominance-only Video. This analog output can drive a 37.5 W load. CHROMA signal, when combined with LUMA comprises an SVideo signal suitable for driving monitors, projectors, VCRs, and other S-Video devices. VREF 4 +1.23 V Voltage Reference Input/Output. Output of an internal 1.23 Volt band-gap voltage reference. If unconnected, except for a 0.1F capacitor to ground for noise decoupling, the internal reference will be used for the three D/A converters. An externally generated voltage reference of +1.2 Volts applied to the VREF pin will override the internal voltage reference and become the new reference for the D/A converters. CBYPR 77 0.1 mF Reference Bypass Capacitor. An external 0.1F capacitor should be connected between CBYPR and VDDA to reduce noise on the internal reference circuitry. RREF 3 392W Current-setting Resistor. A 392W resistor connected between the RREF terminal and ground establishes the reference current for the three internal D/A converters. Resistor value determines the full-scale output current (and therefore the peak video level) of the D/A converters. Pin Name POSR, D Pin Function Description A/D Converter Interface R, G, B Video Outputs Voltage Reference 5 TMC2360 TMC2360 PRODUCT SPECIFICATION Pin Descriptions (continued) Pin Name Type/ Value Pin Number Pin Function Description Microprocessor Interface MPEN 30 TTL Microprocessor Port Enable. With MPEN = LOW, the port is disabled and control is via individual pins. With MPEN = HIGH, selected functions may be accessed through the microprocessor port. A0 32 TTL External PXCK Phase-locked Loop Select/Address Bit. Dual function pin. If MPEN = HIGH, A0 is the microprocessor port address bit A0. If MPEN = LOW, A0 configures the PXCK PLL inputs and outputs. A1 31 TTL External ADCLK Phase-locked Loop Select. If MPEN = LOW, A1 configures the ADCLK PLL inputs and outputs. R/W 33 TTL Read/Write. Read/Write selects the direction of the 8-bit data bus. CE 34 TTL Chip Enable. When CE = H, D7-0 are high impedance. When CE = L, R/W sets D7-0 to either the read or write state. 18, 19, 20, 21, 22, 23, 24, 25 TTL Data bits. Data bus is high impedance unless CE = L and R/W = H. 7, 9, 14, 29, 35, 62, +5.0 V Digital Power Supply. Supplies +5V power to internal digital circuits. 51, 52, 60, 75, 76 +5.0 V Analog Power Supply. Supples +5V power to internal analog circuits. VDD and VDDA must originate from the same source. VDDPLLA 65 +5.0 V A/D Phase Locked Loop +5V Power. VDDPLLA and VDD must originate from the same source. VDDPLLP 68 +5.0 V Encoder Phase Locked Loop +5V Power. VDDPLLP and VDD must originate from the same source. DGND 5, 8, 10, 15, 28, 36, 61 0.0 V Digital Ground. Ground point for internal digital circuits. AGND 1, 49, 54, 58, 63, 66, 79 0.0 V Analog Ground. Ground point for internal analog circuits. DGND and AGND should be connected to the same ground plane. D7-0 Power and Ground VDD VDDA Notes: CMOSP = CMOS with light pull-up CMOSS = CMOS with Schmitt Trigger 6 PRODUCT SPECIFICATION TMC2360 TMC2360 Clocks There are three internal clocks, ADCLK, PXCK, and 27MHz. ADCLK is the clock for the A/D converters with sampling on the edge selected by PHASE. PXCK is the encoder clock for sequencing data to the D/A converters at a 2X rate. 27MHz is the reference clock from which the chroma subcarrier data is synthesized. ADCLK and PXCK clocks may be derived from internal or external phase-locked loops. Only an external controller containing the phase detector, charge pump, and VCO is needed for each loop. An internal divider programmed with the correct counts is included within the TMC2360 TMC2360. Control of the internal/external PLL modes is either via the A0 and A1 pins (see Table 1) or through the VGA1 Control register, which can be programmed via the microprocessor port. With control via A0 and A1 pins, the outputs PDIVM and ADIVN are high impedance unless either PLL is programmed to be external. A0 and A1 also control the direction of the ADCLK and PXCK clock pins. Each clock (ADCLK and PXCK) is an output in the internal mode and an output in the external mode. Table 1. Internal/External Phase-locked Loop Selection (MPEN = L) A1 A0 PLLA PLLP ADIVN PDIVM ADCLK PXCK 0 0 Internal Internal High-Z High-Z Output Output 0 1 Internal External 1/N 1/M Output Input 1 0 External Internal 1/N 1/M Input Output 1 1 External External 1/N 1/M Input Input A/D Clock (ADCLK) ADCLK is the buffered analog-to-digital converter clock output which is derived from incoming VGA horizontal sync (VGAHS) by a phase-lock loop (PLL). Either an internal PLL or an external PLL controller may be selected by programming pin A1. LPF 680pF 39K 0.1µF A/D Clock frequency is set by the PLL divide-by-N counter where N is the number of A/D samples between the horizontal sync pulses in each VGA line. 29001A Figure 1. PLL Low Pass Filter Pre-programmed values selected by the TVSTD1-0 and PAL800 PAL800 control inputs set N and the clock frequency as shown in Table 2. Pixel Clock (PXCK) PXCK is the buffered video encoder clock output which is derived from the incoming VGA HSYNC signal by a second phase-lock loop. Either an internal PLL or an external PLL controller may be selected by programming pin A0. Table 2. VGA A/D Clock ADCLK Television Standard TVSTD1-0 PAL800 PAL800 Freq. (MHz) N NTSC 0x 0 25.175 800 PAL640 PAL640 10 0 25.250 808 PAL800 PAL800 10 1 36.000 1152 PALM 11 0 25.175 800 With the internal loop selected, Figure 1 shows the recommended loop filter, which should be connected to LPFP. For an internal loop, the recommended loop filter to be connected to the LPFA pin is shown in Figure 1. Clock frequency is set by the PLL divide-by-M counter. M is the number of encoder samples between horizontal sync pulses. Because of 2X oversampling, the pixel rate is twice the TV square pixel rate. Table 3 shows the video output clock rates and M values. 7 TMC2360 TMC2360 PRODUCT SPECIFICATION Table 3. NTSC and PAL Pixel Clocks Table 4. VGA Input Formats PAL800 PAL800 H xV Input Pixels Frame Rate (Hz) Line Rate (kHz) 0x 0 640 x 480 59.94 31.469 10 0 640 x 480 50 31.250 10 1 800 x 600 50 31.250 11 0 640 x 480 60 31.469 Television Standard Line Rate (kHz) Pixel Rate (MHz) M NTSC 15.734 24.545 780 TVSTD1-0 PAL 15.625 29.500 944 PALM 15.750 24.570 780 Reference Clock Accuracy of the PAL/NTSC subcarrier depends on the 27 MHz reference signal applied to the XTAL1. This signal may be derived from a clock connected directly to the XTAL1 pin or a crystal and capacitors connected across XTAL1-2 as shown in Figure 2. XTAL1 XTAL2 C1 C2 AGND 29002A Figure 2. Crystal Oscillator Circuit Capacitors C1 and C2 must be adjusted to trim the frequency within 20 ppm. C1 and C2 have the same value, with series capacitance equal to the load recommended for the crystal. Processing Flicker Filter Annoying artifacts can be eliminated by selecting one of three filter modes, which trade-off vertical resolution against flicker. Without the filter, one contrasting VGA line may be encoded into one field of the TV video, which will flicker at 30 Hz with NTSC and 25 Hz with PAL. As shown in Table 5, if VSCOM = LOW, pulsing the FIL pin indexes the TMC2360 TMC2360 through a loop of three filter modes and a color bar pattern. Table 5. FIL Filter Mode Select Sequence FIL ¯ HIGH (default) ¯ MEDIUM ¯ No filter Color bars Typical crystal parameters are 50 ppm accuracy with a 20 pF load and ±80 ppm pullability. Digitizing A/D Reference Filter Mode Video Encoder D/A Reference An on-chip voltage follower is included to supply current to the ADC reference VRT from VTOUT. A stable voltage source greater than the input peak amplitude should be connected to VTIN. Peak D/A converter current for the video outputs is set by a resistor connected to RREF. For 1 volt video, with a 37.5 ohm load, the correct value of RREF is 392 ohm. To trim the video output level, RREF can be replaced with a potentiometer. (See the Applications Circuit, Figure 15). Input Signal Conditioning Television Standard Selection ADC performance can be optimized by driving the RGB video inputs with either a 75 ohm or a low impedance source. NTSC and PAL standards are preprogrammed into the TMC2360 TMC2360 to preset horizontal and vertical timing, subcarrier frequency, and chrominance phase. Frame rate of the VGA source must match the field rate of the selected video standard. Input Format Selection One of four input VGA formats can be accepted by setting the TVSTD1-0 and PAL800 PAL800 inputs as shown in Table 4. Each VGA input option corresponds to a VGA active video area, frame rate and line rate with a corresponding TV output format. 8 Depending upon the status of the Vertical Sync Communications (VSCOM) pin, the video output format may be selected by either the TVSTD1-0 pins or by VSCOM codes. Table 6 shows how the TVSTD1-0 pins select the TV output format with VSCOM = LOW. PRODUCT SPECIFICATION TMC2360 TMC2360 Table 6. TVSTD Control When Under Manual Control (VSCOM = 0) TVSTD1-0 Television Standard Video Field Rate 01 NTSC 59.94 Hz 00 NTSC-EIA 59.94 Hz 10 PAL/B, G, I 50 Hz 11 PAL/M 60 Hz If VCSOM = HIGH, Vertical Sync Communications are enabled. VSCOM is described under the Vertical Sync Command section below. Image Positioning POSD and POSR position controls change encoder timing relative to incoming PC video, shifting the viewed image either horizontally or vertically to reveal portions of the image located near the edges or in the overscan areas. At power-up, the default position is the midpoint of the adjustment range. Each POSD HIGH pulse moves the TV window down eight lines. At the lowest position (-64 lines) the direction reverses and the pulses move the image up in 8-line increments to the highest position (+64 lines). At this point the direction again reverses and the next sixteen pulses move the image down to the lowest position. Each POSR HIGH pulse moves the TV window eight pixels to the right. At the maximum right position (+64 pixels) the direction reverses and the next sixteen pulses move the window left to the maximum left position (-64 pixels). Direction again reverses and the next sixteen pulse move the image right. DPMS = LOW, the display will be blue if either or both VGAHS or VGAVS are inactive. Table 8. Video Output Control CVIDEN SVIDEN VGAHS & VGAVS Composite Video S-Video H X YES Active X X H YES X Active L L X Blank Blank H H NO Blue Blue Powerdown Mode PWRDN eliminates current drain by the D/A converter, VTOUT voltage follower and clock outputs. With PWRDN = HIGH, all outputs are enabled. If PWRDN = LOW, all outputs are disabled including the ADCLK, PXCK, VTOUT and the D/A converters. Software Control Display Power Management Signaling (DPMS) Display Power Management is compliant with VESA DPMS Proposal 1.0. With DPMS = HIGH, the operational state of the TMC2360 TMC2360 is controlled by the pulse activity on VGAHS and VGAVS. Table 9 shows how the TMC2360 TMC2360 responds. "No Pulses" on VSYNC or HSYNC is declared on the second missing VSYNC or HSYNC pulse. Following an OFF state, detection of VGAHS and/or VGAVS restores either the Suspend, Standby, or On state. Without a RESET, POSD,R controls will loop, causing the window to move down/up, right/left. Regardless of the state of DPMS, absence of VGAHS and/or VGAVS pulses will cause the TMC2360 TMC2360 processor to sleep. However, with DPMS = HIGH, in the Off state, the A/Ds, D/As, and clocks are also set to sleep. Blank and Blue Vertical Sync Communications (VSCOM) TV video can set to active (converted VGA source), blank or blue by the BLANK and BLUE inputs. VSCOM is a unique feature incorporated into the TMC2360 TMC2360. With VSCOM = HIGH, the TMC2360 TMC2360 interprets commands that are encoded within the VGA vertical sync period. TV Standard and Flicker Filter may be selected by commands from the PC that supplies the VGA signal. Table 7. Video Output for BLANK and BLUE inputs BLANK BLUE Video L X Video H L Black H H Blue Power Management D/A Power Control During the vertical sync period, the number of horizontal sync pulses is counted. Table 10 shows how the selected Television Standard changes with the code set into the TVSTD1-0 inputs and the number of horizontal syncs per vertical sync interval. Table 11 shows how the Filter Mode is selected with VSCOM. Notice that if one standard, such as PAL800 PAL800 is selected, then counts of 10, 11 and 12 enable selection of three filter modes. Table 8 shows how the Composite and S-video outputs are enabled by the CVIDEN and SVIDEN controls. If 9 TMC2360 TMC2360 PRODUCT SPECIFICATION Table 9. Display Power Management Signaling (DPMS) States State VGAHS VGAVS TMC2360 TMC2360 State On Pulses Pulses On, video active Stand-by No Pulses Pulses Stand-by, screen blanked (color set by BLUE) Suspend Pulses No Pulses Stand-by, screen blanked (color set by BLUE) Off No Pulses No Pulses Off, screen black (equivalent to PWRDN, except A/D Clock and 27MHZ 27MHZ oscillator are active.) Table 10. TVSTD Control When Under Software Control (VSCOM = 1) TVSTD1-0 Hsyncs per Vsync Interval Television Standard VGA Frame Rate XX 10,11,12 PAL 800 (B, G, I) 50 Hz X0 6,7,9 PAL 640 (B, G, I) 50 Hz 01 6,7,9 PAL-M 60 Hz 11 6,7,9 (reserved) 0X 1-5,8,14,15 NTSC-EIAJ 60 Hz 10 1-5,8,14,15 NTSC 60 Hz 11 1-5,8,14,15 (reserved) XX 0,13 Blank (with prior standard) Table 11. VSCOM Filter Command Interpretation (VSCOM=1) HSYNCs per VSYNC Interval Filter Mode 50/60 Hz Table 12. Microprocessor Addressable Registers A1 A0 Address Register Value Register 5, 9, 12 No Filter 0 0 x Address Register 4, 7, 11 2-line filter 0 1 x0 VGA Register 0 1, 2, 3, 6, 8, 10, 14, 15 3-line filter 0 1 x1 VGA Register 1 Blank (with prior mode) 0 1 x6 Revision ID (xxh) 0 1 x7 Part ID (0Fh) 0, 13 Microprocessor Interface Table 12 shows the five registers that may be read after the Address Register has been loaded. Only the two VGA registers and the Address Register may be written. For microprocessor control, 40h must be written into VGA register 1. To disable control through VGA Register 0, 00h must be written into register 1. Bit assignments of VGA register 0 are listed in Table 13. Bit assignments of VGA register 1 are listed in Table 14. For communications through the microprocessor port, set MPEN = HIGH. Read and write timing is shown in Figure 3 and Figure 4. To access a VGA register, write the address of the selected register into the lower four bits of the eight bit Address Register with A0 = LOW. Then with A0 = HIGH, read or write to the selected register. Table 13. VGA Control Register 0 Bit Map Bit # Name Function 7 - 0 (reserved) 6-5 FIL 0 0 No Filter 0 1 2-line Filter 1 x 3-line Filter 4-2 TVSTD 0 0 0 NTSC-EIA 0 0 1 NTSC 0 1 0 PALM 0 1 1 PAL640 PAL640 1 x x PAL800 PAL800 1-0 VIDEO 0 0 Black 0 1 Ramp 1 0 Color Bars 1 1 Normal 10 PRODUCT SPECIFICATION TMC2360 TMC2360 Video Formats Table 14. VGA Control Register 1 Bit Map Bit # Name Function 7 - 0 (reserved) 6 MODE 0 Normal Table 15 and Table 16 show expected VGA Video input formats. 1 Bypass FIL and TVSTD Pins Outgoing TV Formats Table 16 shows the four different TV formats that may be selected as outputs by the TVSTD1-0 inputs. 5-3 - 0 (reserved) 2 DIVMN Incoming VGA Formats 0 (reserved) 1 Enable ADIVN and PVIDM 1 EXTPLL 0 EXTPLLA Table 17 and Table 18 show the Horizontal and Vertical Timing for the NTSC and PAL formats. 0 Disable external PXCK PLL 1 Enable external PXCK PLL 0 Disable external ACLK PLL 1 Enable external ACLK PLL Table 15. VGA Horizontal Timing Parameters Television Standard TVSTD1-0 PAL800 PAL800 Line Rate (kHz) Front Porch (pixels) Horiz Sync (pixels) Back Porch (pixels) Active Video (pixels) NTSC(-EIA) 0x 0 31.469 18 96 46 640 PAL/B, G, I 10 0 31.250 18 96 54 640 PAL/B, G, I 10 1 31.250 98 96 158 800 PAL/M 11 0 31.500 18 96 46 640 Table 16. VGA Vertical Timing Parameters Frame Rate (Hz) TVSTD1-0 PAL800 PAL800 NTSC(-EIA) 0x x 59.94 Line Rate (kHz) Full Frame (lines) Front Porch (lines) Vert. Sync (lines) 31.469 525 13 2-16 32 480 PAL/B, G, I 10 0 50 31.250 625 61 2-16 84 480 PAL/B, G, I 10 1 50 31.250 625 1 2-16 24 600 PAL/M 11 x 60 31.469 525 13 2-16 32 480 Television Standard Vsync + Back Porch Active Video (lines) (lines) Table 17. NTSC and PAL Horizontal Timing Television Field Rate Lines Standard (Hz) per frame Line Rate (kHz) 2x pix Rate (MHz) fSC Freq. (MHz) Front Porch pixels Horiz Sync pixels Back Active Line Porch Video H pixels pixels pixels NTSC 59.94 525 15.734 24.545 3.579 18 58 58 646 780 PAL 50.00 625 15.625 29.500 4.433 18 70 82 774 944 PALM 60 525 15.734 25.570 3.576 18 58 58 646 780 Table 18. NTSC and PAL Vertical Timing TV Std Field Rate Lines per (Hz) frame Line Rate (kHz) Front Porch Vertical Sync Back Porch (lines) (lines) (lines) Active Video (lines) NTSC 59.94 525 15.734 3-3.5 3 14-14.5 242.5 PAL 50.00 625 15.625 2.5 2.5 21 286.5 PALM 60.00 525 15.750 3 3 14 242.5 11 TMC2360 TMC2360 PRODUCT SPECIFICATION Timing Diagrams VGA HSYNC Line 1 Line 2 Line 3 Line 4 Line 5 VGA VSYNC -Line 4/1- TV SYNC F1 -Line 5/2- -Line 267/314- -Line 5/3- -Line 268/315- TV SYNC F2 65-3687-02 Figure 3. Nominal VGA-NTSC/PAL Vertical Sync Timing VGA HSYNC VGA in Line 35/103 Video Field 1 Line 284/365 Video Field 2 65-3687-03 Figure 4. Nominal VGA640-NTSC/PAL VGA640-NTSC/PAL, No Filter Timing VGA HSYNC VGA in Line 35/103 Video Field 1 Line 21/52 Line 284/365 Video Field 2 3687-04 Figure 5. Nominal VGA-NTSC/PAL, Medium Filter Timing VGA HSYNC VGA in Video Field 1 Video Field 2 Line 35/103 Line 21/52 Line 22/53 Line 284/365 65-3687-05 Figure 6. Nominal VGA-NTSC/PAL, High Filter Timing 12 PRODUCT SPECIFICATION TMC2360 TMC2360 Timing Diagrams (continued) tPLCS tDOM tHA tSA tPHCS tDOZ tHOM CE RW A0 D[0:9] 65-3547-02 Figure 7. Microprocessor Read Timing tPLCS tSA tHA tPHCS tSD tHD CE RW A0 D[0:9] 65-3547-03 Figure 8. Microprocessor Write Timing 13 TMC2360 TMC2360 PRODUCT SPECIFICATION Equivalent Circuits VDD VDD p p Digital Input Digital Output n GND n Figure 9. Equivalent Digital Input Circuit VDDA 27011D 27011D GND 27014D 27014D Figure 10. Equivalent Digital Output Circuit VRT RT Internal Reference Ladder VIN 270½ total 29030 AGND VRB 29003 Figure 11. Equivalent A/D Input Circuit Figure 12. Equivalent A/D Reference Input Circuit VDD VDD p p RREF n p VREF VDD OUT GND 27012B 27012B Figure 13. Equivalent D/A Reference Input Circuit 14 GND 27013B 27013B Figure 14. Equivalent D/A Output Circuit PRODUCT SPECIFICATION TMC2360 TMC2360 Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Min. Typ. Max. Unit Power Supply Voltages VDDA (Measured to AGND) -0.5 7.0 V VDD (Measured to DGND) -0.5 7.0 V VDDA (Measured to VDD) -0.5 0.5 V AGND (Measured to DGND) -0.5 0.5 V -0.5 VDD + 0.5 V -10.0 10.0 mA -0.5 VDDA + 0.5 V -10.0 10.0 mA -0.5 VDD + 0.5 V -6.0 6.0 mA 1 second 110 °C Junction 150 °C Lead Soldering (10 seconds) 300 °C Vapor Phase Soldering (1 minute) 220 °C 150 °C ±150 V Digital Inputs Applied Voltage (Measured to DGND)2 Forced current 3, 4 Analog Inputs Applied Voltage (Measured to AGND)2 Forced current 3, 4 Digital Outputs Applied Voltage (Measured to DGND)2 Forced current 3, 4 Short circuit duration (single output in HIGH state to ground) Temperature Operating, Ambient Storage -20 -65 Electrostatic Discharge5 Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 5. EIAJ test method. Operating Conditions Parameter Min. Nom. Max. Units VDD Digital Power Supply Voltage 4.75 5.0 5.25 V VDDA Analog Power Supply Voltage 4.75 5.0 5.25 V AGND Analog Ground (Measured to DGND) -0.1 0 0.1 V VRT Reference Voltage, Top 0.5 0.75 2.0 V VIN Analog Input Range VRT V VREF External Reference Voltage 1.235 V IREF D/A Converter Reference Current (IREF = VREF/RREF, flowing out of the RREF pin) 3.15 mA RREF Reference Resistor, VREF = Nom 392 W ROUT DAC Total Output Load Resistance 37.5 W TA Ambient Temperature, Still Air 0 0 70 °C 15 TMC2360 TMC2360 PRODUCT SPECIFICATION Electrical Characteristics Parameter Conditions Min. Typ. Max. Unit 400 mA Power Supply Currents IDD Operating CVIDEN = H, SVIDEN = H 300 IDDS Standby CVIDEN = L, SVIDEN = L 100 IDDQ Power-Down PWRDN = L IDDSV S-Video Active CVIDEN = L, SVIDEN = H IDDCV Composite Video Active CVIDEN = H, SVIDEN = L mA 5 mA 250 350 mA 200 270 mA 10 pF Digital Inputs and Outputs CI Input Capacitance 5 CO Output Capacitance 10 IIH Input Current, HIGH VDD = Max, VIN = VDD VDD = Max, VIN = 0 V pF ±10 mA ±10 mA IIL Input Current, LOW VIHTTL Input Voltage, Logic HIGH (TTL) VILTTL Input Voltage, Logic LOW (TTL) VIHCMOS Input Voltage, Logic HIGH (CMOS) VILCMOS Input Voltage, Logic LOW (CMOS) VT+ Schmitt Trigger Positive Threshold 3.0 V VT- Schmitt Trigger Negative Threshold 0.8 V IOH Output Current, Logic HIGH -2.0 mA IOL Output Current, Logic LOW 2.0 mA VOH Output Voltage, HIGH IOH = -2mA VOL Output Voltage, LOW IOL = 2mA 2.0 V 0.8 3.5 V V 1.5 2.4 V V 0.4 V Analog Inputs CAI A/D Input Capacitance RIN A/D Input Resistance ICB A/D Input Current VRO Voltage Reference Output Internal Reference 0.988 IRO VREF Output Current External VREF ADCLK = LOW ADCLK = HIGH 4 12 500 pF pF 1000 KW ±15 mA 1.482 V -150 +150 mA -0.4 2 V 1.235 Analog Outputs VOC Video Output Compliance ROUT Video Output Resistance COUT Video Output Capacitance IOS Short-Circuit Current -20 IILP Input Current, LOW with pull-up -100 16 15 15 COUT = 0 mA, Frequency = 1 MHz KW pF -80 mA mA PRODUCT SPECIFICATION TMC2360 TMC2360 Switching Characteristics Parameter Conditions Min. Typ.1 Max. Unit Clocks fXTAL Crystal/Reference Clock Frequency 27 MHz fXTOL Crystal/Reference Clock Frequency Tolerance 50 ppm tPWH Reference Clock Pulse Width, HIGH 18.5 ns tPWL Reference Clock Pulse Width, LOW 18.5 ns 60 Hz Modes 30.840 31.469 32.100 KHz 50 Hz Modes 30.630 31.250 31.880 KHz 60 Hz Modes 525 50 Hz Modes 625 Syncs fH NH VGAHS Frequency Lines per VGA frame ±0 Tolerance tPWHS VGAHS Pulsewidth 2 ms tVS-HS VGAVS to VGAHS Delay 0 ns tDS Sync Delay (VGA Sync to Sync Out) 100 ns Video Output tDOV Analog Output Delay (PXCK Out to Video Out) tR D/A Output Current Risetime (10% to 90%) 2.2 ns tF D/A Output Current Falltime (90% to 10%) 2 ns SKEW D/A to D/A Skew 15 -3 0 3 ns ns Controls tPWH Control Input Pulse Width, HIGH 50 ns tPWL Control Input Pulse Width, LOW 50 ns Microprocessor Interface tPLCS CS Pulse Width, LOW 12 ns tPHCS CS Pulse Width, HIGH 8 ns tSA Address Setup Time 2 ns tHA Address Hold Time 4 ns tSD Data Setup Time 7 ns tHD Data Hold Time 2 ns tDOZ Output Delay, CS to low-Z 4 ns tHOM Output Hold Time, CS to high-Z 9 tDOM Output Delay, CS to Data Valid ns 40 ns Notes: 1. Values shown in Typ column are typical for VDD = VDDA = +5V and TA = 25°C. 17 TMC2360 TMC2360 PRODUCT SPECIFICATION System Performance Characteristics Parameter Conditions Min Typ1 Max Unit A/D Converter Input ELI A/D Integral Linearity Error, Independent VRT = 0.7V ±1 LSB ELD A/D Differential Linearity Error VRT = 0.7V ±1 LSB EAP Aperture Error 30 ps EOT Offset Voltage, Top RT ­ VIN for most positive code transition -20 45 80 mV EOB Offset Voltage, Bottom VIN for most negative code transition 30 65 110 mV 9 9 9 Bits D/A Converter Output RES D/A Converter Resolution dp Differential Phase PXCK = 27 MHz, 40 IRE Ramp 0.5 degree dg Differential Gain PXCK = 27 MHz, 40 IRE Ramp 1.5 % PSRR Power Supply Rejection Ratio CBYP = 0.1 mF, f = 1 KHz 0.5 %/ %VDD Notes: 1. Values shown in Typ column are typical for VDD = VDDA = +5V and TA = 25°C. 18 PRODUCT SPECIFICATION Applications Discussion Applications Circuit Two applications circuits are shown. Figure 15 is the standard applications circuit. Figure 16 is a simplified circuit that exploits many of the internal features of the TMC2360 TMC2360. The standard applications circuit is intended for third party add-on modules that interface a PC to a TV. Emitter followers buffer the VGA RGB signals so that VGA monitor disconnect does not impact the level of the TV image. Reference clock source is a crystal which requires tuning. A clock oscillator is recommended. VREF and VTIN are derived from an external voltage reference with an adjustment potentiometer. Although intended for VGA controller applications, the simplified circuit embodies many techniques that can be exported to other applications. Bandwidth of the incoming RGB signals is limited to 12 MHz to equalize intensities of parallel vertical lines. Pull-up resistors compensate for the bottom offset voltages of the A/D converters. RREF is comprised of two series resistors which divide down the voltage for VT. Sinx/x filters are omitted since with 2x oversampling, losses are small (~ 1 dB). A low pass equiphase filter in the CVBS channel cuts HF transients for vectorscope measurements. PLL power is derived from two separately filtered sources. TMC2360 TMC2360 Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor A/D conversion. Consider the following suggestions for layout: 1. Keep the critical analog traces as short as possible and as far as possible from all digital signals. Locate the TMC2360 TMC2360 near the board edge, close to the analog input/output connectors. 2. The power plane for the TMC2360 TMC2360 should be separate from that which supplies the rest of the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the TMC2360 TMC2360 is the same as that of the system's digital circuitry, power to the TMC2360 TMC2360 should be decoupled with ferrite beads and 0.1mF capacitors to reduce noise. 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. 4. Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They supply different circuits on the integrated circuit, each of which generate varying amounts and types of noise. For best results, use 0.1mF ceramic capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. 5. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC2360 TMC2360, the voltage reference, or the analog inputs. Capacitive coupling of digital power supply noise from this layer to the TMC2360 TMC2360 and its related analog circuitry can have an adverse effect on performance. Grounding Analog and digital circuits are separated within the TMC2360 TMC2360. To keep digital system noise from the A/D and D/A converters, it is recommended that power supply voltages (VDD and VDDA) originate from the same low-noise source, and that ground connections (DGND and AGND) be made to the analog ground plane. Power supply connections should be individually decoupled at each pin. Digital circuitry deriving input from the TMC2360 TMC2360 should be referred to the system digital ground plane. The 27 MHz clock reference or crystal should be handled carefully. Jitter and noise on this clock will degrade performance. With an external clock, the line should be terminated to eliminate overshoot and ringing. Locate phase locked loop components close to the relevant TMC2360 TMC2360 pins. Isolate these components from noise. 19 TMC2360 TMC2360 PRODUCT SPECIFICATION 1.8µH VIDEO FROM TMC2360 TMC2360 1.0µH 75½ VGAVS VGAHS VGA IN VDD DGND LPF CHROMA LUMA COMPOSITE 150 R Bead +5V 220 3.3k½ 0.1µF VREF 75½ LM185 LM185 -1.2 RREF 392½ 150 VGA OUT Bead TMC2360 TMC2360 G +5V 220 +5V VDDA CBYPR 47pF Bead 330pF 0.1µF AGND Bead 330pF VIDEO OUT 0.1µF 75½ 100pF +5V Bead 100µF VDDA VDDPLLD VDDPLLE 100µF VIDEO OUTPUT TO 75½ LOAD 1N5818 1N5818 27pF 47pF Video Output Processor 75½ 4.3k½ VTIN VTOUT VT 10k½ 0.1µF 0.1µF 2.7pF 5.6pF Bead 47pF XTAL1 150 Bead B HC-49/U HC-49/U 27.00000MHz XTAL2 +5V 220 47pF 27MHz PXCK ADCLK 75½ 56pF 39K LPFD LPFE TVSTD1 TVSTD0 PAL800 PAL800 DPMS VSCOM PWRDN PHASE CVIDEN SVIDEN BLANK BLUE POSR POSD FIL VSOUT HSOUT MPEN, A1, A0 0.1µF 39K 680p 0.1µF 680p 47k 0.1µF 47k 0.1µF 47k 0.1µF 4.7k Notes: 1. Microprocessor bus is No Connect. 2. RESET is no connect. 3. Crystal oscillator connected to XTAL1 is recommended. 4. Contact factory for reference designs. 24463A +5V Figure 15. Typical application circuit with internal phase-locked loops 20 R8 274 C4 47pF +5 VDC DGND AGND L3 BEAD C14 47µF Beads may be replaced with lengths of copper trace. L2 BEAD 47pF/274 ohm filters band limit incoming video to 12 MHz to eliminate aliasing effects when sampling VGA signals with high frequency components. VGA HSYNC VGA VSYNC BLUE GREEN R7 274 Tap VGA RGB and sync signals from graphics controller. R5 274 RED C17 0.1 C4 47pF C15 0.1 C21 0.1 C16 0.1 TVSTD pins preprogrammed for NTSC. No connect pins have internal pull-ups. C4 47pF C20 0.1 C22 0.1 C18 0.1 OUT U2 XCOHALF VDDA VDD 5 R4 27K VDDA R3 27K VDDA R2 27K VDDA G R 42 47 FIL 48 POS_R 71 POS_D RESET 6 39 PHASE 40 TVSTD_1 41 TVSTD_0 PAL800 PAL800 37 38 BLUE 44 BLANK 43 VSCOM DPMS 70 XTAL_1 69 XTAL_2 74 73 CVIDEN SVIDEN 72 PWRDN B 46 VGAHS 45 VGAVS 50 53 59 U1 2360KL 2360KL R15 100 R14 100 VDDA C23 0.1 C19 0.1 77 26 27 80 78 2 57 3 VDDPLLP VDDPLLA VDDD LPFP 67 LPFA 64 VREF 4 VTOUT 56 VT 55 VTIN RREF C11 680pF C9 0.1 C7 0.1 C1 0.1 VDDA C13 0.1 R13 39K C8 0.1 R11 237 R10 158 R9 75 R6 75 R1 75 C10 680pF C12 0.1 R12 39K C2 91pF L1 1.2UH D1 MBR0540T1 MBR0540T1 J2 RCA JACK CVBS CON4 J1 S-Video 1 2 3 4 Diodes extend ESD latchup protection but may be omitted. CVBS filter removes steps and aliasing frequencies from video out. C3 470pF VDDA Caution, sections of this circuit have been prototyped but the circuit has not been prototyped in its entirety. Use for reference only. Sum of resistors sets video output level. Ratio set digitization range. S-video filters may be removed if end product is compliant with FCC emission standards. XTL27 XTL27 11 PXCK 12 13 ADCLK CBYPR VSOUT HSOUT LUMA CHROMA COMPOSITE ADIVN PDIVM D7 D6 D5 D4 D3 D2 D1 D0 MPEN A1 A0 R/W CE 16 17 18 19 20 21 22 23 24 25 30 31 32 33 34 Optional bias resistors compensate for bottom offset voltage of A/D converters. PRODUCT SPECIFICATION TMC2360 TMC2360 Figure 16. Simplified Applications Circuit 21 TMC2360 TMC2360 Suggested User Instructions For a product incorporating the TMC2360 TMC2360, part of the documentation is expected to include operating instructions describing the functions of the TMC2360 TMC2360 user controls. A recommended text fragment follows. PRODUCT SPECIFICATION When the HORIZONTAL POSITION button is depressed, the TV window moves eight pixels to the right. At the maximum right position (+64 pixels) the direction reverses and the next sixteen pulses move the window left to the maximum left position (-64 pixels). Direction again reverses and the next sixteen pulses move the image right. Three external controls may be used to: Flicker Filter 1) position the image within the boundaries of the TV screen. Annoying artifacts can be eliminated by selecting one of three filter modes which trade-off vertical resolution against flicker. For example, without the filter, a single VGA line is encoded into only one field of the TV display. If there is high contrast between this line and adjacent lines, it will flicker at 30 Hz in NTSC or 25 Hz in PAL. 2) control vertical resolution. Each control is a button that can be momentarily depressed to execute one cycle of the selected function. Position Controls Position controls shift the viewed image horizontally or vertically to reveal portions of the image that are located near the edges or in the overscan areas. At power-up, the default position is the midpoint of the adjustment range. Each time the VERTICAL POSITION button is depressed, the TV window moves down by eight lines. At the lowest position (-64 lines) the direction reverses and depressing the button moves the image up in 8-line increments to the highest position (+64 lines). At this point the direction again reverses and the next sixteen pulses move the image down to the lowest position. Depressing the FILTER button indexes through the filter functions shown in the table below: FIL Filter Mode ¯ Soft vertical resolution without flicker ¯ Medium vertical resolution, some flicker ¯ Sharp vertical resolution with flicker Color bars The filter should be selected for best appearance on the TV screen. Optimal selection will depend on the image being encoded. Related Products · TMC2302 TMC2302 Image Manipulation Sequencer 22 PRODUCT SPECIFICATION TMC2360 TMC2360 Notes: 23 TMC2360 TMC2360 Notes: 24 PRODUCT SPECIFICATION PRODUCT SPECIFICATION TMC2360 TMC2360 Notes: 25 TMC2360 TMC2360 PRODUCT SPECIFICATION Mechanical Dimensions 80-Lead MQFP Package (KL) Inches Symbol Min. Millimeters Min. .134 - .120 .018 .009 .005 .904 .923 .783 .791 .667 .687 .547 .555 .0315 BSC .025 .041 80 24 16 A A1 A2 B Max. - .25 2.55 .30 - .010 .100 .012 C D D1 E E1 e L N ND NE a ccc 0¡ - Max. 3.40 - 3.05 .45 .23 .13 22.95 23.45 19.90 20.10 16.95 17.45 13.90 14.10 .80 BSC .65 1.03 80 24 16 7¡ .004 0¡ - Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 5M-1982. 2. Controlling dimension is millimeters. 3, 5 5 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness. 4 7¡ 0.10 D D1 .20 (.008) Min. e 0¡ Min. Datum Plane C E1 E Pin 1 Identifier a .13 (.005) R Min. B L 0.063" Ref (1.60mm) Lead Detail See Lead Detail A Base Plane A2 A1 26 .13 (.30) R .005 (.012) Seating Plane -CLEAD COPLANARITY ccc C PRODUCT SPECIFICATION TMC2360 TMC2360 Mechanical Dimensions (continued) 80-Lead MQFP Package (KM) - 3.2mm Footprint, 2.0mm Thickness Inches Symbol Millimeters Min. Max. Min. Max. A A1 A2 B C D D1 E - .010 .075 .012 .005 .904 .783 .667 .096 - .083 .018 .009 .923 .791 .687 - .25 1.90 .30 .13 22.95 19.90 16.95 2.45 - 2.10 .45 .23 23.45 20.10 17.45 E1 e L N ND NE .547 .555 .0315 BSC .029 .041 80 24 16 Notes: Notes a ccc 0¡ - 2. Controlling dimension is millimeters. 3, 5 5 0¡ - 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness. 13.90 14.10 .80 BSC .73 1.03 80 24 16 7¡ .004 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 5M-1982. 4 7¡ 0.10 D D1 .20 (.008) Min. e 0¡ Min. Datum Plane .13 (.30) R .005 (.012) C E1 E Pin 1 Identifier a .13 (.005) R Min. B L 0.063" Ref (1.60mm) Lead Detail See Lead Detail A Base Plane A2 A1 Seating Plane -CLEAD COPLANARITY ccc C 27 PRODUCT SPECIFICATION TMC2360 TMC2360 Ordering Information Product Number Temperature Range Screening Package Package Marking TMC2360KLC TMC2360KLC 0°C to 70°C Commercial 80 Lead MQFP 2360KLC 2360KLC TMC2360KMC TMC2360KMC 0°C to 70°C Commercial 80 Lead MQFP 2360KMC 2360KMC LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS70002360 DS70002360 Ó 1998 Fairchild Semiconductor Corporation