CCIR-601/624 TMC22153 17-1F 27-2F FMT422 UG07-0 VG07-0 YG09-8 UG010-8 VG09-8 - Datasheet Archive

 

TMC22x5y Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit Description · Very

 

www.fairchildsemi.com TMC22x5y Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit Description · Very high performance, low cost · Adaptive comb-based decoding · Multiple pin-compatible versions - 3-line, 2-line, and band-split - 8- and 10-bit processing · Internal digital linestores · Supports field- and frame-based decoding · Multiple input formats - CCIR-601/624 CCIR-601/624 (D1), D2, CVBS, YC · Multiple output formats - CCIR-601/624 CCIR-601/624 (D1), RGB, YCBCR · 10-18 Mpps data rate · Parallel and serial control interface · Single +5V power supply The TMC22x5y family of Digital Video Decoders offers unprecedented, broadcast-quality video processing performance in a single chip. It accepts line-locked or subcarrierlocked composite, YC, or D1 digital video and produces digital components in a variety of formats. An internal three-line adaptive comb decoder structure produces optimal picture quality with a wide range of source material. Field- and frame-based decoding is supported with external memory. Full comb programmability allows the user to tailor the decoder's response to a particular systems goals. A family of products offers 3-line, 2-line, and simple decoders in 8-bit and 10-bit versions-all in a pin and softwarecompatible format. Serial and parallel control ports are provided. These submicron CMOS devices are packaged in a 100-lead Metric Quad Flat Pack (MQFP). Applications · Studio television equipment · Personal computer video input · MPEG and JPEG compression inputs Block Diagram BUFFER MASTER1-0 Y/C Split0 VIDEOA9-0 Input Processor Linestore1 Y/C Split1 VIDEOB9-0 Linestore2 CLOCK LDV HSYNC VSYNC Adaptive Comb Filter G/Y9-0 Chroma Demod Output Processor R/Cr9-0 Burst Locked Loop Comb Fail Y/C Split2 B/Cb9-0 FID2-0 AVOUT DHSYNC DVSYNC Internal Sync Pulse Generator Global Control Parallel Control A1-0 R/W CS D 7-0 SET RESET SER Serial Control SA2-0 SDA SCL 65-22x5y-01 Rev. 0.9.1 PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information. Preliminary Information Features TMC22x5y PRODUCT SPECIFICATION Preliminary Information Table of Contents Features .1 Applications .1 Description .1 Block Diagram .1 Contents .2 List of Tables and Figures .3 General Description .4 Input Processor.4 Adaptive Comb Filter.4 Output Processor .5 Parallel and Serial Microprocessor Interfaces.5 Pin Assignments .5 Pin Descriptions.6 Control Register Map.8 Control Register Definitions .11 Decoder Introduction.38 YC Separation .38 Comb Filter Architecture for YC Separation .39 YC Line-Based Comb Filters.40 D1 Line-Based Comb Filters .40 NTSC Frame and Field Based Decoders .40 Composite Frame-Based Comb Filters .40 Composite Field-Based Comb Filters .40 PAL Frame and Field-Based Decoders .40 Composite PAL Frame Based Comb Filters.40 The TMC22x5y Comb Filter Architecture.42 TMC22x5y Functional Description .43 Input Processor.43 Bandsplit Filter (BSF) .43 Comb Filter Input.44 Adaptive Comb Filter.45 Comb Fails.48 Comb Fail Detection .48 Generation of the Comb Fail Signals .49 Luma Error Signals .49 Hue and Saturation Error Signals.49 Picture Correlation .49 Adapting the Comb Filter .49 XLUT .50 Digital Burst Locked Loop .52 Color Kill Counter .52 PAL Color Frame Bit .53 Hue Control.53 2 System Monitoring of the Burst Loop Error . 53 Clamp Circuit . 54 Pedestal Removal . 54 Luma Notch Filter . 55 Matrix . 55 Programmable U Scalar. 55 Programmable V Scalar. 55 Programmable Y Scalar. 55 Programmable MS Scalar. 55 Fixed (B-Y) and (R-Y) Scalars . 55 Y Offset . 56 Matrix Limiters. 56 Examples of Output Matrix Operation . 56 Simple Luma Color Correction . 57 CBCR MSB Inversion . 57 Output Rounding . 57 Output Formats. 57 Decimating CBCR Data. 57 Multiplexed YCBCR Output (TRS Words Inserted). 57 YC Outputs. 57 The LDV Clock . 57 Sync Pulse Generator . 58 Internal Field and Line Numbering Scheme . 58 Timing Parameters . 60 Subcarrier Programming . 60 Horizontal Timing . 60 Vertical Blanking . 61 VINDO Operation . 62 Video Measurement. 64 Pixel Grab. 64 Composite Line Grab . 66 Serial Control Port (R-Bus). 67 Equivalent Circuits and Threshold Levels . 70 Absolute Maximum Ratings. 71 Operating Conditions . 72 Electrical Characteristics. 74 Switching Characteristics. 75 System Performance Characteristics . 75 Programming Examples. 76 Programming Worksheet . 80 Related Products . 81 Ordering Information . 84 PRODUCT SPECIFICATION TMC22x5y List of Tables and Figures Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Logic Symbol. 4 Pixel Data Format . 4 Fundamental Decoder Block Diagram . 38 Comparison of the Frequency Spectrum of NTSC and PAL Composite Video Signals . 38 Examples of Notch and Bandpass Filters. 39 . 39 Chrominance Vector Rotation in PAL and NTSC . 40 Chrominance Vector Rotation Over 4 Fields in NTSC . 40 Chrominance Vector Rotation Over 4 Fields in PAL. 41 Figure 10. TMC22x5y Line Based Comb Filter Architecture . 42 Figure 11. Input Processor . 43 Figure 12. Complementary Bandsplit Filter . 43 Figure 13. Bandsplit Filter, Full Frequency Response . 44 Figure 14. Bandsplit Filter, Passband Response . 44 Figure 15. Block Diagram of Comb Filter Input . 45 Figure 16. Signal Flow Around the Adaptive Comb Filter . 46 Figure 17. Example of a Comb Fail Using a NTSC Two Line Comb Filter. 48 Figure 18. Generation of Upper and Lower Comb Fail Signals . 49 Figure 19. Comb Filter Selection . 50 Figure 20. XLUT Input Selection . 51 Figure 21. Block Diagram of Digital Burst Locked Loop . 52 Figure 22. Gaussian Low Pass Filters. 53 Figure 23. Gaussian LPF Passband Detail. 53 Figure 24. Output Processor Block Diagram. 54 Figure 25. Adaptive Notch Filters . 55 Figure 26. Luminance Notch Filter . 55 Figure 27. Horizontal Timing . 60 Figure 28. NTSC Vertical Interval. 61 Figure 29. PAL-B,G,H,I,N Vertical Interval. 62 Figure 30. PAL-M Vertical Interval . 63 Figure 31. Pixel Grab Locations. 64 Figure 32. Relationship Between Pixel Count and Pixel Grab Value. 65 Figure 33. Microprocessor Parallel Port ­ Write Timing. 67 Figure 34. Microprocessor Parallel Port ­ Read Timing. 67 Figure 35. Serial Port Read/Write Timing. 68 Figure 36. Serial Interface ­ Typical Byte Transfer. 69 Figure 37. Equivalent Digital Input Circuit . 70 Figure 38. Equivalent Digital Output . 70 Figure 39. Threshold Levels for Three-state. 70 Figure 40. Input Timing Parameters . 71 Figure 41. Functional Block Diagram of the TMC22x5y G/Y, B/U, and R/V Output Stage. 72 Figure 42. Output Timing Parameters . 73 3 Preliminary Information Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. TMC22x5y Decoder Family. 3 Normalized Subcarrier Frequency as a Function of Pixel Data Rates. 43 Comb Filter Architecture . 47 Simple Example of an Adaptive Comb Filter Architecture . 47 Adaption Modes . 50 XLUT Input Selection . 51 XLUT Output Function . 51 XLUT Special Function Definitions. 51 PAL-B,G,H,I Bruch Blanking Sequence . 52 PAL-M Bruch Blanking Sequence . 53 Blanking Level Selection . 54 Adaptive Notch Threshold Control. 54 Matrix Limiters. 56 Output Format . 57 NTSC Field and Line Numbering . 58 PAL B,G,H,I Field and Line Numbering . 58 PAL M Field and Line Numbering . 58 Vertical Blanking Period . 59 Vertical Burst Blanking Period. 59 Table of Line Idents, LID[4:0] . 59 Timing Offsets . 60 PAL VINDO operation . 64 Pixel Grab Control. 65 Parallel Port Control. 66 Serial Port Addresses . 68 TMC22x5y PRODUCT SPECIFICATION General Description three-line comb filter can be programmed to emulate any of the other parts. All prototyping can be performed with this version to evaluate performance tradeoffs, and lower-cost versions are easily substituted in production. The TMC22x5y digital decoder can be used as a universal input to digital video processing systems by decoding digital composite video and transcoding digital component inputs into a common data format. Input Processor The digital comb filter decoder implements one of sixteen comb filter architectures to produce luminance and color difference component signals which are virtually free of the cross-color and cross-luminance artifacts associated with simple bandsplit filter decoders. The digitized video and clocks provided to the decoder can be either locked to the line frequency or the subcarrier frequency of the digitized waveform, providing broadcast quality decoding from the NTSC square pixel rate of 12.27 MHz to the PAL four times subcarrier pixel rate of 17.73 MHz. MSB Table 1. TMC22x5y Decoder Family Preliminary Information TMC2215y Function TMC2205y 3 3 2 1 2 1 10-bit Data 8-bit Data D1 Interface fSC-Locked Mode Genlock Mode Frame-Based Comb 3-Line Comb 2-Line Comb Line Grab Pixel Grab Because the cost/performance tradeoff varies among applications, the TMC22x5y decoder has been developed as a family of six parts. They are all assembled in the same package, and fit the same footprint. The register maps are identical. VIDEOA9-0 VIDEOB9-0 G/Y9-0 B/CB9-0 R/CR9-0 TMC22x5y Multistandard Digital Video Decoder FID2-0 AVOUT DHSYNC DVSYNC SER SET RESET SA2-0 SDA SCL CS R/W 65-22x5y-02 Figure 1. Logic Symbol The devices come in 8- and 10-bit resolution versions (see Figure 2 for data alignment between 8- and 10-bit versions). Within each resolution version there are three models, offering three-line adaptive comb filtering, two-line adaptive comb filtering, and simple decoding. The TMC22153 TMC22153 10-bit 4 ··· VA1 VA0 VA2 VB2 VB1 VB0 G/Y2 G/Y1 G/Y0 10 bit B/CB2 B/CB1 B/CB0 R/CR2 R/CR1 R/CR0 ··· VA2 VB2 G/Y2 B/CB2 R/CR2 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C 8 bit Figure 2. Pixel Data Format Field-Based Comb D7-0 A1-0 VA8 VA9 VB9 VB8 G/Y9 G/Y8 B/CB9 B/CB 8 R/CR9 R/CR8 VA8 VA9 VB9 VB8 G/Y9 G/Y8 B/CB9 B/CB 8 R/CR9 R/CR8 Line-Locked Mode CLOCK LDV HSYNC VSYNC MASTER BUFFER LSB Inputs containing embedded GRS (Fairchild Video Input Processors), TRS words (D1 multiplexed component signals), and TRS-ID words (deserialized D2 signals) can be used to lock the internal horizontal and vertical state machines to the embedded information. If this information is not provided, external horizontal and vertical syncs are required for all line-locked input formats, and are optional for NTSC inputs locked to four times the subcarrier (4*Fsc). A simple sync separator is provided for digitized inputs locked to the subcarrier frequency: the internal sync separator locks to the mid point of syncs during the vertical field group, then flywheels during the active portion of the field. For this reason, the DHSYNC and DVSYNC operations are not guaranteed in subcarrier mode. Adaptive Comb Filter The line based adaptive comb filter in the TMC22x5y adds or subtracts the high frequency data from three adjacent field lines to produce the average of the high frequency luminance by canceling the chrominance signals, which in flat fields of color are 180 degrees apart. Unfortunately flat fields of color are rare and, when vertical transitions in the picture occur, the output of the comb filter contains a mixture of both high frequency luminance and chrominance, at which time the comb fails. To avoid the comb filter artifacts that occur when this happens, three sets of error signals are sent to a user-programmable lookup table, allowing the output of the comb filter to be mixed with the output of an internal bandsplit decoder. To produce these comb fail error signals, the video on each of the inputs to the comb filter is passed through a simple bandsplit decoder. The low-frequency portion of the signal is assumed to be luminance and the high frequency portion is PRODUCT SPECIFICATION TMC22x5y processed as chrominance to find the magnitude and phase of the chrominance vector. These three components are then compared across the (0H & 1H) and (1H & 2H) taps of the comb filter to produce the difference in luminance, chrominance magnitude, and chrominance phase. These differences are then translated in the user-programmable lookup table to produce the "K" signal which controls the complementary mix between the output of the comb filter and the simple bandsplit decoder. That is, the "K" signals controls how much of the combed high frequency luminance signal is subtracted from the simple bandsplit chrominance for chroma combs, or added to the low frequency output of the bandsplit for luma comb filters. Output Processor The parallel microprocessor interface employs 12 pins, the serial port uses 5. A single pin, SER, selects between the two interface modes. In parallel interface mode, one address line is decoded for access to the internal control register and its pointer. Controls are reached by loading a desired address through the 8-bit D7-0 port, followed by the desired data (read or write) for that address. The control register address pointer auto-increments to address 3Fh and then remains there. A 2-line serial interface may also be used for initialization and control. The same set of registers accessed by the parallel port is available to the serial port. The device address in the serial interface is selected via pins SA2-0. The RESET pin sets all internal state machines to their initialized conditions and places the decoder in a power-down mode. All register data are maintained while in power-down mode. Pin Assignments 100 81 1 80 30 51 31 50 65-22x5y-03 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name G/Y1 G/Y0 LDV GND VDD B/Cb9 B/Cb8 B/Cb7 B/Cb6 B/Cb5 B/Cb4 B/Cb3 B/Cb2 B/Cb1 B/Cb0 GND VDD R/Cr9 R/Cr8 R/Cr7 R/Cr6 R/Cr5 R/Cr4 R/Cr3 R/Cr2 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name R/Cr1 R/Cr0 GND VDD AVOUT FID0 FID1 FID2 DHSYNC DVSYNC D0 D1 D2 GND VDD D3 D4 D5 D6 D7 GND VDD HSYNC VSYNC BUFFER Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name RESET SET SER SA0 SA1 SA2 GND SDA SCL CS R/W A0 A1 GND VDD VIDEOB0 VIDEOB1 VIDEOB2 VIDEOB3 VIDEOB4 VIDEOB5 VIDEOB6 VIDEOB7 VIDEOB8 VIDEOB9 Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name GND VIDEOA0 VIDEOA1 VIDEOA2 VIDEOA3 VIDEOA4 VIDEOA5 VIDEOA6 VIDEOA7 VIDEOA8 VIDEOA9 MASTER0 MASTER1 CLOCK GND VDD GND G/Y9 G/Y8 G/Y7 G/Y6 G/Y5 G/Y4 G/Y3 G/Y2 5 Preliminary Information The demodulated chrominance signal and the luminance signal are passed through a programmable output matrix, producing RGB, YUV, or YCBCR. When the clock is at 27MHz, a D1 signal can be produced on the R/V output with the embedded TRS words fixed to the external HSYNC and VSYNC timing. Parallel and Serial Microprocessor Interfaces TMC22x5y PRODUCT SPECIFICATION Pin Descriptions Pin Name Pin Number Value Pin Function Description Inputs 86, 85, 84, 83, 82, 81, 80, 79, 78, 77 TTL Video input A. An 8 or 10 bit data input to the input multiplexer. For 8-bit versions (TMC2205y) the data are left-justified (VIDEOA9-2). VIDEOB9-0 75, 74, 73, 72, 71, 70, 69, 68, 67, 66 TTL Video input B. An 8 or 10 bit data input to the input multiplexer. For 8-bit versions (TMC2205y) the data are left-justified (VIDEOB9-2). VSYNC 49 TTL Vertical sync input. A vertical sync signal (active low) occurring at the start of the first vertical sync pulse in a vertical field group. A falling edge of VSYNC which is coincident with a falling edge of HSYNC indicates field 1. This signal is active only when SPGIP1-0 = 00. HSYNC Preliminary Information VIDEOA9-0 48 TTL Horizontal sync input. A horizontal sync signal (active low) occurring at the falling edge of the video sync. This signal is active only when SPGIP1-0 = 00. 88, 87 TTL Master decoder control. MASTER1-0 00 01 10 11 Adaptive comb decoder Simple bandsplit decoder Non adaptive comb filter Flat notched luma and simple bandsplit chroma BUFFER 50 TTL Control register select. This signal switches between two sets of registers which control the gain or hue values in the output matrix. When BUFFER = 0, registers 17-1F 17-1F are active. When BUFFER = 1, registers 27-2F 27-2F take control. CLOCK 89 TTL Master processing clock. The clock signal can either be at twice the pixel data rate in the line locked modes, or at four times the subcarrier frequency in the subcarrier mode. The interpretation of the CLOCK signal is set by the CKSEL register bit. SET 52 TTL Programmable function pin. The function specified by the SET register is active when SET is low. The decoder returns to its previous operation when SET goes high. G/Y9-0 93, 94, 95, 96, 97, 98, 99, 100, 1, 2 TTL Green or Luminance digital output. For 8-bit versions (TMC2205y) the data are left-justified (G/Y9-2). B/CB9-0 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 TTL Blue or CB digital output. For 8-bit versions (TMC2205y) the data are left-justified (B/CB 9-2). R/CR9-0 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 TTL Red or CR digital output. For 8-bit versions (TMC2205y) the data are left-justified (R/CR 9-2). DVSYNC 35 TTL Vertical sync output. The DVSYNC signal occurs once per field and lasts for 1 video line. DHSYNC 34 TTL Horizontal sync output. The DHSYNC signal occurs once per line and lasts for 64 clock periods. LDV 3 TTL Data synchronization output. LDV can be an internally or externally generated clock signal. The internal LDV signal is produced when the CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data rate clock phase locked to the falling edge of the HSYNC. The external LDV can be selected under software control, and must be at the CLOCK, or a sub multiple of the CLOCK, frequency. Outputs 6 PRODUCT SPECIFICATION TMC22x5y Pin Descriptions (cont.) Pin Name Pin Number Value Pin Function Description AVOUT 30 TTL Active video output flag. The active video output is HIGH during the video portion of each line and LOW during the horizontal and vertical blanking intervals. FID2-0 33, 32, 31 TTL Field identification output. A 3 bit field ident from the DRS signal. D7-0 45, 44, 43, 42, 41, 38, 37, 36 TTL Parallel control port data I/O. All control parameters are loaded into and read back over this 8 bit data port. A1-0 63, 62 TTL Parallel control port address inputs. These pins govern whether the microprocessor interface selects a table/register address or reads/ writes table/register contents. CS 60 TTL Parallel control port chip select. When CS is high the microprocessor interface port, D7-0, is set to HIGH impedance and ignored. When CS is LOW, the microprocessor can read or write parameters over D7-0. R/W 61 TTL Parallel control port read/write control. When R/W and CS are LOW, the microprocessor can write to the control registers or XLUT over D7-0. When R/W is HIGH and CS is LOW, it can read the contents of any selected XLUT address or control register over D7-0. RESET 51 TTL Chip master reset. Bringing RESET LOW sets the software reset control bit, SRESET, LOW and disables the digital outputs. If HRESET is LOW the decoder outputs remain disabled after RESET goes HIGH until the SRESET bit is set high by the host. If HRESET is HIGH when RESET goes HIGH the decoder the internal state machines are enabled. SER 53 TTL Serial/parallel interface select. This pin will select between a parallel (HIGH) or serial (LOW) interface port. SDA 58 R-Bus Serial data interface. Bi-directional serial interface to the control port. SCL 59 R-Bus Serial interface clock. 56, 55, 54 TTL Serial Address. Three bits providing the lsbs of the serial chip ID used to identify the decoder. VDD 5, 17, 29, 40, 47, 65, 91 +5 V Power Supply. Positive power supply for digital circuits, +5V. GND 4, 16, 28, 39, 46, 57, 64, 76, 90, 92 0.0 V Ground. Ground for digital circuits, 0V. mP Interface Power Supply 7 Preliminary Information SA2-0 TMC22x5y PRODUCT SPECIFICATION Control Register Map Reg The TMC22x5y is initialized and controlled by a set of registers which determine the operating modes. An external controller is employed to write and read the Control Registers through either the 8-bit parallel or 2-line serial interface port. The parallel port, D7-0, is governed by pins CS, R/W, and A1-0. The serial port is controlled by SDA and SCL. Reg Bit Name Function Bit Name Function Luma Processor Control 06 7-6 06 5 ANEN Adaptive notch enable reserved, set to zero 06 4 ANR Adaptive notch rounding 06 3-2 ANT Adaptive notch threshold 06 1 ANSEL Adaptive notch select 06 0 NOTCH Notch enable Comb Processor Control Global Control 7 SRST Software reset 07 7 LS1BY Line store 1 bypass 00 6 HRST Hardware reset 07 6 LS1IN Line store 1 input 00 5-3 SET SET pin function 07 5 LS2DLY Line store 2 delay 00 Preliminary Information 00 2 DHVEN Output H&V sync enable 07 4 SPLIT Line store 2 data width Selects video standard 07 3 BSFBY Bandsplit filter bypass 07 2 BSFSEL Bandsplit filter select 07 1 BSFMSB Inverts msb of bandsplit filter 07 0 GRSDLY Delays input to GRS decode by 1H 00 1-0 STD Input Processor Control 01 7 reserved, set to zero 01 6 IPMUX Input mux control 01 5 IP8B 8 bit input format 01 4 TDEN TRS detect enable 01 3 TBLK TRS blank enable 08 7-2 MIDS Mid-sync level 01 2 IPCMSB Chroma input msb invert 08 1-0 CLMP Black level clamp selection 01 1 ABMUX AB mux control 01 0 CKSEL Input clock rate select 09 7-4 PCKF Clock rate 09 3-0 VSTD Video standard Burst Loop Control 02 7 02 6 VIPEN Video Input Processor enable 02 5-4 LOCK Global lock mode 02 3 BLM BLL lock mode 02 2 KILD Color kill disable 02 1 DMODBY Demod bypass 02 0 CINT CBCR interpolation enable 03 7-5 BLFS Burst loop filter select 03 4 CCEN Chroma coring enable 03 3-2 CCOR Chroma coring threshold 03 1 GAUBY Gaussian filter bypass 03 0 GAUSEL Gaussian filter select Burst Threshold 7-0 BTH Burst threshold Pedestal 05 8 7-0 Extended DRS reserved, set to zero Chroma Processor Control 04 Mid-Sync Level PED Pedestal level Output Control 0A 7 OP8B Output rounded to 8 bits 0A 6-5 OPLMT Output limit select 0A 4-3 MSEN Mixed sync enable 0A 2 OPCMSB Chroma output msb invert 0A 1 YBAL Luma color correction 0A 0 BUREN Output burst enable 0B 7 FMT422 FMT422 Enables CBCR output mux 0B 6 CDEC CBCR decimation enable 0B 5 YUVT Enables D1 output 0B 4-2 0B 1 DRSEN DRS output enable 0B 0 DRSCK DRS data rate reserved, set to zero Comb Filter Control 0C 7-6 ADAPT Adaption mode 0C 5 YCES YC input error signal control 0C 4 YCSEL luma/chroma comb filter select PRODUCT SPECIFICATION Reg Bit Name 0C 3-0 COMB 0D 7-6 CEST TMC22x5y Function Reg Bit Name Function Comb filter architecture 19 7-0 UG07-0 UG07-0 U gain, 8 lsbs Chroma error signal transform 1A 7-0 VG07-0 VG07-0 V gain, 8 lsbs 1B 7-6 YG09-8 YG09-8 Y gain, 2 msbs UG010-8 UG010-8 U gain, 3 msbs 0D 5 CESG Chroma error signal gain 1B 5-3 0D 4 YESG Luma error signal gain 1B 2 0D 3 CESTBY Chroma error signal bypass 1B 1-0 VG09-8 VG09-8 V gain, 2 msbs 0D 2 XFEN XLUT filter enable 1C 7-0 YOFF07-0 YOFF07-0 Y offset, 8 lsbs 0D 1 FAST Adaption speed select 1D 7-3 0D 0 YWBY Luma weighting bypass 1D 2 YOFF08 YOFF08 Y offset, msb 0E 7-6 XIP XLUT input select 1D 1-0 SG07-0 SG07-0 Msync gain, 2 msbs 0E 5-4 XSF XLUT special function 1E 7-0 SYSPH07-0 SYSPH07-0 8 lsbs of phase 0E 3-2 YMUX Y output select 1F 7-0 SYSPH015- SYSPH015- 8 msbs of phase 0E 1-0 CMUX C output select 0F 7 0F 6-5 0F reserved, set to zero reserved, set to zero Preliminary Information 8 Normalized Subcarrier Frequency reserved, set to zero 20 7-4 CAT Adaption Threshold 20 3-0 4 DCES D1 CBCR error signal 21 7-0 FSC11-4 FSC11-4 Lower 8 bits of fSC 0F 3-2 IPCF Comb filter input select 22 7-0 FSC19-12 FSC19-12 Middle 8 bits of fSC 0F 1 YCCOMP YC or Composite input select 23 7-0 FSC27-20 FSC27-20 Top 8 bits of fSC 0F 0 SYNC Sync processor select 2425 7-0 FSC3-0 Bottom 4 bits of fSC reserved, set to zero reserved, set to zero Sync Pulse Generator Output Format Control 10 7-0 STS7-0 Sync to sync 8 lsbs 26 7-6 11 7-0 STB Sync to burst 26 5 LDVIO LDV clock select 12 7-0 BTV Burst to video 26 4 OPCKS Output clock select 13 7-0 AV7-0 Active video line 8 lsbs 26 3 DPCEN DPC enable 14 7-6 reserved, set to zero 26 2-0 DPC Decoder product code 14 5-4 14 3 14 2-0 AV9-8 Active video line 2 msbs Buffered register set 1 Active when BUFFER pin set HIGH reserved, set to zero STS10-8 STS10-8 reserved, set to zero 7 15 6-2 VINDO 27 7-0 SG17-0 SG17-0 Msync gain, 8 lsbs reserved, set to zero 15 Sync to sync 3 msbs 28 7-0 YG17-0 YG17-0 Y gain, 8 lsbs Number of lines in vertical window 29 7-0 UG17-0 UG17-0 U gain, 8 lsbs 2A 7-0 VG17-0 VG17-0 V gain, 8 lsbs 15 1 VDIV Action inside VINDO 2B 7-6 YG19-8 YG19-8 Y gain, 2 msbs 15 0 VDOV Action outside VINDO 2B 5-3 UG110-8 UG110-8 U gain, 3 msbs 16 7-6 reserved, set to zero 2B 2 16 5-4 NFDLY new field detect delay 2B 1-0 VG19-8 VG19-8 V gain, 2 msbs 16 3-2 SPGIP SPG input select 2C 7-0 YOFF17-0 YOFF17-0 Y offset, 8 lsbs 16 1-0 MSIP Mixed sync separator input select 2D 7-3 2D 2 YOFF18 YOFF18 Y offset, msb 2D 1-0 SG17-0 SG17-0 Msync gain, 2 msbs Msync gain, 8 lsbs 2E 7-0 SYSPH17-0 SYSPH17-0 8 lsbs of phase Y gain, 8 lsbs 2F 7-0 SYSPH115- SYSPH115- 8 msbs of phase Buffered register set 0 Active when BUFFER pin set LOW 17 18 7-0 7-0 SG07-0 SG07-0 YG07-0 YG07-0 reserved, set to zero reserved, set to zero 8 9 TMC22x5y Reg Bit PRODUCT SPECIFICATION Name Function Video Measurement Reg Bit Name Function 41 6 BGST Start of burst gate 7 set to zero 41 5 VACT2 Half line flag 30 6 LGF Line grab flag 41 4 PALODD PAL Ident 30 5 LGEN Line grab enable 41 3 VFLY Vertical count reset 30 4 LGEXT Ext line grab enable 41 2 FGRAB Field grab 30 3 reserved, set to zero 41 1 LGRAB Line grab 30 2 PGG Pixel grab gate 41 0 PGRAB Pixel grab 30 1 PGEN Pixel grab enable 42 7 FLD Field flag (F in D1 output) 30 0 PGEXT Ext pixel grab enable 42 6 VBLK 31 Preliminary Information 30 7-0 PG7-0 Pixel grab, 8 lsbs Vertical blanking (V in D1 output) 32 7-0 LG7-0 Line grab, 8 lsbs 42 5 HBLK Horizontal blanking (H in D1 output) 42 4-0 LID Line identification 43 7 YGO Y/G overflow 43 6 YGU Y/G underflow 43 5 UBO CB/B overflow 43 4 UBU CB/B underflow 43 3 VRO CR/R overflow 43 2 VRU CR/R underflow 43 1-0 44 7 MONO Color kill active 44 6-0 FPERR Frequency/Phase error 45 7-0 DRS DRS signal 46 7-0 PARTID Reads back xxh 47 7-0 REVID Revision number 33 7 33 6-4 FG reserved, set to zero Field grab number 33 3 LG8 Msb of line grab 33 2-0 PG10-8 PG10-8 Pixel grab, 3 msbs 34 7-0 GY9-2 G/Y grab, 8 msbs 35 7-0 BU9-2 B/U grab, 8 msbs 36 7-0 RV9-2 R/V grab, 8 msbs 37 7-6 37 5-4 GY1-0 G/Y grab, 2 lsbs 37 3-2 BU1-0 B/U grab, 2 lsbs 37 1-0 RV1-0 R/V grab, 2 lsbs 38 7-0 Y9-2 Luma grab, 8 msbs 39 7-0 M9-2 Msync grab, 8 msbs 3A 7-0 U9-2 U grab, 8 msbs 3B 7-0 V9-2 V grab, 8 msbs 484A 7-0 3C 7-6 Y1-0 Luma grab, 2 lsbs 4B 7 3C 5-4 M1-0 Msync grab, 2 lsbs 4B 3C 3-2 U1-0 U grab, 2 lsbs 3C 1-0 V1-0 V grab, 2 lsbs reserved Test Control 3D3F 7-0 TEST set to zero Auto-increment stops at 3F Status - Read Only 40 7-0 DDSPH DDS phase, 8 msbs 41 7 LINEST Pixel count reset 10 reserved reserved PKILL Phase kill from comb fail 6-5 CFSTAT Comb filter status 4B 4-0 XOP XLUT output 4CFF 7-0 reserved Notes: 1. Functions are listed in the order of reading and writing. 2. For each register listed above up to register 3F, all bits not specified are reserved and must be set to zero to ensure proper operation. PRODUCT SPECIFICATION TMC22x5y Control Register Definitions Global Control Register (00) 7 6 SRST 5 4 HRST 3 SET 2 DHVEN 1 0 STD Bit Name Description 00 7 SRST Software reset. When LOW, resets and holds internal state machines and disables outputs. When HIGH (normal), starts and runs state machines and enables outputs. This bit is ignored while HRST is high. 00 6 HRST Hardware reset. When HRST is HIGH, SRST is forced low when RESET pin is taken LOW. State machines are reset and held. When HRST is low the RESET pin can be taken HIGH at any time. The state machines remain disabled until SRST is programmed HIGH. When HRST is high the state machines are enabled as soon as the RESET pin goes HIGH. 00 5-3 SET SET pin function. These bits control the set function when the SET pin goes low. A = all outputs high-impedance B = internal state machines C = burst locked loop SET Function 000 Reset and hold A, B, & C. 001 Set output to BLUE and flywheel B & C. (RGB outputs) Set output to "color" and flywheel B & C (YCBCR outputs) 010 Hold A, lock B & C to external input 011 Reset C only 100 Reset B & C 101 Set output to BLUE and lock B & C to input video (RGB output) 110 Line and pixel grab depending on VMCR6-0 (reg 30) 111 Toggle reset function of SET = 010. For each SET = 0 pulse the chip operation will change from normal to that of SET = 010 or visa versa. The first SET pulse after a software or hardware reset, with SET = 111, causes a toggle to SET = 010. 00 2 DHVEN Output H&V sync enable. Disables DHSYNC and DVSYNC signals when HIGH. 00 1-0 STD Selects video standard. Selects video standard. SET Function 00 NTSC 01 reserved 10 PAL/M 11 All PAL standards except PAL/M 11 Preliminary Information Reg TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Input Processor Control (01) 7 6 5 4 3 2 1 0 Reserved IPMUX IP8B TDEN TBLK IPCMSB ABMUX CKSEL Bit Name Description 01 7 Reserved Reserved, set to zero. 01 Preliminary Information Reg 6 IPMUX Input mux control. Used to select the Video Input Processor, D1, or D2 data as the VA input to the input processor. VIDEOA is selected for VA and VIDEOB is selected for VB when IPMUX is set LOW. VIDEOB is selected for VA and VIDEOA for VB when IPMUX is set HIGH. For YC inputs, the luma data must be passed through the VA input and chroma through the VB input. IPMUX should be set LOW for line locked composite inputs. 01 5 IP8B 8 bit input format. Bottom two bits of inputs VIDEOA9-0 and VIDEOB9-0 are set to zero when HIGH. 01 4 TDEN TRS detect enable. When HIGH, the TRS words embedded in incoming video are used to reset the horizontal and vertical state machines. When LOW the externally provided or internally generated HSYNC and VSYNC are used to reset the horizontal and vertical state machines. 01 3 TBLK TRS blank enable. Blanks the TRS and AUX data words when HIGH. For line locked and D1 data, the TRS and AUX data words are set to the luma and chroma blanking levels as appropriate. For D2 (4*fSC) data, the TRS and AUX data words are set to the sync tip level. 01 2 IPCMSB Chroma input msb invert. The msb of the chroma or CBCR data are inverted when HIGH. 01 1 ABMUX AB mux control. Selects the primary and secondary inputs to the decoder from the DA and DB outputs of the input processor. When ABMUX is LOW, DA is selected as the primary and DB as the secondary decoder input. 01 0 CKSEL Input clock rate select. Set HIGH for line locked clocks and LOW for subcarrier locked clocks. Line locked clocks should be at twice the pixel data rate, and the subcarrier clock should be at four times the subcarrier frequency. 12 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Burst Loop Control (02) 7 6 Reserved VIPEN 5 4 2 1 0 BLM LOCK 3 KILD DMODBY CINT Reg Bit Name Description 02 7 Reserved Reserved, set to zero. 02 6 VIPEN Video Input Processor enable. Selects interface protocol for Fairchild video input devices. Active only when LOCK1-0 = 10. VIPEN Function 1 02 5-4 LOCK Video Input Processor Interface TMC22071 TMC22071 Interface Global Lock mode. Sets the decoder locking mode. LOCK Function 00 01 BLM Video Input Processor Mode 11 3 Subcarrier Locked Mode 10 02 Line Locked Mode D1 Mode BLL lock mode. Sets the decoder burst locking mode. BLM Function 0 Frequency Lock 1 Phase Lock 02 2 KILD Color kill disable. Color killer is disabled when HIGH. 02 1 DMODBY Demod bypass. Chroma data bypasses the demodulator when HIGH. 02 0 CINT CBCR interpolation enable. Interpolation of CBCR input data from 0:2:2 to 0:4:4 is enabled when HIGH. 13 Preliminary Information 0 TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Chroma Processor Control (03) 7 6 5 4 BLFS 3 CCEN 2 CCOR Reg Bit Name 7-5 BLFS 0 GAUBY GAUSEL Description 03 1 Burst loop filter select. BLFS fS (Mpps) Recommended Criteria 13.5 PAL, Line-Locked YC 000 Preliminary Information 000 15 PAL, Line-Locked YC 001 12.27 NTSC, Line-Locked YC 001 13.5 PAL, Line-Locked Composite 010 13.5 NTSC, Line-Locked YC 010 15 PAL, Line-Locked Composite 011 14.32 NTSC, Subcarrier-Locked YC 011 17.73 PAL, Subcarrier-Locked Composite 100 17.73 PAL, Subcarrier-Locked YC 101 13.5 NTSC, Line-Locked Composite 110 12.27 NTSC, Line-Locked Composite 111 14.32 NTSC, Subcarrier-Locked Composite 03 4 CCEN Chroma coring enable. Enables Chroma Coring when HIGH. 03 3-2 CCOR Chroma coring threshold. Sets the Chroma Coring threshold. CCOR Function 00 1 lsb 01 2 lsb 10 3 lsb 11 4 lsb 03 1 GAUBY Gaussian filter bypass. The chroma data bypasses the Gaussian LPF when HIGH. 03 0 GAUSEL Gaussian LPF select. Selects the Gaussian filter response to be used on the demodulated chrominance. GAUSEL Function 0 Select Gaussian LPF resp. 2 1 Select Gaussian LPF resp. 1 See Figure 6 for filter responses. 14 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Burst Threshold (04) 7 6 5 4 3 2 1 0 BTH Reg Bit Name Description 04 7-0 BTH Burst threshold. The 8 bit value to be compared against the demodulated U and V component data. If over 127 lines occur in a field in which the burst is below this threshold, then the color is set to chroma black for the next field. Pedestal (05) 7 6 5 4 3 2 1 0 Reg Bit Name Description 05 7-0 PED Pedestal level. An 8 bit magnitude subtracted from the luma data to remove the setup before processing by the output matrix. Luma Processor Control (06) 7 6 5 4 ANEN Reserved ANR 3 2 ANT 1 0 YSEL NOTCH Reg Bit Name Description 06 7-6 Reserved Reserved, set to zero. 06 5 ANEN Adaptive notch enable. Enables adaptive notch when HIGH. 06 4 ANR Adaptive notch rounding. Sets adaptive notch rounding point. ANR Function 0 1 06 3-2 ANT Round to 10 bits Round to 8 bits Adaptive notch threshold level. Sets the adaptive notch threshold. ANT Function 00 01 YSEL Magnitude difference less than 16 11 1 Magnitude difference less than 24 10 06 Magnitude difference less than 32 Magnitude difference less than 8 Adaptive notch select. Selects adaptive notch filter response. YSEL Function 0 1 06 0 NOTCH Adaptive notch response ANF1 Adaptive notch response ANF2 Notch enable. Adaptive notch filter ANF3 selected when HIGH and ANEN is HIGH, non-adaptive notch filter selected when HIGH and ANEN is LOW. Function may be overridden by XSF (Reg 0E, bits 5-4). 15 Preliminary Information PED TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Comb Processor Control (07) 7 6 5 4 3 2 1 0 LS1BY LS1IN LS2DLY SPLIT BSFBY BSFSEL BSFMSB GRSDLY Reg Bit Name Description 07 7 LS1BY Line store 1 bypass. Bypasses linestore 1 when HIGH. 07 6 LS1IN Line store 1 input. Selects the input of linestore 1: LS1IN Function Preliminary Information 0 Primary Input 1 Secondary Input 07 5 LS2DLY Line store 2 delay. LSTORE2 uses STS to store 1H when LOW and uses VL to store SAV to EAV (or max count) when HIGH. 07 4 SPLIT Line store 2 delay. Splits data through LSTORE2, 9 bits chroma and 7 bits luma when HIGH (chroma combs) and 8 bits chroma and 8 bits luma when LOW (luma comb). 07 3 BSFBY Bandsplit filter bypass. Bandsplit filter is bypassed when HIGH. 07 2 BSFSEL Bandsplit filter select. Selects the bandsplit filter to be used: BSFSEL Function 0 Select bandsplit filter response 1 1 Select bandsplit filter response 2 07 1 BSFMSB Inverts msb of bandsplit filter. When HIGH, inverts the msb of the input to the bandsplit filter. 07 0 GRSDLY Delays input to GRS decode. When HIGH, delays the input to the GRS extraction circuit by 1H. Mid-Sync Level (08) 7 6 5 4 3 2 1 0 MIDS Reg Bit Name Description 08 7-2 MIDS Mid sync level. Sets the mid point of syncs in the mixed sync separator, in the subcarrier locked mode. 08 1-0 CLMP Clamp input selection CLMP[1:0] Function 00 Clamp disabled, black level set to 240 01 Clamp disabled, black level set to 256 10 Clamp enabled, use VIDEOB as reference 11 Clamp enabled, use internal LPF as reference Notes: 1. CLMP[1:0] controls the clamp algorithm in silicon revision G only. For silicon revisions A through F these two bits provide the lsbs of the sync level selection. 16 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Extended DRS (09) 7 6 5 4 3 2 PCKF 1 0 VSTD Reg Bit Name Description 09 7-4 PCKF Clock rate. PCKF Function reserved 0100 14.32 MHz 0101 17.73 MHz 0110 reserved 0111 reserved 1000 12.27 MHz 1001 14.75 MHz 1010 15.00 MHz 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 VSTD reserved 0011 3-0 reserved 0010 09 13.50 MHz 0001 reserved Preliminary Information 0000 Video Standard. Selects the video standard. VSTD Function 0000 NTSC-M 0001 NTSC-EIAJ 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 PAL-B, G, H, I 1001 PAL-M 1010 PAL-N (Argentina, Paraguay, Uruguay) 1011 PAL-N (Jamaica) 1100 reserved 1101 reserved 1110 reserved 1111 reserved 17 TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Output Control (0A) 7 6 5 4 OP8B OPLMT OPLMT 3 MSEN 2 1 0 OPCMSB YBAL BUREN Reg Bit Name Description 0A 7 OP8B Output rounded to 8 bits. Rounds the outputs to 8 bits when HIGH. The two lsbs are set to zero. 0A 6-5 OPLMT Output limit select. Sets the output format and limiters: OPLMT Function Preliminary Information 00 01 MSEN RGB output format Limited to 64 to 940 11 4-3 YCBCR output format Y limited to 0 to 1023 CBCR limited to ±511 10 0A RGB output format Limited to 0 to 1023 YCBCR output format Y limited to 64 to 940 CBCR limited to ±448 Mixed sync enable. Sets composite sync output format: MSEN Function 00 No sync, & "super blacks" disabled 01 No sync, & "super blacks" disabled 10 Sync on G/Y output only, & "super blacks" enabled 11 Sync on RGB outputs, & "super blacks" enabled 0A 2 OPCMSB Chroma output msb invert. Inverts the msb of the CBCR or Chroma output when HIGH. 0A 1 YBAL Luma color correction. Setting this bit HIGH forces the chroma to zero whenever the luma equals or exceeds the luma limit. 0A 0 BUREN Output burst enable. When HIGH, passes the burst through on the chroma channel. Sets the burst region to zero when LOW. Notes: 1. To enable "super blacks" and disable syncs of the output simply set MSEN[1] HIGH and the sync gain to zero. 18 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Output Control (0B) 7 6 5 4 FMT422 FMT422 CDEC YUVT 3 2 Reserved 1 0 DRSEN DRSCK Bit Name Description 0B 7 FMT422 FMT422 Enables CBCR output mux. When HIGH, multiplexes the CB and CR data onto the same data bus. The chroma or multiplexed CBCR output appears on the B/CB output. The R/CR output is forced low. 0B 6 CDEC CBCR decimation enable. When HIGH, the CBCR data are decimated to 0:2:2 in the output processor. 0B 5 YUVT Enables D1 output. When HIGH, enables 4:2:2 multiplexed YCBCR onto the R/CR data output with TRS words inserted into the output data stream. The Y data are still available on the G/Y output and multiplexed CBCR is available on the B/U output. 0B 4-2 Reserved Reserved, set to zero. 0B 1 DRSEN DRS output enable. When HIGH, enables the DRS onto the G/Y output. 0B 0 DRSCK DRS data rate. Sets the DRS output data rate. DRSCK Function 0 Embeds data bytes (8 bits) at PCK clock rate 1 Embeds data nibbles (4 bits) at PXCK clock rate 19 Preliminary Information Reg TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Comb Filter Control (0C) 7 6 4 YCES ADAPT 5 3 YCSEL 2 1 0 COMB Reg Bit Name Description 0C 7-6 ADAPT Adaption mode. Sets the 3-line comb filter adaption mode in NTSC. 3 line (tap) comb only. Never adapts to a 2 line (tap) filter. The higher set of comb filter error signals are sent to the XLUT. NTSC or PAL comb filter. 11 YCES Adapts to the best of two field or frame based comb in NTSC only. 10 5 Adapts to best of 3 types of line based comb filters in NTSC only. 01 0C Function 00 Preliminary Information ADAPT[1:0] Adapts to best of two 3 line chroma comb filters in PAL only. YC input error signal control. Error signal control for YC input, luma comb. YCES 4 YCSEL LPF and HPF error signal, between (0H & 1H) or (1H & 2H) in NTSC or between (0H & 2H) in PAL,are sent to XLUT 1 0C Function 0 LPF error signal, between (0H & 1H) and (1H & 2H) in NTSC or between (0H & 2H) in PAL, are sent to XLUT Luma/chroma comb filter select. Selects luma or chroma comb filter. YCSEL Function 0 0C 3-0 COMB Chroma comb filter 1 Luma comb filter Comb filter architecture. COMB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 20 Function YC or composite comb filter architectures PAL or NTSC 3 line comb NTSC 3 line comb (0H & 1H) NTSC 3 line comb (1H & 2H) NTSC 2 line comb (0H & 1H) NTSC (2 line) field comb NTSC or PAL field comb NTSC (2 line) frame comb NTSC or PAL frame comb D1 comb filter architectures 3 line comb 3 line comb (0H & 1H) 3 line comb (1H & 2H) 3 line comb (0H & 2H) (2 line) field comb field or 2 line (0H & 1H) comb (2 line) frame comb frame comb PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Comb Filter Control (0D) 7 6 4 3 2 1 0 CESG CEST 5 YESG CESTBY XFEN FAST YWBY Reg Bit Name Description 0D 7-6 CEST Chroma error signal transform. NTSC 12.27MHz PAL 14.75MHz 11 CESG 4*Fsc & 13.5MHz 10 5 Clock Rate (MHz) PAL/NTSC 01 0D Video Standard 00 PAL 15MHz Chroma error signal gain. CESG Function 0 1 0D 4 YESG Normal chroma fail signal levels Double the chroma error signal levels Luma error signal gain. YESG Function 0 Normal luma fail signal levels 1 Double the luma error signal levels 0D 3 CESTBY Chroma error signal bypass. When HIGH, bypasses chroma error signal. 0D 2 XFEN XLUT filter enable. When HIGH, enables the LPF on the XLUT output. 0D 1 FAST Adaption speed select. When HIGH, the 3 line comb filter selects between comb filter architectures on a pixel by pixel basis. When LOW, the selection is filtered. 0D 0 YWBY Luma weighting bypass. When HIGH bypasses the luma fail weighting. 21 Preliminary Information CEST TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Comb Filter Control (0E) 7 6 XIP 5 4 3 XSF 2 1 YMUX 0 CMUX Reg Bit Name Description 0E 7-6 XIP XLUT input select. Selects the comb fail signals presented to the XLUT: 3 bits of phase error (X[7:5]), 3 bits of chroma magnitude error (X[4:2]), and 2 bits of luma magnitude error (X[1:0]). 11 XSF 4 bits of chroma (X[7:4]) and luma magnitude error (X[3:0]). 10 5-4 2 bits of phase error (X[7:6]), 3 bits of chroma (X[5:3]) and luma magnitude error (X[3:0]). 01 0E Input to XLUT 00 Preliminary Information XIP[1:0] 4 bits of phase error (X[7:4]) and chroma magnitude error (X[3:0]). XLUT special function. XSF Simple Simple Comb 10 Flat with notch Simple 11 YMUX Comb 01 3-2 Chroma 00 0E Luma Flat with notch Comb Y output select. Output selection of luma 4:1 mux YMUX Output 00 01 CMUX Flat 11 1-0 Flat - Comb 10 0E Comb Simple C output select. Output selection of chroma 4:1 mux CMUX Output 00 01 Flat - Comb 10 Flat 11 22 Comb Simple PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Comb Filter Control (0F) 7 6 Reserved 5 4 3 DCES CAT 2 0 YCCOMP IPCF 1 SYNC Reg Bit Name Description 0F 7 Reserved Reserved, set to zero. 0F 6-5 CAT Adaption threshold. Fixes threshold at which different comb filters are selected. 0F 4 DCES 5% of max error 15% of max error 25% of max error 50% of max error D1 CBCR error signal. When set LOW for D1 chroma comb filters: a) In 3 line comb filter architectures, the magnitude error between the component data for that pixel selects the 3 line comb or adapts to a 2 line comb. On a "CB pixel" the error signal selected on pixel (x+4) is sent to the XLUT with the magnitude difference between "CR pixels" on the same piar of lines, but from pixel (x+3). Likewise on a "CR pixel" the error signal selected on pixel (x+5) is sent to the XLUT with the magnitude difference between "CB pixels" on the same lines but from pixel (x+4). b) In 2 line comb filters the magnitude differences between the same pair of lines is always sent to the XLUT, On a "CB pixel" the error from the preceding "CR pixel" is used and on a "CR pixel" the preceding "CB pixel" would be used. When set HIGH for D1 chroma filters: This is used for 3 line comb filter architecture that are inhibited from adapting to 2 line comb filter architectures. The input to the XLUT is the magnitude error in CR between (0H & 1H) and (1H & 2H) on "CR pixels" and the magnitude error between (0H & 1H) and (1H & 2H) on "CB pixels". 0F 3-2 IPCF Comb filter input select. Selects primary inputs to the comb filter. IPCF Function 0 0 1 1 Flat video LPF output HPF output Reserved 0 1 0 1 0F 1 YCCOMP YC or Composite input select. Selects YC inputs when HIGH and composite inputs when LOW. 0F 0 SYNC Sync processor select. The syncs are obtained by a LPF when HIGH and by the comb filter when LOW. Sync Pulse Generator (10) 7 6 5 4 3 2 1 0 STS7 STS6 STS5 STS4 STS3 STS2 STS1 STS0 Reg Bit Name Description 10 7-0 STS7-0 Sync to sync 8 lsbs. Bottom 8 bits of the number of pixels between sync pulses. 23 Preliminary Information 0 1 0 1 0 0 1 1 TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Sync Pulse Generator (11) 7 6 5 4 3 2 1 0 STB Reg Bit Name Description 11 7-0 STB Sync to burst. Controls the number of pixels from sync to burst. This signal starts the burst sample and hold. In SC mode, subtract 25 from the desired delay to generate this value. Preliminary Information Sync Pulse Generator (12) 7 6 5 4 3 2 1 0 BTV Reg Bit Name Description 12 7-0 BTV Burst to video. Controls the number of pixels from STB to the start of active video. Sync Pulse Generator (13) 7 6 5 4 3 2 1 0 AV7 AV6 AV5 AV4 AV3 AV2 AV1 AV0 Reg Bit Name Description 13 7-0 AV7-0 Active video line 8 lsbs. Bottom 8 bits of the number of pixels during the active video line. Sync Pulse Generator (14) 7 6 5 4 3 2 1 0 AV9 Reserved AV8 Reserved STS10 STS10 STS9 STS8 Reg Bit Name Description 14 7-6 Reserved Reserved, set to zero. 14 5-4 AV9-8 Active video line 2 msbs. Two most significant bits of AV. 14 3 Reserved Reserved, set to zero. 14 2-0 STS10-8 STS10-8 Sync to sync 3 msbs. Three most significant bits of STS. 24 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Sync Pulse Generator (15) 7 6 5 4 Reserved 3 2 0 VDIV VINDO 1 VDOV Bit Name Description 15 7 Reserved Reserved, set to zero. 15 6-2 VINDO Number of lines in vertical window. The number of lines (0 to 31) after the last EQ pulse that the decoder passes through the Vertical INterval winDOw. 15 1 VDIV Action inside VINDO. The vertical data inside the `VINDO' is passed through a simple decoder when LOW, or is passed unprocessed on the luma channel with the chroma channel set to zero when HIGH. 15 0 VDOV Action outside VINDO. The vertical data after the `VINDO' and before the end of vertical blanking is blanked (YUV = 0) when LOW, or passed through the simple decoder when HIGH. Sync Pulse Generator (16) 7 6 Reserved 5 4 3 NFDLY 2 1 SPGIP Reg Bit Name Description 16 7-6 Reserved Reserved, set to zero. 16 5-4 NFDLY 0 MSIP new field detect delay. NTSC frame detect delay: NFDLY Function 00 SPGIP pixel count = 2 11 3-2 pixel count = 1 10 16 pixel count = 0 01 pixel count = 3 SPG input select. Selects the input to the Sync Pulse Generator: SPGIP Input 00 External HSYNC and VSYNC 01 Digitized sync (subcarrier mode) 10 TRS words embedded in the D1 data stream 11 TRS words embedded in the D2 data stream 16 1 MSIP Mixed sync separator input. Set HIGH for external VIDEOB reference or LOW for output of Low Pass Filter. 16 0 SMO State Machine Offset. Set HIGH for a 1H offset and LOW for a 0H offset. 25 Preliminary Information Reg TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Buffered register set 0 (17) Active when BUFFER pin set LOW. 7 6 5 4 3 2 1 0 SG07 SG06 SG05 SG04 SG03 SG02 SG01 SG00 Reg Bit Name Description 17 7-0 SG07-0 SG07-0 Msync gain, 8 lsbs. Bottom 8 bits of mixed sync scalar lsb = 1/256 Preliminary Information Buffered register set 0 (18) Active when BUFFER pin set LOW. 7 6 5 4 3 2 1 0 YG07 YG06 YG05 YG04 YG03 YG02 YG01 YG00 Reg Bit Name Description 18 7-0 YG07-0 YG07-0 Y gain, 8 lsbs. Bottom 8 bits of the luma gain lsb = 1/256 Buffered register set 0 (19) Active when BUFFER pin set LOW. 7 6 5 4 3 2 1 0 UG07 UG06 UG05 UG04 UG03 UG02 UG01 UG00 Reg Bit Name Description 19 7-0 UG07-0 UG07-0 U gain, 8 lsbs. Bottom 8 bits of the U gain lsb = 1/256 Buffered register set 0 (1A) Active when BUFFER pin set LOW. 7 6 5 4 3 2 1 0 VG07 VG06 VG05 VG04 VG03 VG02 VG01 VG00 Reg Bit Name Description 1A 7-0 VG07-0 VG07-0 V gain, 8 lsbs. Bottom 8 bits of the V gain lsb = 1/256 Buffered register set 0 (1B) Active when BUFFER pin set LOW. 7 6 5 4 3 2 1 0 YG09 YG08 UG010 UG010 UG09 UG08 Reserved VG09 VG08 Reg Bit Name Description 1B 7-6 YG09-8 YG09-8 Y gain, 2 msb. Top 2 bits of the Y gain. msb = 2 1B 5-3 UG010-8 UG010-8 U gain, 3 msbs. Top 3 bits of the U gain. msb = 4 1B 2 Reserved Reserved, set to zero. 1B 1-0 VG09-8 VG09-8 V gain, 2 msbs. Top 2 bits of the V gain. msb = 2 26 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Buffered register set 0 (1C) Active when BUFFER pin set LOW. 7 6 5 4 3 2 1 0 YOFF07 YOFF07 YOFF06 YOFF06 YOFF05 YOFF05 YOFF04 YOFF04 YOFF03 YOFF03 YOFF02 YOFF02 YOFF01 YOFF01 YOFF00 YOFF00 Reg Bit Name Description 1C 7-0 YOFF07-0 YOFF07-0 Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset Buffered register set 0 (1D) Active when BUFFER pin set LOW. 7 6 5 4 3 1 0 SG01 SG00 Reg Bit Name Description 1D 7-3 Reserved Reserved, set to zero. 1D 2 YOFF08 YOFF08 Y offset, msb. msb of YOFF 1D 1-0 SG01-0 SG01-0 Preliminary Information 2 YOFF08 YOFF08 Reserved Msync gain, 2 msbs. Top 2 bits of mixed sync scalar. msb = 2 Buffered register set 0 (1E) Active when BUFFER pin set LOW. 7 6 5 4 3 2 1 0 SYSPH07 SYSPH07 SYSPH06 SYSPH06 SYSPH05 SYSPH05 SYSPH04 SYSPH04 SYSPH03 SYSPH03 SYSPH02 SYSPH02 SYSPH01 SYSPH01 VAXIS0 Reg Bit Name Description 1E 7-1 SYSPH07-1 SYSPH07-1 7 lsbs of phase. Bottom 7 bits of the system phase offset 1E 0 VAXIS0 V axis Flip. The PAL V axis sign bit is flipped when HIGH. Buffered register set 0 (1F) Active when BUFFER pin set LOW. 7 6 5 4 3 2 1 0 SYSPH015 SYSPH015 SYSPH014 SYSPH014 SYSPH013 SYSPH013 SYSPH012 SYSPH012 SYSPH011 SYSPH011 SYSPH010 SYSPH010 SYSPH09 SYSPH09 SYSPH08 SYSPH08 Reg Bit Name Description 1F 7-0 SYSPH015-8 SYSPH015-8 8 msbs of phase offset. Top 8 bits of 15 bit phase offset. Normalized Subcarrier Frequency (20) 7 6 5 4 FSC3 FSC2 FSC1 FSC0 3 2 1 0 Reserved Reg Bit Name Description 20 7-4 FSC3-0 Bottom 4 bits of fsc. Bottom 4 bits of the 28 bit subcarrier SEED 20 3-0 Reserved Reserved, set to zero. 27 TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Normalized Subcarrier Frequency (21) 7 6 5 4 3 2 1 0 FSC11 FSC11 FSC10 FSC10 FSC9 FSC8 FSC7 FSC6 FSC5 FSC4 Reg Bit Name Description 21 7-0 FSC11-4 FSC11-4 Lower 8 bits of fsc. Lower 8 bits of the 28 bit subcarrier SEED Normalized Subcarrier Frequency (22) Preliminary Information 7 6 5 4 3 2 1 0 FSC19 FSC19 FSC18 FSC18 FSC17 FSC17 FSC16 FSC16 FSC15 FSC15 FSC14 FSC14 FSC13 FSC13 FSC12 FSC12 Reg Bit Name Description 22 7-0 FSC19-12 FSC19-12 Middle 8 bits of fsc. Middle 8 bits of the 28 bit subcarrier SEED Normalized Subcarrier Frequency (23) 7 6 5 4 3 2 1 0 FSC27 FSC27 FSC26 FSC26 FSC25 FSC25 FSC24 FSC24 FSC23 FSC23 FSC22 FSC22 FSC21 FSC21 FSC20 FSC20 Reg Bit Name Description 23 7-0 FSC27-20 FSC27-20 Top 8 bits of fsc. Top 8 bits of the 28 bit subcarrier SEED Normalized Subcarrier Frequency (24-25) 7 6 5 4 3 Reserved Reg Bit Name Description 24-25 7-0 Reserved Reserved, set to zero. 28 2 1 0 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Output Format Control (26) 7 6 4 3 LDVIO Reserved 5 OPCKS 2 DPCEN 1 0 DPC Bit Name Description 26 7-6 Reserved Reserved, set to zero. 26 5 LDVIO LDV clock select. LDV is an output when LOW and an input when HIGH 26 4 OPCKS Output clock select. The output data are clocked by the CLOCK pin when LOW and by the LDV pin when HIGH. 26 3 DPCEN DPC enable. When HIGH on the TMC22153 TMC22153, the Decoder Product Code is enabled: a value written into DPC determines the decoder product emulated by the TMC22153 TMC22153. In all other versions of the decoder, DPC is read-only, and returns the code of the particular encoder version installed. 26 2-0 DPC Decoder product code DPC Function 000 Reserved 001 TMC22051 TMC22051 010 TMC22052 TMC22052 011 TMC22053 TMC22053 100 Reserved 101 TMC22151 TMC22151 110 TMC22152 TMC22152 111 TMC22153 TMC22153 Read/Write in the TMC22153 TMC22153 only. Read-only in all other devices. Buffered register set 1 (27) Active when BUFFER pin set HIGH. 7 6 5 4 3 2 1 0 SG17 SG16 SG15 SG14 SG13 SG12 SG11 SG10 Reg Bit Name Description 27 7-0 SG17-0 SG17-0 Msync gain, 8 lsbs. Bottom 8 bits of mixed sync scalar lsb = 1/256 Buffered register set 1 (28) Active when BUFFER pin set HIGH. 7 6 5 4 3 2 1 0 YG17 YG16 YG15 YG14 YG13 YG12 YG11 YG10 Reg Bit Name Description 28 7-0 YG17-0 YG17-0 Y gain, 8 lsbs. Bottom 8 bits of the luma gain lsb = 1/256 29 Preliminary Information Reg TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Buffered register set 1 (29) Active when BUFFER pin set HIGH. 7 6 5 4 3 2 1 0 UG17 UG16 UG15 UG14 UG13 UG12 UG11 UG10 Reg Bit Name Description 29 7-0 UG17-0 UG17-0 U gain, 8 lsbs. Bottom 8 bits of the U gain lsb = 1/256 Preliminary Information Buffered register set 1 (2A) Active when BUFFER pin set HIGH. 7 6 5 4 3 2 1 0 VG17 VG16 VG15 VG14 VG13 VG12 VG11 VG10 Reg Bit Name Description 2A 7-0 VG17-0 VG17-0 V gain, 8 lsbs. Bottom 8 bits of the V gain lsb = 1/256 Buffered register set 1 (2B) Active when BUFFER pin set HIGH. 7 6 5 4 3 2 1 0 YG19 YG18 UG110 UG110 UG19 UG18 Reserved VG19 VG18 Reg Bit Name Description 2B 7-6 YG19-8 YG19-8 Y gain, 2 msbs. Top 2 bits of the Y gain msb = 2 2B 5-3 UG110-8 UG110-8 U gain, 3 msbs. Top 3 bits of the U gain. msb = 4 2B 2 Reserved reserved, set to zero 2B 1-0 VG19-8 VG19-8 V gain, 2 msbs. Top 2 bits of the V gain msb = 2 Buffered register set 1 (2C) Active when BUFFER pin set HIGH. 7 6 5 4 3 2 1 0 YOFF17 YOFF17 YOFF16 YOFF16 YOFF15 YOFF15 YOFF14 YOFF14 YOFF13 YOFF13 YOFF12 YOFF12 YOFF11 YOFF11 YOFF10 YOFF10 Reg Bit Name Description 2C 7-0 YOFF17-0 YOFF17-0 Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset 30 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Buffered register set 1 (2D) Active when BUFFER pin set HIGH. 7 6 5 4 3 1 0 YOFF18 YOFF18 Reserved 2 SG17 SG10 Reg Bit Name Description 2D 7-3 Reserved Reserved, set to zero. 2D 2 YOFF18 YOFF18 Y offset, msb. msb of YOFF 2D 1-0 SG17,0 Msync gain, 2 msbs. Top 2 bits of mixed sync scalar msb = 2 Preliminary Information Buffered register set 1 (2E) Active when BUFFER pin set HIGH. 7 6 5 4 3 2 1 0 SYSPH17 SYSPH17 SYSPH16 SYSPH16 SYSPH15 SYSPH15 SYSPH14 SYSPH14 SYSPH13 SYSPH13 SYSPH12 SYSPH12 SYSPH11 SYSPH11 SYSPH10 SYSPH10 Reg Bit Name Description 2E 7-1 SYSPH17-0 SYSPH17-0 8 lsbs of phase. Bottom 8 bits of the system phase offset 2E 0 VAXIS0 V axis Flip. The PAL V axis sign bit is flipped when HIGH. Buffered register set 1 (2F) Active when BUFFER pin set HIGH. 7 6 5 4 3 2 1 0 SYSPH115 SYSPH115 SYSPH114 SYSPH114 SYSPH113 SYSPH113 SYSPH112 SYSPH112 SYSPH111 SYSPH111 SYSPH110 SYSPH110 SYSPH19 SYSPH19 SYSPH18 SYSPH18 Reg Bit Name Description 2F 7-0 SYSPH015-0 SYSPH015-0 8 msbs of phase offset. Top 8 bits of 15 bit phase offset. 31 TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Video Measurement (30) 7 6 5 4 3 2 1 0 Reserved LGF LGEN LGEXT RESERVED PGG PGEN PGEXT Bit Name Description 30 7 Reserved Reserved, set to zero. 30 6 LGF Line grab flag. Set HIGH when the decoder has grabbed a line, and must be reset LOW before another line can be grabbed. 30 Preliminary Information Reg 5 LGEN Line grab enable. When HIGH, the line grabber is used to freeze the contents of the line store, at the programmed line and field count. The phase and frequency of the frozen line are also stored from the DRS, and are continually used to reset the DDS, once per line, until LGF is set LOW. When LGEN is LOW, the line freeze is disabled, the internal loops operate normally, and the line grab signal is used only to gate the pixel grab. 30 4 LGEXT Ext line grab enable. The SET pin is used to produce the line grabber pulse when HIGH and the internal line decode is used when LGEXT is LOW. 30 3 Reserved Reserved, set to zero. 30 2 PGG Pixel grab gate. When HIGH the pixel grab is gated by the field and line grab signals to enable one pixel per four fields in NTSC and 8 field in PAL to be grabbed. This function is disabled if PGEN is set LOW. 30 1 PGEN Pixel grab enable. When HIGH the 10 bit G/Y, B/U, and R/V data, and the mixed sync and luma data after the comb filter, and the demodulated (B-Y) and (R-Y) color difference signals are grabbed once every line at the programmed pixel grab number. When LOW the contents of the pixel grab registers are held and the pixel grab pulse is ignored. 30 0 PGEXT Ext pixel grab enable. The SET pin is used to produce the pixel grab pulse when HIGH and the internal pixel decode is used when PGEXT is LOW. Video Measurement (31) 7 6 5 4 3 2 1 0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Reg Bit Name Description 31 7-0 PG7-0 Pixel grab, 8 lsbs. Bottom 8 bits of the pixel grab. Video Measurement (32) 7 6 5 4 3 2 1 0 LG7 LG6 LG5 LG4 LG3 LG2 LG1 LG0 Reg Bit Name Description 32 7-0 LG7-0 Line grab, 8 lsbs. Bottom 8 bits of the line grab. 32 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Video Measurement (33) 7 6 Reserved 5 4 2 1 0 LG8 FG 3 PG10 PG9 PG8 Reg Bit Name Description 33 7 Reserved Reserved. 33 6-4 FG Field grab number. Field grab number 33 3 LG8 Msb of line grab. msb of line grab 33 2-0 PG10-8 PG10-8 Pixel grab, 3 msbs. 3 msbs of pixel grab Preliminary Information Registers 34-3C 34-3C are Read-Only Register (34) 7 6 5 4 3 2 1 0 GY9 GY8 GY7 GY6 GY5 GY4 GY3 GY2 Reg Bit Name Description 34 7-0 GY9-2 G/Y grab, 8 msbs. Top 8 bits of the "grabbed" G/Y data Register (35) 7 6 5 4 3 2 1 0 BU9 BU8 BU7 BU6 BU5 BU4 BU3 BU2 Reg Bit Name Description 35 7-0 BU9-2 B/U grab, 8 msbs. Top 8 bits of the "grabbed" B/U data Register (36) 7 6 5 4 3 2 1 0 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 Reg Bit Name Description 36 7-0 RV9-2 R/V grab, 8 msbs. Top 8 bits of the "grabbed" R/V data Register (37) 7 6 Reserved 5 4 3 2 1 0 GY1 GY0 BU1 BU0 RV1 RV0 Reg Bit Name Description 37 7-6 Reserved Reserved. 37 5-4 GY1-0 G/Y grab, 2 lsbs. Bottom two bits of G/Y data 37 3-2 BU1-0 B/U grab, 2 lsbs. Bottom two bits of B/U data 37 1-0 RV1-0 R/V grab, 2 lsbs. Bottom two bits of R/V data 33 TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Register (38) 7 6 5 4 3 2 1 0 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Reg Bit Name Description 38 7-0 Y9-2 Luma grab, 8 msbs. Top 8 bits of the "grabbed" luma data after YPROC Register (39) Preliminary Information 7 6 5 4 3 2 1 0 M9 M8 M7 M6 M5 M4 M3 M2 Reg Bit Name Description 39 7-0 M9-2 Msync grab, 8 msbs. Top 8 bits of the "grabbed" mixed sync data after YPROC Register (3A) 7 6 5 4 3 2 1 0 U9 U8 U7 U6 U5 U4 U3 U2 Reg Bit Name Description 3A 7-0 U9-2 U grab, 8 msbs. Top 8 bits of the "grabbed" U data Register (3B) 7 6 5 4 3 2 1 0 V9 V8 V7 V6 V5 V4 V3 V2 Reg Bit Name Description 3B 7-0 V9-2 V grab, 8 msbs. Top 8 bits of the "grabbed" V data Register (3C) 7 6 5 4 3 2 1 0 Y1 Y0 M1 M0 U1 U0 V1 V0 Reg Bit Name Description 3C 7-6 Y1-0 Luma grab, 2 lsbs. Bottom 2 bits of luma data 3C 5-4 M1-0 Msync grab, 2 lsbs. Bottom 2 bits of mixed sync data 3C 3-2 U1-0 U grab, 2 lsbs. Bottom 2 bits of U data 3C 1-0 V1-0 V grab, 2 lsbs. Bottom 2 bits of V data 34 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Test Control (3D-3F) 7 6 5 4 3 2 1 0 1 0 TEST Reg Bit Name Description 3D-3F 7-0 TEST Must be set to zero. Auto increment stops at 3F Status - Read Only (40) 7 6 5 4 3 2 Reg Bit Name Description 40 7-0 DDSPH DDS phase, 8 msbs. The top 8 bits of the sine data generated in the internal DDS. Status - Read Only (41) 7 6 5 4 3 2 1 0 LINEST BGST VACT2 PALODD VFLY FGRAB LGRAB PGRAB 1 0 Reg Bit Name Description 41 7 LINEST Pixel count reset. Pixel count reset 41 6 BGST Start of burst gate. Start of burst gate 41 5 VACT2 Half line flag. Half line flag 41 4 PALODD PAL Ident. PAL Ident (low on NTSC lines) 41 3 VFLY Vertical count reset. Vertical count reset 41 2 FGRAB Field grab. Field grab 41 1 LGRAB Line grab. Line grab 41 0 PGRAB Pixel grab. Pixel grab Status - Read Only (42) 7 6 5 4 FLD VBLK 3 HBLK 2 LID Reg Bit Name Description 42 7 FLD Field flag (F in D1 output). Field flag (F in D1 output) 42 6 VBLK Vertical blanking (V in D1 output). Vertical blanking (V in D1 output) 42 5 HBLK Horizontal blanking (H in D1 output). Horizontal blanking (H in D1 output) 42 4-0 LID Line identification. Line identification 35 Preliminary Information DDSPH TMC22x5y PRODUCT SPECIFICATION Control Register Definitions (continued) Status - Read Only (43) 7 6 5 4 3 2 YGO YGU UBO UBU VRO VRU Reg Bit Name 7 YGO 6 YGU Y/G underflow. Y/G underflow 43 5 UBO CB/B overflow. CB/B overflow 43 4 UBU CB/B underflow. CB/B underflow 43 Preliminary Information Reserved Y/G overflow. Y/G overflow 43 0 Description 43 1 3 VRO CR/R overflow. CR/R overflow 43 2 VRU CR/R underflow. CR/R underflow 43 1-0 Reserved Reserved. Status - Read Only (44) 7 6 5 4 3 MONO 2 1 0 FPERR Reg Bit Name Description 44 7 MONO Color kill flag. High when burst detected and LOW when monochrome signal is detected. 44 6-0 FPERR Frequency/Phase error. Top 7 bits of the modulo two pi frequency or phase error. Reported once per line. Status - Read Only (45) 7 6 5 4 3 2 1 0 1 0 DRS Reg Bit Name Description 45 7-0 DRS DRS signal. The 8-bit Decoder Reference Signal. Status - Read Only (46) 7 6 5 4 3 2 PARTID Reg Bit Name Description 46 7-0 PARTID Part family ID. Reads back the 8-bit part ID number. Read-only. Returns CDh. 36 PRODUCT SPECIFICATION TMC22x5y Control Register Definitions (continued) Status - Read Only (47) 7 6 5 4 3 2 1 0 REVID Reg Bit Name Description 47 7-0 REVID Revision number. The 8-bit chip revision number. Status - Read Only (48-4A) 7 6 5 4 3 2 1 0 3 2 1 0 1 0 Reg Bit Name Description 48-4A 7-0 Reserved Preliminary Information Reserved Reserved. Status - Read Only (4B) 7 6 PKILL 5 4 CFSTAT XOP Reg Bit Name Description 4B 7 PKILL Phase kill from comb fail. Phase kill from comb fail. 4B 6-5 CFSTAT Comb filter status. Comb filter status. CFSTAT STATUS 00 01 XOP 3-tap [upper] comb 11 4-0 3 tap [lower] comb 10 4B 3 tap comb 2 tap comb XLUT output. XLUT output. Status - Read Only (4C-FF) 7 6 5 4 3 2 Reserved Reg Bit 4C-FF 7-0 Name Description Reserved Reserved. 37 TMC22x5y PRODUCT SPECIFICATION Decoder Introduction The complete separation of composite video signals into pure luminance (luma) and chrominance (chroma) signals is practically impossible, especially when the input source contains intraframe motion. Therefore, the luminance (luma) signal will generally contain some high frequency chrominance, termed cross luma, and the chroma signal will contains some of the high frequency luma signal, centered around the subcarrier frequency, termed cross color. The degree of cross luma and cross color is directly proportional to the filter used for the YC separation, the picture content, and the complexity of any post processing of the decoded signals. Preliminary Information All composite video decoders perform fundamentally the same operation. The first stage is to separate the luminance and chrominance. The second stage is to lock the internally generated sine and cosine waveforms to the burst on the decoded chrominance signal, demodulate, and then filter the chrominance signal to produce the color difference signals. The last stage either scales the luminance and color difference signals, or converts them into red, green, and blue component video signals. These three stages are shown in Figure 3. ­ G Luminance Y Y Green ­ Red ­ Blue ­ Matrix YC Filter R ­ Composite ­ C ­ U Chrominance V B Demodulation Burst Locked Loop ­ sin(wt) cos(wt+f) 65-22x5y-44 Figure 3. Fundamental Decoder Block Diagram The Luma Notch and Chroma Bandpass Technique for YC Separation YC Separation The relationship between the chrominance and luminance bandwidths is shown for both PAL and NTSC in Figure 4, wherein the shaded area denotes the part of the composite video frequency spectrum shared by both the chrominance and high frequency luminance signals. The simplest method of separating these chrominance and luminance signals, is to assume the chroma bandwidth is limited to a few hundred kilohertz around the subcarrier frequency. In this case a notch filter designed to remove just these frequencies from the composite video frequency spectrum provides the luma signal, while a bandpass filter PAL Amplitude (dB) NTSC Chrominance Subcarrier Sound Carrier Center Frequency 0 Amplitude (dB) -3 Chrominance Subcarrier Sound Carrier Center Frequency 0 -3 Luminance Luminance Chrominance (& High Frequency Luminance) Chrominance (& High Frequency Luminance) -20 -20 1 2 3 4 5 6 Frequency (MHz) 1 2 3 4 4.5 Frequency (MHz) Figure 4. Comparison of the Frequency Spectrum of NTSC and PAL Composite Video Signals 38 PRODUCT SPECIFICATION TMC22x5y Notch Filter Amplitude (dB) Bandpass Filter Amplitude (dB) Chrominance Subcarrier 0 0 -3 Chrominance Subcarrier -3 Luminance Chrominance (& High Frequency Luminance) Chrominance (& High Frequency Luminance) -20 -20 FSC Frequency FSC Frequency centered at the subcarrier frequency produces the chroma signal. This simple technique works well in pictures containing large flat areas of color, however this is rarely the case. If, as is generally true, the picture contains high frequency luma and chroma transitions, for example herring bone suit jackets, branches of trees, text, etc., cross color and cross luma artifacts are evident. The presence of cross color or cross luma is generally acceptable when viewing the decoded picture on a monitor from several feet, as would be the case in most homes on commercial television sets. However, these artifacts become increasingly difficult to process, or ignore, when the image is to be compressed or manipulated. In these cases more sophisticated methods of separating the luma and chroma signals, such as frame, field, or line based comb filter decoders, are required. Another important disadvantage of the "luma notch filter and bandpass chroma" technique is that once a notch filter has been used on the luminance channel this portion of the luminance frequency spectrum is lost. This effect becomes increasingly objectionable if the decoder component outputs are subsequently re-encoded into a composite video signal. Comb Filter Architectures for YC Separation A comb filter uses the relationship between the number of subcarrier cycles per line period, to cancel the chrominance signal over multiple line periods. This is shown for an NTSC two line comb filter in Figure 6. In NTSC there a 227.5 subcarrier cycles per line period, therefore the subcarrier can be canceled by simply adding two consecutive field scan lines. In PAL(B/I/ etc.) there are 283.7516 subcarrier cycles per line period, ignoring the 0.0016 cycle advance caused by the 25Hz offset, the PAL subcarrier can be canceled by adding the first and third line of three consecutive field scan lines. Due to the 270 degree advance, it is not possible to use information from consecutive field lines without adding a PAL modifier. A PAL modifier produces a 90 degree phase shift in the chrominance signal by multiplying the chrominance signal by a signal at two times the subcarrier frequency that is phased locked to the subcarrier burst reference in the composite video waveform. In addition the PAL modifier inverts the V component of the chrominance signal. This document refers to line based comb decoders when discussing decoders that use inputs from sequential scan lines, i.e. lines from the same field, field based comb decoders when describing decoders that use inputs from sequential fields, and finally frame based comb decoders when examining decoders that use inputs from sequential frames. + Delay = 1/T 1/2 Amplitude 1.0 1/2T 1T 3/2T 2T 5/2T 3T 7/2T 4T 9/2T 5T 11/2T 11/2T 6T Frequency Figure 6. Composite Line-Based Comb Decoders The phase relationship of the quadrature modulated chrominance signal can also be represented as in Figure 7. The three line comb based decoder is clearly biased towards 1H which illustrates the inherent one line delay through a 3 line comb, while a two line comb based decoder is biased towards 0H. In the following discussions a flat color represents video of constant luma and chroma magnitude and phase. In NTSC, adding two adjacent lines of flat color will cancel the chroma and leave the luma whereas subtracting two lines of flat color will cancel the luma and leave the chroma. In a 3 line comb filter the flat color on 0H and 2H is added to provide the flat color average before adding or subtracting from 1H. In PAL, adding the flat color from 0H and 2H will cancel the chroma and leave the luma while subtracting the flat color from 0H and 2H will cancel the luma and leave the chroma. However, chroma generated in this manner has no simple 39 Preliminary Information Figure 5. Examples of Notch and Bandpass Filters TMC22x5y PRODUCT SPECIFICATION phase relationship to the chroma on 1H. Therefore normally 0H and 2H are added together to produce the average luma across 3 lines and this is then subtracted from 1H to produce the combed chroma. FIELD LINE no PAL NTSC I U 0 N Q V 1 NTSC Frame and Field Based Decoders Composite Frame-Based Comb Filters In NTSC the chrominance vectors advance by 180 degrees every line, therefore after 525 lines the 2 adjacent frame lines 0H and FR0H and the two consecutive field lines FR0H and FR1H are 180 degrees apart. The flat color on FR0H and FR1H can be added or subtracted to provide the luminance or chrominance to subtract from 0H. M V Q 0 N+1 U LINE no 2H Preliminary Information M+1 1H N+2 Q (1H) I V 0 N+4 I I (FR0H) (0H) I V Q I (F0H) I 285 Q Q I Q 65-22x5y-48 I Q I U Q Q 0H 22 0 (F1H) Q N+3 M+3 I 23 Q Q I Figure 7. Chrominance Vector Rotation in PAL and NTSC YC Line-Based Comb Filters The luminance and chrominance signals, are by definition, already separated for YC inputs. However, if the original source was composite, there is a distinct possibility that there is some residual luminance (cross color) in the chrominance signal and some residual chrominance (cross luma) in the luminance signal. It is therefore legitimate to treat these signals as if they were simply the output from bandsplit filters and process the luma and chroma signals accordingly. D1 Line-Based Comb Filters A D1 data stream consists of multiplexed Y, Cb and CR component data. If the original source was composite there maybe luminance (cross color) in CBCR and chrominance (cross luma) in Y. In the first case any luminance that was passed through a demodulator along with the chroma to produce the baseband CBCR color difference signals would have the same characteristics as chroma. That is to say, the cross color would advance by 180° every line in NTSC and every 2 lines in PAL. It is therefore possible to remove this cross color in a comb filter. In the latter case any chrominance that is still in the Y data can obviously be removed in a comb filter as well. The original source for the D1 signal could also have been computer graphics. In this case, the comb filter can be used to remove the picture flicker and convert the output to RGB. 40 I Q Q 284 M+2 V 1 Q I U 0 FIELD 4 (FR1H) 21 U 1 FIELD 3 I 283 1 FIELD 2 FIELD 1 286 Q Q I 24 I Q I Q I 65-22x5y-49 Figure 8. Chrominance Vector Rotation Over 4 Fields in NTSC Composite Field-Based Comb Filters In NTSC field based comb decoders, there is an external delay of 263 lines, therefore the 2 adjacent picture lines 0H and F0H and the two consecutive field lines F0H and F1H are 180 degrees apart. The flat color on F0H and F1H can be added or subtracted to provide the luminance or chrominance to subtract from 0H. PAL Frame- and Field-Based Decoders Composite PAL Frame-Based Comb Filters In PAL the chrominance vectors advance by 270 degrees every line. After 625 lines the two adjacent frame lines 0H and FR0h are 90 degrees apart. It is therefore necessary to delay the FR0H data by an addition line so that 0H and FR0H are 180 degrees apart. The flat color on 0H and FR0H can now be added to provide the luminance or subtracted to produce chrominance. PRODUCT SPECIFICATION LINE no TMC22x5y FIELD 2 FIELD 1 FIELD 3 V U 23 FIELD 4 U V U (F0H) U 336 24 (0H) (FR0h) V U V U U 337 25 V V V U V U V U V (FR0H) V V U U 26 U Preliminary Information U 338 V V 65-22x5y-50 Figure 9. Chrominance Vector Rotation Over 4 Fields in PAL In fields 5, 6, 7, and 8 the U and V vectors are 180 degrees advanced from fields 1, 2, 3, and 4. Composite, PAL Field-Based Comb Filters In PAL field based comb decoders, there is an external delay of 312 lines, therefore the 2 adjacent picture lines 0H and F0H are 180 degrees apart. In fields 5, 6, 7, and 8 the U and V vectors are 180 degrees advanced from fields 1, 2, 3, and 4. 41 TMC22x5y PRODUCT SPECIFICATION The TMC22x5y Comb Filter Architecture Preliminary Information The TMC22x5y, when implementing a line based comb filter, has a core architecture as shown in Figure 10. The concept of the complementary bandsplit filter is also observed in the complementary comb filter architecture. It is therefore possible to adapt between the complementary comb filter and bandsplit filter without throwing away any of the original composite video frequency spectrum. The first step in the complementary comb filter is to separate the high frequency luminance from the chrominance signal. This combed high frequency luma signal is shown as YCOMB in Figure 10. The second step is to produce an array of comb filter error signals that indicate the degree of confidence that the YCOMB signal is just the high frequency luma and not a combination of high frequency luma and chroma smeared over the number of lines used in the comb filter. The signal representing this degree of confidence is termed "K" in Figure 10. The last step is to provide a complementary cross fade between the YCOMB signal and the output of the complementary bandsplit filter, shown as SIMPLE in Figure 10. The FLAT signal is simply a delayed version of the input to the comb filter, therefore the sum of Output1 and Output2 will always be equal to the FLAT video input. The TMC22x53 comb filter architecture has three taps. These taps are three consecutive field lines in a line based comb, three consecutive picture lines in a field based comb, or lines that are one frame and one field line apart in the frame based comb. In addition to these different inputs to the comb filter, NTSC and PAL video signals comb over different taps in different architectures, as described in the comb filter introduction. The total internal pipeline latency is 1H + 38 pixels for 3 line comb filters, for all other comb filter and simple decoder architectures the pipeline latency is 38 pixels. XLUT ­ Output1 SIMPLE Input 1H Bandsplit Filters COMB Filter YCOMB X + Simple +/- {k * Ycomb} 1H XLUT K Figure 10. TMC22x5y Line Based Comb Filter Architecture 42 Output2 PRODUCT SPECIFICATION TMC22x5y TMC22x5y Functional Description Input Processor Input The input processor selects between the two external video sources on VIDEO A and VIDEO B. If the TRS stripper or GRS stacker is active, then the user must select the input with either the GRS (in genlock mode) or with the embedded TRS words as output VA. If the input data are separate luma and chroma or Y and CBCR data the input processor must be programmed to put the chrominance or CBCR onto output VB and the luminance or Y onto VA. Bandsplit Filter (BSF) In its simple mode of operation, the TMC22x5y uses a complementary bandsplit filter, instead of a notch filter for the luma and a bandpass for the chroma. The notch and bandpass filter technique, removes frequency bands from the composite video spectrum which can never be retrieved. The complementary bandsplit filter technique, shown in Figure 12, allows the decoded component video signals to be re-encoded into a composite video signal with the minimum of losses to the composite video spectrum. msb x IPMUX IP8B TDEN Figure 12. Complementary Bandsplit Filter The complementary bandsplit filter separates the base band composite video into two bands by passing it through a low pass filter and subtracting the low pass (luma) data from the composite video to produce the high pass (chroma) data. As the base bandwidths and subcarrier frequencies of the different NTSC and PAL video formats are so different, and the decoder has to be capable of working over a large frequency range, it is necessary to provide two low pass filters. These filters are selectable by the BSFSEL register bit and are independent of the video standard. A comparison of the different data rates to normalized subcarrier frequencies is provided in Table 2. The complementary bandsplit low pass frequency response is shown in Figure 13 and Figure 14. TBLK lsb ICPMSB ABMUX CKSEL TRS Stripper (D1/D2/D3) and GRS Stacker (TMC22071 TMC22071) DA Primary Data to Comb Filter 2:2 MUX 2:2 MUX VideoB HPF Output 65-22x5y-53 Input Processor Control Register VA VideoA ­ VB MSB Invert DB Secondary Data to Comb Filter 65-22x5y-52 Figure 11. Input Processor 43 Preliminary Information To ensure that the chrominance data or the CBCR data are in two's complement arithmetic format, the register bit MSBI inverts the msb of the DB input. For composite inputs, the IPCMSB register bit should be set LOW, as the ABMUX register bit is used to select the input(s) to the comb filter. LPF Output LPF TMC22x5y PRODUCT SPECIFICATION 1 0 0 0.40 0.30 0.20 0.00 -70 0.10 -60 Preliminary Information Normalized Frequency Bandsplit Filter 1 -4 65-22x5y-55 65-22x5y-54 -50 -3 -5 -6 0.15 Bandsplit Filter 1 0.10 -40 Bandsplit Filter 2 -2 0.05 -30 -1 0.00 Bandsplit Filter 2 Attenuation (dB) -20 0.50 Attenuation (dB) -10 Normalized Frequency Figure 13. Bandsplit Filter, Full Frequency Response Figure 14. Bandsplit Filter, Passband Response Table 2. Normalized Subcarrier Frequency as a Function of Pixel Data Rates Pixel Rate (MHz) FSC (MHz) Normalized FSC 12.27 3.57954545 0.2917 NTSC square pixel rate 13.50 3.57954545 0.2652 NTSC D1 pixel rate 13.50 4.43361875 0.3284 PAL-I D1 pixel rate 14.32 3.57954545 0.2500 NTSC four times subcarrier (D2/D3) 14.75 4.43361875 0.3006 PAL-I square pixel rate 15.00 4.43361875 0.2956 PAL-I square pixel rate 17.73 4.43361875 0.2500 PAL-I four times subcarrier (D2/D3) 13.5 3.57561149 0.2649 PAL-M D1 pixel rate 13.5 3.58205625 0.2653 PAL-N D1 pixel rate 14.30 3.57561149 0.2500 PAL-M four times subcarrier (D2/D3) Comb Filter Input The inputs to the comb filter are selected from either the high frequency outputs of the bandsplit filters, if using a chroma comb filter, or the full composite waveforms when implementing a luma comb. The two sets of high and low frequency signals from the bandsplit filters are used for both the 44 Comments luma and chroma SIMPLE signals, and in the generation of the comb fail signals. These signals are denoted xHL, xHH, and xHF where L denotes the low frequency portion of the signal, H the high frequency portion of the signal and F the full frequency spectrum of the input signal from line x; and are shown in Figure 15. PRODUCT SPECIFICATION TMC22x5y 0HF Primary Input 0HL LPF BSFSEL ­ 2:1 MUX 1HH 1HF LSTORE1 [9:0] 1HL LPF Preliminary Information 2:1 MUX Secondary Input LS1IN BSFSEL LS1BY ­ LSTORE2 2HH 1HH 2HH + 1HH (lsbs) 1HL (lsbs) 2:1 MUX 2:1 MUX LSTORE2 2HX LSTORE2 2HL 1HL 1HH 2HF 2HL Split DELAY VIDEOB 65-22x5y-56 Figure 15. Block Diagram of Comb Filter Input The primary and secondary inputs are selected within the input processor. The primary input is normally the undelayed composite video signal in line, field, and frame based comb filters or either the luma or chroma channel when processing YC or D1 signals. The secondary provides the field or frame delayed composite input for field and frame based comb filters and the chroma or luma channel when processing YC or D1 signals. When implementing a line based comb filter the outputs of 1H bandsplit filter, ie 1HH, 1HL, are delayed through the second line store, LSTORE2. The number of bits delayed is dependent upon the type of comb filter being implemented. For chroma comb filters all the bits of the 1HH signal are delayed, as this information supplies the outer tap of the chroma comb filter, while only the upper bits of 1HL are delayed as this data is used only in the generation of the luma error signals. In the case of luma combs an equal number of bits of the 1HH and 1HL signals are delayed and summed together to produce the 2HF signal for the outer tap of the luma comb filter. The configuration of LSTORE2 is determined by the SPLIT register bit. It is important to note that when implementing a field or frame based comb filter the secondary input must be selected by setting the LSIN register bit HIGH, and the first line store, LSTORE1, must be bypassed by setting the LS1BY register bit HIGH. For YC and D1 processing the secondary input bypasses the comb filter completely and provides the VIDEOB signal input the 3:1 multiplexer used to select the FLAT signal, see Figure 16. 45 TMC22x5y PRODUCT SPECIFICATION Adaptive Comb Filter Preliminary Information The IPCF[1:0] register bits select the inputs to the adaptive comb filter, this would normally be xHH for chroma combs, xHF for luma combs, and xHL if the luminance signal was to be sampled dropped on the output of the TMC22x5y. The Gaussian filters in the sample drop mode already l