TMC2067P7C TMC1185 TMC22153 TMC2242 TMC2068P7C TMC22071A EL4390 ADS800 TMC2242B

TMC2067P7C Dual A/D Demonstration Board for the TMC1185 10-Bit Analog-to-Digital Converter Features Description · Analog

www.fairchildsemi.com TMC2067P7C TMC2067P7C Dual A/D Demonstration Board for the TMC1185 TMC1185 10-Bit Analog-to-Digital Converter Features Description · Analog Composite and YC input processing · 10-bit Digital Composite and YC outputs · Fairchild demo board compatibility The TMC2067P7C TMC2067P7C provides a high quality 10-bit front end for the TMC22153 TMC22153 digital decoder. Applications · Evaluation of TMC1185 TMC1185, 10-bit A/D · Evaluation of TMC2242 TMC2242, Decimation filter · Input to the TMC2068P7C TMC2068P7C Decoder demonstration board. Block Diagram TMC1185 TMC1185 Output to Genlock Y/Composite LPF and Clamp Circuit Y/Comp Input S-VHS TMC1185 TMC1185 10 bit ADCs Chrominance BPF and Clamp Circuit TMC2242 TMC2242 Digital LPFs Digital Outputs: 10 bit Composite/Luma 10 bit Chroma TMC2242 TMC2242 Digital Inputs: ADC Clock Clamp Signal Chroma Input SW1 96 Way Edge Connector (Male) SW2 Analog Front End for the TMC22153 TMC22153 Digital Decoder 65-2067-01 Rev. 0.9.0 PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information. Preliminary Information Composite and YC inputs are clamped and filtered before being oversampled in the TMC1185 TMC1185 10-bit A/D. The A/D outputs are decimated in TMC2242 TMC2242 half band filters to provide the pixel data to the TMC22153 TMC22153 digital decoder demonstration board. TMC2067P7C TMC2067P7C Preliminary Information Functional Description The Y/COMP (luminance/composite) analog input is buffered to a BNC for connection to the TMC22071A TMC22071A genlocking video digitizer on the TMC2068P7C TMC2068P7C decoder demonstration board. The Y/COMP signal is also passed through a simple antialiasing low pass filter. The filtered Y/COMP signal is clamped to the back porch level using the Elantec EL4390 EL4390. The clamp pulse is provided by an FPGA on the TMC2068P7C TMC2068P7C decoder demonstration board, which is locked to the horizontal sync produced by the TMC22071A TMC22071A. The clamped Y/COMP signal is transformed into the differential input signal required by the TMC1185 TMC1185, 10-bit ADC. The differential Y/COMP signal is oversampled in the TMC1185 TMC1185, using the PXCK clock from the TMC22071A TMC22071A, and then decimated in the TMC2242 TMC2242 digital low pass filter. The CHROMA (chrominance) analog input is passed through a simple bandsplit filter which acts as both the antialiasing filter for the TMC1185 TMC1185 and suppresses low frequency noise or signals on the CHROMA signal. The filter output is clamped to the chroma black level using the Elantec EL4390 EL4390 using the same clamp pulse used to clamp the Y/COMP signal. The clamped CHROMA signal is transformed into the differential input signal required by the TMC1185 TMC1185. The differential CHROMA signal is oversampled in the TMC1185 TMC1185, using the PXCK clock from the TMC22071A TMC22071A, and then decimated in the TMC2242 TMC2242 digital low pass filter. The mode of operation of the TMC2242 TMC2242 digital half band filters can be independently controlled using the the two DIP switches, SW1 and SW2, provided. An S-VHS connector is also provided and is directly coupled to the BNCs, therefore care should be taken not to connect inputs to both the BNCs and the S-VHS connector simultaneously. 12-Bit Option The footprint for the Burr Brown 12-bit A/D (ADS800 ADS800) is compatible with the Fairchild TMC1185 TMC1185 10-bit A/D, it is therefore possible to replace the TMC1185 TMC1185 and reconfigure the TMC2242 TMC2242, using the DIP switches, to evaluate the TMC22153 TMC22153 performance with a 12-bit oversampled A/D front end, which is then decimated and rounded to 10-bits. This improves the overall S/N performance by decreasing the noise introduced by the quantization of the video signal. This option is not presently provided, and requires the board to be purchased and modified by the customer. However, applications support will be provided to assist in any modifications that are required. PRODUCT SPECIFICATION the edge connector P2B pin 6. Optional AC coupling is provided by C3, C4 and R9. U9:B provides the necessary gain to drive the A-D converter and is provided with a gain adjustment, RV3. The output of U9:B drives the anti-alias filter consisting of R45, C52, L5, C53, L6, C54 and R47. This filter provides a Butterworth response with about 30dB of attenuation at 13.5MHz. Since the filter introduces some group delay it is followed by an all-pass delay correction circuit consisting of U9:A and its associated components. (Additional correction is provided by the D-A driver/inverter circuit described below.) The output of the anti-alias filter at U9:A pin 1 connects to one input of the clamp circuit consisting of U3 and its associated components. C18 provides DC isolation and storage of the clamp potential. The clamp pulse at pin 6 of U3 samples the reference potential at pin 14 to establish the clamp point for the A channel. The optimum position for the clamp pulse is immediately after the color burst to avoid phase and amplitude modulation of the burst. The clamp amplifier has a gain of two to compensate for the 6dB loss through the anti-alias filter (set by R24 and R25). The A-D has an input range of 1.25 to 3.25 volts and so the clamp reference voltage is chosen to put the composite signal within this range after a gain of two has been applied. The second channel of the clamp circuit is used as a buffer for the A-D midpoint (CM) reference signal used by the inverters. This is achieved by connecting the clamp reference input of this channel to the amplifier input and running the amplifier at unity gain. The clamped A channel signal connects to buffer U10:B and inverter U10:A. Both the buffer and inverter are configured for all-pass operation in order to provide additional group delay correction. The buffer is mainly required to provide delay matching between the normal and inverted inputs of the A-D converter. The inverter, U10:A obtains its invert reference from the buffered CM output of the A-D ensuring that the A channel signal is inverted about the midpoint of the A-D input range. The normal and inverted outputs from U:10 connect to the differential inputs of the A-D converter, U11, via the filter networks consisting of R56, C62 and R52, C57. For a detailed description of the A-D converter operation refer to the Fairchild TMC1185 TMC1185 data sheet. The digital output of the A-D converter connects to the TMC2242B TMC2242B decimator, U7, where the pixel rate is halved. For more information on the decimator, refer to the Fairchild TMC2242B TMC2242B data sheet. Detailed Circuit Description Chroma Channel Composite/Luma Channel The B Channel is similar to the A channel except that the anti-alias filter is implemented as a bandpass filter and the clamp axis is chosen for a bipolar signal (i.e. A-D midpoint reference). The input stage U2:B is AC coupled from J4 via C5 and R11. The SVHS connector, J3, bridges the The Y or Composite input from BNC J1 is terminated at R4 and buffered by U1:A to provide a synchronizing output at J2. In addition a second signal is buffered through U1:B to 2 PRODUCT SPECIFICATION TMC2067P7C TMC2067P7C Y/Composite and Chroma inputs so that only one set of inputs can be used at a time. The all-pass sections in his channel are primarily used to match the delay through the two channels. c. Since the positive analog and digital supplies may now be the same, care should be taken to provide adequate filtering for the analog section of the circuit. Engineering Notes The following notes relate to the ORCAD schematics and are supplemental to the circuit description. 1. 3. The A-D midpoint reference (CM) for the inverters comes from the A channel A-D. This is done to make use of the available buffer in the EL4390 EL4390 and avoid having an additional reference buffer. Although there may be a slight difference between the two references the DC level of the chroma channel is not critical since it is re-established in the TMC22x5y. The schematic has been designed for +/- 12V operation. If it is desired to run the system from +/- 5V supplies, it will be necessary to make the following changes: a. Replace the EL2260 EL2260 op. amps with EL2270 EL2270 op. amps. b. Connect two series connected diodes (1N914 1N914 or similar) in series with the outputs of the EL4390 EL4390 at pins 10 and 15 with the cathodes of the diodes towards the output pins of the EL4390 EL4390. Add a pull up resistor (470 ohms) from the anode of the last diode and the junction of R9 to +5V. Add a similar resistor on the other channel at the junction with R22. 4. The power input filtering from the 96 pin connector uses ferrite beads. This should be adequate provided that the supplies do not have excessive low frequency noise. If the +5V digital supply from the main board is questionable it would be better to run a separate trace direct from the power supply to the 96 pin connector. Even using +/12V supplies it is still necessary that the +5V supply be reasonably clean since it is driving the A-D converters. 5. It is assumed that the trace length associated with the decimator outputs is relatively short (