SLAU025 TLV1571/1578 89/336/EEC 92/31/EEC 93/68/EEC ENV50204 EN55011 - Datasheet Archive

 

and Use of the TLV571/TLV157x EVM User's Guide September 1999 Mixed Signal Products SLAU025 IMPORTANT NOTICE Texas Instruments

 

Characteristics, Operation, and Use of the TLV571/TLV157x EVM User's Guide September 1999 Mixed Signal Products SLAU025 SLAU025 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright © 1999, Texas Instruments Incorporated Information About Cautions and Warnings Preface Read This First About This Manual This user`s guide describes the characteristics, operation, and use of the 10-bit TLV1571/1578 TLV1571/1578 analog-to-digital converter (ADC) evaluation module. How to Use This Manual This document contains the following chapters: - Chapter 1 EVM Overview Chapter 2 Getting Started Chapter 3 User Configurations Chapter 4 Control Registers Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. Read This First iii Trademarks The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. CE/FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 FCC rules. This device has been tested and found to comply with the limits for a CISPRII Group 1 and the following directives: EMC Directive 89/336/EEC 89/336/EEC amending directive 92/31/EEC 92/31/EEC and 93/68/EEC 93/68/EEC as per ENV50204 ENV50204: 1995, EN55011 EN55011: 1995 Class A, EN61000-4-4 EN61000-4-4: 1995, and EN6100-4-3 EN6100-4-3: 1993. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Trademarks TI is a trademark of Texas Instruments Incorporated iv Running Title-Attribute Reference Contents 1 EVM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 ADC System Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 Control/Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 EVM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 DSK/Microprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 PCI Daughtercard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Power and Cabling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 PCA as Part of a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 DSK/Microprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 PCI2040 PCI2040 'C54x Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 PCA Options Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 3 User Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 User Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Analog Input Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1 Apply to ADC Multiplexer (TLV1578 TLV1578 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2 Direct Connect (TLV1578 TLV1578 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.3 Apply Direct to Signal Conditioning (TLV1578 TLV1578) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.4 Apply Direct to Signal Conditioning (TLV1571/TLV571 TLV1571/TLV571) . . . . . . . . . . . . . . . . . . . 3-9 3.5 Generating a Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.5.1 Onboard Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.5.2 External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.6 Host Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.7 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.7.1 Software Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.7.2 Hardware Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.8 ADC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Chapter Title-Attribute Reference 1-1 1-2 1-3 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-4 1-4 1-5 1-5 1-5 1-6 1-7 v Running Title-Attribute Reference 3.9 4 3.8.1 External Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 DSK/Microprocessor Mode ('C54x DSKplus, 'C203 EVM, 'C3x DSK) . . . . . . 3.8.3 PCI2040 PCI2040 and 'C5402 C5402 DSK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 Synchronizing the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connector Pin and Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Control Register 0 ­ CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Control Register 1 ­ CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-15 3-16 3-16 3-17 4-1 4-2 4-2 4-4 Figures 1­1 1­2 1­3 2­1 2­2 2­3 2­4 2­5 2­6 3­1 3­2 3­3 3­4 3­5 3­6 3­7 3­8 3­9 vi Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Mating of Connectors J7 and J10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Mounting the EVM on the PC12040 PC12040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 PWB Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Layer 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Silk Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 EVM Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Reconfiguration Hardware Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Direct Connect Jumper Configuration for TLV1578 TLV1578 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Gain Circuit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Onboard Signal Conditioning Circuit for TLV1 571/TLV571 571/TLV571 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Onboard Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 External Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Hardware Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 External Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Running Title-Attribute Reference Tables 1­1 1­2 1­3 2­1 3­1 3­2 3­3 3­4 3­5 3­6 3­7 3­8 3­9 3­10 3­11 3­12 3­13 3­14 3­15 3­16 3­17 3­18 3­19 3­20 4­1 4­2 4­3 Package Styles Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 General ADC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Possible ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Parts List for the TLV571/TLV157x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Jumper Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Analog Voltage Supply Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Analog Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Shipping Condition of Jumpers W1 and W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 TLV1578 TLV1578 Shipping Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 TLV1571/571 TLV1571/571 Shipping Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Shipping Condition for VEREFP and VREFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Host Interface Jumpers Shipping Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Stand-Alone Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Loopback Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Stand-Alone Selection, 20 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Stand-Alone Selection, 10 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Stand-Alone Selection External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 PCI2040 PCI2040 EVM 'C5402 C5402 DSK Selection, 12.5 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Connector Pin and Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 J5 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 J6 Analog Signal Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 J7 DSK/Microprocessor Control Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 J10 Parallel Data Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Function of Connectors J11 and J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Data Bus Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Control Register 0 (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Control Register 1 (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Contents vii viii Chapter 1 EVM Overview This chapter gives a general overview of the TLV1578/TLV1571/TLV571 TLV1578/TLV1571/TLV571 evaluation module (EVM), and provides a general description of the features and functions that should be considered in using this module properly. Topic Page 1.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 ADC System Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 EVM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Power and Cabling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.5 PCA as Part of a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.6 PCA Options Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 EVM Overview 1-1 System Block Diagram 1.1 System Block Diagram The TLV1578/TLV1571/TLV571 TLV1578/TLV1571/TLV571 EVM provides a practical platform for evaluating the following devices: - TLV1578 TLV1578 10-bit, eight-channel data acquisition system TLV1571 TLV1571 10-bit, one-channel data acquisition system TLV571 TLV571 8-bit, one-channel data acquisition system The EVM supports two package styles as shown in Table 1­1. Table 1­1. Package Styles Available DA Package Supported? DW Package Supported? PW Package§ Supported? TLV1578 TLV1578 Yes, 32 pins No No TLV1571 TLV1571 No No Yes, 24 pins TLV571 TLV571 No No Yes, 24 pins Device The DA package is a TSSOP device, with pins on a 0.65-mm pitch. The DW package is a small outline (SO) device, with pins on a 1.27-mm pitch. § The PW package is a TSSOP device, with pins on a 0.65-mm pitch. The system block diagram is shown below. This illustration provides a general overview of the EVM. It is not meant to replace the circuit diagram, but to give a brief indication of the features and functions available. It should be read in combination with the circuit diagram supplied. The elements of this block diagram are discussed in Figure 1­1. Figure 1­1. Block Diagram DSK/Micro Interface J6 8 ADC Analog Inputs 8 J10 16 J1 J2 Signal Conditioning J3 J7 Control/ Interface DAC J4 PCI Interface J8 J5 1-2 VCC GND J9 ADC System Discussion 1.2 ADC System Discussion This printed wiring board (PWB) EVM supports three analog-to-digital converters (ADCs). - TLV1578 TLV1578 TLV1571 TLV1571 TLV571 TLV571 From a physical and functional viewpoint, the significant distinction between these parts is that the TLV1578 TLV1578 features an 8­1 multiplexer (MUX). This allows selection of the analog-input channel to be digitized. The TLV1571 TLV1571 and TLV571 TLV571 do not provide a MUX. General features of these ADCs are given in Table 1­2. Table 1­2. General ADC Features Resolution Channels Sweep Mode Self-Test Output Throughput at 5 V Available Package EVM Order Number TLV1578 TLV1578 10 bit 8 Yes Yes 1.25 MSPS DA TLV1578 TLV1578 TLV1571 TLV1571 10 bit 1 No Yes 1.25 MSPS DW/PW TLV1571 TLV1571 TLV571 TLV571 8 bit 1 No No 1.25 MSPS DW/PW TLV571 TLV571 Device 1.2.1 ADC This successive approximation scheme relies on charge redistribution to count and weigh each bit from MSB to LSB. Each bit of the ADC has a corresponding capacitor. The procedure involves successively comparing the charge on each capacitor to a reference value. As the process develops, the digital bit corresponding to each capacitor is either set or cleared. 1.2.2 DAC A 12-bit digital-to-analog converter (DAC) present on the EVM can be used either as an independent device (via either the DSP starter kit (DSK) interface or the peripheral component interconnect (PCI) interface), or can be arranged to operate in synchronization with the ADC. 1.2.3 Signal Conditioning Signal conditioning is available prior to conversion. The conditioning circuit consists of an operational amplifier in a noninverting configuration. The nominal gain for the circuit is one, but you can change it. The slew rate of the amplifier should be sufficiently high (25 V/µS) to respond to fast-changing signals such as square-wave inputs. 1.2.4 Control/Interface The control signals can be derived from either a DSK/microprocessor or a dedicated PCI-based DSP. The signals from either source are the same. The decision regarding which host system to use is left to the discretion of the user. EVM Overview 1-3 EVM Operating Modes 1.3 EVM Operating Modes There are three modes of oepration for the EVM: - Stand-alone mode DSK/Microprocessor mode PCI daughtercard Each of these modes is discussed below. 1.3.1 Stand-Alone Mode Upon power up, all the bits in both ADC control registers are cleared; this allows the ADC to immediately begin conversion from a known condition. The stand-alone mode is the minimal operating mode for the system. Conversions are automatic and do not require a host. 1.3.2 DSK/Microprocessor Mode The DSP starter kit (DSK)/microprocessor mode supports parallel transfers via TI's range of DSK modules-'C54xDSKplus, 'C54xDSK, or the 'C203DSK C203DSK. In general, any microprocessor that can provide basic address, data, and control signals can be interfaced to the EVM. 1.3.3 PCI Daughtercard The EVM also supports the TMS320C6000 TMS320C6000 daughtercard specification. This specification introduces a standard physical and electrical interface to 'C6000 C6000 and 'C5000 C5000 systems integrated on a PCI card. The PCI local bus is a high-performance bus that provides a processor-independent data path between the CPU and high-speed peripherals. 1.4 Power and Cabling Requirements The EVM dc supply voltage is 3 V to 5 V and should be set to approximately 3.3 V or 5.3 V, respectively. The power and externally applied reference voltage should be supplied to the EVM through shielded twisted-pair wire for best performance. This type of power cabling minimizes any stray or transient pickup from the higher-frequency digital circuitry. 1-4 PCA as Part of a System 1.5 PCA as Part of a System 1.5.1 Stand-Alone Mode The stand-alone mode allows the ADC and DAC to operate without a host system. The following steps are required to achieve this: - Supply +5 V and ground via J5 Jumper between pins 15 and 16 of J7 Jumper between pins 19 and 20 of J7 Jumper between pins 21 and 22 of J7 Clip (or wire-wrap) a connection between TP3 and pin 13 of J7 Remove W22 (located on the breadboard area) Supply and analog signal for conversion via J6 (ribbon cable) or J1 (BNC) Supply a convert signal via J11 Initiate conversion by momentarily pressing SW1 Subsequent conversions occur automatically. No DSP or microprocessor is required. 1.5.2 DSK/Microprocessor Mode In this mode the DSP supplies control and address signals via J7, and data via J10. EVM Overview 1-5 PCA as Part of a System Figure 1­2. Mating of Connectors J7 and J10 1.5.3 PCI2040 PCI2040 'C54x Mounting In this mode, J8 and J9 mate directly to corresponding connectors in the motherboard card (see Figure 1­3). 1-6 PCA Options Available Figure 1­3. Mounting the EVM on the PC12040 PC12040 1.6 PCA Options Available To ensure the flexibility of the printed-circuit board (PCB), three possible ADCs featured in this series are described in Table 1­3. Table 1­3. Possible ADCs ADC Part No. No. of Channels No. of Bits Speed EVM Order No. TLV571 TLV571 1 10 1.25 MSPS TLV571 TLV571 TLV1571 TLV1571 1 10 1.25 MSPS TLV1571 TLV1571 TLV1578 TLV1578 8 10 1.25 MSPS TLV1578 TLV1578 Ensure that the printed-circuit assembly (PCA) has the correct check mark on the silkscreen. Each PCA may have additional hardware to install, if appropriate. EVM Overview 1-7 1-8 Chapter 2 Getting Started This chapter describes the physical characteristics and PCB layout of the EVM, and lists the components used on the module. Topic Page 2.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Getting Started 2-1 Physical Description 2.1 Physical Description The PWB is constructed in four layers as shown in the following illustrations. The dimensions of the PWB are 5.25 in × 3.5 in (133.35 mm × 88.9 mm). See Figure 2­1. Figure 2­1. PWB Layers Component Side Tracking Layer Layer 1 DGND/AGND Layer 2 DVDD/AVDD Layer 3 Tracking Layer Layer 4 Solder Side Figures 2­2 through 2­5 show the tracking for each layer. Figure 2­2. Layer 1 2-2 Physical Description Figure 2­3. Layer 2 Figure 2­4. Layer 3 Getting Started 2-3 Physical Description Figure 2­5. Layer 4 Note: This layer is the solder-side of the PCA and is shown reversed for clarity. Figure 2­6. Silk Screen 2-4 Parts List 2.2 Parts List This table lists the parts required for the TLV571/TLV157x devices. Table 2­1. Parts List for the TLV571/TLV157x Devices Quantity Value 571 1571 1578 8 8 16 Ref. Des. Footprint Description Manufacturer Part Number PCB fabrication N/A N/A TLV157X TLV157X Rev ­ PCB fabrication TBD TLV157X TLV157X 8 0.1 µF C24 C25 C29 C30 C40 C41 C43 C45 1206 Ceramic, X7R, 50 V, 10% Kemet C1206C104K5RAC C1206C104K5RAC 16 16 0.1 µF C19 C22 C23 C27 C28 C3 C32 C33 C35 C36 C37C4 C37C4 C42 C7 C8 C9 805 Ceramic, X7R, 50 V, 10% Kemet C0805C104K5RAC C0805C104K5RAC 2 2 2 100 pF C34 C38 805 Ceramic, COG, 50V, 2% Kemet C0805C101G5GAC C0805C101G5GAC 4 4 4 10 µF C20 C21 C26 C31 3528 10 µF, 10 V, 10%, tantalum Kemet T491B106K010AS T491B106K010AS 1 1 1500 pF C44 1206 Ceramic, X7R, 50 V, 10% Kemet C1206C152K5RAC C1206C152K5RAC 9 1500 pF C5 C6 C10 C11 C12 C16 C17 C18 C44 1206 Ceramic, X7R, 50 V, 10% Kemet C1206C152K5RAC C1206C152K5RAC 3 3 3 270 pF C13 C14 C39 805 Ceramic, COG, 50 V, 2% Kemet C0805C271G5GAC C0805C271G5GAC 4 4 4 4.7 µF C1 C2 C46 C47 3216 4.7 µF, 10 V, 10%, tantalum Kemet T491A475K010AS T491A475K010AS 1 1 1 560 pF C15 805 Ceramic, COG, 50 V, 2% Kemet C0805C561G5GAC C0805C561G5GAC 1 1 1 GRN LED D1 1206 Green, 20 mA, 1206 size Chicago Miniature CMD11-21VGC/TR8 CMD11-21VGC/TR8 2 2 2 26PIN 26PIN_IDC J6 J7 13X2X 13X2X.1 26-pin header Samtec TSW-113-07-L-D TSW-113-07-L-D 1 1 1 34PIN 34PIN_IDC J10 17X2X 17X2X.1 34-pin header for IDC Samtec TSW-117-07-L-D TSW-117-07-L-D 1 1 1 KRMZ2 J5 N/A 2-terminal screw connector Lumberg KRMZ2 4 4 RA-SMA_JACK J3 J4 J11 J12 N/A Right angle PCB mount SMA jack Lighthorse Technologies LTI-SALF54NT LTI-SALF54NT 5 RA-SMA_JACK J1 J3 J4 J11 J12 N/A Right angle PCB mount SMA jack Lighthorse Technologies LTI-SALF54NT LTI-SALF54NT 2 2 2 TFM-140 TFM-140 J8 J9 N/A 80-pin 0.050" centers Samtec TFM-140-31-S-D-A TFM-140-31-S-D-A 1 1 1 1.0 µH L2 DO1608C DO1608C DO1608C DO1608C Series­Coil Craft Coil Craft DO1608C-102 DO1608C-102 1 1 1 4.7 µH L1 DO1608C DO1608C DO1608C DO1608C Series­Coil Craft Coil Craft DO1608C-472 DO1608C-472 5 5 5 33 X 8 R30 R52 R53 R59 R61 2NBS16 2NBS16 8-element ­ isolated resistor pack Bourns 2NBS16-TJ1-330 2NBS16-TJ1-330 Getting Started 2-5 Parts List Table 2­1. Parts List for the TLV571/TLV157x Devices(Continued) Quantity Value Ref. Des. Footprint Description Manufacturer Part Number 4 4 4 0 R3 R39 R54 R70 1206 1206 chip res., 5% Bourns CR1206-FX-000 CR1206-FX-000 1 1 1 10 R60 1206 1206 chip res., 1% Bourns CR1206-FX-10R0 CR1206-FX-10R0 4 4 4 100 R13 R14 R15 R17 1206 1206 chip res., 1% Bourns CR1206-FX-1000 CR1206-FX-1000 10K R1 R4 R5 R16 R18 R19 R23 R24 R25 R26 R27 R35 R36 R49 R50 R51R56 R51R56 R57 R58 R64 R68 R69 R72 R73 1206 1206 chip res., 1% Bourns CR1206-FX-1002 CR1206-FX-1002 24 22 22 10K R1 R4 R5 R16 R18 R19 R23 R24 R25 R26 R27 R35 R36 R49 R50 R51R56 R51R56 R57 R58 R64 R72 R73 1206 1206 chip res., 1% Bourns CR1206-FX-1002 CR1206-FX-1002 1 1 1K R32 1206 1206 chip res., 1% Bourns CR1206-FX-1001 CR1206-FX-1001 3 3 3 2.49K R29 R37 R38 1206 1206 chip res., 1% Bourns CR1206-FX-2491 CR1206-FX-2491 10 10 33 R28 R42 R43 R44 R45 R46 R47 R48 R63 R66 1206 1206 chip res., 5% Bourns CR1206-FX-330 CR1206-FX-330 18 33 R6 R8 R10 R11 R12 R20 R21 R22 R28 R42 R43 R44 R45 R46 R47 R48 R63 R66 1206 1206 chip res., 5% Bourns CR1206-FX-330 CR1206-FX-330 1 2 2 2 332 R40 R71 1206 1206 chip res., 1% Bourns CR1206-FX-3320 CR1206-FX-3320 1 1 1 470 R67 1206 1206 chip res., 5% Bourns CR1206-FX-470 CR1206-FX-470 1 1 1 499 R31 1206 1206 chip res.,1% Bourns CR1206-FX-4990 CR1206-FX-4990 3 3 3 5K POT R33 R34 R41 32X4W 32X4W 4 mm, 5T, SM potentiometer Bourns 3214W-1-502-W 1 1 1 Panasonic EVQ-PJSO4K SW1 EVQ-PJ Momentary push button Panasonic EVQ-PJ 3 3 3 Test point TP2 TP4 TP9 N/A Turret type test point Cambion 180-7337-02-05 7 7 7 Test point TP1 TP3 TP5 TP6 TP7 TP8 TP10 N/A Test point ­ single 0.025" Pin Samtec TSW-101-07-LS TSW-101-07-LS 1 1 1 SN74AHC04 SN74AHC04 U1 14-SOP 14-SOP(D) Hex inverter Texas Instruments SN74AHC04D SN74AHC04D 2-6 Parts List Table 2­1. Parts List for the TLV571/TLV157x Devices (Continued) Quantity Value Ref. Des. Footprint Description Manufacturer Part Number 1 1 1 SN74AHC08 SN74AHC08 U3 14-SOP 14-SOP(D) Quad NAND gate Texas Instruments SN74AHC08D SN74AHC08D 1 1 1 SN74AHC138 SN74AHC138 U6 16-SOP 16-SOP(D) 3­8 LINE DEC/DEMUL Texas Instruments SN74AHC138D SN74AHC138D 2 2 2 SN74AHC245 SN74AHC245 U12 U13 20-SOP 20-SOP(DW) Octal bus transceiver, 3-state Texas Instruments SN74AHC245DW SN74AHC245DW 1 1 1 SN74AHC32 SN74AHC32 U2 14-SOP 14-SOP(D) Quad 2-Input positive OR gate Texas Instruments SN74AHC32D SN74AHC32D 1 1 1 SN74AHC541 SN74AHC541 U8 20-SOP 20-SOP(DW) Octal buffer and driver Texas Instruments SN74AHC541DW SN74AHC541DW 1 1 1 SN74AHC74 SN74AHC74 U15 14-SOP 14-SOP(D) Dual D-type FF Texas Instruments SN74AHC74D SN74AHC74D 1 1 1 TL1431 TL1431 U7 8-SOP(D) Precision programmable reference Texas Instruments TL1431CD/ TL1431CD/ TL1431QD TL1431QD 2 TL7726 TL7726 U4 U5 8-SOP(D) Hex clamp circuit Texas Instruments TL7726CD/TL7726ID TL7726CD/TL7726ID /TL7726QD /TL7726QD TLV571 TLV571 U10 24-PW 24-PW 8-bit single channel ADC Texas Instruments TLV571CPW/ TLV571CPW/ TLV571IPW TLV571IPW TLV1571 TLV1571 U10 24-PW 24-PW 10-bit single channel ADC Texas Instruments TLV1571CPW/ TLV1571CPW/ TLV1571IPW TLV1571IPW 1 TLV1578 TLV1578 U10 32-DA 32-DA 10-bit eight channel ADC Texas Instruments TLV578CDA/ TLV578CDA/ TLV578IDA TLV578IDA 1 1 1 1 1 TLV2771 TLV2771 U14 5-SOT(DBV) Low-power single op amp Texas Instruments TLV2771IDBV/ TLV2771IDBV/ TLV2771CDBV TLV2771CDBV 1 1 1 TLV2772 TLV2772 U11 8-SOP(D) Dual op amp in 8-pin SOP package Texas Instruments TLV2772ID/ TLV2772ID/ TLV2772AID/ TLV2772AID/ TLV2772CD/ TLV2772CD/ TLV2772AMD TLV2772AMD 1 1 1 TLV5619 TLV5619 U9 20-SOP 20-SOP(DW) 12-bit parallel DAC Texas Instruments TLV5619CDW/ TLV5619CDW/ TLV5619IDW TLV5619IDW 4 4 Shunt jumper W11 W6 W16 W21, W22 2pos_jump 2-position jumper 0.1" spacing Samtec TSW-102-07-LS TSW-102-07-LS 3 Shunt jumper W11 W6 W16 2pos_jump 2-position jumper 0.1" spacing Samtec TSW-102-07-LS TSW-102-07-LS 17 2-way shunt jumper W1 W2 W3 W4 W5 W7 W8 W9 W10 W12 W13 W14 W15 W17 W18 W19 W20 3pos_jump 3-position jumper 0.1" spacing Samtec TSW-103-07-LS TSW-103-07-LS CR1206-FX-49R9 CR1206-FX-49R9 17 17 Customer-Installed Options 5 5 5 49.9 R2 R7 R9 R62 R65 1206 1206 chip res., 1% Bourns 1 1 1 SIT R55 1206 1/4W 1206 chip resistor Any 1 1 1 RA ­ SMA J2 RA_SMA_JA CK Right angle PCB mount SMA jack Amphenol Note: 901-143-3 Manufacturer and part number data is supplied for reference only. Substitutions are permissible on all but TI parts. Getting Started 2-7 2-8 Chapter 3 User Configurations This chapter describes the user-definable options. Topic Page 3.1 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 User Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Analog Input Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5 Generating a Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6 Host Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.7 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.8 ADC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.9 Connector Pin and Function Assignments . . . . . . . . . . . . . . . . . . . . . 3-17 User Configurations 3-1 Schematic Diagram 3.1 Schematic Diagram Figure 3­1 illustrates the EVM schematic. 3-2 W19 25MHz (10MHz) 1 26 24 22 20 18 16 14 12 10 8 6 4 2 J7 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 5 6 9 8 R42 A15 U15B PRE CLK D CLR CLKOUT DSP_0 DSP_1 DSP_2 DSP_3 DSP_4 DSP_5 DSP_6 DSP_7 DSP_8 DSP_9 DSP_10 DSP_11 DSP_12 DSP_13 DSP_14 DSP_15 SN74AHC74 SN74AHC74 Q Q U15A 1 3 4 3 2 1 10 11 12 13 1 VCCD VCCD 49.9 R62 CLK U1D R66 33 470 R67 8 J12 10K R27 SN74AHC04 SN74AHC04 9 ADC_CLK R43 R44 R45 R46 R47 R48 W5 1 33 33 W17 W18 PRE CLK D CLR SN74AHC74 SN74AHC74 Q Q 3 3 EREFM EREFP AOUT CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CLK XF R/W# (WE#) I/O_STRB# INT0# A0 A1 33 12.5MHz (5MHz) 25 23 21 19 17 15 13 11 9 7 5 3 1 J10 3 CLK 1 3 5 7 9 11 13 15 17 19 21 23 25 26PIN 26PIN_IDC 2 4 6 8 10 12 14 16 18 20 22 24 26 J6 2 3 4 5 6 7 8 9 19 1 J1 R59A R59B R59C R59D R59E R59F R59G R59H R61A R61B R61C R61D R61E R61F R61G R61H U8 GND Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 VCC 10K 10K 10K 10K 49.9 R7 33 DIR 33 C40 0.1uF W22 SN74AHC541 SN74AHC541 A1 A2 A3 A4 A5 A6 A7 A8 OE2 OE1 R23 R24 R25 R26 VCCD C41 0.1uF R64 10K VCCD R30H 11 10 18 17 16 15 14 13 12 11 20 3 10K R74 U13 2 3 4 5 6 7 8 9 1 19 2 3 4 5 6 7 8 9 1 33 12 13 GND B1 B2 B3 B4 B5 B6 B7 B8 VCC GND B1 B2 B3 B4 B5 B6 B7 B8 VCC SN74AHC245 SN74AHC245 A1 A2 A3 A4 A5 A6 A7 A8 DIR /OE A1 A2 A3 A4 A5 A6 A7 A8 DIR /OE 10 18 17 16 15 14 13 12 11 20 10 18 17 16 15 14 13 12 11 20 33 R11 33 R12 33 R8 R52A R52B R52C R52D R52E R52F R52G R52H R53A R53B R53C R53D R53E R53F R53G R53H VCCD VCCD CSADC# 33 R63 33 R6 CH1 B_XF B_R/W# B_I/OSTRB# B_INT0# B_A1 B_A0 CH3 CH2 W2 CSDAC# C28 0.1uF 49.9 R9 U12 SN74AHC245 SN74AHC245 SN74AHC08 SN74AHC08 19 J2 CH0 ADC_CLK VCCD R30A R30B R30C R30D R30E R30F 1 U3D W1 33 33 R68 10K TLV571 TLV571 ONLY WR# RD# R16 10K U4B TL7726 TL7726 U4C TL7726 TL7726 U4D TL7726 TL7726 U4E TL7726 TL7726 VCCD D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 R69 10K 10K R5 C11 1500pF C12 1500pF C6 1500pF C5 1500pF CSADC# 3 4 5 6 CH7 CH6 CH5 CH4 33 R20 33 R21 33 R22 33 R10 6 5 4 3 B_I/OSTRB# R70 U10 CH7 CH6 CH5 CH4 NC/MO AIN AVDD AGND REFM REFP CSTART D9 D8 D7 D6 D5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C16 1500pF C17 1500pF C18 1500pF C10 1500pF B_R/W# (LOOP BACK) W6 R19 10K VCCD 0 Ohms DAC_WE# CHO CH1 CH2 CH3 CS WR RD CLK DGND DVDD INT / EOC D0 D1 D2 D3 D4 NOTE: TLV571/TLV1571 TLV571/TLV1571 DO NOT HAVE CH0­CH7 AND PIN 28 IS NC. TLV1578DA TLV1578DA or TLV571/TLV1571PW TLV571/TLV1571PW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D6 D7 D8 D9 D10 R30G U5E TL7726 TL7726 U5D TL7726 TL7726 U5C TL7726 TL7726 U5B TL7726 TL7726 U1A 6 2 U1C C24 0.1uF 5 4 2 1 U2A U2B SN74AHC32 SN74AHC32 6 3 R65 49.9 TP7 WR# DIR 100 R14 C14 270pF C29 0.1uF 0.1uF SN74AHC32 SN74AHC32 5 J11 TP8 C30 VCCA SN74AHC04 SN74AHC04 D[0.15] SN74AHC04 SN74AHC04 1 100 R15 D11 D12 D13 D14 D15 4 U1B W20 TP5 TP6 W14 SW1 4 5 6 4 5 1 2 3 100 R17 R18 10K VCCD 100 R13 1 2 U3A B_XF 8 C15 560pF W13 U3C VCCA 3 1 3 W8 3 1 10 9 RD# J3 B_INT0# CH0 R2 49.9 TP10 R4 10K W21 VCCD VREFP VREFM W15 W16 TLV2771 TLV2771 U14 VCCA CSADC# CSTART# CSDAC# SN74AHC08 SN74AHC08 CSTART# W9 B_XF 3 1 R55 TBD R54 0 SN74AHC08 SN74AHC08 270pF 6 15 14 13 12 11 10 9 7 SN74AHC138 SN74AHC138 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U6 VREF_DAC C13 3 1 C39 270 pF 10 R60 G1 G2A G2B A B C SN74AHC08 SN74AHC08 U3B 3 SN74AHC04 SN74AHC04 C25 0.1uF 3 1 B_A0 B_A1 R36 10K VCCD 16 VCCD DGND 8 Figure 3­1. EVM Schematic Diagram Schematic Diagram User Configurations 3-3 D1 7 U5F TL7726 TL7726 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D4 D5 VCCA R38 2.49K 0 R39 R31 499 7 2 VREF_DAC 10uF + C21 U5A TL7726 TL7726 2 D[0.15] R71 1K GREEN 33 R28 8 1 VCCA C20 10uF U9 1 2 3 4 5 6 7 8 9 10 U4F TL7726 TL7726 U4A TL7726 TL7726 R33 5K POT D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 + C19 0.1uF 2.49K R41 5K POT R32 1K R34 5K POT 20 19 18 17 16 15 14 13 12 11 C35 0.1uF C33 0.1uF C8 R1 10K 1 C7 3 3 3 W12 W10 AOUT 1 1 C31 10uF C23 + + C36 1 0.1uF C32 3 C37 0.1uF C27 0.1uF W4 0.1uF 0.1uF 0.1uF C22 J4 W11 R35 10K VCCD 10K R57 EREFM 10K C26 10uF EREFP R49 W7 0.1uF 0.1uF 0.1uF C9 VCCD C44 1500pF R40 332 C45 0.1uF VCCD D1 D0 CS WE LDAC PD GND OUT REFIN VDD VCCA C43 0.1uF TLV5619 TLV5619 R73 10K TL1431CD TL1431CD U7 R37 2.49K VCCA R72 10K 8 User Configurations 1 3-4 R29 Figure 3­1. EVM Schematic Diagram (Continued) R56 R58 R51 R50 0.1uF C42 DAC_WE# WR# CSDAC# 6 5 2 3 4 1 7 10K 10K U11B TLV2772 TLV2772 10K 10K U11A TLV2772 TLV2772 VCCA 8 A15 DSP_7 DSP_5 DSP_3 DSP_1 DSP_15 DSP_13 DSP_11 DSP_9 A1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 J9 TFM­140 VREFM +3.3V +5V C38 100pF C34 100pF VREFP 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 8 DSP_14 DSP_12 DSP_10 DSP_8 A0 4.7uH L1 0.1uF C3 TP3 TP4 TP9 R/W# (WE#) INT0# XF + TP2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 0 C46 4.7uF 3 1 CLKOUT I/O_STRB# 0.1uF C4 W3 +5V +3.3V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 R3 + +5V 1.0uH L2 TFM­140 J8 C1 4.7uF VCCA +3.3V +5V PCI2040 PCI2040 C54x Interface J5 2 1 3­5V SN74AHC04 SN74AHC04 10 SN74AHC04 SN74AHC04 12 SN74AHC32 SN74AHC32 U1E DSP_6 DSP_4 DSP_2 DSP_0 11 SN74AHC32 SN74AHC32 U1F U2C U2D +5V +3.3V 11 13 10 9 13 12 C47 4.7uF TP1 4.7uF + C2 VCCD + +3.3V Schematic Diagram User Options 3.2 User Options The PCA ships in a state that enables immediate evaluation of the analog-to-digital converter (ADC). However, you can reconfigure various options through hardware. This chapter discusses these options to ensure that any reconfiguration is conducted properly. The hardware on the PCA falls into various groups: - 18 jumpers 4 wire links 2 resistors 1 momentary push switch Table 3­1 lists jumper options, a brief description of each function, and information on where the option can be found. Table 3­1. Jumper Functions Jumper Reference Function Description Section W1 Ch 0 input 3.4.2 W2 Ch 1 input 3.4.2 W3 Selects 5-V or 3.3-V operation 3.3 W4 Configure for ADC loopback 3.7.1.2 W5 Maps PCA address 3.6 W6 Provides WR to DAC in loopback mode 3.7.1.2 W7 Loopback mode-provides CS to DAC 3.7.1.2 W8 Stand-alone mode Provides RD signal to ADC 3.7.1.1 3.7.1.2 W9 Selects an internal start conversion signal 3.7.2 W10 Select internal or external voltage reference 3.5 W11 Loopback mode-maintains DAC in nonpower-down mode 3.7.1.2 W12 Select internal or external voltage reference 3.5 W13 Provides positive reference voltage to ADC 3.5 W14 Supplies signal to ADC for conversion 3.4.2 W15 Provides negative reference voltage to ADC 3.5 W16 Selects input to gain stage amplifier 3.4.2 W17 ADC clock Select external or internal clock 3.8.2 3.8.3 W18 Select ADC clock 3.8.2 3.8.3 W19 Select internal clock speed 3.8.2 3.8.3 W20 Selects internal or external conversion 3.7.2 W21 Connects CH0 to J3 and W14 3.4.2 W22 Supports stand-alone mode Comment 3.4.2 User Configurations Wire link Wire link Wire link Wire link 3-5 Analog Supply Voltage Figure 3­2 indicates the physical locations of this hardware. Figure 3­2. Reconfiguration Hardware Location 1571, 1578, 571 EVM 3.3 Analog Supply Voltage Two options supply power to the analog section of the EVM: - 5V 3.3 V Select either option via jumper W3 in accordance with the following tables. Table 3­2. Analog Voltage Supply Configuration Options Jumper W3 Pins 2 and 3 3.3-V operation Jumper installed Jumper not installed 5-V operation 3-6 Pins 1 and 2 Jumper not installed Jumper installed Analog Input Configurations 3.4 Analog Input Configurations A variety of options are available to configure the analog inputs. This section describes these options, along with the jumper settings required. The two alternatives for the analog inputs are given in the following table. Table 3­3. Analog Input Options Connector Reference and Type Analog Input Option Inp t IDC SMA J1 Apply signal to ADC multi lexer multiplexer A ly J6 ­ 2 x 13 plug lug J2 Apply signal direct to converter J3 The user can select various configurations within each of these options. These are discussed below. 3.4.1 Apply to ADC Multiplexer (TLV1578 TLV1578 Only) Eight possible analog inputs are provided via connector J6. Section 3.9 Connects Pin and Function Assignments, gives the pin assignments for J6. 3.4.2 Direct Connect (TLV1578 TLV1578 Only) Analog inputs can also be taken directly from SMA connectors J1 (for channel 0), and J2 (for channel 1). In this configuration the user should remove the respective jumper on pins 1 and 2 and replace on pins 2 and 3. Figure 3­3. Direct Connect Jumper Configuration for TLV1578 TLV1578 J6 Pin 1 CH0 W1 ADC 1 Channel 0 2 CH0 3 J1 J6 Pin 3 CH1 MUX W2 1 2 Channel 1 CH1 3 J2 Table 3­4. Shipping Condition of Jumpers W1 and W2 Jumper Pins 1 and 2 Pins 2 and 3 W1 Jumper not installed Jumper installed W2 Jumper installed Jumper not installed User Configurations 3-7 Analog Input Configurations 3.4.3 Apply Direct to Signal Conditioning (TLV1578 TLV1578) The MUX output of the TLV1578 TLV1578 does not have an internal connection to the ADC. This output is available in case you want to provide some signal conditioning prior to conversion. There are three options when supplying a direct signal: - As the output of the MUX Via IDC J6 pin 1 Via J3, the surface-mounted BNC When applying a signal via J3, clamping of the input voltage will be possible only if W1 is jumpered from 1 to 2 and W21 is intact. This signal conditioning consists of an op amp configured as a voltage follower with a nominal gain of 1. Alternate values for R54 and R55 affect the gain of this amplifier, as shown by the following expression: G +1) R54 R55 The configuration for this conditioning circuit is selected via wire links and a jumper, as shown in the following illustration. Figure 3­4. Gain Circuit Selection CH0 J6 Pin 1 TLV1578 TLV1578 W21 ADC Input W14 3 J3 2 1 W16 Gain Circuit R54 G=1+ R55 1 TP10 2 3-8 MUX Output Analog Input Configurations Table 3­5. TLV1578 TLV1578 Shipping Condition TLV1578 TLV1578 Shipping Condition Reference Description Position 1 ­ 2 W14 Selects input signal to ADC Gain circuit output External input via J3 or channel 0 via W21 Installed W16 Link selects input for signal conditioning Multiplexer output External input via J3 or channel 0 via W21 Installed W21 Link connects channel 0 to J3 / W14 / W16 Installed R54 0 Installed R55 N/A Position 2 ­ 3 Not installed 3.4.4 Not installed Apply Direct to Signal Conditioning (TLV1571/TLV571 TLV1571/TLV571) Because the TLV1571 TLV1571 and TLV571 TLV571 do not possess internal multiplexers, the configuration to allow an analog input signal to use the onboard signal conditioning circuit is slightly different, as illustrated in the following figure. Figure 3­5. Onboard Signal Conditioning Circuit for TLV1571/TLV571 TLV1571/TLV571 CH0 J6 Pin 1 TLV1578 TLV1578 W21 ADC Input W14 3 J3 2 1 W16 Gain Circuit R54 G=1+ R55 1 TP10 2 MUX Output User Configurations 3-9 Generating a Voltage Reference Table 3­6. TLV1571/571 TLV1571/571 Shipping Condition Reference Description Position 1 ­ 2 Position 2 ­ 3 W14 Selects input signal to ADC Installed Not installed W16 Link selects input for signal conditioning Multiplexer output External input via J3 or channel 0 via W21 Install jumper between TP10 and pin 1 of W16 W21 Link connects channel 0 to J3 / W14 / W16 Installed R54 0 Installed R55 N/A Not installed 3.5 Generating a Voltage Reference Two options provide the voltage reference: 3.5.1 Onboard reference (preferable) External reference Onboard Reference To set the onboard upper and lower reference voltage, use the jumper configuration shown in Figure 3­6. Figure 3­6. Onboard Reference Voltage W10 (a) Upper Limit Onboard Reference Voltage Upper Limit 1 2 1 3 W13 2 VREFP To ADC 3 External Reference Voltage Upper Limit VCC (A) To set the onboard lower reference voltage, the user should follow the jumper configuration shown in the following figure. (b) Lower Limit W12 Onboard Reference Voltage, Lower Limit 1 2 3 External Reference Voltage, Lower Limit 1 W15 2 VREFM To ADC 3 AGND 3-10 Generating a Voltage Reference Table 3­7. Shipping Condition for VEREFP and VREFM Jumper Pins 1 and 2 Pins 2 and 3 W10 Jumper installed Jumper not installed W13 Jumper installed Jumper not installed W12 Jumper installed Jumper not installed W15 Jumper installed Jumper not installed VREFP setting VREFM setting 3.5.2 External Reference It is important to understand that the reference voltage plays a fundamental part in the conversion process. Changes in the value of the reference voltage are reflected in the full-scale range of the device. The variation in voltage for the reference should, ideally, contribute less than 1/2 an LSB of error to the total conversion process. External reference voltages can be supplied via J6; see Section 3­9 Connector Pin and Function Assignments for pinout details. The jumper configuration for this option is given in the following figure. Under no circumstance should the external voltage exceed the supply voltage by more than 0.3 V. User Configurations 3-11 Host Interface Selection Figure 3­7. External Reference Voltage (a) Upper Limit W10 Onboard Reference Voltage, Upper Limit 1 W13 2 1 3 2 REFP 3 To ADC External Reference Voltage, Upper Limit VCC (A) (b) Lower Limit W12 Onboard Reference Voltage, Lower Limit 1 W15 2 3 External Reference Voltage, Lower Limit 1 2 REFM 3 To ADC AGND 3.6 Host Interface Selection Two operating modes are available for this EVM, as described in Chapter 2, Getting Started. After deciding the operating mode for the EVM, confirm the setting for jumper W5. If the EVM is mounted on the PCI2040 PCI2040 (C5410 C5410) EVM, or on the C5402DSK C5402DSK, the control signals and the internal ADC and DAC registers are accessible by setting a jumper across pins 2 and 3 of W5. If the EVM is to be used as a stand-alone with an alternate DSP or microprocessor host (for example the `C54x DSKplus, `C203 DSP EVM, or the `C3x DSK), the control signals and ADC and DAC registers are accessed by setting a jumper across pins 1 and 2 of W5. Table 3­8. Host Interface Jumpers Shipping Condition Jumper Pins 2 and 3 W5 3-12 Pins 1 and 2 Jumper installed Jumper not installed Conversion Modes 3.7 Conversion Modes The ADC provides two sampling/conversion methods-software mode and hardware mode. This section presents the user configuration options. 3.7.1 Software Mode Software mode is selected by setting the CR0 bit 7 of the ADC to 1. Control of conversions is managed by the RD and WR signals. In this mode, the system can operate either in stand-alone or in loopback mode. The stand-alone mode is the shipping configuration; this allows you to immediately begin evaluation. 3.7.1.1 Stand-Alone Mode A pulse initiates stand-alone mode. You supply the pulse by momentarily pressing SW1. The ADC handles subsequent conversions automatically. Table 3­9. Stand-Alone Mode Configuration Jumper Pins 2 and 3 W8 Jumper not installed Jumper installed SW1 3.7.1.2 Pins 1 and 2 Initiate first conversion Loopback Mode Loopback mode permits the ADC and DAC to operate synchronously. The jumper conditions are shown in the following table. Table 3­10.Loopback Mode Configuration Jumper Pins 1 and 2 Pins 2 and 3 W4 Jumper not installed Jumper not installed W6 Installed W7 Jumper not installed Jumper installed W8 Jumper not installed Jumper installed W11 Not installed J4 Analog output SW1 Initiate first conversion User Configurations 3-13 Conversion Modes 3.7.2 Hardware Mode Hardware mode is selected by setting the CR0 bit 7 of the ADC to 0. In this mode, conversion control is handled by the CSTART signal. This is illustrated in Figure 3­8. CSTART can be generated from one of three sources and is supplied directly to the ADC. Figure 3­8. Hardware Mode W9 CSTART 3 ADC 2 XF 1 CSTART W20 3 2 J11 1 3.7.2.1 CSTART CSTART is generated by a dummy access (read or write) to address XX.XX3h. Jumper Pins 2 and 3 W9 Jumper not installed Jumper installed W20 3.7.2.2 Pins 1 and 2 Jumper not installed Jumper installed XF0 CSTART is generated by the DSP signal XF0. Jumper Pins 2 and 3 W9 Jumper installed Jumper not installed W20 3.7.2.3 Pins 1 and 2 Jumper not installed Jumper installed External Trigger CSTART is generated externally. Jumper W9 Don't care W20 Jumper installed J11 3-14 Pins 1 and 2 Pins 2 and 3 Feed external signal in via this connector. Jumper not installed ADC Clock 3.8 ADC Clock The ADC requires an internal or external clock. There are various possible external sources for the clock required by the ADC. The choices are simple and are discussed in the following sections. 3.8.1 External Clock Generation The maximum operational speed of the ADC is 20 MHz when it operates from a Vcc supply of 5 V, or 10 MHz at 3.3 V. This clock signal derives from three possible sources: in stand-alone configuration from J10 or J7; otherwise, from J8 when mounted on a PCI2040 PCI2040 EVM or 'C5402 C5402 DSK. Figure 3­9. External Clock Signal J8 50-MHz Clock ÷2 J10 40-MHz Clock W19 ÷2 3 W18 2 3 1 2 ADC Clock ADC 1 J12 W17 3 2 CLK 1 J7 3.8.2 User Configurable DSK/Microprocessor Mode ('C54x DSKplus, 'C203 EVM, 'C3x DSK) Two configurations are available. On the preferred mode of operation in a stand-alone configuration, the clock signal is present on J10. The clock frequency, via the 'C54x DSK adapter board, is set at 40 MHz. This frequency is too fast for the ADC. To provide an acceptable frequency, the EVM divides the input clock. You can decide if the clock frequency required is 20 MHz or 10 MHz, and set the jumper positions accordingly. User Configurations 3-15 ADC Clock Table 3­11. Stand-Alone Selection, 20 MHz Jumper Pins 1 and 2 Pins 2 and 3 W17 Jumper not installed Jumper installed W18 Jumper not installed Jumper installed W19 Jumper installed Jumper not installed Table 3­12.Stand-Alone Selection, 10 MHz Jumper Pins 1 and 2 Pins 2 and 3 W17 Jumper not installed Jumper installed W18 Jumper not installed Jumper installed W19 Jumper not installed Jumper installed In stand-alone mode, you may choose to supply the ADC clock externally. In this case, you are responsible for ensuring that the frequency of the clock meets the ADC specifications, and apply the clock signal via J12. Table 3­13.Stand-Alone Selection External Clock Jumper Pins 2 and 3 W17 Jumper installed Jumper not installed W18 3.8.3 Pins 1 and 2 Jumper installed Jumper not installed PCI2040 PCI2040 and 'C5402 C5402 DSK Configuration When the EVM mates to the PCI2040 PCI2040 card or `C5402 C5402 DSK, the clock signal is present on J8. The clock frequency, via the PCI2040 PCI2040 card or `C5402 C5402 DSK, is set at 50 MHz. This frequency is too fast for the ADC. To provide an acceptable frequency, the EVM divides the input clock. You must select both division elements to derive an appropriate ADC frequency. Table 3­14.PCI2040 PCI2040 EVM 'C5402 C5402 DSK Selection, 12.5 MHz Jumper Pins 2 and 3 W17 Jumper not installed Jumper installed W18 Jumper not installed Jumper installed W19 3.8.4 Pins 1 and 2 Jumper not installed Jumper installed Synchronizing the EVM Regardless of whether the EVM mates onto a PCI 2040, the `C5402 C5402 DSK, or is stand-alone, the clock can be synchronized with other equipment via J12 and/or J7 by choosing the appropriate jumper positions. 3-16 Connector Pin and Function Assignments 3.9 Connector Pin and Function Assignments This section details the pinouts and functions for all user connectors. Table 3­15.Connector Pin and Function Assignments Reference Designator Function J1 Input signal applied to MUX Channel 0 J2 Input signal applied to MUX Channel 1 J3 Input signal applied directly to ADC J4 Output signal from DAC Table 3­16.J5 Power Connector Pin Number Function 1 Power 3 V ­ 5 V 2 AGND Table 3­17.J6 Analog Signal Connector Pin Number Function Pin Number Function 1 Channel 0 2 AGND 3 Channel 1 4 AGND 5 Channel 2 6 AGND 7 Channel 3 8 AGND 9 Channel 4 10 AGND 11 Channel 5 12 AGND 13 Channel 6 14 AGND 15 Channel 7 16 AGND 17 Ground (signal) 18 AGND 19 Analog Output 20 AGND 21 Ground (signal) 22 AGND 23 External ref. lower 24 AGND 25 External ref. upper 26 AGND User Configurations 3-17 Connector Pin and Function Assignments Table 3­18.J7 DSK/Microprocessor Control Connector Pin Number Function Pin Number Function 1 Not connected 2 Ground (digital) 3 Not connected 4 Ground (digital) 5 Not connected 6 Ground (digital) 7 Not connected 8 Ground (digital) 9 Not connected 10 Ground (digital) 11 Not connected 12 Ground (digital) 13 A1 14 Ground (digital) 15 A0 16 Ground (digital) 17 INT0 18 Ground (digital) 19 I/O_STRB 20 Ground (digital) 21 R/W 22 Ground (digital) 23 XF 24 Ground (digital) 25 CLK 26 Ground (digital) J8 and J9 are 80-pin headers that mate directly to the PCI mothercard as described in Chapter 1, EVM Overview. Consequently, you cannot change the functions associated with these headers, so they are not described in this section. 3-18 Connector Pin and Function Assignments Table 3­19.J10 Parallel Data Connector Pin Number Function Pin Number Function 1 DSP_15 (MSB) 2 Ground (digital) 3 DSP_14 4 Ground (digital) 5 DSP_13 6 Ground (digital) 7 DSP_12 8 Ground (digital) 9 DSP_11 10 Ground (digital) 11 DSP_10 12 Ground (digital) 13 DSP_09 14 Ground (digital) 15 DSP_08 16 Ground (digital) 17 DSP_07 18 Ground (digital) 19 DSP_06 20 Ground (digital) 21 DSP_05 22 Ground (digital) 23 DSP_04 24 Ground (digital) 25 DSP_03 26 Ground (digital) 27 DSP_02 28 Ground (digital) 29 DSP_01 30 Ground (digital) 31 DSP_00 (LSB) 32 Ground (digital) 33 CLKOUT 34 Ground (digital) Table 3­20.Function of Connectors J11 and J12 Reference Designator Function J11 ADC CSTART signal (optional) J12 ADC Clock signal (optional) User Configurations 3-19 3-20 Chapter 4 Control Registers Registers 0 and 1 inside the TLV1578 TLV1578 / TLV1571 TLV1571 / TLV571 TLV571 control various ADC features and functions. This section describes the function of these registers. Topic Page 4.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Control Register 0 ­ CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3 Control Register 1 ­ CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Control Registers 4-1 Programming Model 4.1 Programming Model The EVM uses an MSB model. The illustration below indicates how bits from a host system are mapped to the corresponding bits on the EVM. To maintain software compatibility between each device in the family, it is important to note that bits D0 and D1 of the TLV571 TLV571 EVM are grounded, and cannot be used. Since these bits control the MUX channel selected and some self-test results, the effect of their loss from the TLV571 TLV571's functionality is small. Table 4­1. Data Bus Bit 15 14 13 12 11 10 9 8 7 6 TLV1578 TLV1578 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 TLV1571 TLV1571 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 TLV571 TLV571 D07 D06 D05 D04 D03 D02 D01 5 4 3 2 1 0 D00 4.2 Control Register 0 ­ CR0 Table 4­2. Control Register 0 (Read/Write) 7 6 5 4 3 STARTSEL PROG EOC CLKSEL SWPWDN 2 MODESEL 1 0 CHSEL (2-0) Bit 7 STARTSEL STARTSEL determines hardware- or software-start for data conversion. 0 Hardware conversion mode selected 1 Software conversion mode selected STARTSEL Bit 6 PROGEOC PROGEOC determines how the ADC signals the host that a conversion has taken place. 0 1 PROGEOC An interrupt signal, INT, is generated after each conversion. An EOC signal is deasserted at the beginning of the conversion, and asserted at the end of the conversion. The INT/EOC signal is available through pin 17 of connector J7. Bit 5 CLKSEL CLKSEL establishes which clock signal is used by the ADC. 0 Internal clock selected The TLV1578 TLV1578 has an integrated oscillator. Its value can be set to 10 ±1 MHz or 20 ±2 MHz by CR1.6. 1 External clock selected The external clock input is available via J10 pin33. CLKSEL 4-2 Control Register 0 ­ CR0 Bit 4 SWPDWN SWPDWN controls the power-down mode. 0 Standard operation (auto-powerdown) 1 Power-down mode selected In this mode the comparators, clock buffers, and internal reference power down, and the current drawn from the device does not exceed 10 µA. SWPWDN Notice that the ADC automatically proceeds to a power-down mode if valid data is available, and it has not been read by the system after one clock cycle. In this mode, referred to as auto-powerdown, the comparators and clock buffers power down; however, the reference voltage does not power down. Consequently, the current drawn from the device is higher but does not exceed 1 mA. Bit 3 MODESEL MODESEL selects between single channel or sweep channel modes. 0 Single channel selected 1 Each channel is accessed sequentially (swept) MODESEL Bit 2 ­ 0 CHSEL CHSEL controls channel selection. The value written to this register depends upon the mode the user has selected (via MODESEL). MODESEL=0: A single channel is selected. D2 D0 Channel Selected 0 0 0 0 0 0 1 1 0 CHSEL D1 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Control Registers 4-3 Control Register 1 ­ CR1 MODESEL=1: Sweep mode is selected. D2 D0 0 0 0 0­1 0 0 1 0­1­2­3 0 1 0 0­1­2­3­4­5 0 1 1 0 ­ 1 ­ 2 ­ 3 ­ 4 ­ 5 ­ 6 ­7 1 0 0 N/A 1 0 1 N/A 1 1 0 N/A 1 CHSEL D1 Channels Sequenced 1 1 N/A 4.3 Control Register 1 ­ CR1 Table 4­3. Control Register 1 (Read/Write) 7 6 5 RESERVED OSCSPD 4 RESESRVED 3 2 1 0 OUTCODE READREG STEST1 STEST0 Bit 7 is reserved. Bit 6 OSCSPD OSCSPD selects the speed of the integrated oscillator. 0 Internal oscillator is set slow ­ 10-MHz clock 1 Internal oscillator is set fast ­ 20-MHz clock STARTSEL Bits 4 and 5 are reserved. The ADC reserves two bits for internal use. You should always write 0 into these two bits. Note: In register readback mode, CR1.5 contains the opposite of what was written in; this should not be a concern. Bit 3 OUTCODE OUTCODE determines which output coding scheme is used by the ADC. 0 Unipolar straight binary code selected 1 Binary 2s-complement code selected OUTCODE 4-4 Control Register 1 ­ CR1 Bit 2, 1, and 0 READREG STEST1 and STEST0 (TLV1578/TLV1571 TLV1578/TLV1571 Only) READREG determines if the ADC performs a self-test (3 self-test modes are available), or if the ADC control registers should be set to read-back mode. 0 Enable self-test 1 Enable register readback READREG Three self-test modes are available. When READREG=1, the output is determined by the value of STEST1 and STEST0. READREG STEST1 STEST0 Outcome 1 0 0 Output = contents of CR0 1 0 1 Output = contents of CR1 1 1 0 Reserved 1 1 1 This bit works in conjunction with STEST0 and STEST1. READREG STEST1 STEST0 Outcome 0 0 0 Output = conversion result 0 0 1 Output = self-test 1 result, 0000h 0 1 0 Output = self-test 2 result, 1/2 full scale 0 1 1 Output = self-test 3 result, full scale Control Registers 4-5 4-6