TLV320AIC28 SLAS418 AIC28 QFN-48 TLV320AIC28IRGZ TLV320AIC28IRGZR OUT32N 0000H - Datasheet Archive

 

www.ti.com SLAS418 - FEBRUARY 2004 STEREO AUDIO CODEC WITH INTEGRATED HEADPHONE AND SPEAKER AMPLIFIERS FEATURES D Stereo Audio

 

TLV320AIC28 TLV320AIC28 www.ti.com SLAS418 SLAS418 - FEBRUARY 2004 STEREO AUDIO CODEC WITH INTEGRATED HEADPHONE AND SPEAKER AMPLIFIERS FEATURES D Stereo Audio DAC and Mono Audio ADC Support Rates Up to 48 ksps D High Quality 95-dB Stereo Audio Playback Performance D MIC Preamp and Hardware Automatic Gain Control With Up to 59.5-dB Gain D Stereo 16-W Headphone Amplifier With Capless Output Option D 400-mW 8-W Audio Power Amp With Direct Battery Supply Connection D 32-W Differential Earpiece Driver D Integrated PLL For Flexible Audio Clock Generation D Low Power 19-mW Stereo Audio Playback at 48 ksps and 3.3-V Analog Supply level D Programmable Digital Audio Bass/Treble/ EQ/De-Emphasis D Auto-Detection of Jack Insertion, Headset Type, and Button Press D Direct Battery Measurement Accepts Up to 6-V Input D On-Chip Temperature and Auxiliary Input Measurement D Programmable Measurement Converter Resolution, Speed, Averaging, and Timing D SPI and I2S Serial Interfaces D Full Power-Down Control D 48-Pin QFN Package APPLICATIONS D Personal Digital Assistants D Cellular Smartphones D Digital Still Cameras D Digital Camcorders D MP3 Players DESCRIPTION The TLV320AIC28 TLV320AIC28 is a low-power, high-performance audio codec with 16/20/24/32-bit 95-dB stereo playback, mono record functionality at up to 48 ksps. Two microphone inputs include independent programmable bias voltages, built-in pre-amps, and hardware automatic gain control, with single-ended or fully-differential signal input capabilities. The stereo 16- headphone drivers on the AIC28 AIC28 support capless as well as ac-coupled output configurations. An 8- BTL differential speaker driver provides up to 400 mW of power and 98-dB SNR, while a differential driver is also available for driving a 32- speaker or telephone earpiece. A programmable digital audio effects processor enables bass, treble, midrange, or equalization playback processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, DSP, left/right justified) in master or slave mode, and also includes an on-chip programmable PLL for flexible clock generation capability. Highly configurable software power control is provided, enabling 48 ksps stereo audio playback to 16- headphones at 19 mW with a 3.3-V analog supply level. The AIC28 AIC28 offers a 12-bit measurement ADC and internal reference voltage. It includes an on-chip temperature sensor capable of reading 0.3°C resolution, as well as a battery measurement input capable of reading battery voltages up to 6 V, while operating at an analog supply as low as 3 V. The AIC28 AIC28 is available in a 48-lead 7 x 7 mm QFN package. US Patent No. 624639 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. I2S is a trademark of Philips Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2004, Texas Instruments Incorporated TLV320AIC28 TLV320AIC28 www.ti.com SLAS418 SLAS418 - FEBRUARY 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320AIC28 TLV320AIC28 QFN-48 QFN-48 RGZ -40°C to +85°C ORDERING NUMBER TRANSPORT MEDIA TLV320AIC28IRGZ TLV320AIC28IRGZ Rails, 52 TLV320AIC28IRGZR TLV320AIC28IRGZR Tape and Reel, 2000 PIN ASSIGNMENTS DVSS DVDD BCLK WCLK SDIN SDOUT MCLK SCLK MISO MOSI SS DAV QFN PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 IOVDD PWR_DN RESET GPIO2 GPIO1 AVDD2 AVSS2 AVDD1 NC NC NC NC 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 AVSS1 VREF VBAT AUX2 AUX1 BUZZ_IN CP_OUT CP_IN MICIN_HND MICBIAS_HND MICIN_HED MICBIAS_HED 13 14 15 16 17 18 19 20 21 22 23 24 2 DRVSS2 OUT8P BVDD OUT8N DRVSS1 VGND SPKFC DRVDD SPK2 SPK1 OUT32N OUT32N MIC_DETECT_IN TLV320AIC28 TLV320AIC28 www.ti.com SLAS418 SLAS418 - FEBRUARY 2004 Terminal Functions PIN NAME 1 IOVDD 2 PWR_DN 3 RESET 4 5 DESCRIPTION PIN NAME DESCRIPTION IO Supply 25 MIC_DETECT_IN Microphone detect input Hardware power down 26 OUT32N OUT32N Hardware reset 27 SPK1 Headset driver output/receiver driver output GPIO2 General purpose IO 28 SPK2 Headset driver output GPIO1 General purpose IO 29 DRVDD Headphone driver power supply 6 AVDD2 PLL analog power supply 30 SPKFC Driver feedback/ speaker detect input 7 AVSS2 Analog ground 31 VGND Virtual ground for audio output 8 AVDD1 Audio ADC, DAC, reference, SAR ADC analog power supply 32 DRVSS1 Driver ground 9 NC No connect 33 OUT8N Loudspeaker driver output 10 NC No connect 34 BVDD Battery power supply 11 NC No connect 35 OUT8P Loudspeaker driver output 12 NC No connect 36 DRVSS2 13 AVSS1 Analog ground 37 DAV 14 VREF Reference voltage for SAR ADC 38 SS 15 VBAT Battery monitor input 39 MOSI SPI Serial data input 16 AUX2 Secondary auxiliary input 40 MISO SPI Serial data output 17 AUX1 First auxiliary input 41 SCLK SPI Serial clock input 18 BUZZ_IN Buzzer input 42 MCLK Master clock 19 CP_OUT Output to cell phone module 43 SDOUT Audio data output 20 CP_IN Input from cell phone module 44 SDIN Audio data input 21 MICIN_HND Handset microphone input 45 WCLK Audio word clock 22 MICBIAS_HND Handset microphone bias voltage 46 BCLK Audio bit clock 23 MICIN_HED Headset microphone input 47 DVDD Digital core supply 24 MICBIAS_HED Headset microphone bias voltage 48 DVSS Digital core and IO ground Receiver driver output Driver ground Auxiliary data available output SPI Slave select input ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1), (2) UNITS AVDD1/2 to AVSS1/2 -0.3 V to 3.9 V DRVDD to DRVSS1/2 -0.3 V to 3.9 V BVDD to DRVSS1/2 -0.3 V to 4.5 V IOVDD to DVSS -0.3 V to 3.9 V Digital input voltage to DVSS -0.3 V to IOVDD + 0.3 V Analog input (except VBAT) voltage to AVSS1/2 -0.3 V to AVDD + 0.3 V VBAT input voltage to AVSS1/2 -0.3 V to 6 V AVSS1/2 to DRVSS1/2 to DVSS -0.1 V to 0.1 V AVDD1/2 to DRVDD -0.1 V to 0.1 V Operating temperature range -40°C to 85°C Storage temperature range -65°C to 105°C Junction temperature (TJ Max) Power dissipation QFN package 105°C (TJ Max - TA)/JA 27°C/W JA Thermal impedance (with thermal pad soldered to board) Lead temperature Infrared (15 sec) 240°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If the AIC28 AIC28 is used to drive high power levels to an 8- load for extended intervals at an ambient temperature above 80°C, multiple vias should be used to electrically and thermally connect the thermal pad on the QFN package to an internal heat dissipating ground plane on the user's PCB. 3 TLV320AIC28 TLV320AIC28 www.ti.com SLAS418 SLAS418 - FEBRUARY 2004 ELECTRICAL CHARACTERISTICS At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BATTERY MONITOR INPUTS Input voltage range 0.5 Input leakage current Accuracy 6.0 V ±1 Variation across temperature after system calibration at 4 V battery voltage and room temperature µA ±15 Battery conversion not selected mV AUXILIARY A/D CONVERTER Resolution Programmable: 8-, 10-,12-bits No missing codes 12-Bit resolution 8 12 Bits 11 Bits Integral nonlinearity -5 5 LSB Offset error -6 6 LSB Gain error -6 6 Noise LSB µVrms 50 VOLTAGE REFERENCE (VREF) VREF output programmed = 2.5 V Voltage range 2.3 VREF output programmed = 1.25 V External reference Reference drift Internal VREF = 1.25 V Current drain Extra current drawn when the internal reference is turned on. 2.5 2.7 V 1.25 1.1 2.5 V 50 ppm/°C 750 µA AUDIO CODEC ADC DECIMATION FILTER CHARACTERISTICS ±0.1 dB -0.25 dB Filter gain at 0.45 Fs -3.0 dB Filter gain at 0.5 Fs -17.5 dB Filter gain from 0 to 0.39 Fs Filter gain at 0.4125 Fs Filter gain from 0.55 Fs to 64 Fs Group delay 4 -75 dB 17/Fs sec TLV320AIC28 TLV320AIC28 www.ti.com SLAS418 SLAS418 - FEBRUARY 2004 ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS MICIN_HED 1020 Hz sine wave input, Fs = 48 ksps MICROPHONE INPUT TO ADC Full-scale input voltage (0 dB) 0.707 Input common mode Vrms 1.5 SNR Measured as idle channel noise, 0 dB gain, A-weighted THD 0.63 Vrms input, 0-dB gain PSRR 217 Hz, 100 mV on AVDD1/2(1) 1020 Hz, 100 mV on AVDD1/2(1) Mute attenuation Output code with 0.63 Vrms sine wave input at 1 kHz 80 90 dBA -81 -72 dB 55 dB 55 dB 0000H 0000H Only ADC on Input resistance V 15 50 k 8 ADC and Sidetone on 16 k Input capacitance 10 pF HEADSET MICROPHONE BIAS Register 1DH/Page 2, D7-D8=00 Register 1DH/Page 2, D7-D8=01 2.5 Register 1DH/Page 2, D7-D8=1X Voltage range 3.3 2 217 Hz, 100 mV on AVDD1/2 55 1020 Hz, 100 mV on BVDD Sourcing current 74 1020 Hz, 100 mV on AVDD1/2 PSRR 55 217 Hz, 100 mV on BVDD V 74 Voltage drop ADC is busy 1 => ADC is not busy (default). WRITE 0 => Normal mode (default). 1 => Stop conversion and power down. D13-D10 D13-D10 ADCSM 0000 R/W ADC Scan Mode. 0000 => No scan 0001 => Reserved 0010 => Reserved 0011 => Reserved 0100 => Reserved 0101 => Reserved 0110 => BAT input is converted and the results returned to the BAT data register. 0111 => AUX2 input is converted and the results returned to the AUX2 data register 1000 => AUX1 input is converted and the results returned to the AUX1 data register. 1001 => Auto Scan function: For AUX1, AUX2, TEMP1 or TEMP2 as chosen using control register 0CH/page 1. Scan continues until stop bit is sent or D13-D10 D13-D10 are changed. 1010 => TEMP1 input is converted and the results returned to the TEMP1 data register. 1011 => Port scan function: BAT, AUX1, AUX2 inputs are measured and the results returned to the appropriate data registers. 1100 => TEMP2 input is converted and the results returned to the TEMP2 data register. 1101 => Reserved 1110 => Reserved 1111 => Reserved D9-D8 RESOL 00 R/W Resolution Control. The ADC resolution is specified with these bits. 00 => 12-bit resolution 01 => 8-bit resolution 10 => 10-bit resolution 11 => 12-bit resolution D7-D6 ADAVG 00 R/W Converter Averaging Control. These two bits allow user to specify the number of averages the converter will perform selected by bit D0, which selects either Mean Filter or Median Filter. Mean Filter Median Filter 00 => No average No average 01 => 4-data average 5-data average 10 => 8-data average 9-data average 11 => 16-data average 15-data average D5-D4 ADCR 00 R/W Conversion Rate Control. These two bits specify the internal clock rate, which the ADC uses to control performing a single conversion. These bits are the same whether reading or writing. tconv + N ) 4 INTCLK Where fINTCLK is the internal clock frequency. For example, with 12-bit resolution and a 2 MHz internal clock frequency, the conversion time is 8 µs. This yields an effective throughput rate of 125 kHz. 00 => 8 MHz internal clock rate (use for 8-bit resolution only) 01 =>4 MHz internal clock rate (use for 8-bit/10-bit resolution only) 10 =>2 MHz internal clock rate 11 =>1 MHz internal clock rate D3-D1 D0 0's AVGFS R 0 R/W Reserved Average Filter Select 0 => Mean Filter 1 => Median Filter 43 TLV320AIC28 TLV320AIC28 www.ti.com SLAS418 SLAS418 - FEBRUARY 2004 REGISTER 01H: Status Register BIT NAME RESET VALUE READ/ WRITE D15-D14 D15-D14 DAV 10 R/W D13 PWRDN 0 R ADC Power down status 0 => ADC is active 1 => ADC stops conversion and powers down 0 R Reserved 0 R Data Available Status 0 => No data available. 1 => Data is available(i.e one set of conversion is done) Note:- This bit gets cleared only after all the converted data have been completely read out. This bit is not valid in case of buffer mode. 0 R Reserved 0 R BAT Data Register Status 0 => No new data is available in BAT data register 1 => New data is available in BAT data register D12 D11 DAVAIL D10-D7 D10-D7 D6 BSTAT FUNCTION Data Available. These two bits program the function of the DAV pin. 00 => Reserved 01 => Acts as data available (active low) only. The DAV goes low as soon as one set of ADC conversion(s) is completed. For scan mode, DAV remains low as long as all the appropriate registers have not been read out. 10 => Reserved 11 => Reserved Note:- D15-D14 D15-D14 should be rpogrammed to 01 for the AIC28 AIC28 to operate properly. Note: This bit gets cleared only after the converted data of BAT has been completely read out of the register. This bit is not valid in case of buffer mode. D5 D4 0 AX1STAT R Reserved 0 R AUX1 Data Register Status 0 => No new data is available in AUX1-data register 1 => New data is available in AUX1-data register Note: This bit gets cleared only after the converted data of AUX1 has been completely read out of the register. This bit is not valid in case of buffer mode. D3 AX2STAT 0 R AUX2 Data Register Status 0 => No new data is available in AUX2-data register 1 => New data is available in AUX2-data register Note: This bit gets cleared only after the converted data of AUX2 has been completely read out of the register. This bit is not valid in case of buffer mode. D2 T1STAT 0 R TEMP1 Data Register Status 0 => No new data is available in TEMP1-data register 1 => New data is available in TEMP1-data register Note: This bit gets cleared only after the converted data of TEMP1 has been completely read out of the register. This bit is not valid in case of buffer mode. D1 T2STAT 0 R TEMP2 Data Register Status 0 => No new data is available in TEMP2-data register 1 => New data is available in TEMP2-data register Note: This bit gets cleared only after the converted data of TEMP2 has been completely read out of the register. This bit is not valid in case of buffer mode. D0 44 0 R Reserved TLV320AIC28 TLV320AIC28 www.ti.com SLAS418 SLAS418 - FEBRUARY 2004 REGISTER 02H: Buffer Control BIT NAME RESET VALUE READ/ WRITE D15 BUFRES 0 R/W Buffer Reset. 0 => Buffer mode is disabled and RDPTR, WRPTR & TGPTR set to their reset value. 1 => Buffer mode is enabled. D14 BUFCONT 0 R/W Buffer Mode Selection 0 => Continuous conversion mode. 1 => Single shot mode. D13-D11 D13-D11 BUFTL 000 R/W Trigger Level TL selection of Buffer used for SAR ADC 000 => 8 001 => 16 010 => 24 011 => 32 100 => 40 101 => 48 110 => 56 111 => 64 D10 BUFOVF 0 R Buffer Full Flag 0 => Buffer is not full. 1 => Buffer is full. This means buffer contains 64 unread converted data. D9 BUFEMF 1 R Buffer Empty Flag 0 => Buffer is not empty. 1 => Buffer is empty. This means there is no unread converted data in the buffer. 0's R Reserved D8-D0 FUNCTION REGISTER 03H: Reference Control BIT NAME RESET VALUE READ/ WRITE FUNCTION D15-D6 D15-D6 0's R D5 0 R/W Reserved Reserved. Alw